1 /*- 2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_regdomain.h> 85 #ifdef IEEE80211_SUPPORT_SUPERG 86 #include <net80211/ieee80211_superg.h> 87 #endif 88 #ifdef IEEE80211_SUPPORT_TDMA 89 #include <net80211/ieee80211_tdma.h> 90 #endif 91 92 #include <net/bpf.h> 93 94 #ifdef INET 95 #include <netinet/in.h> 96 #include <netinet/if_ether.h> 97 #endif 98 99 #include <dev/ath/if_athvar.h> 100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101 #include <dev/ath/ath_hal/ah_diagcodes.h> 102 103 #include <dev/ath/if_ath_debug.h> 104 #include <dev/ath/if_ath_misc.h> 105 #include <dev/ath/if_ath_tsf.h> 106 #include <dev/ath/if_ath_tx.h> 107 #include <dev/ath/if_ath_sysctl.h> 108 #include <dev/ath/if_ath_led.h> 109 #include <dev/ath/if_ath_keycache.h> 110 #include <dev/ath/if_ath_rx.h> 111 #include <dev/ath/if_ath_beacon.h> 112 #include <dev/ath/if_athdfs.h> 113 114 #ifdef ATH_TX99_DIAG 115 #include <dev/ath/ath_tx99/ath_tx99.h> 116 #endif 117 118 #include <dev/ath/if_ath_rx_edma.h> 119 120 #ifdef ATH_DEBUG_ALQ 121 #include <dev/ath/if_ath_alq.h> 122 #endif 123 124 /* 125 * some general macros 126 */ 127 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1) 128 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1) 129 130 MALLOC_DECLARE(M_ATHDEV); 131 132 /* 133 * XXX TODO: 134 * 135 * + Add an RX lock, just to ensure we don't have things clash; 136 * + Make sure the FIFO is correctly flushed and reinitialised 137 * through a reset; 138 * + Handle the "kickpcu" state where the FIFO overflows. 139 * + Implement a "flush" routine, which doesn't push any 140 * new frames into the FIFO. 141 * + Verify multi-descriptor frames work! 142 * + There's a "memory use after free" which needs to be tracked down 143 * and fixed ASAP. I've seen this in the legacy path too, so it 144 * may be a generic RX path issue. 145 */ 146 147 /* 148 * XXX shuffle the function orders so these pre-declarations aren't 149 * required! 150 */ 151 static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, 152 int nbufs); 153 static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype); 154 static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf); 155 static int ath_edma_recv_proc_queue(struct ath_softc *sc, 156 HAL_RX_QUEUE qtype, int dosched); 157 158 static void 159 ath_edma_stoprecv(struct ath_softc *sc, int dodelay) 160 { 161 struct ath_hal *ah = sc->sc_ah; 162 163 ATH_RX_LOCK(sc); 164 ath_hal_stoppcurecv(ah); 165 ath_hal_setrxfilter(ah, 0); 166 ath_hal_stopdmarecv(ah); 167 168 DELAY(3000); 169 170 /* Flush RX pending for each queue */ 171 /* XXX should generic-ify this */ 172 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) { 173 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 174 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 175 } 176 177 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) { 178 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 179 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 180 } 181 ATH_RX_UNLOCK(sc); 182 } 183 184 /* 185 * Re-initialise the FIFO given the current buffer contents. 186 * Specifically, walk from head -> tail, pushing the FIFO contents 187 * back into the FIFO. 188 */ 189 static void 190 ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype) 191 { 192 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 193 struct ath_buf *bf; 194 int i, j; 195 196 ATH_RX_LOCK_ASSERT(sc); 197 198 i = re->m_fifo_head; 199 for (j = 0; j < re->m_fifo_depth; j++) { 200 bf = re->m_fifo[i]; 201 DPRINTF(sc, ATH_DEBUG_EDMA_RX, 202 "%s: Q%d: pos=%i, addr=0x%jx\n", 203 __func__, 204 qtype, 205 i, 206 (uintmax_t)bf->bf_daddr); 207 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype); 208 INCR(i, re->m_fifolen); 209 } 210 211 /* Ensure this worked out right */ 212 if (i != re->m_fifo_tail) { 213 device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n", 214 __func__, 215 i, 216 re->m_fifo_tail); 217 } 218 } 219 220 /* 221 * Start receive. 222 * 223 * XXX TODO: this needs to reallocate the FIFO entries when a reset 224 * occurs, in case the FIFO is filled up and no new descriptors get 225 * thrown into the FIFO. 226 */ 227 static int 228 ath_edma_startrecv(struct ath_softc *sc) 229 { 230 struct ath_hal *ah = sc->sc_ah; 231 232 ATH_RX_LOCK(sc); 233 234 /* Enable RX FIFO */ 235 ath_hal_rxena(ah); 236 237 /* 238 * Entries should only be written out if the 239 * FIFO is empty. 240 * 241 * XXX This isn't correct. I should be looking 242 * at the value of AR_RXDP_SIZE (0x0070) to determine 243 * how many entries are in here. 244 * 245 * A warm reset will clear the registers but not the FIFO. 246 * 247 * And I believe this is actually the address of the last 248 * handled buffer rather than the current FIFO pointer. 249 * So if no frames have been (yet) seen, we'll reinit the 250 * FIFO. 251 * 252 * I'll chase that up at some point. 253 */ 254 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) { 255 DPRINTF(sc, ATH_DEBUG_EDMA_RX, 256 "%s: Re-initing HP FIFO\n", __func__); 257 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP); 258 } 259 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_LP) == 0) { 260 DPRINTF(sc, ATH_DEBUG_EDMA_RX, 261 "%s: Re-initing LP FIFO\n", __func__); 262 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP); 263 } 264 265 /* Add up to m_fifolen entries in each queue */ 266 /* 267 * These must occur after the above write so the FIFO buffers 268 * are pushed/tracked in the same order as the hardware will 269 * process them. 270 */ 271 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP, 272 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen); 273 274 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP, 275 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen); 276 277 ath_mode_init(sc); 278 ath_hal_startpcurecv(ah); 279 280 ATH_RX_UNLOCK(sc); 281 282 return (0); 283 } 284 285 static void 286 ath_edma_recv_flush(struct ath_softc *sc) 287 { 288 289 DPRINTF(sc, ATH_DEBUG_RECV, "%s: called\n", __func__); 290 291 ATH_PCU_LOCK(sc); 292 sc->sc_rxproc_cnt++; 293 ATH_PCU_UNLOCK(sc); 294 295 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0); 296 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0); 297 298 ATH_PCU_LOCK(sc); 299 sc->sc_rxproc_cnt--; 300 ATH_PCU_UNLOCK(sc); 301 } 302 303 /* 304 * Process frames from the current queue. 305 * 306 * TODO: 307 * 308 * + Add a "dosched" flag, so we don't reschedule any FIFO frames 309 * to the hardware or re-kick the PCU after 'kickpcu' is set. 310 * 311 * + Perhaps split "check FIFO contents" and "handle frames", so 312 * we can run the "check FIFO contents" in ath_intr(), but 313 * "handle frames" in the RX tasklet. 314 */ 315 static int 316 ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype, 317 int dosched) 318 { 319 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 320 struct ath_rx_status *rs; 321 struct ath_desc *ds; 322 struct ath_buf *bf; 323 struct mbuf *m; 324 struct ath_hal *ah = sc->sc_ah; 325 uint64_t tsf; 326 int16_t nf; 327 int ngood = 0, npkts = 0; 328 ath_bufhead rxlist; 329 struct ath_buf *next; 330 331 TAILQ_INIT(&rxlist); 332 333 tsf = ath_hal_gettsf64(ah); 334 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 335 sc->sc_stats.ast_rx_noise = nf; 336 337 ATH_RX_LOCK(sc); 338 339 do { 340 bf = re->m_fifo[re->m_fifo_head]; 341 /* This shouldn't occur! */ 342 if (bf == NULL) { 343 device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n", 344 __func__, 345 qtype); 346 break; 347 } 348 m = bf->bf_m; 349 ds = bf->bf_desc; 350 351 /* 352 * Sync descriptor memory - this also syncs the buffer for us. 353 * 354 * EDMA descriptors are in cached memory. 355 */ 356 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 357 BUS_DMASYNC_POSTREAD); 358 rs = &bf->bf_status.ds_rxstat; 359 bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr, 360 NULL, rs); 361 #ifdef ATH_DEBUG 362 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 363 ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK); 364 #endif /* ATH_DEBUG */ 365 #ifdef ATH_DEBUG_ALQ 366 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 367 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 368 sc->sc_rx_statuslen, (char *) ds); 369 #endif /* ATH_DEBUG */ 370 if (bf->bf_rxstatus == HAL_EINPROGRESS) 371 break; 372 373 /* 374 * Completed descriptor. 375 * 376 * In the future we'll call ath_rx_pkt(), but it first 377 * has to be taught about EDMA RX queues (so it can 378 * access sc_rxpending correctly.) 379 */ 380 DPRINTF(sc, ATH_DEBUG_EDMA_RX, 381 "%s: Q%d: completed!\n", __func__, qtype); 382 npkts++; 383 384 /* 385 * Remove the FIFO entry and place it on the completion 386 * queue. 387 */ 388 re->m_fifo[re->m_fifo_head] = NULL; 389 TAILQ_INSERT_TAIL(&rxlist, bf, bf_list); 390 391 /* Bump the descriptor FIFO stats */ 392 INCR(re->m_fifo_head, re->m_fifolen); 393 re->m_fifo_depth--; 394 /* XXX check it doesn't fall below 0 */ 395 } while (re->m_fifo_depth > 0); 396 397 /* Append some more fresh frames to the FIFO */ 398 if (dosched) 399 ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen); 400 401 ATH_RX_UNLOCK(sc); 402 403 /* Handle the completed descriptors */ 404 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) { 405 /* 406 * Skip the RX descriptor status - start at the data offset 407 */ 408 m_adj(bf->bf_m, sc->sc_rx_statuslen); 409 410 /* Handle the frame */ 411 /* 412 * Note: this may or may not free bf->bf_m and sync/unmap 413 * the frame. 414 */ 415 rs = &bf->bf_status.ds_rxstat; 416 if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf)) 417 ngood++; 418 } 419 420 /* Free in one set, inside the lock */ 421 ATH_RX_LOCK(sc); 422 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) { 423 /* Free the buffer/mbuf */ 424 ath_edma_rxbuf_free(sc, bf); 425 } 426 ATH_RX_UNLOCK(sc); 427 428 /* rx signal state monitoring */ 429 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 430 if (ngood) 431 sc->sc_lastrx = tsf; 432 433 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 2, 434 "ath edma rx proc: npkts=%d, ngood=%d", 435 npkts, ngood); 436 437 /* Handle resched and kickpcu appropriately */ 438 ATH_PCU_LOCK(sc); 439 if (dosched && sc->sc_kickpcu) { 440 ATH_KTR(sc, ATH_KTR_ERROR, 0, 441 "ath_edma_recv_proc_queue(): kickpcu"); 442 device_printf(sc->sc_dev, 443 "%s: handled npkts %d ngood %d\n", 444 __func__, npkts, ngood); 445 446 /* 447 * XXX TODO: what should occur here? Just re-poke and 448 * re-enable the RX FIFO? 449 */ 450 sc->sc_kickpcu = 0; 451 } 452 ATH_PCU_UNLOCK(sc); 453 454 return (ngood); 455 } 456 457 static void 458 ath_edma_recv_tasklet(void *arg, int npending) 459 { 460 struct ath_softc *sc = (struct ath_softc *) arg; 461 struct ifnet *ifp = sc->sc_ifp; 462 #ifdef IEEE80211_SUPPORT_SUPERG 463 struct ieee80211com *ic = ifp->if_l2com; 464 #endif 465 466 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n", 467 __func__, 468 npending); 469 470 ATH_PCU_LOCK(sc); 471 if (sc->sc_inreset_cnt > 0) { 472 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n", 473 __func__); 474 ATH_PCU_UNLOCK(sc); 475 return; 476 } 477 sc->sc_rxproc_cnt++; 478 ATH_PCU_UNLOCK(sc); 479 480 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1); 481 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1); 482 483 /* XXX inside IF_LOCK ? */ 484 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 485 #ifdef IEEE80211_SUPPORT_SUPERG 486 ieee80211_ff_age_all(ic, 100); 487 #endif 488 if (! IFQ_IS_EMPTY(&ifp->if_snd)) 489 ath_tx_kick(sc); 490 } 491 if (ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 492 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 493 494 ATH_PCU_LOCK(sc); 495 sc->sc_rxproc_cnt--; 496 ATH_PCU_UNLOCK(sc); 497 } 498 499 /* 500 * Allocate an RX mbuf for the given ath_buf and initialise 501 * it for EDMA. 502 * 503 * + Allocate a 4KB mbuf; 504 * + Setup the DMA map for the given buffer; 505 * + Keep a pointer to the start of the mbuf - that's where the 506 * descriptor lies; 507 * + Take a pointer to the start of the RX buffer, set the 508 * mbuf "start" to be there; 509 * + Return that. 510 */ 511 static int 512 ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 513 { 514 515 struct mbuf *m; 516 int error; 517 int len; 518 519 ATH_RX_LOCK_ASSERT(sc); 520 521 m = m_getm(NULL, sc->sc_edma_bufsize, M_NOWAIT, MT_DATA); 522 if (! m) 523 return (ENOBUFS); /* XXX ?*/ 524 525 /* XXX warn/enforce alignment */ 526 527 len = m->m_ext.ext_size; 528 #if 0 529 device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n", 530 __func__, 531 m, 532 len, 533 mtod(m, char *)); 534 #endif 535 536 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 537 538 /* 539 * Create DMA mapping. 540 */ 541 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 542 bf->bf_dmamap, m, bf->bf_segs, &bf->bf_nseg, BUS_DMA_NOWAIT); 543 if (error != 0) { 544 device_printf(sc->sc_dev, "%s: failed; error=%d\n", 545 __func__, 546 error); 547 m_freem(m); 548 return (error); 549 } 550 551 /* 552 * Populate ath_buf fields. 553 */ 554 555 bf->bf_desc = mtod(m, struct ath_desc *); 556 bf->bf_daddr = bf->bf_segs[0].ds_addr; 557 bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */ 558 bf->bf_m = m; 559 560 /* Zero the descriptor */ 561 memset(bf->bf_desc, '\0', sc->sc_rx_statuslen); 562 563 #if 0 564 /* 565 * Adjust mbuf header and length/size to compensate for the 566 * descriptor size. 567 */ 568 m_adj(m, sc->sc_rx_statuslen); 569 #endif 570 571 /* Finish! */ 572 573 return (0); 574 } 575 576 static struct ath_buf * 577 ath_edma_rxbuf_alloc(struct ath_softc *sc) 578 { 579 struct ath_buf *bf; 580 int error; 581 582 ATH_RX_LOCK_ASSERT(sc); 583 584 /* Allocate buffer */ 585 bf = TAILQ_FIRST(&sc->sc_rxbuf); 586 /* XXX shouldn't happen upon startup? */ 587 if (bf == NULL) 588 return (NULL); 589 590 /* Remove it from the free list */ 591 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 592 593 /* Assign RX mbuf to it */ 594 error = ath_edma_rxbuf_init(sc, bf); 595 if (error != 0) { 596 device_printf(sc->sc_dev, 597 "%s: bf=%p, rxbuf alloc failed! error=%d\n", 598 __func__, 599 bf, 600 error); 601 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 602 return (NULL); 603 } 604 605 return (bf); 606 } 607 608 static void 609 ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf) 610 { 611 612 ATH_RX_LOCK_ASSERT(sc); 613 614 /* We're doing this multiple times? */ 615 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 616 617 if (bf->bf_m) { 618 m_freem(bf->bf_m); 619 bf->bf_m = NULL; 620 } 621 622 /* XXX lock? */ 623 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 624 } 625 626 /* 627 * Allocate up to 'n' entries and push them onto the hardware FIFO. 628 * 629 * Return how many entries were successfully pushed onto the 630 * FIFO. 631 */ 632 static int 633 ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs) 634 { 635 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 636 struct ath_buf *bf; 637 int i; 638 639 ATH_RX_LOCK_ASSERT(sc); 640 641 /* 642 * Allocate buffers until the FIFO is full or nbufs is reached. 643 */ 644 for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) { 645 /* Ensure the FIFO is already blank, complain loudly! */ 646 if (re->m_fifo[re->m_fifo_tail] != NULL) { 647 device_printf(sc->sc_dev, 648 "%s: Q%d: fifo[%d] != NULL (%p)\n", 649 __func__, 650 qtype, 651 re->m_fifo_tail, 652 re->m_fifo[re->m_fifo_tail]); 653 654 /* Free the slot */ 655 ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]); 656 re->m_fifo_depth--; 657 /* XXX check it's not < 0 */ 658 re->m_fifo[re->m_fifo_tail] = NULL; 659 } 660 661 bf = ath_edma_rxbuf_alloc(sc); 662 /* XXX should ensure the FIFO is not NULL? */ 663 if (bf == NULL) { 664 device_printf(sc->sc_dev, "%s: Q%d: alloc failed?\n", 665 __func__, 666 qtype); 667 break; 668 } 669 670 re->m_fifo[re->m_fifo_tail] = bf; 671 672 /* 673 * Flush the descriptor contents before it's handed to the 674 * hardware. 675 */ 676 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 677 BUS_DMASYNC_PREREAD); 678 679 /* Write to the RX FIFO */ 680 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: putrxbuf=%p\n", 681 __func__, 682 qtype, 683 bf->bf_desc); 684 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype); 685 686 re->m_fifo_depth++; 687 INCR(re->m_fifo_tail, re->m_fifolen); 688 } 689 690 /* 691 * Return how many were allocated. 692 */ 693 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n", 694 __func__, 695 qtype, 696 nbufs, 697 i); 698 return (i); 699 } 700 701 static int 702 ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype) 703 { 704 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 705 int i; 706 707 ATH_RX_LOCK_ASSERT(sc); 708 709 for (i = 0; i < re->m_fifolen; i++) { 710 if (re->m_fifo[i] != NULL) { 711 #ifdef ATH_DEBUG 712 struct ath_buf *bf = re->m_fifo[i]; 713 714 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 715 ath_printrxbuf(sc, bf, 0, HAL_OK); 716 #endif 717 ath_edma_rxbuf_free(sc, re->m_fifo[i]); 718 re->m_fifo[i] = NULL; 719 re->m_fifo_depth--; 720 } 721 } 722 723 if (re->m_rxpending != NULL) { 724 m_freem(re->m_rxpending); 725 re->m_rxpending = NULL; 726 } 727 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0; 728 729 return (0); 730 } 731 732 /* 733 * Setup the initial RX FIFO structure. 734 */ 735 static int 736 ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype) 737 { 738 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 739 740 ATH_RX_LOCK_ASSERT(sc); 741 742 if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) { 743 device_printf(sc->sc_dev, "%s: qtype=%d, failed\n", 744 __func__, 745 qtype); 746 return (-EINVAL); 747 } 748 device_printf(sc->sc_dev, "%s: type=%d, FIFO depth = %d entries\n", 749 __func__, 750 qtype, 751 re->m_fifolen); 752 753 /* Allocate ath_buf FIFO array, pre-zero'ed */ 754 re->m_fifo = malloc(sizeof(struct ath_buf *) * re->m_fifolen, 755 M_ATHDEV, 756 M_NOWAIT | M_ZERO); 757 if (re->m_fifo == NULL) { 758 device_printf(sc->sc_dev, "%s: malloc failed\n", 759 __func__); 760 return (-ENOMEM); 761 } 762 763 /* 764 * Set initial "empty" state. 765 */ 766 re->m_rxpending = NULL; 767 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0; 768 769 return (0); 770 } 771 772 static int 773 ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype) 774 { 775 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 776 777 device_printf(sc->sc_dev, "%s: called; qtype=%d\n", 778 __func__, 779 qtype); 780 781 free(re->m_fifo, M_ATHDEV); 782 783 return (0); 784 } 785 786 static int 787 ath_edma_dma_rxsetup(struct ath_softc *sc) 788 { 789 int error; 790 791 /* 792 * Create RX DMA tag and buffers. 793 */ 794 error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 795 "rx", ath_rxbuf, sc->sc_rx_statuslen); 796 if (error != 0) 797 return error; 798 799 ATH_RX_LOCK(sc); 800 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP); 801 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP); 802 ATH_RX_UNLOCK(sc); 803 804 return (0); 805 } 806 807 static int 808 ath_edma_dma_rxteardown(struct ath_softc *sc) 809 { 810 811 ATH_RX_LOCK(sc); 812 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP); 813 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP); 814 815 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP); 816 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP); 817 ATH_RX_UNLOCK(sc); 818 819 /* Free RX ath_buf */ 820 /* Free RX DMA tag */ 821 if (sc->sc_rxdma.dd_desc_len != 0) 822 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 823 824 return (0); 825 } 826 827 void 828 ath_recv_setup_edma(struct ath_softc *sc) 829 { 830 831 /* Set buffer size to 4k */ 832 sc->sc_edma_bufsize = 4096; 833 834 /* Fetch EDMA field and buffer sizes */ 835 (void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen); 836 837 /* Configure the hardware with the RX buffer size */ 838 (void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize - 839 sc->sc_rx_statuslen); 840 841 device_printf(sc->sc_dev, "RX status length: %d\n", 842 sc->sc_rx_statuslen); 843 device_printf(sc->sc_dev, "RX buffer size: %d\n", 844 sc->sc_edma_bufsize); 845 846 sc->sc_rx.recv_stop = ath_edma_stoprecv; 847 sc->sc_rx.recv_start = ath_edma_startrecv; 848 sc->sc_rx.recv_flush = ath_edma_recv_flush; 849 sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet; 850 sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init; 851 852 sc->sc_rx.recv_setup = ath_edma_dma_rxsetup; 853 sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown; 854 } 855