1 /*- 2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_regdomain.h> 85 #ifdef IEEE80211_SUPPORT_SUPERG 86 #include <net80211/ieee80211_superg.h> 87 #endif 88 #ifdef IEEE80211_SUPPORT_TDMA 89 #include <net80211/ieee80211_tdma.h> 90 #endif 91 92 #include <net/bpf.h> 93 94 #ifdef INET 95 #include <netinet/in.h> 96 #include <netinet/if_ether.h> 97 #endif 98 99 #include <dev/ath/if_athvar.h> 100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101 #include <dev/ath/ath_hal/ah_diagcodes.h> 102 103 #include <dev/ath/if_ath_debug.h> 104 #include <dev/ath/if_ath_misc.h> 105 #include <dev/ath/if_ath_tsf.h> 106 #include <dev/ath/if_ath_tx.h> 107 #include <dev/ath/if_ath_sysctl.h> 108 #include <dev/ath/if_ath_led.h> 109 #include <dev/ath/if_ath_keycache.h> 110 #include <dev/ath/if_ath_rx.h> 111 #include <dev/ath/if_ath_beacon.h> 112 #include <dev/ath/if_athdfs.h> 113 114 #ifdef ATH_TX99_DIAG 115 #include <dev/ath/ath_tx99/ath_tx99.h> 116 #endif 117 118 #include <dev/ath/if_ath_rx_edma.h> 119 120 /* 121 * some general macros 122 */ 123 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1) 124 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1) 125 126 MALLOC_DECLARE(M_ATHDEV); 127 128 /* 129 * XXX TODO: 130 * 131 * + Add an RX lock, just to ensure we don't have things clash; 132 * + Make sure the FIFO is correctly flushed and reinitialised 133 * through a reset; 134 * + Handle the "kickpcu" state where the FIFO overflows. 135 * + Implement a "flush" routine, which doesn't push any 136 * new frames into the FIFO. 137 * + Verify multi-descriptor frames work! 138 * + There's a "memory use after free" which needs to be tracked down 139 * and fixed ASAP. I've seen this in the legacy path too, so it 140 * may be a generic RX path issue. 141 */ 142 143 /* 144 * XXX shuffle the function orders so these pre-declarations aren't 145 * required! 146 */ 147 static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, 148 int nbufs); 149 static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype); 150 static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf); 151 static int ath_edma_recv_proc_queue(struct ath_softc *sc, 152 HAL_RX_QUEUE qtype, int dosched); 153 154 static void 155 ath_edma_stoprecv(struct ath_softc *sc, int dodelay) 156 { 157 struct ath_hal *ah = sc->sc_ah; 158 159 ATH_RX_LOCK(sc); 160 ath_hal_stoppcurecv(ah); 161 ath_hal_setrxfilter(ah, 0); 162 ath_hal_stopdmarecv(ah); 163 164 DELAY(3000); 165 166 /* Flush RX pending for each queue */ 167 /* XXX should generic-ify this */ 168 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) { 169 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 170 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 171 } 172 173 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) { 174 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 175 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 176 } 177 ATH_RX_UNLOCK(sc); 178 } 179 180 /* 181 * Re-initialise the FIFO given the current buffer contents. 182 * Specifically, walk from head -> tail, pushing the FIFO contents 183 * back into the FIFO. 184 */ 185 static void 186 ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype) 187 { 188 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 189 struct ath_buf *bf; 190 int i, j; 191 192 ATH_RX_LOCK_ASSERT(sc); 193 194 i = re->m_fifo_head; 195 for (j = 0; j < re->m_fifo_depth; j++) { 196 bf = re->m_fifo[i]; 197 DPRINTF(sc, ATH_DEBUG_EDMA_RX, 198 "%s: Q%d: pos=%i, addr=0x%jx\n", 199 __func__, 200 qtype, 201 i, 202 (uintmax_t)bf->bf_daddr); 203 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype); 204 INCR(i, re->m_fifolen); 205 } 206 207 /* Ensure this worked out right */ 208 if (i != re->m_fifo_tail) { 209 device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n", 210 __func__, 211 i, 212 re->m_fifo_tail); 213 } 214 } 215 216 /* 217 * Start receive. 218 * 219 * XXX TODO: this needs to reallocate the FIFO entries when a reset 220 * occurs, in case the FIFO is filled up and no new descriptors get 221 * thrown into the FIFO. 222 */ 223 static int 224 ath_edma_startrecv(struct ath_softc *sc) 225 { 226 struct ath_hal *ah = sc->sc_ah; 227 228 ATH_RX_LOCK(sc); 229 230 /* Enable RX FIFO */ 231 ath_hal_rxena(ah); 232 233 /* 234 * Entries should only be written out if the 235 * FIFO is empty. 236 * 237 * XXX This isn't correct. I should be looking 238 * at the value of AR_RXDP_SIZE (0x0070) to determine 239 * how many entries are in here. 240 * 241 * A warm reset will clear the registers but not the FIFO. 242 * 243 * And I believe this is actually the address of the last 244 * handled buffer rather than the current FIFO pointer. 245 * So if no frames have been (yet) seen, we'll reinit the 246 * FIFO. 247 * 248 * I'll chase that up at some point. 249 */ 250 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) { 251 DPRINTF(sc, ATH_DEBUG_EDMA_RX, 252 "%s: Re-initing HP FIFO\n", __func__); 253 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP); 254 } 255 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_LP) == 0) { 256 DPRINTF(sc, ATH_DEBUG_EDMA_RX, 257 "%s: Re-initing LP FIFO\n", __func__); 258 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP); 259 } 260 261 /* Add up to m_fifolen entries in each queue */ 262 /* 263 * These must occur after the above write so the FIFO buffers 264 * are pushed/tracked in the same order as the hardware will 265 * process them. 266 */ 267 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP, 268 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen); 269 270 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP, 271 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen); 272 273 ath_mode_init(sc); 274 ath_hal_startpcurecv(ah); 275 276 ATH_RX_UNLOCK(sc); 277 278 return (0); 279 } 280 281 static void 282 ath_edma_recv_flush(struct ath_softc *sc) 283 { 284 285 device_printf(sc->sc_dev, "%s: called\n", __func__); 286 287 ATH_PCU_LOCK(sc); 288 sc->sc_rxproc_cnt++; 289 ATH_PCU_UNLOCK(sc); 290 291 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0); 292 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0); 293 294 ATH_PCU_LOCK(sc); 295 sc->sc_rxproc_cnt--; 296 ATH_PCU_UNLOCK(sc); 297 } 298 299 /* 300 * Process frames from the current queue. 301 * 302 * TODO: 303 * 304 * + Add a "dosched" flag, so we don't reschedule any FIFO frames 305 * to the hardware or re-kick the PCU after 'kickpcu' is set. 306 * 307 * + Perhaps split "check FIFO contents" and "handle frames", so 308 * we can run the "check FIFO contents" in ath_intr(), but 309 * "handle frames" in the RX tasklet. 310 */ 311 static int 312 ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype, 313 int dosched) 314 { 315 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 316 struct ath_rx_status *rs; 317 struct ath_desc *ds; 318 struct ath_buf *bf; 319 struct mbuf *m; 320 struct ath_hal *ah = sc->sc_ah; 321 uint64_t tsf; 322 int16_t nf; 323 int ngood = 0, npkts = 0; 324 ath_bufhead rxlist; 325 struct ath_buf *next; 326 327 TAILQ_INIT(&rxlist); 328 329 tsf = ath_hal_gettsf64(ah); 330 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 331 sc->sc_stats.ast_rx_noise = nf; 332 333 ATH_RX_LOCK(sc); 334 335 do { 336 bf = re->m_fifo[re->m_fifo_head]; 337 /* This shouldn't occur! */ 338 if (bf == NULL) { 339 device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n", 340 __func__, 341 qtype); 342 break; 343 } 344 m = bf->bf_m; 345 ds = bf->bf_desc; 346 347 /* 348 * Sync descriptor memory - this also syncs the buffer for us. 349 * 350 * EDMA descriptors are in cached memory. 351 */ 352 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 353 BUS_DMASYNC_POSTREAD); 354 rs = &bf->bf_status.ds_rxstat; 355 bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr, 356 NULL, rs); 357 #ifdef ATH_DEBUG 358 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 359 ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK); 360 #endif 361 if (bf->bf_rxstatus == HAL_EINPROGRESS) 362 break; 363 364 /* 365 * Completed descriptor. 366 * 367 * In the future we'll call ath_rx_pkt(), but it first 368 * has to be taught about EDMA RX queues (so it can 369 * access sc_rxpending correctly.) 370 */ 371 DPRINTF(sc, ATH_DEBUG_EDMA_RX, 372 "%s: Q%d: completed!\n", __func__, qtype); 373 npkts++; 374 375 /* 376 * Remove the FIFO entry and place it on the completion 377 * queue. 378 */ 379 re->m_fifo[re->m_fifo_head] = NULL; 380 TAILQ_INSERT_TAIL(&rxlist, bf, bf_list); 381 382 /* Bump the descriptor FIFO stats */ 383 INCR(re->m_fifo_head, re->m_fifolen); 384 re->m_fifo_depth--; 385 /* XXX check it doesn't fall below 0 */ 386 } while (re->m_fifo_depth > 0); 387 388 /* Append some more fresh frames to the FIFO */ 389 if (dosched) 390 ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen); 391 392 ATH_RX_UNLOCK(sc); 393 394 /* Handle the completed descriptors */ 395 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) { 396 /* 397 * Skip the RX descriptor status - start at the data offset 398 */ 399 m_adj(bf->bf_m, sc->sc_rx_statuslen); 400 401 /* Handle the frame */ 402 /* 403 * Note: this may or may not free bf->bf_m and sync/unmap 404 * the frame. 405 */ 406 rs = &bf->bf_status.ds_rxstat; 407 if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf)) 408 ngood++; 409 } 410 411 /* Free in one set, inside the lock */ 412 ATH_RX_LOCK(sc); 413 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) { 414 /* Free the buffer/mbuf */ 415 ath_edma_rxbuf_free(sc, bf); 416 } 417 ATH_RX_UNLOCK(sc); 418 419 /* rx signal state monitoring */ 420 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 421 if (ngood) 422 sc->sc_lastrx = tsf; 423 424 CTR2(ATH_KTR_INTR, "ath edma rx proc: npkts=%d, ngood=%d", 425 npkts, ngood); 426 427 /* Handle resched and kickpcu appropriately */ 428 ATH_PCU_LOCK(sc); 429 if (dosched && sc->sc_kickpcu) { 430 CTR0(ATH_KTR_ERR, "ath_edma_recv_proc_queue(): kickpcu"); 431 device_printf(sc->sc_dev, 432 "%s: handled npkts %d ngood %d\n", 433 __func__, npkts, ngood); 434 435 /* 436 * XXX TODO: what should occur here? Just re-poke and 437 * re-enable the RX FIFO? 438 */ 439 sc->sc_kickpcu = 0; 440 } 441 ATH_PCU_UNLOCK(sc); 442 443 return (ngood); 444 } 445 446 static void 447 ath_edma_recv_tasklet(void *arg, int npending) 448 { 449 struct ath_softc *sc = (struct ath_softc *) arg; 450 struct ifnet *ifp = sc->sc_ifp; 451 #ifdef IEEE80211_SUPPORT_SUPERG 452 struct ieee80211com *ic = ifp->if_l2com; 453 #endif 454 455 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n", 456 __func__, 457 npending); 458 459 ATH_PCU_LOCK(sc); 460 if (sc->sc_inreset_cnt > 0) { 461 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n", 462 __func__); 463 ATH_PCU_UNLOCK(sc); 464 return; 465 } 466 sc->sc_rxproc_cnt++; 467 ATH_PCU_UNLOCK(sc); 468 469 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1); 470 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1); 471 472 /* XXX inside IF_LOCK ? */ 473 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 474 #ifdef IEEE80211_SUPPORT_SUPERG 475 ieee80211_ff_age_all(ic, 100); 476 #endif 477 if (! IFQ_IS_EMPTY(&ifp->if_snd)) 478 ath_tx_kick(sc); 479 } 480 if (ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 481 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 482 483 ATH_PCU_LOCK(sc); 484 sc->sc_rxproc_cnt--; 485 ATH_PCU_UNLOCK(sc); 486 } 487 488 /* 489 * Allocate an RX mbuf for the given ath_buf and initialise 490 * it for EDMA. 491 * 492 * + Allocate a 4KB mbuf; 493 * + Setup the DMA map for the given buffer; 494 * + Keep a pointer to the start of the mbuf - that's where the 495 * descriptor lies; 496 * + Take a pointer to the start of the RX buffer, set the 497 * mbuf "start" to be there; 498 * + Return that. 499 */ 500 static int 501 ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 502 { 503 504 struct mbuf *m; 505 int error; 506 int len; 507 508 ATH_RX_LOCK_ASSERT(sc); 509 510 m = m_getm(NULL, sc->sc_edma_bufsize, M_DONTWAIT, MT_DATA); 511 if (! m) 512 return (ENOBUFS); /* XXX ?*/ 513 514 /* XXX warn/enforce alignment */ 515 516 len = m->m_ext.ext_size; 517 #if 0 518 device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n", 519 __func__, 520 m, 521 len, 522 mtod(m, char *)); 523 #endif 524 525 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 526 527 /* 528 * Create DMA mapping. 529 */ 530 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 531 bf->bf_dmamap, m, bf->bf_segs, &bf->bf_nseg, BUS_DMA_NOWAIT); 532 if (error != 0) { 533 device_printf(sc->sc_dev, "%s: failed; error=%d\n", 534 __func__, 535 error); 536 m_freem(m); 537 return (error); 538 } 539 540 /* 541 * Populate ath_buf fields. 542 */ 543 544 bf->bf_desc = mtod(m, struct ath_desc *); 545 bf->bf_daddr = bf->bf_segs[0].ds_addr; 546 bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */ 547 bf->bf_m = m; 548 549 /* Zero the descriptor */ 550 memset(bf->bf_desc, '\0', sc->sc_rx_statuslen); 551 552 #if 0 553 /* 554 * Adjust mbuf header and length/size to compensate for the 555 * descriptor size. 556 */ 557 m_adj(m, sc->sc_rx_statuslen); 558 #endif 559 560 /* Finish! */ 561 562 return (0); 563 } 564 565 static struct ath_buf * 566 ath_edma_rxbuf_alloc(struct ath_softc *sc) 567 { 568 struct ath_buf *bf; 569 int error; 570 571 ATH_RX_LOCK_ASSERT(sc); 572 573 /* Allocate buffer */ 574 bf = TAILQ_FIRST(&sc->sc_rxbuf); 575 /* XXX shouldn't happen upon startup? */ 576 if (bf == NULL) 577 return (NULL); 578 579 /* Remove it from the free list */ 580 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 581 582 /* Assign RX mbuf to it */ 583 error = ath_edma_rxbuf_init(sc, bf); 584 if (error != 0) { 585 device_printf(sc->sc_dev, 586 "%s: bf=%p, rxbuf alloc failed! error=%d\n", 587 __func__, 588 bf, 589 error); 590 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 591 return (NULL); 592 } 593 594 return (bf); 595 } 596 597 static void 598 ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf) 599 { 600 601 ATH_RX_LOCK_ASSERT(sc); 602 603 /* We're doing this multiple times? */ 604 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 605 606 if (bf->bf_m) { 607 m_freem(bf->bf_m); 608 bf->bf_m = NULL; 609 } 610 611 /* XXX lock? */ 612 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 613 } 614 615 /* 616 * Allocate up to 'n' entries and push them onto the hardware FIFO. 617 * 618 * Return how many entries were successfully pushed onto the 619 * FIFO. 620 */ 621 static int 622 ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs) 623 { 624 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 625 struct ath_buf *bf; 626 int i; 627 628 ATH_RX_LOCK_ASSERT(sc); 629 630 /* 631 * Allocate buffers until the FIFO is full or nbufs is reached. 632 */ 633 for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) { 634 /* Ensure the FIFO is already blank, complain loudly! */ 635 if (re->m_fifo[re->m_fifo_tail] != NULL) { 636 device_printf(sc->sc_dev, 637 "%s: Q%d: fifo[%d] != NULL (%p)\n", 638 __func__, 639 qtype, 640 re->m_fifo_tail, 641 re->m_fifo[re->m_fifo_tail]); 642 643 /* Free the slot */ 644 ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]); 645 re->m_fifo_depth--; 646 /* XXX check it's not < 0 */ 647 re->m_fifo[re->m_fifo_tail] = NULL; 648 } 649 650 bf = ath_edma_rxbuf_alloc(sc); 651 /* XXX should ensure the FIFO is not NULL? */ 652 if (bf == NULL) { 653 device_printf(sc->sc_dev, "%s: Q%d: alloc failed?\n", 654 __func__, 655 qtype); 656 break; 657 } 658 659 re->m_fifo[re->m_fifo_tail] = bf; 660 661 /* 662 * Flush the descriptor contents before it's handed to the 663 * hardware. 664 */ 665 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 666 BUS_DMASYNC_PREREAD); 667 668 /* Write to the RX FIFO */ 669 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: putrxbuf=%p\n", 670 __func__, 671 qtype, 672 bf->bf_desc); 673 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype); 674 675 re->m_fifo_depth++; 676 INCR(re->m_fifo_tail, re->m_fifolen); 677 } 678 679 /* 680 * Return how many were allocated. 681 */ 682 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n", 683 __func__, 684 qtype, 685 nbufs, 686 i); 687 return (i); 688 } 689 690 static int 691 ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype) 692 { 693 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 694 int i; 695 696 ATH_RX_LOCK_ASSERT(sc); 697 698 for (i = 0; i < re->m_fifolen; i++) { 699 if (re->m_fifo[i] != NULL) { 700 #ifdef ATH_DEBUG 701 struct ath_buf *bf = re->m_fifo[i]; 702 703 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 704 ath_printrxbuf(sc, bf, 0, HAL_OK); 705 #endif 706 ath_edma_rxbuf_free(sc, re->m_fifo[i]); 707 re->m_fifo[i] = NULL; 708 re->m_fifo_depth--; 709 } 710 } 711 712 if (re->m_rxpending != NULL) { 713 m_freem(re->m_rxpending); 714 re->m_rxpending = NULL; 715 } 716 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0; 717 718 return (0); 719 } 720 721 /* 722 * Setup the initial RX FIFO structure. 723 */ 724 static int 725 ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype) 726 { 727 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 728 729 ATH_RX_LOCK_ASSERT(sc); 730 731 if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) { 732 device_printf(sc->sc_dev, "%s: qtype=%d, failed\n", 733 __func__, 734 qtype); 735 return (-EINVAL); 736 } 737 device_printf(sc->sc_dev, "%s: type=%d, FIFO depth = %d entries\n", 738 __func__, 739 qtype, 740 re->m_fifolen); 741 742 /* Allocate ath_buf FIFO array, pre-zero'ed */ 743 re->m_fifo = malloc(sizeof(struct ath_buf *) * re->m_fifolen, 744 M_ATHDEV, 745 M_NOWAIT | M_ZERO); 746 if (re->m_fifo == NULL) { 747 device_printf(sc->sc_dev, "%s: malloc failed\n", 748 __func__); 749 return (-ENOMEM); 750 } 751 752 /* 753 * Set initial "empty" state. 754 */ 755 re->m_rxpending = NULL; 756 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0; 757 758 return (0); 759 } 760 761 static int 762 ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype) 763 { 764 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 765 766 device_printf(sc->sc_dev, "%s: called; qtype=%d\n", 767 __func__, 768 qtype); 769 770 free(re->m_fifo, M_ATHDEV); 771 772 return (0); 773 } 774 775 static int 776 ath_edma_dma_rxsetup(struct ath_softc *sc) 777 { 778 int error; 779 780 /* 781 * Create RX DMA tag and buffers. 782 */ 783 error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 784 "rx", ath_rxbuf, sc->sc_rx_statuslen); 785 if (error != 0) 786 return error; 787 788 ATH_RX_LOCK(sc); 789 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP); 790 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP); 791 ATH_RX_UNLOCK(sc); 792 793 return (0); 794 } 795 796 static int 797 ath_edma_dma_rxteardown(struct ath_softc *sc) 798 { 799 800 ATH_RX_LOCK(sc); 801 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP); 802 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP); 803 804 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP); 805 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP); 806 ATH_RX_UNLOCK(sc); 807 808 /* Free RX ath_buf */ 809 /* Free RX DMA tag */ 810 if (sc->sc_rxdma.dd_desc_len != 0) 811 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 812 813 return (0); 814 } 815 816 void 817 ath_recv_setup_edma(struct ath_softc *sc) 818 { 819 820 /* Set buffer size to 4k */ 821 sc->sc_edma_bufsize = 4096; 822 823 /* Fetch EDMA field and buffer sizes */ 824 (void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen); 825 826 /* Configure the hardware with the RX buffer size */ 827 (void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize - 828 sc->sc_rx_statuslen); 829 830 device_printf(sc->sc_dev, "RX status length: %d\n", 831 sc->sc_rx_statuslen); 832 device_printf(sc->sc_dev, "RX buffer size: %d\n", 833 sc->sc_edma_bufsize); 834 835 sc->sc_rx.recv_stop = ath_edma_stoprecv; 836 sc->sc_rx.recv_start = ath_edma_startrecv; 837 sc->sc_rx.recv_flush = ath_edma_recv_flush; 838 sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet; 839 sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init; 840 841 sc->sc_rx.recv_setup = ath_edma_dma_rxsetup; 842 sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown; 843 } 844