1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42 #include "opt_inet.h" 43 #include "opt_ath.h" 44 /* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51 #include "opt_ah.h" 52 #include "opt_wlan.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysctl.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/kernel.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 #include <sys/errno.h> 65 #include <sys/callout.h> 66 #include <sys/bus.h> 67 #include <sys/endian.h> 68 #include <sys/kthread.h> 69 #include <sys/taskqueue.h> 70 #include <sys/priv.h> 71 #include <sys/module.h> 72 #include <sys/ktr.h> 73 #include <sys/smp.h> /* for mp_ncpus */ 74 75 #include <machine/bus.h> 76 77 #include <net/if.h> 78 #include <net/if_var.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_var.h> 87 #include <net80211/ieee80211_regdomain.h> 88 #ifdef IEEE80211_SUPPORT_SUPERG 89 #include <net80211/ieee80211_superg.h> 90 #endif 91 #ifdef IEEE80211_SUPPORT_TDMA 92 #include <net80211/ieee80211_tdma.h> 93 #endif 94 95 #include <net/bpf.h> 96 97 #ifdef INET 98 #include <netinet/in.h> 99 #include <netinet/if_ether.h> 100 #endif 101 102 #include <dev/ath/if_athvar.h> 103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 104 #include <dev/ath/ath_hal/ah_diagcodes.h> 105 106 #include <dev/ath/if_ath_debug.h> 107 #include <dev/ath/if_ath_misc.h> 108 #include <dev/ath/if_ath_tsf.h> 109 #include <dev/ath/if_ath_tx.h> 110 #include <dev/ath/if_ath_sysctl.h> 111 #include <dev/ath/if_ath_led.h> 112 #include <dev/ath/if_ath_keycache.h> 113 #include <dev/ath/if_ath_rx.h> 114 #include <dev/ath/if_ath_beacon.h> 115 #include <dev/ath/if_athdfs.h> 116 #include <dev/ath/if_ath_descdma.h> 117 118 #ifdef ATH_TX99_DIAG 119 #include <dev/ath/ath_tx99/ath_tx99.h> 120 #endif 121 122 #ifdef ATH_DEBUG_ALQ 123 #include <dev/ath/if_ath_alq.h> 124 #endif 125 126 #include <dev/ath/if_ath_lna_div.h> 127 128 /* 129 * Calculate the receive filter according to the 130 * operating mode and state: 131 * 132 * o always accept unicast, broadcast, and multicast traffic 133 * o accept PHY error frames when hardware doesn't have MIB support 134 * to count and we need them for ANI (sta mode only until recently) 135 * and we are not scanning (ANI is disabled) 136 * NB: older hal's add rx filter bits out of sight and we need to 137 * blindly preserve them 138 * o probe request frames are accepted only when operating in 139 * hostap, adhoc, mesh, or monitor modes 140 * o enable promiscuous mode 141 * - when in monitor mode 142 * - if interface marked PROMISC (assumes bridge setting is filtered) 143 * o accept beacons: 144 * - when operating in station mode for collecting rssi data when 145 * the station is otherwise quiet, or 146 * - when operating in adhoc mode so the 802.11 layer creates 147 * node table entries for peers, 148 * - when scanning 149 * - when doing s/w beacon miss (e.g. for ap+sta) 150 * - when operating in ap mode in 11g to detect overlapping bss that 151 * require protection 152 * - when operating in mesh mode to detect neighbors 153 * o accept control frames: 154 * - when in monitor mode 155 * XXX HT protection for 11n 156 */ 157 u_int32_t 158 ath_calcrxfilter(struct ath_softc *sc) 159 { 160 struct ieee80211com *ic = &sc->sc_ic; 161 u_int32_t rfilt; 162 163 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 164 if (!sc->sc_needmib && !sc->sc_scanning) 165 rfilt |= HAL_RX_FILTER_PHYERR; 166 if (ic->ic_opmode != IEEE80211_M_STA) 167 rfilt |= HAL_RX_FILTER_PROBEREQ; 168 /* XXX ic->ic_monvaps != 0? */ 169 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0) 170 rfilt |= HAL_RX_FILTER_PROM; 171 172 /* 173 * Only listen to all beacons if we're scanning. 174 * 175 * Otherwise we only really need to hear beacons from 176 * our own BSSID. 177 * 178 * IBSS? software beacon miss? Just receive all beacons. 179 * We need to hear beacons/probe requests from everyone so 180 * we can merge ibss. 181 */ 182 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 183 rfilt |= HAL_RX_FILTER_BEACON; 184 } else if (ic->ic_opmode == IEEE80211_M_STA) { 185 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 186 rfilt |= HAL_RX_FILTER_MYBEACON; 187 } else { /* scanning, non-mybeacon chips */ 188 rfilt |= HAL_RX_FILTER_BEACON; 189 } 190 } 191 192 /* 193 * NB: We don't recalculate the rx filter when 194 * ic_protmode changes; otherwise we could do 195 * this only when ic_protmode != NONE. 196 */ 197 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 198 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 199 rfilt |= HAL_RX_FILTER_BEACON; 200 201 /* 202 * Enable hardware PS-POLL RX only for hostap mode; 203 * STA mode sends PS-POLL frames but never 204 * receives them. 205 */ 206 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 207 0, NULL) == HAL_OK && 208 ic->ic_opmode == IEEE80211_M_HOSTAP) 209 rfilt |= HAL_RX_FILTER_PSPOLL; 210 211 if (sc->sc_nmeshvaps) { 212 rfilt |= HAL_RX_FILTER_BEACON; 213 if (sc->sc_hasbmatch) 214 rfilt |= HAL_RX_FILTER_BSSID; 215 else 216 rfilt |= HAL_RX_FILTER_PROM; 217 } 218 if (ic->ic_opmode == IEEE80211_M_MONITOR) 219 rfilt |= HAL_RX_FILTER_CONTROL; 220 221 /* 222 * Enable RX of compressed BAR frames only when doing 223 * 802.11n. Required for A-MPDU. 224 */ 225 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 226 rfilt |= HAL_RX_FILTER_COMPBAR; 227 228 /* 229 * Enable radar PHY errors if requested by the 230 * DFS module. 231 */ 232 if (sc->sc_dodfs) 233 rfilt |= HAL_RX_FILTER_PHYRADAR; 234 235 /* 236 * Enable spectral PHY errors if requested by the 237 * spectral module. 238 */ 239 if (sc->sc_dospectral) 240 rfilt |= HAL_RX_FILTER_PHYRADAR; 241 242 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n", 243 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]); 244 return rfilt; 245 } 246 247 static int 248 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 249 { 250 struct ath_hal *ah = sc->sc_ah; 251 int error; 252 struct mbuf *m; 253 struct ath_desc *ds; 254 255 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 256 257 m = bf->bf_m; 258 if (m == NULL) { 259 /* 260 * NB: by assigning a page to the rx dma buffer we 261 * implicitly satisfy the Atheros requirement that 262 * this buffer be cache-line-aligned and sized to be 263 * multiple of the cache line size. Not doing this 264 * causes weird stuff to happen (for the 5210 at least). 265 */ 266 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 267 if (m == NULL) { 268 DPRINTF(sc, ATH_DEBUG_ANY, 269 "%s: no mbuf/cluster\n", __func__); 270 sc->sc_stats.ast_rx_nombuf++; 271 return ENOMEM; 272 } 273 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 274 275 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 276 bf->bf_dmamap, m, 277 bf->bf_segs, &bf->bf_nseg, 278 BUS_DMA_NOWAIT); 279 if (error != 0) { 280 DPRINTF(sc, ATH_DEBUG_ANY, 281 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 282 __func__, error); 283 sc->sc_stats.ast_rx_busdma++; 284 m_freem(m); 285 return error; 286 } 287 KASSERT(bf->bf_nseg == 1, 288 ("multi-segment packet; nseg %u", bf->bf_nseg)); 289 bf->bf_m = m; 290 } 291 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 292 293 /* 294 * Setup descriptors. For receive we always terminate 295 * the descriptor list with a self-linked entry so we'll 296 * not get overrun under high load (as can happen with a 297 * 5212 when ANI processing enables PHY error frames). 298 * 299 * To insure the last descriptor is self-linked we create 300 * each descriptor as self-linked and add it to the end. As 301 * each additional descriptor is added the previous self-linked 302 * entry is ``fixed'' naturally. This should be safe even 303 * if DMA is happening. When processing RX interrupts we 304 * never remove/process the last, self-linked, entry on the 305 * descriptor list. This insures the hardware always has 306 * someplace to write a new frame. 307 */ 308 /* 309 * 11N: we can no longer afford to self link the last descriptor. 310 * MAC acknowledges BA status as long as it copies frames to host 311 * buffer (or rx fifo). This can incorrectly acknowledge packets 312 * to a sender if last desc is self-linked. 313 */ 314 ds = bf->bf_desc; 315 if (sc->sc_rxslink) 316 ds->ds_link = bf->bf_daddr; /* link to self */ 317 else 318 ds->ds_link = 0; /* terminate the list */ 319 ds->ds_data = bf->bf_segs[0].ds_addr; 320 ath_hal_setuprxdesc(ah, ds 321 , m->m_len /* buffer size */ 322 , 0 323 ); 324 325 if (sc->sc_rxlink != NULL) 326 *sc->sc_rxlink = bf->bf_daddr; 327 sc->sc_rxlink = &ds->ds_link; 328 return 0; 329 } 330 331 /* 332 * Intercept management frames to collect beacon rssi data 333 * and to do ibss merges. 334 */ 335 void 336 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 337 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) 338 { 339 struct ieee80211vap *vap = ni->ni_vap; 340 struct ath_softc *sc = vap->iv_ic->ic_softc; 341 uint64_t tsf_beacon_old, tsf_beacon; 342 uint64_t nexttbtt; 343 int64_t tsf_delta; 344 int32_t tsf_delta_bmiss; 345 int32_t tsf_remainder; 346 uint64_t tsf_beacon_target; 347 int tsf_intval; 348 349 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 350 tsf_beacon_old |= le32dec(ni->ni_tstamp.data); 351 352 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 353 tsf_intval = 1; 354 if (ni->ni_intval > 0) { 355 tsf_intval = TU_TO_TSF(ni->ni_intval); 356 } 357 #undef TU_TO_TSF 358 359 /* 360 * Call up first so subsequent work can use information 361 * potentially stored in the node (e.g. for ibss merge). 362 */ 363 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf); 364 switch (subtype) { 365 case IEEE80211_FC0_SUBTYPE_BEACON: 366 /* 367 * Always update the per-node beacon RSSI if we're hearing 368 * beacons from that node. 369 */ 370 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgbrssi, rssi); 371 372 /* 373 * Only do the following processing if it's for 374 * the current BSS. 375 * 376 * In scan and IBSS mode we receive all beacons, 377 * which means we need to filter out stuff 378 * that isn't for us or we'll end up constantly 379 * trying to sync / merge to BSSes that aren't 380 * actually us. 381 */ 382 if (IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) { 383 /* update rssi statistics for use by the hal */ 384 /* XXX unlocked check against vap->iv_bss? */ 385 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 386 387 388 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 389 tsf_beacon |= le32dec(ni->ni_tstamp.data); 390 391 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 392 393 /* 394 * Let's calculate the delta and remainder, so we can see 395 * if the beacon timer from the AP is varying by more than 396 * a few TU. (Which would be a huge, huge problem.) 397 */ 398 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 399 400 tsf_delta_bmiss = tsf_delta / tsf_intval; 401 402 /* 403 * If our delta is greater than half the beacon interval, 404 * let's round the bmiss value up to the next beacon 405 * interval. Ie, we're running really, really early 406 * on the next beacon. 407 */ 408 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 409 tsf_delta_bmiss ++; 410 411 tsf_beacon_target = tsf_beacon_old + 412 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 413 414 /* 415 * The remainder using '%' is between 0 .. intval-1. 416 * If we're actually running too fast, then the remainder 417 * will be some large number just under intval-1. 418 * So we need to look at whether we're running 419 * before or after the target beacon interval 420 * and if we are, modify how we do the remainder 421 * calculation. 422 */ 423 if (tsf_beacon < tsf_beacon_target) { 424 tsf_remainder = 425 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 426 } else { 427 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 428 } 429 430 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu (%u), new_tsf=%llu (%u), target_tsf=%llu (%u), delta=%lld, bmiss=%d, remainder=%d\n", 431 __func__, 432 (unsigned long long) tsf_beacon_old, 433 (unsigned int) (tsf_beacon_old >> 10), 434 (unsigned long long) tsf_beacon, 435 (unsigned int ) (tsf_beacon >> 10), 436 (unsigned long long) tsf_beacon_target, 437 (unsigned int) (tsf_beacon_target >> 10), 438 (long long) tsf_delta, 439 tsf_delta_bmiss, 440 tsf_remainder); 441 442 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu (%u), nexttbtt=%llu (%u), delta=%d\n", 443 __func__, 444 (unsigned long long) tsf_beacon, 445 (unsigned int) (tsf_beacon >> 10), 446 (unsigned long long) nexttbtt, 447 (unsigned int) (nexttbtt >> 10), 448 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 449 450 /* We only do syncbeacon on STA VAPs; not on IBSS */ 451 if (vap->iv_opmode == IEEE80211_M_STA && 452 sc->sc_syncbeacon && 453 ni == vap->iv_bss && 454 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 455 DPRINTF(sc, ATH_DEBUG_BEACON, 456 "%s: syncbeacon=1; syncing\n", 457 __func__); 458 /* 459 * Resync beacon timers using the tsf of the beacon 460 * frame we just received. 461 */ 462 ath_beacon_config(sc, vap); 463 sc->sc_syncbeacon = 0; 464 } 465 } 466 467 /* fall thru... */ 468 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 469 if (vap->iv_opmode == IEEE80211_M_IBSS && 470 vap->iv_state == IEEE80211_S_RUN && 471 ieee80211_ibss_merge_check(ni)) { 472 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 473 uint64_t tsf = ath_extend_tsf(sc, rstamp, 474 ath_hal_gettsf64(sc->sc_ah)); 475 /* 476 * Handle ibss merge as needed; check the tsf on the 477 * frame before attempting the merge. The 802.11 spec 478 * says the station should change it's bssid to match 479 * the oldest station with the same ssid, where oldest 480 * is determined by the tsf. Note that hardware 481 * reconfiguration happens through callback to 482 * ath_newstate as the state machine will go from 483 * RUN -> RUN when this happens. 484 */ 485 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 486 DPRINTF(sc, ATH_DEBUG_STATE, 487 "ibss merge, rstamp %u tsf %ju " 488 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 489 (uintmax_t)ni->ni_tstamp.tsf); 490 (void) ieee80211_ibss_merge(ni); 491 } 492 } 493 break; 494 } 495 } 496 497 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 498 static void 499 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m, 500 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 501 { 502 503 /* Fill in the extension bitmap */ 504 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 505 506 /* Fill in the vendor header */ 507 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 508 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 509 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 510 511 /* XXX what should this be? */ 512 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 513 sc->sc_rx_th.wr_vh.vh_skip_len = 514 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 515 516 /* General version info */ 517 sc->sc_rx_th.wr_v.vh_version = 1; 518 519 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 520 521 /* rssi */ 522 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 523 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 524 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 525 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 526 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 527 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 528 529 /* evm */ 530 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 531 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 532 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 533 /* These are only populated from the AR9300 or later */ 534 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 535 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 536 537 /* direction */ 538 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 539 540 /* RX rate */ 541 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 542 543 /* RX flags */ 544 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 545 546 if (rs->rs_isaggr) 547 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 548 if (rs->rs_moreaggr) 549 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 550 551 /* phyerr info */ 552 if (rs->rs_status & HAL_RXERR_PHY) { 553 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 554 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 555 } else { 556 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 557 } 558 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 559 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 560 } 561 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 562 563 static void 564 ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 565 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 566 { 567 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 568 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 569 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 570 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 571 const HAL_RATE_TABLE *rt; 572 uint8_t rix; 573 574 rt = sc->sc_currates; 575 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 576 rix = rt->rateCodeToIndex[rs->rs_rate]; 577 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 578 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 579 580 /* 802.11 specific flags */ 581 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 582 if (rs->rs_status & HAL_RXERR_PHY) { 583 /* 584 * PHY error - make sure the channel flags 585 * reflect the actual channel configuration, 586 * not the received frame. 587 */ 588 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 589 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 590 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 591 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 592 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 593 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 594 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 595 struct ieee80211com *ic = &sc->sc_ic; 596 597 if ((rs->rs_flags & HAL_RX_2040) == 0) 598 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 599 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 600 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 601 else 602 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 603 604 if (rs->rs_flags & HAL_RX_GI) 605 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 606 } 607 608 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 609 if (rs->rs_status & HAL_RXERR_CRC) 610 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 611 /* XXX propagate other error flags from descriptor */ 612 sc->sc_rx_th.wr_antnoise = nf; 613 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 614 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 615 #undef CHAN_HT 616 #undef CHAN_HT20 617 #undef CHAN_HT40U 618 #undef CHAN_HT40D 619 } 620 621 static void 622 ath_handle_micerror(struct ieee80211com *ic, 623 struct ieee80211_frame *wh, int keyix) 624 { 625 struct ieee80211_node *ni; 626 627 /* XXX recheck MIC to deal w/ chips that lie */ 628 /* XXX discard MIC errors on !data frames */ 629 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 630 if (ni != NULL) { 631 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 632 ieee80211_free_node(ni); 633 } 634 } 635 636 /* 637 * Process a single packet. 638 * 639 * The mbuf must already be synced, unmapped and removed from bf->bf_m 640 * by this stage. 641 * 642 * The mbuf must be consumed by this routine - either passed up the 643 * net80211 stack, put on the holding queue, or freed. 644 */ 645 int 646 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 647 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 648 struct mbuf *m) 649 { 650 uint64_t rstamp; 651 /* XXX TODO: make this an mbuf tag? */ 652 struct ieee80211_rx_stats rxs; 653 int len, type, i; 654 struct ieee80211com *ic = &sc->sc_ic; 655 struct ieee80211_node *ni; 656 int is_good = 0; 657 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 658 659 /* 660 * Calculate the correct 64 bit TSF given 661 * the TSF64 register value and rs_tstamp. 662 */ 663 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 664 665 /* 802.11 return codes - These aren't specifically errors */ 666 if (rs->rs_flags & HAL_RX_GI) 667 sc->sc_stats.ast_rx_halfgi++; 668 if (rs->rs_flags & HAL_RX_2040) 669 sc->sc_stats.ast_rx_2040++; 670 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 671 sc->sc_stats.ast_rx_pre_crc_err++; 672 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 673 sc->sc_stats.ast_rx_post_crc_err++; 674 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 675 sc->sc_stats.ast_rx_decrypt_busy_err++; 676 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 677 sc->sc_stats.ast_rx_hi_rx_chain++; 678 if (rs->rs_flags & HAL_RX_STBC) 679 sc->sc_stats.ast_rx_stbc++; 680 681 if (rs->rs_status != 0) { 682 if (rs->rs_status & HAL_RXERR_CRC) 683 sc->sc_stats.ast_rx_crcerr++; 684 if (rs->rs_status & HAL_RXERR_FIFO) 685 sc->sc_stats.ast_rx_fifoerr++; 686 if (rs->rs_status & HAL_RXERR_PHY) { 687 sc->sc_stats.ast_rx_phyerr++; 688 /* Process DFS radar events */ 689 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 690 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 691 /* Now pass it to the radar processing code */ 692 ath_dfs_process_phy_err(sc, m, rstamp, rs); 693 } 694 695 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 696 if (rs->rs_phyerr < 64) 697 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 698 goto rx_error; /* NB: don't count in ierrors */ 699 } 700 if (rs->rs_status & HAL_RXERR_DECRYPT) { 701 /* 702 * Decrypt error. If the error occurred 703 * because there was no hardware key, then 704 * let the frame through so the upper layers 705 * can process it. This is necessary for 5210 706 * parts which have no way to setup a ``clear'' 707 * key cache entry. 708 * 709 * XXX do key cache faulting 710 */ 711 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 712 goto rx_accept; 713 sc->sc_stats.ast_rx_badcrypt++; 714 } 715 /* 716 * Similar as above - if the failure was a keymiss 717 * just punt it up to the upper layers for now. 718 */ 719 if (rs->rs_status & HAL_RXERR_KEYMISS) { 720 sc->sc_stats.ast_rx_keymiss++; 721 goto rx_accept; 722 } 723 if (rs->rs_status & HAL_RXERR_MIC) { 724 sc->sc_stats.ast_rx_badmic++; 725 /* 726 * Do minimal work required to hand off 727 * the 802.11 header for notification. 728 */ 729 /* XXX frag's and qos frames */ 730 len = rs->rs_datalen; 731 if (len >= sizeof (struct ieee80211_frame)) { 732 ath_handle_micerror(ic, 733 mtod(m, struct ieee80211_frame *), 734 sc->sc_splitmic ? 735 rs->rs_keyix-32 : rs->rs_keyix); 736 } 737 } 738 counter_u64_add(ic->ic_ierrors, 1); 739 rx_error: 740 /* 741 * Cleanup any pending partial frame. 742 */ 743 if (re->m_rxpending != NULL) { 744 m_freem(re->m_rxpending); 745 re->m_rxpending = NULL; 746 } 747 /* 748 * When a tap is present pass error frames 749 * that have been requested. By default we 750 * pass decrypt+mic errors but others may be 751 * interesting (e.g. crc). 752 */ 753 if (ieee80211_radiotap_active(ic) && 754 (rs->rs_status & sc->sc_monpass)) { 755 /* NB: bpf needs the mbuf length setup */ 756 len = rs->rs_datalen; 757 m->m_pkthdr.len = m->m_len = len; 758 ath_rx_tap(sc, m, rs, rstamp, nf); 759 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 760 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 761 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 762 ieee80211_radiotap_rx_all(ic, m); 763 } 764 /* XXX pass MIC errors up for s/w reclaculation */ 765 m_freem(m); m = NULL; 766 goto rx_next; 767 } 768 rx_accept: 769 len = rs->rs_datalen; 770 m->m_len = len; 771 772 if (rs->rs_more) { 773 /* 774 * Frame spans multiple descriptors; save 775 * it for the next completed descriptor, it 776 * will be used to construct a jumbogram. 777 */ 778 if (re->m_rxpending != NULL) { 779 /* NB: max frame size is currently 2 clusters */ 780 sc->sc_stats.ast_rx_toobig++; 781 m_freem(re->m_rxpending); 782 } 783 m->m_pkthdr.len = len; 784 re->m_rxpending = m; 785 m = NULL; 786 goto rx_next; 787 } else if (re->m_rxpending != NULL) { 788 /* 789 * This is the second part of a jumbogram, 790 * chain it to the first mbuf, adjust the 791 * frame length, and clear the rxpending state. 792 */ 793 re->m_rxpending->m_next = m; 794 re->m_rxpending->m_pkthdr.len += len; 795 m = re->m_rxpending; 796 re->m_rxpending = NULL; 797 } else { 798 /* 799 * Normal single-descriptor receive; setup packet length. 800 */ 801 m->m_pkthdr.len = len; 802 } 803 804 /* 805 * Validate rs->rs_antenna. 806 * 807 * Some users w/ AR9285 NICs have reported crashes 808 * here because rs_antenna field is bogusly large. 809 * Let's enforce the maximum antenna limit of 8 810 * (and it shouldn't be hard coded, but that's a 811 * separate problem) and if there's an issue, print 812 * out an error and adjust rs_antenna to something 813 * sensible. 814 * 815 * This code should be removed once the actual 816 * root cause of the issue has been identified. 817 * For example, it may be that the rs_antenna 818 * field is only valid for the last frame of 819 * an aggregate and it just happens that it is 820 * "mostly" right. (This is a general statement - 821 * the majority of the statistics are only valid 822 * for the last frame in an aggregate. 823 */ 824 if (rs->rs_antenna > 7) { 825 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 826 __func__, rs->rs_antenna); 827 #ifdef ATH_DEBUG 828 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 829 #endif /* ATH_DEBUG */ 830 rs->rs_antenna = 0; /* XXX better than nothing */ 831 } 832 833 /* 834 * If this is an AR9285/AR9485, then the receive and LNA 835 * configuration is stored in RSSI[2] / EXTRSSI[2]. 836 * We can extract this out to build a much better 837 * receive antenna profile. 838 * 839 * Yes, this just blurts over the above RX antenna field 840 * for now. It's fine, the AR9285 doesn't really use 841 * that. 842 * 843 * Later on we should store away the fine grained LNA 844 * information and keep separate counters just for 845 * that. It'll help when debugging the AR9285/AR9485 846 * combined diversity code. 847 */ 848 if (sc->sc_rx_lnamixer) { 849 rs->rs_antenna = 0; 850 851 /* Bits 0:1 - the LNA configuration used */ 852 rs->rs_antenna |= 853 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 854 >> HAL_RX_LNA_CFG_USED_S); 855 856 /* Bit 2 - the external RX antenna switch */ 857 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 858 rs->rs_antenna |= 0x4; 859 } 860 861 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 862 863 /* 864 * Populate the rx status block. When there are bpf 865 * listeners we do the additional work to provide 866 * complete status. Otherwise we fill in only the 867 * material required by ieee80211_input. Note that 868 * noise setting is filled in above. 869 */ 870 if (ieee80211_radiotap_active(ic)) { 871 ath_rx_tap(sc, m, rs, rstamp, nf); 872 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 873 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 874 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 875 } 876 877 /* 878 * From this point on we assume the frame is at least 879 * as large as ieee80211_frame_min; verify that. 880 */ 881 if (len < IEEE80211_MIN_LEN) { 882 if (!ieee80211_radiotap_active(ic)) { 883 DPRINTF(sc, ATH_DEBUG_RECV, 884 "%s: short packet %d\n", __func__, len); 885 sc->sc_stats.ast_rx_tooshort++; 886 } else { 887 /* NB: in particular this captures ack's */ 888 ieee80211_radiotap_rx_all(ic, m); 889 } 890 m_freem(m); m = NULL; 891 goto rx_next; 892 } 893 894 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 895 const HAL_RATE_TABLE *rt = sc->sc_currates; 896 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 897 898 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 899 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 900 } 901 902 m_adj(m, -IEEE80211_CRC_LEN); 903 904 /* 905 * Locate the node for sender, track state, and then 906 * pass the (referenced) node up to the 802.11 layer 907 * for its use. 908 */ 909 ni = ieee80211_find_rxnode_withkey(ic, 910 mtod(m, const struct ieee80211_frame_min *), 911 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 912 IEEE80211_KEYIX_NONE : rs->rs_keyix); 913 sc->sc_lastrs = rs; 914 915 if (rs->rs_isaggr) 916 sc->sc_stats.ast_rx_agg++; 917 918 /* 919 * Populate the per-chain RSSI values where appropriate. 920 */ 921 bzero(&rxs, sizeof(rxs)); 922 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI | 923 IEEE80211_R_C_CHAIN | 924 IEEE80211_R_C_NF | 925 IEEE80211_R_C_RSSI | 926 IEEE80211_R_TSF64 | 927 IEEE80211_R_TSF_START; /* XXX TODO: validate */ 928 rxs.c_rssi = rs->rs_rssi; 929 rxs.c_nf = nf; 930 rxs.c_chain = 3; /* XXX TODO: check */ 931 rxs.c_rx_tsf = rstamp; 932 933 for (i = 0; i < 3; i++) { 934 rxs.c_rssi_ctl[i] = rs->rs_rssi_ctl[i]; 935 rxs.c_rssi_ext[i] = rs->rs_rssi_ext[i]; 936 /* 937 * XXX note: we currently don't track 938 * per-chain noisefloor. 939 */ 940 rxs.c_nf_ctl[i] = nf; 941 rxs.c_nf_ext[i] = nf; 942 } 943 944 if (ni != NULL) { 945 /* 946 * Only punt packets for ampdu reorder processing for 947 * 11n nodes; net80211 enforces that M_AMPDU is only 948 * set for 11n nodes. 949 */ 950 if (ni->ni_flags & IEEE80211_NODE_HT) 951 m->m_flags |= M_AMPDU; 952 953 /* 954 * Inform rate control about the received RSSI. 955 * It can then use this information to potentially drastically 956 * alter the available rate based on the RSSI estimate. 957 * 958 * This is super important when associating to a far away station; 959 * you don't want to waste time trying higher rates at some low 960 * packet exchange rate (like during DHCP) just to establish 961 * that higher MCS rates aren't available. 962 */ 963 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgrssi, 964 rs->rs_rssi); 965 ath_rate_update_rx_rssi(sc, ATH_NODE(ni), 966 ATH_RSSI(ATH_NODE(ni)->an_node_stats.ns_avgrssi)); 967 968 /* 969 * Sending station is known, dispatch directly. 970 */ 971 (void) ieee80211_add_rx_params(m, &rxs); 972 type = ieee80211_input_mimo(ni, m); 973 ieee80211_free_node(ni); 974 m = NULL; 975 /* 976 * Arrange to update the last rx timestamp only for 977 * frames from our ap when operating in station mode. 978 * This assumes the rx key is always setup when 979 * associated. 980 */ 981 if (ic->ic_opmode == IEEE80211_M_STA && 982 rs->rs_keyix != HAL_RXKEYIX_INVALID) 983 is_good = 1; 984 } else { 985 (void) ieee80211_add_rx_params(m, &rxs); 986 type = ieee80211_input_mimo_all(ic, m); 987 m = NULL; 988 } 989 990 /* 991 * At this point we have passed the frame up the stack; thus 992 * the mbuf is no longer ours. 993 */ 994 995 /* 996 * Track legacy station RX rssi and do any rx antenna management. 997 */ 998 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 999 if (sc->sc_diversity) { 1000 /* 1001 * When using fast diversity, change the default rx 1002 * antenna if diversity chooses the other antenna 3 1003 * times in a row. 1004 */ 1005 if (sc->sc_defant != rs->rs_antenna) { 1006 if (++sc->sc_rxotherant >= 3) 1007 ath_setdefantenna(sc, rs->rs_antenna); 1008 } else 1009 sc->sc_rxotherant = 0; 1010 } 1011 1012 /* Handle slow diversity if enabled */ 1013 if (sc->sc_dolnadiv) { 1014 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 1015 } 1016 1017 if (sc->sc_softled) { 1018 /* 1019 * Blink for any data frame. Otherwise do a 1020 * heartbeat-style blink when idle. The latter 1021 * is mainly for station mode where we depend on 1022 * periodic beacon frames to trigger the poll event. 1023 */ 1024 if (type == IEEE80211_FC0_TYPE_DATA) { 1025 const HAL_RATE_TABLE *rt = sc->sc_currates; 1026 ath_led_event(sc, 1027 rt->rateCodeToIndex[rs->rs_rate]); 1028 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 1029 ath_led_event(sc, 0); 1030 } 1031 rx_next: 1032 /* 1033 * Debugging - complain if we didn't NULL the mbuf pointer 1034 * here. 1035 */ 1036 if (m != NULL) { 1037 device_printf(sc->sc_dev, 1038 "%s: mbuf %p should've been freed!\n", 1039 __func__, 1040 m); 1041 } 1042 return (is_good); 1043 } 1044 1045 #define ATH_RX_MAX 128 1046 1047 /* 1048 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 1049 * the EDMA code does. 1050 * 1051 * XXX TODO: then, do all of the RX list management stuff inside 1052 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 1053 * code is doing it right. 1054 */ 1055 static void 1056 ath_rx_proc(struct ath_softc *sc, int resched) 1057 { 1058 #define PA2DESC(_sc, _pa) \ 1059 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1060 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1061 struct ath_buf *bf; 1062 struct ath_hal *ah = sc->sc_ah; 1063 #ifdef IEEE80211_SUPPORT_SUPERG 1064 struct ieee80211com *ic = &sc->sc_ic; 1065 #endif 1066 struct ath_desc *ds; 1067 struct ath_rx_status *rs; 1068 struct mbuf *m; 1069 int ngood; 1070 HAL_STATUS status; 1071 int16_t nf; 1072 u_int64_t tsf; 1073 int npkts = 0; 1074 int kickpcu = 0; 1075 int ret; 1076 1077 /* XXX we must not hold the ATH_LOCK here */ 1078 ATH_UNLOCK_ASSERT(sc); 1079 ATH_PCU_UNLOCK_ASSERT(sc); 1080 1081 ATH_PCU_LOCK(sc); 1082 sc->sc_rxproc_cnt++; 1083 kickpcu = sc->sc_kickpcu; 1084 ATH_PCU_UNLOCK(sc); 1085 1086 ATH_LOCK(sc); 1087 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1088 ATH_UNLOCK(sc); 1089 1090 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1091 ngood = 0; 1092 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1093 sc->sc_stats.ast_rx_noise = nf; 1094 tsf = ath_hal_gettsf64(ah); 1095 do { 1096 /* 1097 * Don't process too many packets at a time; give the 1098 * TX thread time to also run - otherwise the TX 1099 * latency can jump by quite a bit, causing throughput 1100 * degredation. 1101 */ 1102 if (!kickpcu && npkts >= ATH_RX_MAX) 1103 break; 1104 1105 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1106 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1107 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__); 1108 break; 1109 } else if (bf == NULL) { 1110 /* 1111 * End of List: 1112 * this can happen for non-self-linked RX chains 1113 */ 1114 sc->sc_stats.ast_rx_hitqueueend++; 1115 break; 1116 } 1117 m = bf->bf_m; 1118 if (m == NULL) { /* NB: shouldn't happen */ 1119 /* 1120 * If mbuf allocation failed previously there 1121 * will be no mbuf; try again to re-populate it. 1122 */ 1123 /* XXX make debug msg */ 1124 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__); 1125 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1126 goto rx_proc_next; 1127 } 1128 ds = bf->bf_desc; 1129 if (ds->ds_link == bf->bf_daddr) { 1130 /* NB: never process the self-linked entry at the end */ 1131 sc->sc_stats.ast_rx_hitqueueend++; 1132 break; 1133 } 1134 /* XXX sync descriptor memory */ 1135 /* 1136 * Must provide the virtual address of the current 1137 * descriptor, the physical address, and the virtual 1138 * address of the next descriptor in the h/w chain. 1139 * This allows the HAL to look ahead to see if the 1140 * hardware is done with a descriptor by checking the 1141 * done bit in the following descriptor and the address 1142 * of the current descriptor the DMA engine is working 1143 * on. All this is necessary because of our use of 1144 * a self-linked list to avoid rx overruns. 1145 */ 1146 rs = &bf->bf_status.ds_rxstat; 1147 status = ath_hal_rxprocdesc(ah, ds, 1148 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1149 #ifdef ATH_DEBUG 1150 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1151 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1152 #endif 1153 1154 #ifdef ATH_DEBUG_ALQ 1155 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1156 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1157 sc->sc_rx_statuslen, (char *) ds); 1158 #endif /* ATH_DEBUG_ALQ */ 1159 1160 if (status == HAL_EINPROGRESS) 1161 break; 1162 1163 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1164 npkts++; 1165 1166 /* 1167 * Process a single frame. 1168 */ 1169 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1170 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1171 bf->bf_m = NULL; 1172 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1173 ngood++; 1174 rx_proc_next: 1175 /* 1176 * If there's a holding buffer, insert that onto 1177 * the RX list; the hardware is now definitely not pointing 1178 * to it now. 1179 */ 1180 ret = 0; 1181 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1182 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1183 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1184 bf_list); 1185 ret = ath_rxbuf_init(sc, 1186 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1187 } 1188 /* 1189 * Next, throw our buffer into the holding entry. The hardware 1190 * may use the descriptor to read the link pointer before 1191 * DMAing the next descriptor in to write out a packet. 1192 */ 1193 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1194 } while (ret == 0); 1195 1196 /* rx signal state monitoring */ 1197 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1198 if (ngood) 1199 sc->sc_lastrx = tsf; 1200 1201 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1202 /* Queue DFS tasklet if needed */ 1203 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1204 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1205 1206 /* 1207 * Now that all the RX frames were handled that 1208 * need to be handled, kick the PCU if there's 1209 * been an RXEOL condition. 1210 */ 1211 if (resched && kickpcu) { 1212 ATH_PCU_LOCK(sc); 1213 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1214 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1215 __func__, npkts); 1216 1217 /* 1218 * Go through the process of fully tearing down 1219 * the RX buffers and reinitialising them. 1220 * 1221 * There's a hardware bug that causes the RX FIFO 1222 * to get confused under certain conditions and 1223 * constantly write over the same frame, leading 1224 * the RX driver code here to get heavily confused. 1225 */ 1226 /* 1227 * XXX Has RX DMA stopped enough here to just call 1228 * ath_startrecv()? 1229 * XXX Do we need to use the holding buffer to restart 1230 * RX DMA by appending entries to the final 1231 * descriptor? Quite likely. 1232 */ 1233 #if 1 1234 ath_startrecv(sc); 1235 #else 1236 /* 1237 * Disabled for now - it'd be nice to be able to do 1238 * this in order to limit the amount of CPU time spent 1239 * reinitialising the RX side (and thus minimise RX 1240 * drops) however there's a hardware issue that 1241 * causes things to get too far out of whack. 1242 */ 1243 /* 1244 * XXX can we hold the PCU lock here? 1245 * Are there any net80211 buffer calls involved? 1246 */ 1247 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1248 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1249 ath_hal_rxena(ah); /* enable recv descriptors */ 1250 ath_mode_init(sc); /* set filters, etc. */ 1251 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */ 1252 #endif 1253 1254 ath_hal_intrset(ah, sc->sc_imask); 1255 sc->sc_kickpcu = 0; 1256 ATH_PCU_UNLOCK(sc); 1257 } 1258 1259 #ifdef IEEE80211_SUPPORT_SUPERG 1260 if (resched) 1261 ieee80211_ff_age_all(ic, 100); 1262 #endif 1263 1264 /* 1265 * Put the hardware to sleep again if we're done with it. 1266 */ 1267 ATH_LOCK(sc); 1268 ath_power_restore_power_state(sc); 1269 ATH_UNLOCK(sc); 1270 1271 /* 1272 * If we hit the maximum number of frames in this round, 1273 * reschedule for another immediate pass. This gives 1274 * the TX and TX completion routines time to run, which 1275 * will reduce latency. 1276 */ 1277 if (npkts >= ATH_RX_MAX) 1278 sc->sc_rx.recv_sched(sc, resched); 1279 1280 ATH_PCU_LOCK(sc); 1281 sc->sc_rxproc_cnt--; 1282 ATH_PCU_UNLOCK(sc); 1283 } 1284 #undef PA2DESC 1285 #undef ATH_RX_MAX 1286 1287 /* 1288 * Only run the RX proc if it's not already running. 1289 * Since this may get run as part of the reset/flush path, 1290 * the task can't clash with an existing, running tasklet. 1291 */ 1292 static void 1293 ath_legacy_rx_tasklet(void *arg, int npending) 1294 { 1295 struct ath_softc *sc = arg; 1296 1297 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1298 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1299 ATH_PCU_LOCK(sc); 1300 if (sc->sc_inreset_cnt > 0) { 1301 device_printf(sc->sc_dev, 1302 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1303 ATH_PCU_UNLOCK(sc); 1304 return; 1305 } 1306 ATH_PCU_UNLOCK(sc); 1307 1308 ath_rx_proc(sc, 1); 1309 } 1310 1311 static void 1312 ath_legacy_flushrecv(struct ath_softc *sc) 1313 { 1314 1315 ath_rx_proc(sc, 0); 1316 } 1317 1318 static void 1319 ath_legacy_flush_rxpending(struct ath_softc *sc) 1320 { 1321 1322 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1323 1324 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1325 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1326 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1327 } 1328 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1329 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1330 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1331 } 1332 } 1333 1334 static int 1335 ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1336 { 1337 struct ath_buf *bf; 1338 1339 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1340 /* 1341 * If there are RX holding buffers, free them here and return 1342 * them to the list. 1343 * 1344 * XXX should just verify that bf->bf_m is NULL, as it must 1345 * be at this point! 1346 */ 1347 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1348 if (bf != NULL) { 1349 if (bf->bf_m != NULL) 1350 m_freem(bf->bf_m); 1351 bf->bf_m = NULL; 1352 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1353 (void) ath_rxbuf_init(sc, bf); 1354 } 1355 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1356 1357 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1358 if (bf != NULL) { 1359 if (bf->bf_m != NULL) 1360 m_freem(bf->bf_m); 1361 bf->bf_m = NULL; 1362 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1363 (void) ath_rxbuf_init(sc, bf); 1364 } 1365 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1366 1367 return (0); 1368 } 1369 1370 /* 1371 * Disable the receive h/w in preparation for a reset. 1372 */ 1373 static void 1374 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1375 { 1376 #define PA2DESC(_sc, _pa) \ 1377 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1378 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1379 struct ath_hal *ah = sc->sc_ah; 1380 1381 ATH_RX_LOCK(sc); 1382 1383 ath_hal_stoppcurecv(ah); /* disable PCU */ 1384 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1385 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1386 /* 1387 * TODO: see if this particular DELAY() is required; it may be 1388 * masking some missing FIFO flush or DMA sync. 1389 */ 1390 #if 0 1391 if (dodelay) 1392 #endif 1393 DELAY(3000); /* 3ms is long enough for 1 frame */ 1394 #ifdef ATH_DEBUG 1395 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1396 struct ath_buf *bf; 1397 u_int ix; 1398 1399 device_printf(sc->sc_dev, 1400 "%s: rx queue %p, link %p\n", 1401 __func__, 1402 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1403 sc->sc_rxlink); 1404 ix = 0; 1405 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1406 struct ath_desc *ds = bf->bf_desc; 1407 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1408 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1409 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1410 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1411 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1412 ix++; 1413 } 1414 } 1415 #endif 1416 1417 (void) ath_legacy_flush_rxpending(sc); 1418 (void) ath_legacy_flush_rxholdbf(sc); 1419 1420 sc->sc_rxlink = NULL; /* just in case */ 1421 1422 ATH_RX_UNLOCK(sc); 1423 #undef PA2DESC 1424 } 1425 1426 /* 1427 * XXX TODO: something was calling startrecv without calling 1428 * stoprecv. Let's figure out what/why. It was showing up 1429 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1430 */ 1431 1432 /* 1433 * Enable the receive h/w following a reset. 1434 */ 1435 static int 1436 ath_legacy_startrecv(struct ath_softc *sc) 1437 { 1438 struct ath_hal *ah = sc->sc_ah; 1439 struct ath_buf *bf; 1440 1441 ATH_RX_LOCK(sc); 1442 1443 /* 1444 * XXX should verify these are already all NULL! 1445 */ 1446 sc->sc_rxlink = NULL; 1447 (void) ath_legacy_flush_rxpending(sc); 1448 (void) ath_legacy_flush_rxholdbf(sc); 1449 1450 /* 1451 * Re-chain all of the buffers in the RX buffer list. 1452 */ 1453 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1454 int error = ath_rxbuf_init(sc, bf); 1455 if (error != 0) { 1456 DPRINTF(sc, ATH_DEBUG_RECV, 1457 "%s: ath_rxbuf_init failed %d\n", 1458 __func__, error); 1459 return error; 1460 } 1461 } 1462 1463 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1464 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1465 ath_hal_rxena(ah); /* enable recv descriptors */ 1466 ath_mode_init(sc); /* set filters, etc. */ 1467 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */ 1468 1469 ATH_RX_UNLOCK(sc); 1470 return 0; 1471 } 1472 1473 static int 1474 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1475 { 1476 int error; 1477 1478 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1479 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1480 if (error != 0) 1481 return (error); 1482 1483 return (0); 1484 } 1485 1486 static int 1487 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1488 { 1489 1490 if (sc->sc_rxdma.dd_desc_len != 0) 1491 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1492 return (0); 1493 } 1494 1495 static void 1496 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1497 { 1498 1499 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1500 } 1501 1502 static void 1503 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1504 int dosched) 1505 { 1506 1507 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1508 } 1509 1510 void 1511 ath_recv_setup_legacy(struct ath_softc *sc) 1512 { 1513 1514 /* Sensible legacy defaults */ 1515 /* 1516 * XXX this should be changed to properly support the 1517 * exact RX descriptor size for each HAL. 1518 */ 1519 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1520 1521 sc->sc_rx.recv_start = ath_legacy_startrecv; 1522 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1523 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1524 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1525 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1526 1527 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1528 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1529 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1530 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1531 } 1532