xref: /freebsd/sys/dev/ath/if_ath_rx.c (revision f5f7c05209ca2c3748fd8b27c5e80ffad49120eb)
1 /*-
2  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification.
11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13  *    redistribution must be conditioned upon including a substantially
14  *    similar Disclaimer requirement for further binary redistribution.
15  *
16  * NO WARRANTY
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27  * THE POSSIBILITY OF SUCH DAMAGES.
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 /*
34  * Driver for the Atheros Wireless LAN controller.
35  *
36  * This software is derived from work of Atsushi Onoe; his contribution
37  * is greatly appreciated.
38  */
39 
40 #include "opt_inet.h"
41 #include "opt_ath.h"
42 /*
43  * This is needed for register operations which are performed
44  * by the driver - eg, calls to ath_hal_gettsf32().
45  *
46  * It's also required for any AH_DEBUG checks in here, eg the
47  * module dependencies.
48  */
49 #include "opt_ah.h"
50 #include "opt_wlan.h"
51 
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
55 #include <sys/mbuf.h>
56 #include <sys/malloc.h>
57 #include <sys/lock.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
64 #include <sys/bus.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
68 #include <sys/priv.h>
69 #include <sys/module.h>
70 #include <sys/ktr.h>
71 #include <sys/smp.h>	/* for mp_ncpus */
72 
73 #include <machine/bus.h>
74 
75 #include <net/if.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/if_types.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_llc.h>
82 
83 #include <net80211/ieee80211_var.h>
84 #include <net80211/ieee80211_regdomain.h>
85 #ifdef IEEE80211_SUPPORT_SUPERG
86 #include <net80211/ieee80211_superg.h>
87 #endif
88 #ifdef IEEE80211_SUPPORT_TDMA
89 #include <net80211/ieee80211_tdma.h>
90 #endif
91 
92 #include <net/bpf.h>
93 
94 #ifdef INET
95 #include <netinet/in.h>
96 #include <netinet/if_ether.h>
97 #endif
98 
99 #include <dev/ath/if_athvar.h>
100 #include <dev/ath/ath_hal/ah_devid.h>		/* XXX for softled */
101 #include <dev/ath/ath_hal/ah_diagcodes.h>
102 
103 #include <dev/ath/if_ath_debug.h>
104 #include <dev/ath/if_ath_misc.h>
105 #include <dev/ath/if_ath_tsf.h>
106 #include <dev/ath/if_ath_tx.h>
107 #include <dev/ath/if_ath_sysctl.h>
108 #include <dev/ath/if_ath_led.h>
109 #include <dev/ath/if_ath_keycache.h>
110 #include <dev/ath/if_ath_rx.h>
111 #include <dev/ath/if_ath_beacon.h>
112 #include <dev/ath/if_athdfs.h>
113 
114 #ifdef ATH_TX99_DIAG
115 #include <dev/ath/ath_tx99/ath_tx99.h>
116 #endif
117 
118 #ifdef	ATH_DEBUG_ALQ
119 #include <dev/ath/if_ath_alq.h>
120 #endif
121 
122 /*
123  * Calculate the receive filter according to the
124  * operating mode and state:
125  *
126  * o always accept unicast, broadcast, and multicast traffic
127  * o accept PHY error frames when hardware doesn't have MIB support
128  *   to count and we need them for ANI (sta mode only until recently)
129  *   and we are not scanning (ANI is disabled)
130  *   NB: older hal's add rx filter bits out of sight and we need to
131  *	 blindly preserve them
132  * o probe request frames are accepted only when operating in
133  *   hostap, adhoc, mesh, or monitor modes
134  * o enable promiscuous mode
135  *   - when in monitor mode
136  *   - if interface marked PROMISC (assumes bridge setting is filtered)
137  * o accept beacons:
138  *   - when operating in station mode for collecting rssi data when
139  *     the station is otherwise quiet, or
140  *   - when operating in adhoc mode so the 802.11 layer creates
141  *     node table entries for peers,
142  *   - when scanning
143  *   - when doing s/w beacon miss (e.g. for ap+sta)
144  *   - when operating in ap mode in 11g to detect overlapping bss that
145  *     require protection
146  *   - when operating in mesh mode to detect neighbors
147  * o accept control frames:
148  *   - when in monitor mode
149  * XXX HT protection for 11n
150  */
151 u_int32_t
152 ath_calcrxfilter(struct ath_softc *sc)
153 {
154 	struct ifnet *ifp = sc->sc_ifp;
155 	struct ieee80211com *ic = ifp->if_l2com;
156 	u_int32_t rfilt;
157 
158 	rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
159 	if (!sc->sc_needmib && !sc->sc_scanning)
160 		rfilt |= HAL_RX_FILTER_PHYERR;
161 	if (ic->ic_opmode != IEEE80211_M_STA)
162 		rfilt |= HAL_RX_FILTER_PROBEREQ;
163 	/* XXX ic->ic_monvaps != 0? */
164 	if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC))
165 		rfilt |= HAL_RX_FILTER_PROM;
166 	if (ic->ic_opmode == IEEE80211_M_STA ||
167 	    ic->ic_opmode == IEEE80211_M_IBSS ||
168 	    sc->sc_swbmiss || sc->sc_scanning)
169 		rfilt |= HAL_RX_FILTER_BEACON;
170 	/*
171 	 * NB: We don't recalculate the rx filter when
172 	 * ic_protmode changes; otherwise we could do
173 	 * this only when ic_protmode != NONE.
174 	 */
175 	if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
176 	    IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
177 		rfilt |= HAL_RX_FILTER_BEACON;
178 
179 	/*
180 	 * Enable hardware PS-POLL RX only for hostap mode;
181 	 * STA mode sends PS-POLL frames but never
182 	 * receives them.
183 	 */
184 	if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL,
185 	    0, NULL) == HAL_OK &&
186 	    ic->ic_opmode == IEEE80211_M_HOSTAP)
187 		rfilt |= HAL_RX_FILTER_PSPOLL;
188 
189 	if (sc->sc_nmeshvaps) {
190 		rfilt |= HAL_RX_FILTER_BEACON;
191 		if (sc->sc_hasbmatch)
192 			rfilt |= HAL_RX_FILTER_BSSID;
193 		else
194 			rfilt |= HAL_RX_FILTER_PROM;
195 	}
196 	if (ic->ic_opmode == IEEE80211_M_MONITOR)
197 		rfilt |= HAL_RX_FILTER_CONTROL;
198 
199 	/*
200 	 * Enable RX of compressed BAR frames only when doing
201 	 * 802.11n. Required for A-MPDU.
202 	 */
203 	if (IEEE80211_IS_CHAN_HT(ic->ic_curchan))
204 		rfilt |= HAL_RX_FILTER_COMPBAR;
205 
206 	/*
207 	 * Enable radar PHY errors if requested by the
208 	 * DFS module.
209 	 */
210 	if (sc->sc_dodfs)
211 		rfilt |= HAL_RX_FILTER_PHYRADAR;
212 
213 	/*
214 	 * Enable spectral PHY errors if requested by the
215 	 * spectral module.
216 	 */
217 	if (sc->sc_dospectral)
218 		rfilt |= HAL_RX_FILTER_PHYRADAR;
219 
220 	DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n",
221 	    __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags);
222 	return rfilt;
223 }
224 
225 static int
226 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
227 {
228 	struct ath_hal *ah = sc->sc_ah;
229 	int error;
230 	struct mbuf *m;
231 	struct ath_desc *ds;
232 
233 	m = bf->bf_m;
234 	if (m == NULL) {
235 		/*
236 		 * NB: by assigning a page to the rx dma buffer we
237 		 * implicitly satisfy the Atheros requirement that
238 		 * this buffer be cache-line-aligned and sized to be
239 		 * multiple of the cache line size.  Not doing this
240 		 * causes weird stuff to happen (for the 5210 at least).
241 		 */
242 		m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
243 		if (m == NULL) {
244 			DPRINTF(sc, ATH_DEBUG_ANY,
245 				"%s: no mbuf/cluster\n", __func__);
246 			sc->sc_stats.ast_rx_nombuf++;
247 			return ENOMEM;
248 		}
249 		m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
250 
251 		error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
252 					     bf->bf_dmamap, m,
253 					     bf->bf_segs, &bf->bf_nseg,
254 					     BUS_DMA_NOWAIT);
255 		if (error != 0) {
256 			DPRINTF(sc, ATH_DEBUG_ANY,
257 			    "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
258 			    __func__, error);
259 			sc->sc_stats.ast_rx_busdma++;
260 			m_freem(m);
261 			return error;
262 		}
263 		KASSERT(bf->bf_nseg == 1,
264 			("multi-segment packet; nseg %u", bf->bf_nseg));
265 		bf->bf_m = m;
266 	}
267 	bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
268 
269 	/*
270 	 * Setup descriptors.  For receive we always terminate
271 	 * the descriptor list with a self-linked entry so we'll
272 	 * not get overrun under high load (as can happen with a
273 	 * 5212 when ANI processing enables PHY error frames).
274 	 *
275 	 * To insure the last descriptor is self-linked we create
276 	 * each descriptor as self-linked and add it to the end.  As
277 	 * each additional descriptor is added the previous self-linked
278 	 * entry is ``fixed'' naturally.  This should be safe even
279 	 * if DMA is happening.  When processing RX interrupts we
280 	 * never remove/process the last, self-linked, entry on the
281 	 * descriptor list.  This insures the hardware always has
282 	 * someplace to write a new frame.
283 	 */
284 	/*
285 	 * 11N: we can no longer afford to self link the last descriptor.
286 	 * MAC acknowledges BA status as long as it copies frames to host
287 	 * buffer (or rx fifo). This can incorrectly acknowledge packets
288 	 * to a sender if last desc is self-linked.
289 	 */
290 	ds = bf->bf_desc;
291 	if (sc->sc_rxslink)
292 		ds->ds_link = bf->bf_daddr;	/* link to self */
293 	else
294 		ds->ds_link = 0;		/* terminate the list */
295 	ds->ds_data = bf->bf_segs[0].ds_addr;
296 	ath_hal_setuprxdesc(ah, ds
297 		, m->m_len		/* buffer size */
298 		, 0
299 	);
300 
301 	if (sc->sc_rxlink != NULL)
302 		*sc->sc_rxlink = bf->bf_daddr;
303 	sc->sc_rxlink = &ds->ds_link;
304 	return 0;
305 }
306 
307 /*
308  * Intercept management frames to collect beacon rssi data
309  * and to do ibss merges.
310  */
311 void
312 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
313 	int subtype, int rssi, int nf)
314 {
315 	struct ieee80211vap *vap = ni->ni_vap;
316 	struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
317 
318 	/*
319 	 * Call up first so subsequent work can use information
320 	 * potentially stored in the node (e.g. for ibss merge).
321 	 */
322 	ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf);
323 	switch (subtype) {
324 	case IEEE80211_FC0_SUBTYPE_BEACON:
325 		/* update rssi statistics for use by the hal */
326 		/* XXX unlocked check against vap->iv_bss? */
327 		ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
328 		if (sc->sc_syncbeacon &&
329 		    ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) {
330 			/*
331 			 * Resync beacon timers using the tsf of the beacon
332 			 * frame we just received.
333 			 */
334 			ath_beacon_config(sc, vap);
335 		}
336 		/* fall thru... */
337 	case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
338 		if (vap->iv_opmode == IEEE80211_M_IBSS &&
339 		    vap->iv_state == IEEE80211_S_RUN) {
340 			uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
341 			uint64_t tsf = ath_extend_tsf(sc, rstamp,
342 				ath_hal_gettsf64(sc->sc_ah));
343 			/*
344 			 * Handle ibss merge as needed; check the tsf on the
345 			 * frame before attempting the merge.  The 802.11 spec
346 			 * says the station should change it's bssid to match
347 			 * the oldest station with the same ssid, where oldest
348 			 * is determined by the tsf.  Note that hardware
349 			 * reconfiguration happens through callback to
350 			 * ath_newstate as the state machine will go from
351 			 * RUN -> RUN when this happens.
352 			 */
353 			if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
354 				DPRINTF(sc, ATH_DEBUG_STATE,
355 				    "ibss merge, rstamp %u tsf %ju "
356 				    "tstamp %ju\n", rstamp, (uintmax_t)tsf,
357 				    (uintmax_t)ni->ni_tstamp.tsf);
358 				(void) ieee80211_ibss_merge(ni);
359 			}
360 		}
361 		break;
362 	}
363 }
364 
365 #ifdef	ATH_ENABLE_RADIOTAP_VENDOR_EXT
366 static void
367 ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m,
368     const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
369 {
370 	struct ath_softc *sc = ifp->if_softc;
371 
372 	/* Fill in the extension bitmap */
373 	sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER);
374 
375 	/* Fill in the vendor header */
376 	sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f;
377 	sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03;
378 	sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00;
379 
380 	/* XXX what should this be? */
381 	sc->sc_rx_th.wr_vh.vh_sub_ns = 0;
382 	sc->sc_rx_th.wr_vh.vh_skip_len =
383 	    htole16(sizeof(struct ath_radiotap_vendor_hdr));
384 
385 	/* General version info */
386 	sc->sc_rx_th.wr_v.vh_version = 1;
387 
388 	sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask;
389 
390 	/* rssi */
391 	sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0];
392 	sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1];
393 	sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2];
394 	sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0];
395 	sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1];
396 	sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2];
397 
398 	/* evm */
399 	sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0;
400 	sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1;
401 	sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2;
402 	/* XXX TODO: extend this to include 3-stream EVM */
403 
404 	/* phyerr info */
405 	if (rs->rs_status & HAL_RXERR_PHY)
406 		sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr;
407 	else
408 		sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff;
409 	sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status;
410 	sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi;
411 }
412 #endif	/* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
413 
414 static void
415 ath_rx_tap(struct ifnet *ifp, struct mbuf *m,
416 	const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
417 {
418 #define	CHAN_HT20	htole32(IEEE80211_CHAN_HT20)
419 #define	CHAN_HT40U	htole32(IEEE80211_CHAN_HT40U)
420 #define	CHAN_HT40D	htole32(IEEE80211_CHAN_HT40D)
421 #define	CHAN_HT		(CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
422 	struct ath_softc *sc = ifp->if_softc;
423 	const HAL_RATE_TABLE *rt;
424 	uint8_t rix;
425 
426 	rt = sc->sc_currates;
427 	KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
428 	rix = rt->rateCodeToIndex[rs->rs_rate];
429 	sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
430 	sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
431 #ifdef AH_SUPPORT_AR5416
432 	sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
433 	if (rs->rs_status & HAL_RXERR_PHY) {
434 		/*
435 		 * PHY error - make sure the channel flags
436 		 * reflect the actual channel configuration,
437 		 * not the received frame.
438 		 */
439 		if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan))
440 			sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
441 		else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan))
442 			sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
443 		else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan))
444 			sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
445 	} else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) {	/* HT rate */
446 		struct ieee80211com *ic = ifp->if_l2com;
447 
448 		if ((rs->rs_flags & HAL_RX_2040) == 0)
449 			sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
450 		else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
451 			sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
452 		else
453 			sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
454 		if ((rs->rs_flags & HAL_RX_GI) == 0)
455 			sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
456 	}
457 
458 #endif
459 	sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf));
460 	if (rs->rs_status & HAL_RXERR_CRC)
461 		sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
462 	/* XXX propagate other error flags from descriptor */
463 	sc->sc_rx_th.wr_antnoise = nf;
464 	sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
465 	sc->sc_rx_th.wr_antenna = rs->rs_antenna;
466 #undef CHAN_HT
467 #undef CHAN_HT20
468 #undef CHAN_HT40U
469 #undef CHAN_HT40D
470 }
471 
472 static void
473 ath_handle_micerror(struct ieee80211com *ic,
474 	struct ieee80211_frame *wh, int keyix)
475 {
476 	struct ieee80211_node *ni;
477 
478 	/* XXX recheck MIC to deal w/ chips that lie */
479 	/* XXX discard MIC errors on !data frames */
480 	ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
481 	if (ni != NULL) {
482 		ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
483 		ieee80211_free_node(ni);
484 	}
485 }
486 
487 int
488 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status,
489     uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf)
490 {
491 	struct ath_hal *ah = sc->sc_ah;
492 	struct mbuf *m = bf->bf_m;
493 	uint64_t rstamp;
494 	int len, type;
495 	struct ifnet *ifp = sc->sc_ifp;
496 	struct ieee80211com *ic = ifp->if_l2com;
497 	struct ieee80211_node *ni;
498 	int is_good = 0;
499 	struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
500 
501 	/*
502 	 * Calculate the correct 64 bit TSF given
503 	 * the TSF64 register value and rs_tstamp.
504 	 */
505 	rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
506 
507 	/* These aren't specifically errors */
508 #ifdef	AH_SUPPORT_AR5416
509 	if (rs->rs_flags & HAL_RX_GI)
510 		sc->sc_stats.ast_rx_halfgi++;
511 	if (rs->rs_flags & HAL_RX_2040)
512 		sc->sc_stats.ast_rx_2040++;
513 	if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE)
514 		sc->sc_stats.ast_rx_pre_crc_err++;
515 	if (rs->rs_flags & HAL_RX_DELIM_CRC_POST)
516 		sc->sc_stats.ast_rx_post_crc_err++;
517 	if (rs->rs_flags & HAL_RX_DECRYPT_BUSY)
518 		sc->sc_stats.ast_rx_decrypt_busy_err++;
519 	if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
520 		sc->sc_stats.ast_rx_hi_rx_chain++;
521 #endif /* AH_SUPPORT_AR5416 */
522 
523 	if (rs->rs_status != 0) {
524 		if (rs->rs_status & HAL_RXERR_CRC)
525 			sc->sc_stats.ast_rx_crcerr++;
526 		if (rs->rs_status & HAL_RXERR_FIFO)
527 			sc->sc_stats.ast_rx_fifoerr++;
528 		if (rs->rs_status & HAL_RXERR_PHY) {
529 			sc->sc_stats.ast_rx_phyerr++;
530 			/* Process DFS radar events */
531 			if ((rs->rs_phyerr == HAL_PHYERR_RADAR) ||
532 			    (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) {
533 				/* Since we're touching the frame data, sync it */
534 				bus_dmamap_sync(sc->sc_dmat,
535 				    bf->bf_dmamap,
536 				    BUS_DMASYNC_POSTREAD);
537 				/* Now pass it to the radar processing code */
538 				ath_dfs_process_phy_err(sc, m, rstamp, rs);
539 			}
540 
541 			/* Be suitably paranoid about receiving phy errors out of the stats array bounds */
542 			if (rs->rs_phyerr < 64)
543 				sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
544 			goto rx_error;	/* NB: don't count in ierrors */
545 		}
546 		if (rs->rs_status & HAL_RXERR_DECRYPT) {
547 			/*
548 			 * Decrypt error.  If the error occurred
549 			 * because there was no hardware key, then
550 			 * let the frame through so the upper layers
551 			 * can process it.  This is necessary for 5210
552 			 * parts which have no way to setup a ``clear''
553 			 * key cache entry.
554 			 *
555 			 * XXX do key cache faulting
556 			 */
557 			if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
558 				goto rx_accept;
559 			sc->sc_stats.ast_rx_badcrypt++;
560 		}
561 		/*
562 		 * Similar as above - if the failure was a keymiss
563 		 * just punt it up to the upper layers for now.
564 		 */
565 		if (rs->rs_status & HAL_RXERR_KEYMISS) {
566 			sc->sc_stats.ast_rx_keymiss++;
567 			goto rx_accept;
568 		}
569 		if (rs->rs_status & HAL_RXERR_MIC) {
570 			sc->sc_stats.ast_rx_badmic++;
571 			/*
572 			 * Do minimal work required to hand off
573 			 * the 802.11 header for notification.
574 			 */
575 			/* XXX frag's and qos frames */
576 			len = rs->rs_datalen;
577 			if (len >= sizeof (struct ieee80211_frame)) {
578 				bus_dmamap_sync(sc->sc_dmat,
579 				    bf->bf_dmamap,
580 				    BUS_DMASYNC_POSTREAD);
581 				ath_handle_micerror(ic,
582 				    mtod(m, struct ieee80211_frame *),
583 				    sc->sc_splitmic ?
584 					rs->rs_keyix-32 : rs->rs_keyix);
585 			}
586 		}
587 		ifp->if_ierrors++;
588 rx_error:
589 		/*
590 		 * Cleanup any pending partial frame.
591 		 */
592 		if (re->m_rxpending != NULL) {
593 			m_freem(re->m_rxpending);
594 			re->m_rxpending = NULL;
595 		}
596 		/*
597 		 * When a tap is present pass error frames
598 		 * that have been requested.  By default we
599 		 * pass decrypt+mic errors but others may be
600 		 * interesting (e.g. crc).
601 		 */
602 		if (ieee80211_radiotap_active(ic) &&
603 		    (rs->rs_status & sc->sc_monpass)) {
604 			bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
605 			    BUS_DMASYNC_POSTREAD);
606 			/* NB: bpf needs the mbuf length setup */
607 			len = rs->rs_datalen;
608 			m->m_pkthdr.len = m->m_len = len;
609 			bf->bf_m = NULL;
610 			ath_rx_tap(ifp, m, rs, rstamp, nf);
611 #ifdef	ATH_ENABLE_RADIOTAP_VENDOR_EXT
612 			ath_rx_tap_vendor(ifp, m, rs, rstamp, nf);
613 #endif	/* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
614 			ieee80211_radiotap_rx_all(ic, m);
615 			m_freem(m);
616 		}
617 		/* XXX pass MIC errors up for s/w reclaculation */
618 		goto rx_next;
619 	}
620 rx_accept:
621 	/*
622 	 * Sync and unmap the frame.  At this point we're
623 	 * committed to passing the mbuf somewhere so clear
624 	 * bf_m; this means a new mbuf must be allocated
625 	 * when the rx descriptor is setup again to receive
626 	 * another frame.
627 	 */
628 	bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD);
629 	bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
630 	bf->bf_m = NULL;
631 
632 	len = rs->rs_datalen;
633 	m->m_len = len;
634 
635 	if (rs->rs_more) {
636 		/*
637 		 * Frame spans multiple descriptors; save
638 		 * it for the next completed descriptor, it
639 		 * will be used to construct a jumbogram.
640 		 */
641 		if (re->m_rxpending != NULL) {
642 			/* NB: max frame size is currently 2 clusters */
643 			sc->sc_stats.ast_rx_toobig++;
644 			m_freem(re->m_rxpending);
645 		}
646 		m->m_pkthdr.rcvif = ifp;
647 		m->m_pkthdr.len = len;
648 		re->m_rxpending = m;
649 		goto rx_next;
650 	} else if (re->m_rxpending != NULL) {
651 		/*
652 		 * This is the second part of a jumbogram,
653 		 * chain it to the first mbuf, adjust the
654 		 * frame length, and clear the rxpending state.
655 		 */
656 		re->m_rxpending->m_next = m;
657 		re->m_rxpending->m_pkthdr.len += len;
658 		m = re->m_rxpending;
659 		re->m_rxpending = NULL;
660 	} else {
661 		/*
662 		 * Normal single-descriptor receive; setup
663 		 * the rcvif and packet length.
664 		 */
665 		m->m_pkthdr.rcvif = ifp;
666 		m->m_pkthdr.len = len;
667 	}
668 
669 	/*
670 	 * Validate rs->rs_antenna.
671 	 *
672 	 * Some users w/ AR9285 NICs have reported crashes
673 	 * here because rs_antenna field is bogusly large.
674 	 * Let's enforce the maximum antenna limit of 8
675 	 * (and it shouldn't be hard coded, but that's a
676 	 * separate problem) and if there's an issue, print
677 	 * out an error and adjust rs_antenna to something
678 	 * sensible.
679 	 *
680 	 * This code should be removed once the actual
681 	 * root cause of the issue has been identified.
682 	 * For example, it may be that the rs_antenna
683 	 * field is only valid for the lsat frame of
684 	 * an aggregate and it just happens that it is
685 	 * "mostly" right. (This is a general statement -
686 	 * the majority of the statistics are only valid
687 	 * for the last frame in an aggregate.
688 	 */
689 	if (rs->rs_antenna > 7) {
690 		device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
691 		    __func__, rs->rs_antenna);
692 #ifdef	ATH_DEBUG
693 		ath_printrxbuf(sc, bf, 0, status == HAL_OK);
694 #endif /* ATH_DEBUG */
695 		rs->rs_antenna = 0;	/* XXX better than nothing */
696 	}
697 
698 	ifp->if_ipackets++;
699 	sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
700 
701 	/*
702 	 * Populate the rx status block.  When there are bpf
703 	 * listeners we do the additional work to provide
704 	 * complete status.  Otherwise we fill in only the
705 	 * material required by ieee80211_input.  Note that
706 	 * noise setting is filled in above.
707 	 */
708 	if (ieee80211_radiotap_active(ic)) {
709 		ath_rx_tap(ifp, m, rs, rstamp, nf);
710 #ifdef	ATH_ENABLE_RADIOTAP_VENDOR_EXT
711 		ath_rx_tap_vendor(ifp, m, rs, rstamp, nf);
712 #endif	/* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
713 	}
714 
715 	/*
716 	 * From this point on we assume the frame is at least
717 	 * as large as ieee80211_frame_min; verify that.
718 	 */
719 	if (len < IEEE80211_MIN_LEN) {
720 		if (!ieee80211_radiotap_active(ic)) {
721 			DPRINTF(sc, ATH_DEBUG_RECV,
722 			    "%s: short packet %d\n", __func__, len);
723 			sc->sc_stats.ast_rx_tooshort++;
724 		} else {
725 			/* NB: in particular this captures ack's */
726 			ieee80211_radiotap_rx_all(ic, m);
727 		}
728 		m_freem(m);
729 		goto rx_next;
730 	}
731 
732 	if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
733 		const HAL_RATE_TABLE *rt = sc->sc_currates;
734 		uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
735 
736 		ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
737 		    sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
738 	}
739 
740 	m_adj(m, -IEEE80211_CRC_LEN);
741 
742 	/*
743 	 * Locate the node for sender, track state, and then
744 	 * pass the (referenced) node up to the 802.11 layer
745 	 * for its use.
746 	 */
747 	ni = ieee80211_find_rxnode_withkey(ic,
748 		mtod(m, const struct ieee80211_frame_min *),
749 		rs->rs_keyix == HAL_RXKEYIX_INVALID ?
750 			IEEE80211_KEYIX_NONE : rs->rs_keyix);
751 	sc->sc_lastrs = rs;
752 
753 #ifdef	AH_SUPPORT_AR5416
754 	if (rs->rs_isaggr)
755 		sc->sc_stats.ast_rx_agg++;
756 #endif /* AH_SUPPORT_AR5416 */
757 
758 	if (ni != NULL) {
759 		/*
760 		 * Only punt packets for ampdu reorder processing for
761 		 * 11n nodes; net80211 enforces that M_AMPDU is only
762 		 * set for 11n nodes.
763 		 */
764 		if (ni->ni_flags & IEEE80211_NODE_HT)
765 			m->m_flags |= M_AMPDU;
766 
767 		/*
768 		 * Sending station is known, dispatch directly.
769 		 */
770 		type = ieee80211_input(ni, m, rs->rs_rssi, nf);
771 		ieee80211_free_node(ni);
772 		/*
773 		 * Arrange to update the last rx timestamp only for
774 		 * frames from our ap when operating in station mode.
775 		 * This assumes the rx key is always setup when
776 		 * associated.
777 		 */
778 		if (ic->ic_opmode == IEEE80211_M_STA &&
779 		    rs->rs_keyix != HAL_RXKEYIX_INVALID)
780 			is_good = 1;
781 	} else {
782 		type = ieee80211_input_all(ic, m, rs->rs_rssi, nf);
783 	}
784 	/*
785 	 * Track rx rssi and do any rx antenna management.
786 	 */
787 	ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
788 	if (sc->sc_diversity) {
789 		/*
790 		 * When using fast diversity, change the default rx
791 		 * antenna if diversity chooses the other antenna 3
792 		 * times in a row.
793 		 */
794 		if (sc->sc_defant != rs->rs_antenna) {
795 			if (++sc->sc_rxotherant >= 3)
796 				ath_setdefantenna(sc, rs->rs_antenna);
797 		} else
798 			sc->sc_rxotherant = 0;
799 	}
800 
801 	/* Newer school diversity - kite specific for now */
802 	/* XXX perhaps migrate the normal diversity code to this? */
803 	if ((ah)->ah_rxAntCombDiversity)
804 		(*(ah)->ah_rxAntCombDiversity)(ah, rs, ticks, hz);
805 
806 	if (sc->sc_softled) {
807 		/*
808 		 * Blink for any data frame.  Otherwise do a
809 		 * heartbeat-style blink when idle.  The latter
810 		 * is mainly for station mode where we depend on
811 		 * periodic beacon frames to trigger the poll event.
812 		 */
813 		if (type == IEEE80211_FC0_TYPE_DATA) {
814 			const HAL_RATE_TABLE *rt = sc->sc_currates;
815 			ath_led_event(sc,
816 			    rt->rateCodeToIndex[rs->rs_rate]);
817 		} else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
818 			ath_led_event(sc, 0);
819 		}
820 rx_next:
821 	return (is_good);
822 }
823 
824 #define	ATH_RX_MAX		128
825 
826 static void
827 ath_rx_proc(struct ath_softc *sc, int resched)
828 {
829 #define	PA2DESC(_sc, _pa) \
830 	((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
831 		((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
832 	struct ath_buf *bf;
833 	struct ifnet *ifp = sc->sc_ifp;
834 	struct ath_hal *ah = sc->sc_ah;
835 #ifdef IEEE80211_SUPPORT_SUPERG
836 	struct ieee80211com *ic = ifp->if_l2com;
837 #endif
838 	struct ath_desc *ds;
839 	struct ath_rx_status *rs;
840 	struct mbuf *m;
841 	int ngood;
842 	HAL_STATUS status;
843 	int16_t nf;
844 	u_int64_t tsf;
845 	int npkts = 0;
846 	int kickpcu = 0;
847 
848 	/* XXX we must not hold the ATH_LOCK here */
849 	ATH_UNLOCK_ASSERT(sc);
850 	ATH_PCU_UNLOCK_ASSERT(sc);
851 
852 	ATH_PCU_LOCK(sc);
853 	sc->sc_rxproc_cnt++;
854 	kickpcu = sc->sc_kickpcu;
855 	ATH_PCU_UNLOCK(sc);
856 
857 	DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__);
858 	ngood = 0;
859 	nf = ath_hal_getchannoise(ah, sc->sc_curchan);
860 	sc->sc_stats.ast_rx_noise = nf;
861 	tsf = ath_hal_gettsf64(ah);
862 	do {
863 		/*
864 		 * Don't process too many packets at a time; give the
865 		 * TX thread time to also run - otherwise the TX
866 		 * latency can jump by quite a bit, causing throughput
867 		 * degredation.
868 		 */
869 		if (!kickpcu && npkts >= ATH_RX_MAX)
870 			break;
871 
872 		bf = TAILQ_FIRST(&sc->sc_rxbuf);
873 		if (sc->sc_rxslink && bf == NULL) {	/* NB: shouldn't happen */
874 			if_printf(ifp, "%s: no buffer!\n", __func__);
875 			break;
876 		} else if (bf == NULL) {
877 			/*
878 			 * End of List:
879 			 * this can happen for non-self-linked RX chains
880 			 */
881 			sc->sc_stats.ast_rx_hitqueueend++;
882 			break;
883 		}
884 		m = bf->bf_m;
885 		if (m == NULL) {		/* NB: shouldn't happen */
886 			/*
887 			 * If mbuf allocation failed previously there
888 			 * will be no mbuf; try again to re-populate it.
889 			 */
890 			/* XXX make debug msg */
891 			if_printf(ifp, "%s: no mbuf!\n", __func__);
892 			TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
893 			goto rx_proc_next;
894 		}
895 		ds = bf->bf_desc;
896 		if (ds->ds_link == bf->bf_daddr) {
897 			/* NB: never process the self-linked entry at the end */
898 			sc->sc_stats.ast_rx_hitqueueend++;
899 			break;
900 		}
901 		/* XXX sync descriptor memory */
902 		/*
903 		 * Must provide the virtual address of the current
904 		 * descriptor, the physical address, and the virtual
905 		 * address of the next descriptor in the h/w chain.
906 		 * This allows the HAL to look ahead to see if the
907 		 * hardware is done with a descriptor by checking the
908 		 * done bit in the following descriptor and the address
909 		 * of the current descriptor the DMA engine is working
910 		 * on.  All this is necessary because of our use of
911 		 * a self-linked list to avoid rx overruns.
912 		 */
913 		rs = &bf->bf_status.ds_rxstat;
914 		status = ath_hal_rxprocdesc(ah, ds,
915 				bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
916 #ifdef ATH_DEBUG
917 		if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
918 			ath_printrxbuf(sc, bf, 0, status == HAL_OK);
919 #endif
920 
921 #ifdef	ATH_DEBUG_ALQ
922 		if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
923 		    if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
924 		    sc->sc_rx_statuslen, (char *) ds);
925 #endif	/* ATH_DEBUG_ALQ */
926 
927 		if (status == HAL_EINPROGRESS)
928 			break;
929 
930 		TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
931 		npkts++;
932 
933 		/*
934 		 * Process a single frame.
935 		 */
936 		if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf))
937 			ngood++;
938 rx_proc_next:
939 		TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
940 	} while (ath_rxbuf_init(sc, bf) == 0);
941 
942 	/* rx signal state monitoring */
943 	ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
944 	if (ngood)
945 		sc->sc_lastrx = tsf;
946 
947 	ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood);
948 	/* Queue DFS tasklet if needed */
949 	if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan))
950 		taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
951 
952 	/*
953 	 * Now that all the RX frames were handled that
954 	 * need to be handled, kick the PCU if there's
955 	 * been an RXEOL condition.
956 	 */
957 	ATH_PCU_LOCK(sc);
958 	if (resched && sc->sc_kickpcu) {
959 		ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu");
960 		device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n",
961 		    __func__, npkts);
962 
963 		/* XXX rxslink? */
964 #if 0
965 		ath_startrecv(sc);
966 #else
967 		/*
968 		 * XXX can we hold the PCU lock here?
969 		 * Are there any net80211 buffer calls involved?
970 		 */
971 		bf = TAILQ_FIRST(&sc->sc_rxbuf);
972 		ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
973 		ath_hal_rxena(ah);		/* enable recv descriptors */
974 		ath_mode_init(sc);		/* set filters, etc. */
975 		ath_hal_startpcurecv(ah);	/* re-enable PCU/DMA engine */
976 #endif
977 
978 		ath_hal_intrset(ah, sc->sc_imask);
979 		sc->sc_kickpcu = 0;
980 	}
981 	ATH_PCU_UNLOCK(sc);
982 
983 	/* XXX check this inside of IF_LOCK? */
984 	if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
985 #ifdef IEEE80211_SUPPORT_SUPERG
986 		ieee80211_ff_age_all(ic, 100);
987 #endif
988 		if (!IFQ_IS_EMPTY(&ifp->if_snd))
989 			ath_tx_kick(sc);
990 	}
991 #undef PA2DESC
992 
993 	/*
994 	 * If we hit the maximum number of frames in this round,
995 	 * reschedule for another immediate pass.  This gives
996 	 * the TX and TX completion routines time to run, which
997 	 * will reduce latency.
998 	 */
999 	if (npkts >= ATH_RX_MAX)
1000 		taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1001 
1002 	ATH_PCU_LOCK(sc);
1003 	sc->sc_rxproc_cnt--;
1004 	ATH_PCU_UNLOCK(sc);
1005 }
1006 
1007 #undef	ATH_RX_MAX
1008 
1009 /*
1010  * Only run the RX proc if it's not already running.
1011  * Since this may get run as part of the reset/flush path,
1012  * the task can't clash with an existing, running tasklet.
1013  */
1014 static void
1015 ath_legacy_rx_tasklet(void *arg, int npending)
1016 {
1017 	struct ath_softc *sc = arg;
1018 
1019 	ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending);
1020 	DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
1021 	ATH_PCU_LOCK(sc);
1022 	if (sc->sc_inreset_cnt > 0) {
1023 		device_printf(sc->sc_dev,
1024 		    "%s: sc_inreset_cnt > 0; skipping\n", __func__);
1025 		ATH_PCU_UNLOCK(sc);
1026 		return;
1027 	}
1028 	ATH_PCU_UNLOCK(sc);
1029 
1030 	ath_rx_proc(sc, 1);
1031 }
1032 
1033 static void
1034 ath_legacy_flushrecv(struct ath_softc *sc)
1035 {
1036 
1037 	ath_rx_proc(sc, 0);
1038 }
1039 
1040 /*
1041  * Disable the receive h/w in preparation for a reset.
1042  */
1043 static void
1044 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay)
1045 {
1046 #define	PA2DESC(_sc, _pa) \
1047 	((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1048 		((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1049 	struct ath_hal *ah = sc->sc_ah;
1050 
1051 	ath_hal_stoppcurecv(ah);	/* disable PCU */
1052 	ath_hal_setrxfilter(ah, 0);	/* clear recv filter */
1053 	ath_hal_stopdmarecv(ah);	/* disable DMA engine */
1054 	/*
1055 	 * TODO: see if this particular DELAY() is required; it may be
1056 	 * masking some missing FIFO flush or DMA sync.
1057 	 */
1058 #if 0
1059 	if (dodelay)
1060 #endif
1061 		DELAY(3000);		/* 3ms is long enough for 1 frame */
1062 #ifdef ATH_DEBUG
1063 	if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
1064 		struct ath_buf *bf;
1065 		u_int ix;
1066 
1067 		device_printf(sc->sc_dev,
1068 		    "%s: rx queue %p, link %p\n",
1069 		    __func__,
1070 		    (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP),
1071 		    sc->sc_rxlink);
1072 		ix = 0;
1073 		TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1074 			struct ath_desc *ds = bf->bf_desc;
1075 			struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
1076 			HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
1077 				bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1078 			if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
1079 				ath_printrxbuf(sc, bf, ix, status == HAL_OK);
1080 			ix++;
1081 		}
1082 	}
1083 #endif
1084 	/*
1085 	 * Free both high/low RX pending, just in case.
1086 	 */
1087 	if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) {
1088 		m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
1089 		sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1090 	}
1091 	if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) {
1092 		m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
1093 		sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1094 	}
1095 	sc->sc_rxlink = NULL;		/* just in case */
1096 #undef PA2DESC
1097 }
1098 
1099 /*
1100  * Enable the receive h/w following a reset.
1101  */
1102 static int
1103 ath_legacy_startrecv(struct ath_softc *sc)
1104 {
1105 	struct ath_hal *ah = sc->sc_ah;
1106 	struct ath_buf *bf;
1107 
1108 	sc->sc_rxlink = NULL;
1109 	sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1110 	sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1111 	TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1112 		int error = ath_rxbuf_init(sc, bf);
1113 		if (error != 0) {
1114 			DPRINTF(sc, ATH_DEBUG_RECV,
1115 				"%s: ath_rxbuf_init failed %d\n",
1116 				__func__, error);
1117 			return error;
1118 		}
1119 	}
1120 
1121 	bf = TAILQ_FIRST(&sc->sc_rxbuf);
1122 	ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1123 	ath_hal_rxena(ah);		/* enable recv descriptors */
1124 	ath_mode_init(sc);		/* set filters, etc. */
1125 	ath_hal_startpcurecv(ah);	/* re-enable PCU/DMA engine */
1126 	return 0;
1127 }
1128 
1129 static int
1130 ath_legacy_dma_rxsetup(struct ath_softc *sc)
1131 {
1132 	int error;
1133 
1134 	error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
1135 	    "rx", sizeof(struct ath_desc), ath_rxbuf, 1);
1136 	if (error != 0)
1137 		return (error);
1138 
1139 	return (0);
1140 }
1141 
1142 static int
1143 ath_legacy_dma_rxteardown(struct ath_softc *sc)
1144 {
1145 
1146 	if (sc->sc_rxdma.dd_desc_len != 0)
1147 		ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
1148 	return (0);
1149 }
1150 
1151 void
1152 ath_recv_setup_legacy(struct ath_softc *sc)
1153 {
1154 
1155 	/* Sensible legacy defaults */
1156 	/*
1157 	 * XXX this should be changed to properly support the
1158 	 * exact RX descriptor size for each HAL.
1159 	 */
1160 	sc->sc_rx_statuslen = sizeof(struct ath_desc);
1161 
1162 	sc->sc_rx.recv_start = ath_legacy_startrecv;
1163 	sc->sc_rx.recv_stop = ath_legacy_stoprecv;
1164 	sc->sc_rx.recv_flush = ath_legacy_flushrecv;
1165 	sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet;
1166 	sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init;
1167 
1168 	sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup;
1169 	sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown;
1170 }
1171