1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_regdomain.h> 85 #ifdef IEEE80211_SUPPORT_SUPERG 86 #include <net80211/ieee80211_superg.h> 87 #endif 88 #ifdef IEEE80211_SUPPORT_TDMA 89 #include <net80211/ieee80211_tdma.h> 90 #endif 91 92 #include <net/bpf.h> 93 94 #ifdef INET 95 #include <netinet/in.h> 96 #include <netinet/if_ether.h> 97 #endif 98 99 #include <dev/ath/if_athvar.h> 100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101 #include <dev/ath/ath_hal/ah_diagcodes.h> 102 103 #include <dev/ath/if_ath_debug.h> 104 #include <dev/ath/if_ath_misc.h> 105 #include <dev/ath/if_ath_tsf.h> 106 #include <dev/ath/if_ath_tx.h> 107 #include <dev/ath/if_ath_sysctl.h> 108 #include <dev/ath/if_ath_led.h> 109 #include <dev/ath/if_ath_keycache.h> 110 #include <dev/ath/if_ath_rx.h> 111 #include <dev/ath/if_ath_beacon.h> 112 #include <dev/ath/if_athdfs.h> 113 114 #ifdef ATH_TX99_DIAG 115 #include <dev/ath/ath_tx99/ath_tx99.h> 116 #endif 117 118 #ifdef ATH_DEBUG_ALQ 119 #include <dev/ath/if_ath_alq.h> 120 #endif 121 122 /* 123 * Calculate the receive filter according to the 124 * operating mode and state: 125 * 126 * o always accept unicast, broadcast, and multicast traffic 127 * o accept PHY error frames when hardware doesn't have MIB support 128 * to count and we need them for ANI (sta mode only until recently) 129 * and we are not scanning (ANI is disabled) 130 * NB: older hal's add rx filter bits out of sight and we need to 131 * blindly preserve them 132 * o probe request frames are accepted only when operating in 133 * hostap, adhoc, mesh, or monitor modes 134 * o enable promiscuous mode 135 * - when in monitor mode 136 * - if interface marked PROMISC (assumes bridge setting is filtered) 137 * o accept beacons: 138 * - when operating in station mode for collecting rssi data when 139 * the station is otherwise quiet, or 140 * - when operating in adhoc mode so the 802.11 layer creates 141 * node table entries for peers, 142 * - when scanning 143 * - when doing s/w beacon miss (e.g. for ap+sta) 144 * - when operating in ap mode in 11g to detect overlapping bss that 145 * require protection 146 * - when operating in mesh mode to detect neighbors 147 * o accept control frames: 148 * - when in monitor mode 149 * XXX HT protection for 11n 150 */ 151 u_int32_t 152 ath_calcrxfilter(struct ath_softc *sc) 153 { 154 struct ifnet *ifp = sc->sc_ifp; 155 struct ieee80211com *ic = ifp->if_l2com; 156 u_int32_t rfilt; 157 158 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 159 if (!sc->sc_needmib && !sc->sc_scanning) 160 rfilt |= HAL_RX_FILTER_PHYERR; 161 if (ic->ic_opmode != IEEE80211_M_STA) 162 rfilt |= HAL_RX_FILTER_PROBEREQ; 163 /* XXX ic->ic_monvaps != 0? */ 164 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 165 rfilt |= HAL_RX_FILTER_PROM; 166 if (ic->ic_opmode == IEEE80211_M_STA || 167 ic->ic_opmode == IEEE80211_M_IBSS || 168 sc->sc_swbmiss || sc->sc_scanning) 169 rfilt |= HAL_RX_FILTER_BEACON; 170 /* 171 * NB: We don't recalculate the rx filter when 172 * ic_protmode changes; otherwise we could do 173 * this only when ic_protmode != NONE. 174 */ 175 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 176 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 177 rfilt |= HAL_RX_FILTER_BEACON; 178 179 /* 180 * Enable hardware PS-POLL RX only for hostap mode; 181 * STA mode sends PS-POLL frames but never 182 * receives them. 183 */ 184 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 185 0, NULL) == HAL_OK && 186 ic->ic_opmode == IEEE80211_M_HOSTAP) 187 rfilt |= HAL_RX_FILTER_PSPOLL; 188 189 if (sc->sc_nmeshvaps) { 190 rfilt |= HAL_RX_FILTER_BEACON; 191 if (sc->sc_hasbmatch) 192 rfilt |= HAL_RX_FILTER_BSSID; 193 else 194 rfilt |= HAL_RX_FILTER_PROM; 195 } 196 if (ic->ic_opmode == IEEE80211_M_MONITOR) 197 rfilt |= HAL_RX_FILTER_CONTROL; 198 199 /* 200 * Enable RX of compressed BAR frames only when doing 201 * 802.11n. Required for A-MPDU. 202 */ 203 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 204 rfilt |= HAL_RX_FILTER_COMPBAR; 205 206 /* 207 * Enable radar PHY errors if requested by the 208 * DFS module. 209 */ 210 if (sc->sc_dodfs) 211 rfilt |= HAL_RX_FILTER_PHYRADAR; 212 213 /* 214 * Enable spectral PHY errors if requested by the 215 * spectral module. 216 */ 217 if (sc->sc_dospectral) 218 rfilt |= HAL_RX_FILTER_PHYRADAR; 219 220 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 221 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 222 return rfilt; 223 } 224 225 static int 226 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 227 { 228 struct ath_hal *ah = sc->sc_ah; 229 int error; 230 struct mbuf *m; 231 struct ath_desc *ds; 232 233 m = bf->bf_m; 234 if (m == NULL) { 235 /* 236 * NB: by assigning a page to the rx dma buffer we 237 * implicitly satisfy the Atheros requirement that 238 * this buffer be cache-line-aligned and sized to be 239 * multiple of the cache line size. Not doing this 240 * causes weird stuff to happen (for the 5210 at least). 241 */ 242 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 243 if (m == NULL) { 244 DPRINTF(sc, ATH_DEBUG_ANY, 245 "%s: no mbuf/cluster\n", __func__); 246 sc->sc_stats.ast_rx_nombuf++; 247 return ENOMEM; 248 } 249 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 250 251 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 252 bf->bf_dmamap, m, 253 bf->bf_segs, &bf->bf_nseg, 254 BUS_DMA_NOWAIT); 255 if (error != 0) { 256 DPRINTF(sc, ATH_DEBUG_ANY, 257 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 258 __func__, error); 259 sc->sc_stats.ast_rx_busdma++; 260 m_freem(m); 261 return error; 262 } 263 KASSERT(bf->bf_nseg == 1, 264 ("multi-segment packet; nseg %u", bf->bf_nseg)); 265 bf->bf_m = m; 266 } 267 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 268 269 /* 270 * Setup descriptors. For receive we always terminate 271 * the descriptor list with a self-linked entry so we'll 272 * not get overrun under high load (as can happen with a 273 * 5212 when ANI processing enables PHY error frames). 274 * 275 * To insure the last descriptor is self-linked we create 276 * each descriptor as self-linked and add it to the end. As 277 * each additional descriptor is added the previous self-linked 278 * entry is ``fixed'' naturally. This should be safe even 279 * if DMA is happening. When processing RX interrupts we 280 * never remove/process the last, self-linked, entry on the 281 * descriptor list. This insures the hardware always has 282 * someplace to write a new frame. 283 */ 284 /* 285 * 11N: we can no longer afford to self link the last descriptor. 286 * MAC acknowledges BA status as long as it copies frames to host 287 * buffer (or rx fifo). This can incorrectly acknowledge packets 288 * to a sender if last desc is self-linked. 289 */ 290 ds = bf->bf_desc; 291 if (sc->sc_rxslink) 292 ds->ds_link = bf->bf_daddr; /* link to self */ 293 else 294 ds->ds_link = 0; /* terminate the list */ 295 ds->ds_data = bf->bf_segs[0].ds_addr; 296 ath_hal_setuprxdesc(ah, ds 297 , m->m_len /* buffer size */ 298 , 0 299 ); 300 301 if (sc->sc_rxlink != NULL) 302 *sc->sc_rxlink = bf->bf_daddr; 303 sc->sc_rxlink = &ds->ds_link; 304 return 0; 305 } 306 307 /* 308 * Intercept management frames to collect beacon rssi data 309 * and to do ibss merges. 310 */ 311 void 312 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 313 int subtype, int rssi, int nf) 314 { 315 struct ieee80211vap *vap = ni->ni_vap; 316 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 317 318 /* 319 * Call up first so subsequent work can use information 320 * potentially stored in the node (e.g. for ibss merge). 321 */ 322 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 323 switch (subtype) { 324 case IEEE80211_FC0_SUBTYPE_BEACON: 325 /* update rssi statistics for use by the hal */ 326 /* XXX unlocked check against vap->iv_bss? */ 327 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 328 if (sc->sc_syncbeacon && 329 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 330 /* 331 * Resync beacon timers using the tsf of the beacon 332 * frame we just received. 333 */ 334 ath_beacon_config(sc, vap); 335 } 336 /* fall thru... */ 337 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 338 if (vap->iv_opmode == IEEE80211_M_IBSS && 339 vap->iv_state == IEEE80211_S_RUN) { 340 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 341 uint64_t tsf = ath_extend_tsf(sc, rstamp, 342 ath_hal_gettsf64(sc->sc_ah)); 343 /* 344 * Handle ibss merge as needed; check the tsf on the 345 * frame before attempting the merge. The 802.11 spec 346 * says the station should change it's bssid to match 347 * the oldest station with the same ssid, where oldest 348 * is determined by the tsf. Note that hardware 349 * reconfiguration happens through callback to 350 * ath_newstate as the state machine will go from 351 * RUN -> RUN when this happens. 352 */ 353 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 354 DPRINTF(sc, ATH_DEBUG_STATE, 355 "ibss merge, rstamp %u tsf %ju " 356 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 357 (uintmax_t)ni->ni_tstamp.tsf); 358 (void) ieee80211_ibss_merge(ni); 359 } 360 } 361 break; 362 } 363 } 364 365 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 366 static void 367 ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m, 368 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 369 { 370 struct ath_softc *sc = ifp->if_softc; 371 372 /* Fill in the extension bitmap */ 373 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 374 375 /* Fill in the vendor header */ 376 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 377 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 378 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 379 380 /* XXX what should this be? */ 381 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 382 sc->sc_rx_th.wr_vh.vh_skip_len = 383 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 384 385 /* General version info */ 386 sc->sc_rx_th.wr_v.vh_version = 1; 387 388 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 389 390 /* rssi */ 391 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 392 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 393 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 394 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 395 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 396 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 397 398 /* evm */ 399 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 400 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 401 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 402 /* These are only populated from the AR9300 or later */ 403 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 404 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 405 406 /* direction */ 407 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 408 409 /* RX rate */ 410 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 411 412 /* RX flags */ 413 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 414 415 if (rs->rs_isaggr) 416 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 417 if (rs->rs_moreaggr) 418 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 419 420 /* phyerr info */ 421 if (rs->rs_status & HAL_RXERR_PHY) { 422 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 423 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 424 } else { 425 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 426 } 427 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 428 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 429 } 430 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 431 432 static void 433 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 434 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 435 { 436 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 437 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 438 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 439 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 440 struct ath_softc *sc = ifp->if_softc; 441 const HAL_RATE_TABLE *rt; 442 uint8_t rix; 443 444 rt = sc->sc_currates; 445 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 446 rix = rt->rateCodeToIndex[rs->rs_rate]; 447 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 448 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 449 #ifdef AH_SUPPORT_AR5416 450 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 451 if (rs->rs_status & HAL_RXERR_PHY) { 452 /* 453 * PHY error - make sure the channel flags 454 * reflect the actual channel configuration, 455 * not the received frame. 456 */ 457 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 458 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 459 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 460 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 461 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 462 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 463 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 464 struct ieee80211com *ic = ifp->if_l2com; 465 466 if ((rs->rs_flags & HAL_RX_2040) == 0) 467 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 468 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 469 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 470 else 471 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 472 if ((rs->rs_flags & HAL_RX_GI) == 0) 473 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 474 } 475 476 #endif 477 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 478 if (rs->rs_status & HAL_RXERR_CRC) 479 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 480 /* XXX propagate other error flags from descriptor */ 481 sc->sc_rx_th.wr_antnoise = nf; 482 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 483 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 484 #undef CHAN_HT 485 #undef CHAN_HT20 486 #undef CHAN_HT40U 487 #undef CHAN_HT40D 488 } 489 490 static void 491 ath_handle_micerror(struct ieee80211com *ic, 492 struct ieee80211_frame *wh, int keyix) 493 { 494 struct ieee80211_node *ni; 495 496 /* XXX recheck MIC to deal w/ chips that lie */ 497 /* XXX discard MIC errors on !data frames */ 498 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 499 if (ni != NULL) { 500 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 501 ieee80211_free_node(ni); 502 } 503 } 504 505 /* 506 * Process a single packet. 507 * 508 * The mbuf must already be synced, unmapped and removed from bf->bf_m 509 * by this stage. 510 * 511 * The mbuf must be consumed by this routine - either passed up the 512 * net80211 stack, put on the holding queue, or freed. 513 */ 514 int 515 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 516 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 517 struct mbuf *m) 518 { 519 struct ath_hal *ah = sc->sc_ah; 520 uint64_t rstamp; 521 int len, type; 522 struct ifnet *ifp = sc->sc_ifp; 523 struct ieee80211com *ic = ifp->if_l2com; 524 struct ieee80211_node *ni; 525 int is_good = 0; 526 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 527 528 /* 529 * Calculate the correct 64 bit TSF given 530 * the TSF64 register value and rs_tstamp. 531 */ 532 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 533 534 /* These aren't specifically errors */ 535 #ifdef AH_SUPPORT_AR5416 536 if (rs->rs_flags & HAL_RX_GI) 537 sc->sc_stats.ast_rx_halfgi++; 538 if (rs->rs_flags & HAL_RX_2040) 539 sc->sc_stats.ast_rx_2040++; 540 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 541 sc->sc_stats.ast_rx_pre_crc_err++; 542 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 543 sc->sc_stats.ast_rx_post_crc_err++; 544 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 545 sc->sc_stats.ast_rx_decrypt_busy_err++; 546 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 547 sc->sc_stats.ast_rx_hi_rx_chain++; 548 #endif /* AH_SUPPORT_AR5416 */ 549 550 if (rs->rs_status != 0) { 551 if (rs->rs_status & HAL_RXERR_CRC) 552 sc->sc_stats.ast_rx_crcerr++; 553 if (rs->rs_status & HAL_RXERR_FIFO) 554 sc->sc_stats.ast_rx_fifoerr++; 555 if (rs->rs_status & HAL_RXERR_PHY) { 556 sc->sc_stats.ast_rx_phyerr++; 557 /* Process DFS radar events */ 558 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 559 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 560 /* Now pass it to the radar processing code */ 561 ath_dfs_process_phy_err(sc, m, rstamp, rs); 562 } 563 564 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 565 if (rs->rs_phyerr < 64) 566 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 567 goto rx_error; /* NB: don't count in ierrors */ 568 } 569 if (rs->rs_status & HAL_RXERR_DECRYPT) { 570 /* 571 * Decrypt error. If the error occurred 572 * because there was no hardware key, then 573 * let the frame through so the upper layers 574 * can process it. This is necessary for 5210 575 * parts which have no way to setup a ``clear'' 576 * key cache entry. 577 * 578 * XXX do key cache faulting 579 */ 580 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 581 goto rx_accept; 582 sc->sc_stats.ast_rx_badcrypt++; 583 } 584 /* 585 * Similar as above - if the failure was a keymiss 586 * just punt it up to the upper layers for now. 587 */ 588 if (rs->rs_status & HAL_RXERR_KEYMISS) { 589 sc->sc_stats.ast_rx_keymiss++; 590 goto rx_accept; 591 } 592 if (rs->rs_status & HAL_RXERR_MIC) { 593 sc->sc_stats.ast_rx_badmic++; 594 /* 595 * Do minimal work required to hand off 596 * the 802.11 header for notification. 597 */ 598 /* XXX frag's and qos frames */ 599 len = rs->rs_datalen; 600 if (len >= sizeof (struct ieee80211_frame)) { 601 ath_handle_micerror(ic, 602 mtod(m, struct ieee80211_frame *), 603 sc->sc_splitmic ? 604 rs->rs_keyix-32 : rs->rs_keyix); 605 } 606 } 607 ifp->if_ierrors++; 608 rx_error: 609 /* 610 * Cleanup any pending partial frame. 611 */ 612 if (re->m_rxpending != NULL) { 613 m_freem(re->m_rxpending); 614 re->m_rxpending = NULL; 615 } 616 /* 617 * When a tap is present pass error frames 618 * that have been requested. By default we 619 * pass decrypt+mic errors but others may be 620 * interesting (e.g. crc). 621 */ 622 if (ieee80211_radiotap_active(ic) && 623 (rs->rs_status & sc->sc_monpass)) { 624 /* NB: bpf needs the mbuf length setup */ 625 len = rs->rs_datalen; 626 m->m_pkthdr.len = m->m_len = len; 627 ath_rx_tap(ifp, m, rs, rstamp, nf); 628 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 629 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 630 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 631 ieee80211_radiotap_rx_all(ic, m); 632 } 633 /* XXX pass MIC errors up for s/w reclaculation */ 634 m_freem(m); m = NULL; 635 goto rx_next; 636 } 637 rx_accept: 638 len = rs->rs_datalen; 639 m->m_len = len; 640 641 if (rs->rs_more) { 642 /* 643 * Frame spans multiple descriptors; save 644 * it for the next completed descriptor, it 645 * will be used to construct a jumbogram. 646 */ 647 if (re->m_rxpending != NULL) { 648 /* NB: max frame size is currently 2 clusters */ 649 sc->sc_stats.ast_rx_toobig++; 650 m_freem(re->m_rxpending); 651 } 652 m->m_pkthdr.rcvif = ifp; 653 m->m_pkthdr.len = len; 654 re->m_rxpending = m; 655 m = NULL; 656 goto rx_next; 657 } else if (re->m_rxpending != NULL) { 658 /* 659 * This is the second part of a jumbogram, 660 * chain it to the first mbuf, adjust the 661 * frame length, and clear the rxpending state. 662 */ 663 re->m_rxpending->m_next = m; 664 re->m_rxpending->m_pkthdr.len += len; 665 m = re->m_rxpending; 666 re->m_rxpending = NULL; 667 } else { 668 /* 669 * Normal single-descriptor receive; setup 670 * the rcvif and packet length. 671 */ 672 m->m_pkthdr.rcvif = ifp; 673 m->m_pkthdr.len = len; 674 } 675 676 /* 677 * Validate rs->rs_antenna. 678 * 679 * Some users w/ AR9285 NICs have reported crashes 680 * here because rs_antenna field is bogusly large. 681 * Let's enforce the maximum antenna limit of 8 682 * (and it shouldn't be hard coded, but that's a 683 * separate problem) and if there's an issue, print 684 * out an error and adjust rs_antenna to something 685 * sensible. 686 * 687 * This code should be removed once the actual 688 * root cause of the issue has been identified. 689 * For example, it may be that the rs_antenna 690 * field is only valid for the lsat frame of 691 * an aggregate and it just happens that it is 692 * "mostly" right. (This is a general statement - 693 * the majority of the statistics are only valid 694 * for the last frame in an aggregate. 695 */ 696 if (rs->rs_antenna > 7) { 697 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 698 __func__, rs->rs_antenna); 699 #ifdef ATH_DEBUG 700 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 701 #endif /* ATH_DEBUG */ 702 rs->rs_antenna = 0; /* XXX better than nothing */ 703 } 704 705 ifp->if_ipackets++; 706 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 707 708 /* 709 * Populate the rx status block. When there are bpf 710 * listeners we do the additional work to provide 711 * complete status. Otherwise we fill in only the 712 * material required by ieee80211_input. Note that 713 * noise setting is filled in above. 714 */ 715 if (ieee80211_radiotap_active(ic)) { 716 ath_rx_tap(ifp, m, rs, rstamp, nf); 717 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 718 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 719 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 720 } 721 722 /* 723 * From this point on we assume the frame is at least 724 * as large as ieee80211_frame_min; verify that. 725 */ 726 if (len < IEEE80211_MIN_LEN) { 727 if (!ieee80211_radiotap_active(ic)) { 728 DPRINTF(sc, ATH_DEBUG_RECV, 729 "%s: short packet %d\n", __func__, len); 730 sc->sc_stats.ast_rx_tooshort++; 731 } else { 732 /* NB: in particular this captures ack's */ 733 ieee80211_radiotap_rx_all(ic, m); 734 } 735 m_freem(m); m = NULL; 736 goto rx_next; 737 } 738 739 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 740 const HAL_RATE_TABLE *rt = sc->sc_currates; 741 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 742 743 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 744 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 745 } 746 747 m_adj(m, -IEEE80211_CRC_LEN); 748 749 /* 750 * Locate the node for sender, track state, and then 751 * pass the (referenced) node up to the 802.11 layer 752 * for its use. 753 */ 754 ni = ieee80211_find_rxnode_withkey(ic, 755 mtod(m, const struct ieee80211_frame_min *), 756 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 757 IEEE80211_KEYIX_NONE : rs->rs_keyix); 758 sc->sc_lastrs = rs; 759 760 #ifdef AH_SUPPORT_AR5416 761 if (rs->rs_isaggr) 762 sc->sc_stats.ast_rx_agg++; 763 #endif /* AH_SUPPORT_AR5416 */ 764 765 if (ni != NULL) { 766 /* 767 * Only punt packets for ampdu reorder processing for 768 * 11n nodes; net80211 enforces that M_AMPDU is only 769 * set for 11n nodes. 770 */ 771 if (ni->ni_flags & IEEE80211_NODE_HT) 772 m->m_flags |= M_AMPDU; 773 774 /* 775 * Sending station is known, dispatch directly. 776 */ 777 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 778 ieee80211_free_node(ni); 779 m = NULL; 780 /* 781 * Arrange to update the last rx timestamp only for 782 * frames from our ap when operating in station mode. 783 * This assumes the rx key is always setup when 784 * associated. 785 */ 786 if (ic->ic_opmode == IEEE80211_M_STA && 787 rs->rs_keyix != HAL_RXKEYIX_INVALID) 788 is_good = 1; 789 } else { 790 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 791 m = NULL; 792 } 793 794 /* 795 * At this point we have passed the frame up the stack; thus 796 * the mbuf is no longer ours. 797 */ 798 799 /* 800 * Track rx rssi and do any rx antenna management. 801 */ 802 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 803 if (sc->sc_diversity) { 804 /* 805 * When using fast diversity, change the default rx 806 * antenna if diversity chooses the other antenna 3 807 * times in a row. 808 */ 809 if (sc->sc_defant != rs->rs_antenna) { 810 if (++sc->sc_rxotherant >= 3) 811 ath_setdefantenna(sc, rs->rs_antenna); 812 } else 813 sc->sc_rxotherant = 0; 814 } 815 816 /* Newer school diversity - kite specific for now */ 817 /* XXX perhaps migrate the normal diversity code to this? */ 818 if ((ah)->ah_rxAntCombDiversity) 819 (*(ah)->ah_rxAntCombDiversity)(ah, rs, ticks, hz); 820 821 if (sc->sc_softled) { 822 /* 823 * Blink for any data frame. Otherwise do a 824 * heartbeat-style blink when idle. The latter 825 * is mainly for station mode where we depend on 826 * periodic beacon frames to trigger the poll event. 827 */ 828 if (type == IEEE80211_FC0_TYPE_DATA) { 829 const HAL_RATE_TABLE *rt = sc->sc_currates; 830 ath_led_event(sc, 831 rt->rateCodeToIndex[rs->rs_rate]); 832 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 833 ath_led_event(sc, 0); 834 } 835 rx_next: 836 /* 837 * Debugging - complain if we didn't NULL the mbuf pointer 838 * here. 839 */ 840 if (m != NULL) { 841 device_printf(sc->sc_dev, 842 "%s: mbuf %p should've been freed!\n", 843 __func__, 844 m); 845 } 846 return (is_good); 847 } 848 849 #define ATH_RX_MAX 128 850 851 static void 852 ath_rx_proc(struct ath_softc *sc, int resched) 853 { 854 #define PA2DESC(_sc, _pa) \ 855 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 856 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 857 struct ath_buf *bf; 858 struct ifnet *ifp = sc->sc_ifp; 859 struct ath_hal *ah = sc->sc_ah; 860 #ifdef IEEE80211_SUPPORT_SUPERG 861 struct ieee80211com *ic = ifp->if_l2com; 862 #endif 863 struct ath_desc *ds; 864 struct ath_rx_status *rs; 865 struct mbuf *m; 866 int ngood; 867 HAL_STATUS status; 868 int16_t nf; 869 u_int64_t tsf; 870 int npkts = 0; 871 int kickpcu = 0; 872 873 /* XXX we must not hold the ATH_LOCK here */ 874 ATH_UNLOCK_ASSERT(sc); 875 ATH_PCU_UNLOCK_ASSERT(sc); 876 877 ATH_PCU_LOCK(sc); 878 sc->sc_rxproc_cnt++; 879 kickpcu = sc->sc_kickpcu; 880 ATH_PCU_UNLOCK(sc); 881 882 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 883 ngood = 0; 884 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 885 sc->sc_stats.ast_rx_noise = nf; 886 tsf = ath_hal_gettsf64(ah); 887 do { 888 /* 889 * Don't process too many packets at a time; give the 890 * TX thread time to also run - otherwise the TX 891 * latency can jump by quite a bit, causing throughput 892 * degredation. 893 */ 894 if (!kickpcu && npkts >= ATH_RX_MAX) 895 break; 896 897 bf = TAILQ_FIRST(&sc->sc_rxbuf); 898 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 899 if_printf(ifp, "%s: no buffer!\n", __func__); 900 break; 901 } else if (bf == NULL) { 902 /* 903 * End of List: 904 * this can happen for non-self-linked RX chains 905 */ 906 sc->sc_stats.ast_rx_hitqueueend++; 907 break; 908 } 909 m = bf->bf_m; 910 if (m == NULL) { /* NB: shouldn't happen */ 911 /* 912 * If mbuf allocation failed previously there 913 * will be no mbuf; try again to re-populate it. 914 */ 915 /* XXX make debug msg */ 916 if_printf(ifp, "%s: no mbuf!\n", __func__); 917 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 918 goto rx_proc_next; 919 } 920 ds = bf->bf_desc; 921 if (ds->ds_link == bf->bf_daddr) { 922 /* NB: never process the self-linked entry at the end */ 923 sc->sc_stats.ast_rx_hitqueueend++; 924 break; 925 } 926 /* XXX sync descriptor memory */ 927 /* 928 * Must provide the virtual address of the current 929 * descriptor, the physical address, and the virtual 930 * address of the next descriptor in the h/w chain. 931 * This allows the HAL to look ahead to see if the 932 * hardware is done with a descriptor by checking the 933 * done bit in the following descriptor and the address 934 * of the current descriptor the DMA engine is working 935 * on. All this is necessary because of our use of 936 * a self-linked list to avoid rx overruns. 937 */ 938 rs = &bf->bf_status.ds_rxstat; 939 status = ath_hal_rxprocdesc(ah, ds, 940 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 941 #ifdef ATH_DEBUG 942 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 943 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 944 #endif 945 946 #ifdef ATH_DEBUG_ALQ 947 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 948 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 949 sc->sc_rx_statuslen, (char *) ds); 950 #endif /* ATH_DEBUG_ALQ */ 951 952 if (status == HAL_EINPROGRESS) 953 break; 954 955 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 956 npkts++; 957 958 /* 959 * Process a single frame. 960 */ 961 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 962 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 963 bf->bf_m = NULL; 964 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 965 ngood++; 966 rx_proc_next: 967 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 968 } while (ath_rxbuf_init(sc, bf) == 0); 969 970 /* rx signal state monitoring */ 971 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 972 if (ngood) 973 sc->sc_lastrx = tsf; 974 975 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 976 /* Queue DFS tasklet if needed */ 977 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 978 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 979 980 /* 981 * Now that all the RX frames were handled that 982 * need to be handled, kick the PCU if there's 983 * been an RXEOL condition. 984 */ 985 if (resched && kickpcu) { 986 ATH_PCU_LOCK(sc); 987 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 988 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 989 __func__, npkts); 990 991 /* 992 * Go through the process of fully tearing down 993 * the RX buffers and reinitialising them. 994 * 995 * There's a hardware bug that causes the RX FIFO 996 * to get confused under certain conditions and 997 * constantly write over the same frame, leading 998 * the RX driver code here to get heavily confused. 999 */ 1000 #if 1 1001 ath_startrecv(sc); 1002 #else 1003 /* 1004 * Disabled for now - it'd be nice to be able to do 1005 * this in order to limit the amount of CPU time spent 1006 * reinitialising the RX side (and thus minimise RX 1007 * drops) however there's a hardware issue that 1008 * causes things to get too far out of whack. 1009 */ 1010 /* 1011 * XXX can we hold the PCU lock here? 1012 * Are there any net80211 buffer calls involved? 1013 */ 1014 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1015 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1016 ath_hal_rxena(ah); /* enable recv descriptors */ 1017 ath_mode_init(sc); /* set filters, etc. */ 1018 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1019 #endif 1020 1021 ath_hal_intrset(ah, sc->sc_imask); 1022 sc->sc_kickpcu = 0; 1023 ATH_PCU_UNLOCK(sc); 1024 } 1025 1026 /* XXX check this inside of IF_LOCK? */ 1027 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 1028 #ifdef IEEE80211_SUPPORT_SUPERG 1029 ieee80211_ff_age_all(ic, 100); 1030 #endif 1031 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1032 ath_tx_kick(sc); 1033 } 1034 #undef PA2DESC 1035 1036 /* 1037 * If we hit the maximum number of frames in this round, 1038 * reschedule for another immediate pass. This gives 1039 * the TX and TX completion routines time to run, which 1040 * will reduce latency. 1041 */ 1042 if (npkts >= ATH_RX_MAX) 1043 sc->sc_rx.recv_sched(sc, resched); 1044 1045 ATH_PCU_LOCK(sc); 1046 sc->sc_rxproc_cnt--; 1047 ATH_PCU_UNLOCK(sc); 1048 } 1049 1050 #undef ATH_RX_MAX 1051 1052 /* 1053 * Only run the RX proc if it's not already running. 1054 * Since this may get run as part of the reset/flush path, 1055 * the task can't clash with an existing, running tasklet. 1056 */ 1057 static void 1058 ath_legacy_rx_tasklet(void *arg, int npending) 1059 { 1060 struct ath_softc *sc = arg; 1061 1062 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1063 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1064 ATH_PCU_LOCK(sc); 1065 if (sc->sc_inreset_cnt > 0) { 1066 device_printf(sc->sc_dev, 1067 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1068 ATH_PCU_UNLOCK(sc); 1069 return; 1070 } 1071 ATH_PCU_UNLOCK(sc); 1072 1073 ath_rx_proc(sc, 1); 1074 } 1075 1076 static void 1077 ath_legacy_flushrecv(struct ath_softc *sc) 1078 { 1079 1080 ath_rx_proc(sc, 0); 1081 } 1082 1083 /* 1084 * Disable the receive h/w in preparation for a reset. 1085 */ 1086 static void 1087 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1088 { 1089 #define PA2DESC(_sc, _pa) \ 1090 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1091 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1092 struct ath_hal *ah = sc->sc_ah; 1093 1094 ath_hal_stoppcurecv(ah); /* disable PCU */ 1095 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1096 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1097 /* 1098 * TODO: see if this particular DELAY() is required; it may be 1099 * masking some missing FIFO flush or DMA sync. 1100 */ 1101 #if 0 1102 if (dodelay) 1103 #endif 1104 DELAY(3000); /* 3ms is long enough for 1 frame */ 1105 #ifdef ATH_DEBUG 1106 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1107 struct ath_buf *bf; 1108 u_int ix; 1109 1110 device_printf(sc->sc_dev, 1111 "%s: rx queue %p, link %p\n", 1112 __func__, 1113 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1114 sc->sc_rxlink); 1115 ix = 0; 1116 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1117 struct ath_desc *ds = bf->bf_desc; 1118 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1119 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1120 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1121 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1122 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1123 ix++; 1124 } 1125 } 1126 #endif 1127 /* 1128 * Free both high/low RX pending, just in case. 1129 */ 1130 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1131 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1132 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1133 } 1134 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1135 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1136 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1137 } 1138 sc->sc_rxlink = NULL; /* just in case */ 1139 #undef PA2DESC 1140 } 1141 1142 /* 1143 * Enable the receive h/w following a reset. 1144 */ 1145 static int 1146 ath_legacy_startrecv(struct ath_softc *sc) 1147 { 1148 struct ath_hal *ah = sc->sc_ah; 1149 struct ath_buf *bf; 1150 1151 sc->sc_rxlink = NULL; 1152 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1153 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1154 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1155 int error = ath_rxbuf_init(sc, bf); 1156 if (error != 0) { 1157 DPRINTF(sc, ATH_DEBUG_RECV, 1158 "%s: ath_rxbuf_init failed %d\n", 1159 __func__, error); 1160 return error; 1161 } 1162 } 1163 1164 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1165 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1166 ath_hal_rxena(ah); /* enable recv descriptors */ 1167 ath_mode_init(sc); /* set filters, etc. */ 1168 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1169 return 0; 1170 } 1171 1172 static int 1173 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1174 { 1175 int error; 1176 1177 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1178 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1179 if (error != 0) 1180 return (error); 1181 1182 return (0); 1183 } 1184 1185 static int 1186 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1187 { 1188 1189 if (sc->sc_rxdma.dd_desc_len != 0) 1190 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1191 return (0); 1192 } 1193 1194 static void 1195 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1196 { 1197 1198 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1199 } 1200 1201 static void 1202 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1203 int dosched) 1204 { 1205 1206 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1207 } 1208 1209 void 1210 ath_recv_setup_legacy(struct ath_softc *sc) 1211 { 1212 1213 /* Sensible legacy defaults */ 1214 /* 1215 * XXX this should be changed to properly support the 1216 * exact RX descriptor size for each HAL. 1217 */ 1218 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1219 1220 sc->sc_rx.recv_start = ath_legacy_startrecv; 1221 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1222 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1223 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1224 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1225 1226 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1227 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1228 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1229 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1230 } 1231