1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_var.h> 77 #include <net/if_dl.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_arp.h> 81 #include <net/ethernet.h> 82 #include <net/if_llc.h> 83 84 #include <net80211/ieee80211_var.h> 85 #include <net80211/ieee80211_regdomain.h> 86 #ifdef IEEE80211_SUPPORT_SUPERG 87 #include <net80211/ieee80211_superg.h> 88 #endif 89 #ifdef IEEE80211_SUPPORT_TDMA 90 #include <net80211/ieee80211_tdma.h> 91 #endif 92 93 #include <net/bpf.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #include <dev/ath/if_athvar.h> 101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 102 #include <dev/ath/ath_hal/ah_diagcodes.h> 103 104 #include <dev/ath/if_ath_debug.h> 105 #include <dev/ath/if_ath_misc.h> 106 #include <dev/ath/if_ath_tsf.h> 107 #include <dev/ath/if_ath_tx.h> 108 #include <dev/ath/if_ath_sysctl.h> 109 #include <dev/ath/if_ath_led.h> 110 #include <dev/ath/if_ath_keycache.h> 111 #include <dev/ath/if_ath_rx.h> 112 #include <dev/ath/if_ath_beacon.h> 113 #include <dev/ath/if_athdfs.h> 114 115 #ifdef ATH_TX99_DIAG 116 #include <dev/ath/ath_tx99/ath_tx99.h> 117 #endif 118 119 #ifdef ATH_DEBUG_ALQ 120 #include <dev/ath/if_ath_alq.h> 121 #endif 122 123 #include <dev/ath/if_ath_lna_div.h> 124 125 /* 126 * Calculate the receive filter according to the 127 * operating mode and state: 128 * 129 * o always accept unicast, broadcast, and multicast traffic 130 * o accept PHY error frames when hardware doesn't have MIB support 131 * to count and we need them for ANI (sta mode only until recently) 132 * and we are not scanning (ANI is disabled) 133 * NB: older hal's add rx filter bits out of sight and we need to 134 * blindly preserve them 135 * o probe request frames are accepted only when operating in 136 * hostap, adhoc, mesh, or monitor modes 137 * o enable promiscuous mode 138 * - when in monitor mode 139 * - if interface marked PROMISC (assumes bridge setting is filtered) 140 * o accept beacons: 141 * - when operating in station mode for collecting rssi data when 142 * the station is otherwise quiet, or 143 * - when operating in adhoc mode so the 802.11 layer creates 144 * node table entries for peers, 145 * - when scanning 146 * - when doing s/w beacon miss (e.g. for ap+sta) 147 * - when operating in ap mode in 11g to detect overlapping bss that 148 * require protection 149 * - when operating in mesh mode to detect neighbors 150 * o accept control frames: 151 * - when in monitor mode 152 * XXX HT protection for 11n 153 */ 154 u_int32_t 155 ath_calcrxfilter(struct ath_softc *sc) 156 { 157 struct ieee80211com *ic = &sc->sc_ic; 158 u_int32_t rfilt; 159 160 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 161 if (!sc->sc_needmib && !sc->sc_scanning) 162 rfilt |= HAL_RX_FILTER_PHYERR; 163 if (ic->ic_opmode != IEEE80211_M_STA) 164 rfilt |= HAL_RX_FILTER_PROBEREQ; 165 /* XXX ic->ic_monvaps != 0? */ 166 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0) 167 rfilt |= HAL_RX_FILTER_PROM; 168 169 /* 170 * Only listen to all beacons if we're scanning. 171 * 172 * Otherwise we only really need to hear beacons from 173 * our own BSSID. 174 */ 175 if (ic->ic_opmode == IEEE80211_M_STA || 176 ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 177 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 178 rfilt |= HAL_RX_FILTER_MYBEACON; 179 } else { /* scanning, non-mybeacon chips */ 180 rfilt |= HAL_RX_FILTER_BEACON; 181 } 182 } 183 184 /* 185 * NB: We don't recalculate the rx filter when 186 * ic_protmode changes; otherwise we could do 187 * this only when ic_protmode != NONE. 188 */ 189 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 190 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 191 rfilt |= HAL_RX_FILTER_BEACON; 192 193 /* 194 * Enable hardware PS-POLL RX only for hostap mode; 195 * STA mode sends PS-POLL frames but never 196 * receives them. 197 */ 198 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 199 0, NULL) == HAL_OK && 200 ic->ic_opmode == IEEE80211_M_HOSTAP) 201 rfilt |= HAL_RX_FILTER_PSPOLL; 202 203 if (sc->sc_nmeshvaps) { 204 rfilt |= HAL_RX_FILTER_BEACON; 205 if (sc->sc_hasbmatch) 206 rfilt |= HAL_RX_FILTER_BSSID; 207 else 208 rfilt |= HAL_RX_FILTER_PROM; 209 } 210 if (ic->ic_opmode == IEEE80211_M_MONITOR) 211 rfilt |= HAL_RX_FILTER_CONTROL; 212 213 /* 214 * Enable RX of compressed BAR frames only when doing 215 * 802.11n. Required for A-MPDU. 216 */ 217 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 218 rfilt |= HAL_RX_FILTER_COMPBAR; 219 220 /* 221 * Enable radar PHY errors if requested by the 222 * DFS module. 223 */ 224 if (sc->sc_dodfs) 225 rfilt |= HAL_RX_FILTER_PHYRADAR; 226 227 /* 228 * Enable spectral PHY errors if requested by the 229 * spectral module. 230 */ 231 if (sc->sc_dospectral) 232 rfilt |= HAL_RX_FILTER_PHYRADAR; 233 234 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n", 235 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]); 236 return rfilt; 237 } 238 239 static int 240 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 241 { 242 struct ath_hal *ah = sc->sc_ah; 243 int error; 244 struct mbuf *m; 245 struct ath_desc *ds; 246 247 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 248 249 m = bf->bf_m; 250 if (m == NULL) { 251 /* 252 * NB: by assigning a page to the rx dma buffer we 253 * implicitly satisfy the Atheros requirement that 254 * this buffer be cache-line-aligned and sized to be 255 * multiple of the cache line size. Not doing this 256 * causes weird stuff to happen (for the 5210 at least). 257 */ 258 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 259 if (m == NULL) { 260 DPRINTF(sc, ATH_DEBUG_ANY, 261 "%s: no mbuf/cluster\n", __func__); 262 sc->sc_stats.ast_rx_nombuf++; 263 return ENOMEM; 264 } 265 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 266 267 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 268 bf->bf_dmamap, m, 269 bf->bf_segs, &bf->bf_nseg, 270 BUS_DMA_NOWAIT); 271 if (error != 0) { 272 DPRINTF(sc, ATH_DEBUG_ANY, 273 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 274 __func__, error); 275 sc->sc_stats.ast_rx_busdma++; 276 m_freem(m); 277 return error; 278 } 279 KASSERT(bf->bf_nseg == 1, 280 ("multi-segment packet; nseg %u", bf->bf_nseg)); 281 bf->bf_m = m; 282 } 283 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 284 285 /* 286 * Setup descriptors. For receive we always terminate 287 * the descriptor list with a self-linked entry so we'll 288 * not get overrun under high load (as can happen with a 289 * 5212 when ANI processing enables PHY error frames). 290 * 291 * To insure the last descriptor is self-linked we create 292 * each descriptor as self-linked and add it to the end. As 293 * each additional descriptor is added the previous self-linked 294 * entry is ``fixed'' naturally. This should be safe even 295 * if DMA is happening. When processing RX interrupts we 296 * never remove/process the last, self-linked, entry on the 297 * descriptor list. This insures the hardware always has 298 * someplace to write a new frame. 299 */ 300 /* 301 * 11N: we can no longer afford to self link the last descriptor. 302 * MAC acknowledges BA status as long as it copies frames to host 303 * buffer (or rx fifo). This can incorrectly acknowledge packets 304 * to a sender if last desc is self-linked. 305 */ 306 ds = bf->bf_desc; 307 if (sc->sc_rxslink) 308 ds->ds_link = bf->bf_daddr; /* link to self */ 309 else 310 ds->ds_link = 0; /* terminate the list */ 311 ds->ds_data = bf->bf_segs[0].ds_addr; 312 ath_hal_setuprxdesc(ah, ds 313 , m->m_len /* buffer size */ 314 , 0 315 ); 316 317 if (sc->sc_rxlink != NULL) 318 *sc->sc_rxlink = bf->bf_daddr; 319 sc->sc_rxlink = &ds->ds_link; 320 return 0; 321 } 322 323 /* 324 * Intercept management frames to collect beacon rssi data 325 * and to do ibss merges. 326 */ 327 void 328 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 329 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) 330 { 331 struct ieee80211vap *vap = ni->ni_vap; 332 struct ath_softc *sc = vap->iv_ic->ic_softc; 333 uint64_t tsf_beacon_old, tsf_beacon; 334 uint64_t nexttbtt; 335 int64_t tsf_delta; 336 int32_t tsf_delta_bmiss; 337 int32_t tsf_remainder; 338 uint64_t tsf_beacon_target; 339 int tsf_intval; 340 341 tsf_beacon_old = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 342 tsf_beacon_old |= LE_READ_4(ni->ni_tstamp.data); 343 344 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 345 tsf_intval = 1; 346 if (ni->ni_intval > 0) { 347 tsf_intval = TU_TO_TSF(ni->ni_intval); 348 } 349 #undef TU_TO_TSF 350 351 /* 352 * Call up first so subsequent work can use information 353 * potentially stored in the node (e.g. for ibss merge). 354 */ 355 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf); 356 switch (subtype) { 357 case IEEE80211_FC0_SUBTYPE_BEACON: 358 /* update rssi statistics for use by the hal */ 359 /* XXX unlocked check against vap->iv_bss? */ 360 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 361 362 tsf_beacon = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 363 tsf_beacon |= LE_READ_4(ni->ni_tstamp.data); 364 365 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 366 367 /* 368 * Let's calculate the delta and remainder, so we can see 369 * if the beacon timer from the AP is varying by more than 370 * a few TU. (Which would be a huge, huge problem.) 371 */ 372 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 373 374 tsf_delta_bmiss = tsf_delta / tsf_intval; 375 376 /* 377 * If our delta is greater than half the beacon interval, 378 * let's round the bmiss value up to the next beacon 379 * interval. Ie, we're running really, really early 380 * on the next beacon. 381 */ 382 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 383 tsf_delta_bmiss ++; 384 385 tsf_beacon_target = tsf_beacon_old + 386 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 387 388 /* 389 * The remainder using '%' is between 0 .. intval-1. 390 * If we're actually running too fast, then the remainder 391 * will be some large number just under intval-1. 392 * So we need to look at whether we're running 393 * before or after the target beacon interval 394 * and if we are, modify how we do the remainder 395 * calculation. 396 */ 397 if (tsf_beacon < tsf_beacon_target) { 398 tsf_remainder = 399 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 400 } else { 401 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 402 } 403 404 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu, new_tsf=%llu, target_tsf=%llu, delta=%lld, bmiss=%d, remainder=%d\n", 405 __func__, 406 (unsigned long long) tsf_beacon_old, 407 (unsigned long long) tsf_beacon, 408 (unsigned long long) tsf_beacon_target, 409 (long long) tsf_delta, 410 tsf_delta_bmiss, 411 tsf_remainder); 412 413 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu, nexttbtt=%llu, delta=%d\n", 414 __func__, 415 (unsigned long long) tsf_beacon, 416 (unsigned long long) nexttbtt, 417 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 418 419 if (sc->sc_syncbeacon && 420 ni == vap->iv_bss && 421 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 422 DPRINTF(sc, ATH_DEBUG_BEACON, 423 "%s: syncbeacon=1; syncing\n", 424 __func__); 425 /* 426 * Resync beacon timers using the tsf of the beacon 427 * frame we just received. 428 */ 429 ath_beacon_config(sc, vap); 430 sc->sc_syncbeacon = 0; 431 } 432 433 434 /* fall thru... */ 435 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 436 if (vap->iv_opmode == IEEE80211_M_IBSS && 437 vap->iv_state == IEEE80211_S_RUN) { 438 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 439 uint64_t tsf = ath_extend_tsf(sc, rstamp, 440 ath_hal_gettsf64(sc->sc_ah)); 441 /* 442 * Handle ibss merge as needed; check the tsf on the 443 * frame before attempting the merge. The 802.11 spec 444 * says the station should change it's bssid to match 445 * the oldest station with the same ssid, where oldest 446 * is determined by the tsf. Note that hardware 447 * reconfiguration happens through callback to 448 * ath_newstate as the state machine will go from 449 * RUN -> RUN when this happens. 450 */ 451 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 452 DPRINTF(sc, ATH_DEBUG_STATE, 453 "ibss merge, rstamp %u tsf %ju " 454 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 455 (uintmax_t)ni->ni_tstamp.tsf); 456 (void) ieee80211_ibss_merge(ni); 457 } 458 } 459 break; 460 } 461 } 462 463 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 464 static void 465 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m, 466 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 467 { 468 469 /* Fill in the extension bitmap */ 470 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 471 472 /* Fill in the vendor header */ 473 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 474 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 475 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 476 477 /* XXX what should this be? */ 478 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 479 sc->sc_rx_th.wr_vh.vh_skip_len = 480 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 481 482 /* General version info */ 483 sc->sc_rx_th.wr_v.vh_version = 1; 484 485 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 486 487 /* rssi */ 488 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 489 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 490 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 491 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 492 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 493 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 494 495 /* evm */ 496 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 497 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 498 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 499 /* These are only populated from the AR9300 or later */ 500 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 501 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 502 503 /* direction */ 504 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 505 506 /* RX rate */ 507 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 508 509 /* RX flags */ 510 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 511 512 if (rs->rs_isaggr) 513 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 514 if (rs->rs_moreaggr) 515 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 516 517 /* phyerr info */ 518 if (rs->rs_status & HAL_RXERR_PHY) { 519 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 520 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 521 } else { 522 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 523 } 524 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 525 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 526 } 527 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 528 529 static void 530 ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 531 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 532 { 533 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 534 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 535 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 536 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 537 const HAL_RATE_TABLE *rt; 538 uint8_t rix; 539 540 rt = sc->sc_currates; 541 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 542 rix = rt->rateCodeToIndex[rs->rs_rate]; 543 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 544 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 545 #ifdef AH_SUPPORT_AR5416 546 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 547 if (rs->rs_status & HAL_RXERR_PHY) { 548 /* 549 * PHY error - make sure the channel flags 550 * reflect the actual channel configuration, 551 * not the received frame. 552 */ 553 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 554 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 555 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 556 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 557 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 558 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 559 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 560 struct ieee80211com *ic = &sc->sc_ic; 561 562 if ((rs->rs_flags & HAL_RX_2040) == 0) 563 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 564 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 565 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 566 else 567 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 568 if ((rs->rs_flags & HAL_RX_GI) == 0) 569 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 570 } 571 572 #endif 573 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 574 if (rs->rs_status & HAL_RXERR_CRC) 575 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 576 /* XXX propagate other error flags from descriptor */ 577 sc->sc_rx_th.wr_antnoise = nf; 578 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 579 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 580 #undef CHAN_HT 581 #undef CHAN_HT20 582 #undef CHAN_HT40U 583 #undef CHAN_HT40D 584 } 585 586 static void 587 ath_handle_micerror(struct ieee80211com *ic, 588 struct ieee80211_frame *wh, int keyix) 589 { 590 struct ieee80211_node *ni; 591 592 /* XXX recheck MIC to deal w/ chips that lie */ 593 /* XXX discard MIC errors on !data frames */ 594 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 595 if (ni != NULL) { 596 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 597 ieee80211_free_node(ni); 598 } 599 } 600 601 /* 602 * Process a single packet. 603 * 604 * The mbuf must already be synced, unmapped and removed from bf->bf_m 605 * by this stage. 606 * 607 * The mbuf must be consumed by this routine - either passed up the 608 * net80211 stack, put on the holding queue, or freed. 609 */ 610 int 611 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 612 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 613 struct mbuf *m) 614 { 615 uint64_t rstamp; 616 int len, type; 617 struct ieee80211com *ic = &sc->sc_ic; 618 struct ieee80211_node *ni; 619 int is_good = 0; 620 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 621 622 /* 623 * Calculate the correct 64 bit TSF given 624 * the TSF64 register value and rs_tstamp. 625 */ 626 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 627 628 /* These aren't specifically errors */ 629 #ifdef AH_SUPPORT_AR5416 630 if (rs->rs_flags & HAL_RX_GI) 631 sc->sc_stats.ast_rx_halfgi++; 632 if (rs->rs_flags & HAL_RX_2040) 633 sc->sc_stats.ast_rx_2040++; 634 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 635 sc->sc_stats.ast_rx_pre_crc_err++; 636 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 637 sc->sc_stats.ast_rx_post_crc_err++; 638 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 639 sc->sc_stats.ast_rx_decrypt_busy_err++; 640 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 641 sc->sc_stats.ast_rx_hi_rx_chain++; 642 if (rs->rs_flags & HAL_RX_STBC) 643 sc->sc_stats.ast_rx_stbc++; 644 #endif /* AH_SUPPORT_AR5416 */ 645 646 if (rs->rs_status != 0) { 647 if (rs->rs_status & HAL_RXERR_CRC) 648 sc->sc_stats.ast_rx_crcerr++; 649 if (rs->rs_status & HAL_RXERR_FIFO) 650 sc->sc_stats.ast_rx_fifoerr++; 651 if (rs->rs_status & HAL_RXERR_PHY) { 652 sc->sc_stats.ast_rx_phyerr++; 653 /* Process DFS radar events */ 654 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 655 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 656 /* Now pass it to the radar processing code */ 657 ath_dfs_process_phy_err(sc, m, rstamp, rs); 658 } 659 660 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 661 if (rs->rs_phyerr < 64) 662 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 663 goto rx_error; /* NB: don't count in ierrors */ 664 } 665 if (rs->rs_status & HAL_RXERR_DECRYPT) { 666 /* 667 * Decrypt error. If the error occurred 668 * because there was no hardware key, then 669 * let the frame through so the upper layers 670 * can process it. This is necessary for 5210 671 * parts which have no way to setup a ``clear'' 672 * key cache entry. 673 * 674 * XXX do key cache faulting 675 */ 676 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 677 goto rx_accept; 678 sc->sc_stats.ast_rx_badcrypt++; 679 } 680 /* 681 * Similar as above - if the failure was a keymiss 682 * just punt it up to the upper layers for now. 683 */ 684 if (rs->rs_status & HAL_RXERR_KEYMISS) { 685 sc->sc_stats.ast_rx_keymiss++; 686 goto rx_accept; 687 } 688 if (rs->rs_status & HAL_RXERR_MIC) { 689 sc->sc_stats.ast_rx_badmic++; 690 /* 691 * Do minimal work required to hand off 692 * the 802.11 header for notification. 693 */ 694 /* XXX frag's and qos frames */ 695 len = rs->rs_datalen; 696 if (len >= sizeof (struct ieee80211_frame)) { 697 ath_handle_micerror(ic, 698 mtod(m, struct ieee80211_frame *), 699 sc->sc_splitmic ? 700 rs->rs_keyix-32 : rs->rs_keyix); 701 } 702 } 703 counter_u64_add(ic->ic_ierrors, 1); 704 rx_error: 705 /* 706 * Cleanup any pending partial frame. 707 */ 708 if (re->m_rxpending != NULL) { 709 m_freem(re->m_rxpending); 710 re->m_rxpending = NULL; 711 } 712 /* 713 * When a tap is present pass error frames 714 * that have been requested. By default we 715 * pass decrypt+mic errors but others may be 716 * interesting (e.g. crc). 717 */ 718 if (ieee80211_radiotap_active(ic) && 719 (rs->rs_status & sc->sc_monpass)) { 720 /* NB: bpf needs the mbuf length setup */ 721 len = rs->rs_datalen; 722 m->m_pkthdr.len = m->m_len = len; 723 ath_rx_tap(sc, m, rs, rstamp, nf); 724 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 725 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 726 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 727 ieee80211_radiotap_rx_all(ic, m); 728 } 729 /* XXX pass MIC errors up for s/w reclaculation */ 730 m_freem(m); m = NULL; 731 goto rx_next; 732 } 733 rx_accept: 734 len = rs->rs_datalen; 735 m->m_len = len; 736 737 if (rs->rs_more) { 738 /* 739 * Frame spans multiple descriptors; save 740 * it for the next completed descriptor, it 741 * will be used to construct a jumbogram. 742 */ 743 if (re->m_rxpending != NULL) { 744 /* NB: max frame size is currently 2 clusters */ 745 sc->sc_stats.ast_rx_toobig++; 746 m_freem(re->m_rxpending); 747 } 748 m->m_pkthdr.len = len; 749 re->m_rxpending = m; 750 m = NULL; 751 goto rx_next; 752 } else if (re->m_rxpending != NULL) { 753 /* 754 * This is the second part of a jumbogram, 755 * chain it to the first mbuf, adjust the 756 * frame length, and clear the rxpending state. 757 */ 758 re->m_rxpending->m_next = m; 759 re->m_rxpending->m_pkthdr.len += len; 760 m = re->m_rxpending; 761 re->m_rxpending = NULL; 762 } else { 763 /* 764 * Normal single-descriptor receive; setup packet length. 765 */ 766 m->m_pkthdr.len = len; 767 } 768 769 /* 770 * Validate rs->rs_antenna. 771 * 772 * Some users w/ AR9285 NICs have reported crashes 773 * here because rs_antenna field is bogusly large. 774 * Let's enforce the maximum antenna limit of 8 775 * (and it shouldn't be hard coded, but that's a 776 * separate problem) and if there's an issue, print 777 * out an error and adjust rs_antenna to something 778 * sensible. 779 * 780 * This code should be removed once the actual 781 * root cause of the issue has been identified. 782 * For example, it may be that the rs_antenna 783 * field is only valid for the lsat frame of 784 * an aggregate and it just happens that it is 785 * "mostly" right. (This is a general statement - 786 * the majority of the statistics are only valid 787 * for the last frame in an aggregate. 788 */ 789 if (rs->rs_antenna > 7) { 790 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 791 __func__, rs->rs_antenna); 792 #ifdef ATH_DEBUG 793 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 794 #endif /* ATH_DEBUG */ 795 rs->rs_antenna = 0; /* XXX better than nothing */ 796 } 797 798 /* 799 * If this is an AR9285/AR9485, then the receive and LNA 800 * configuration is stored in RSSI[2] / EXTRSSI[2]. 801 * We can extract this out to build a much better 802 * receive antenna profile. 803 * 804 * Yes, this just blurts over the above RX antenna field 805 * for now. It's fine, the AR9285 doesn't really use 806 * that. 807 * 808 * Later on we should store away the fine grained LNA 809 * information and keep separate counters just for 810 * that. It'll help when debugging the AR9285/AR9485 811 * combined diversity code. 812 */ 813 if (sc->sc_rx_lnamixer) { 814 rs->rs_antenna = 0; 815 816 /* Bits 0:1 - the LNA configuration used */ 817 rs->rs_antenna |= 818 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 819 >> HAL_RX_LNA_CFG_USED_S); 820 821 /* Bit 2 - the external RX antenna switch */ 822 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 823 rs->rs_antenna |= 0x4; 824 } 825 826 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 827 828 /* 829 * Populate the rx status block. When there are bpf 830 * listeners we do the additional work to provide 831 * complete status. Otherwise we fill in only the 832 * material required by ieee80211_input. Note that 833 * noise setting is filled in above. 834 */ 835 if (ieee80211_radiotap_active(ic)) { 836 ath_rx_tap(sc, m, rs, rstamp, nf); 837 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 838 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 839 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 840 } 841 842 /* 843 * From this point on we assume the frame is at least 844 * as large as ieee80211_frame_min; verify that. 845 */ 846 if (len < IEEE80211_MIN_LEN) { 847 if (!ieee80211_radiotap_active(ic)) { 848 DPRINTF(sc, ATH_DEBUG_RECV, 849 "%s: short packet %d\n", __func__, len); 850 sc->sc_stats.ast_rx_tooshort++; 851 } else { 852 /* NB: in particular this captures ack's */ 853 ieee80211_radiotap_rx_all(ic, m); 854 } 855 m_freem(m); m = NULL; 856 goto rx_next; 857 } 858 859 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 860 const HAL_RATE_TABLE *rt = sc->sc_currates; 861 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 862 863 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 864 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 865 } 866 867 m_adj(m, -IEEE80211_CRC_LEN); 868 869 /* 870 * Locate the node for sender, track state, and then 871 * pass the (referenced) node up to the 802.11 layer 872 * for its use. 873 */ 874 ni = ieee80211_find_rxnode_withkey(ic, 875 mtod(m, const struct ieee80211_frame_min *), 876 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 877 IEEE80211_KEYIX_NONE : rs->rs_keyix); 878 sc->sc_lastrs = rs; 879 880 #ifdef AH_SUPPORT_AR5416 881 if (rs->rs_isaggr) 882 sc->sc_stats.ast_rx_agg++; 883 #endif /* AH_SUPPORT_AR5416 */ 884 885 if (ni != NULL) { 886 /* 887 * Only punt packets for ampdu reorder processing for 888 * 11n nodes; net80211 enforces that M_AMPDU is only 889 * set for 11n nodes. 890 */ 891 if (ni->ni_flags & IEEE80211_NODE_HT) 892 m->m_flags |= M_AMPDU; 893 894 /* 895 * Sending station is known, dispatch directly. 896 */ 897 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 898 ieee80211_free_node(ni); 899 m = NULL; 900 /* 901 * Arrange to update the last rx timestamp only for 902 * frames from our ap when operating in station mode. 903 * This assumes the rx key is always setup when 904 * associated. 905 */ 906 if (ic->ic_opmode == IEEE80211_M_STA && 907 rs->rs_keyix != HAL_RXKEYIX_INVALID) 908 is_good = 1; 909 } else { 910 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 911 m = NULL; 912 } 913 914 /* 915 * At this point we have passed the frame up the stack; thus 916 * the mbuf is no longer ours. 917 */ 918 919 /* 920 * Track rx rssi and do any rx antenna management. 921 */ 922 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 923 if (sc->sc_diversity) { 924 /* 925 * When using fast diversity, change the default rx 926 * antenna if diversity chooses the other antenna 3 927 * times in a row. 928 */ 929 if (sc->sc_defant != rs->rs_antenna) { 930 if (++sc->sc_rxotherant >= 3) 931 ath_setdefantenna(sc, rs->rs_antenna); 932 } else 933 sc->sc_rxotherant = 0; 934 } 935 936 /* Handle slow diversity if enabled */ 937 if (sc->sc_dolnadiv) { 938 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 939 } 940 941 if (sc->sc_softled) { 942 /* 943 * Blink for any data frame. Otherwise do a 944 * heartbeat-style blink when idle. The latter 945 * is mainly for station mode where we depend on 946 * periodic beacon frames to trigger the poll event. 947 */ 948 if (type == IEEE80211_FC0_TYPE_DATA) { 949 const HAL_RATE_TABLE *rt = sc->sc_currates; 950 ath_led_event(sc, 951 rt->rateCodeToIndex[rs->rs_rate]); 952 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 953 ath_led_event(sc, 0); 954 } 955 rx_next: 956 /* 957 * Debugging - complain if we didn't NULL the mbuf pointer 958 * here. 959 */ 960 if (m != NULL) { 961 device_printf(sc->sc_dev, 962 "%s: mbuf %p should've been freed!\n", 963 __func__, 964 m); 965 } 966 return (is_good); 967 } 968 969 #define ATH_RX_MAX 128 970 971 /* 972 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 973 * the EDMA code does. 974 * 975 * XXX TODO: then, do all of the RX list management stuff inside 976 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 977 * code is doing it right. 978 */ 979 static void 980 ath_rx_proc(struct ath_softc *sc, int resched) 981 { 982 #define PA2DESC(_sc, _pa) \ 983 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 984 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 985 struct ath_buf *bf; 986 struct ath_hal *ah = sc->sc_ah; 987 #ifdef IEEE80211_SUPPORT_SUPERG 988 struct ieee80211com *ic = &sc->sc_ic; 989 #endif 990 struct ath_desc *ds; 991 struct ath_rx_status *rs; 992 struct mbuf *m; 993 int ngood; 994 HAL_STATUS status; 995 int16_t nf; 996 u_int64_t tsf; 997 int npkts = 0; 998 int kickpcu = 0; 999 int ret; 1000 1001 /* XXX we must not hold the ATH_LOCK here */ 1002 ATH_UNLOCK_ASSERT(sc); 1003 ATH_PCU_UNLOCK_ASSERT(sc); 1004 1005 ATH_PCU_LOCK(sc); 1006 sc->sc_rxproc_cnt++; 1007 kickpcu = sc->sc_kickpcu; 1008 ATH_PCU_UNLOCK(sc); 1009 1010 ATH_LOCK(sc); 1011 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1012 ATH_UNLOCK(sc); 1013 1014 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1015 ngood = 0; 1016 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1017 sc->sc_stats.ast_rx_noise = nf; 1018 tsf = ath_hal_gettsf64(ah); 1019 do { 1020 /* 1021 * Don't process too many packets at a time; give the 1022 * TX thread time to also run - otherwise the TX 1023 * latency can jump by quite a bit, causing throughput 1024 * degredation. 1025 */ 1026 if (!kickpcu && npkts >= ATH_RX_MAX) 1027 break; 1028 1029 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1030 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1031 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__); 1032 break; 1033 } else if (bf == NULL) { 1034 /* 1035 * End of List: 1036 * this can happen for non-self-linked RX chains 1037 */ 1038 sc->sc_stats.ast_rx_hitqueueend++; 1039 break; 1040 } 1041 m = bf->bf_m; 1042 if (m == NULL) { /* NB: shouldn't happen */ 1043 /* 1044 * If mbuf allocation failed previously there 1045 * will be no mbuf; try again to re-populate it. 1046 */ 1047 /* XXX make debug msg */ 1048 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__); 1049 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1050 goto rx_proc_next; 1051 } 1052 ds = bf->bf_desc; 1053 if (ds->ds_link == bf->bf_daddr) { 1054 /* NB: never process the self-linked entry at the end */ 1055 sc->sc_stats.ast_rx_hitqueueend++; 1056 break; 1057 } 1058 /* XXX sync descriptor memory */ 1059 /* 1060 * Must provide the virtual address of the current 1061 * descriptor, the physical address, and the virtual 1062 * address of the next descriptor in the h/w chain. 1063 * This allows the HAL to look ahead to see if the 1064 * hardware is done with a descriptor by checking the 1065 * done bit in the following descriptor and the address 1066 * of the current descriptor the DMA engine is working 1067 * on. All this is necessary because of our use of 1068 * a self-linked list to avoid rx overruns. 1069 */ 1070 rs = &bf->bf_status.ds_rxstat; 1071 status = ath_hal_rxprocdesc(ah, ds, 1072 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1073 #ifdef ATH_DEBUG 1074 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1075 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1076 #endif 1077 1078 #ifdef ATH_DEBUG_ALQ 1079 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1080 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1081 sc->sc_rx_statuslen, (char *) ds); 1082 #endif /* ATH_DEBUG_ALQ */ 1083 1084 if (status == HAL_EINPROGRESS) 1085 break; 1086 1087 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1088 npkts++; 1089 1090 /* 1091 * Process a single frame. 1092 */ 1093 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1094 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1095 bf->bf_m = NULL; 1096 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1097 ngood++; 1098 rx_proc_next: 1099 /* 1100 * If there's a holding buffer, insert that onto 1101 * the RX list; the hardware is now definitely not pointing 1102 * to it now. 1103 */ 1104 ret = 0; 1105 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1106 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1107 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1108 bf_list); 1109 ret = ath_rxbuf_init(sc, 1110 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1111 } 1112 /* 1113 * Next, throw our buffer into the holding entry. The hardware 1114 * may use the descriptor to read the link pointer before 1115 * DMAing the next descriptor in to write out a packet. 1116 */ 1117 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1118 } while (ret == 0); 1119 1120 /* rx signal state monitoring */ 1121 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1122 if (ngood) 1123 sc->sc_lastrx = tsf; 1124 1125 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1126 /* Queue DFS tasklet if needed */ 1127 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1128 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1129 1130 /* 1131 * Now that all the RX frames were handled that 1132 * need to be handled, kick the PCU if there's 1133 * been an RXEOL condition. 1134 */ 1135 if (resched && kickpcu) { 1136 ATH_PCU_LOCK(sc); 1137 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1138 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1139 __func__, npkts); 1140 1141 /* 1142 * Go through the process of fully tearing down 1143 * the RX buffers and reinitialising them. 1144 * 1145 * There's a hardware bug that causes the RX FIFO 1146 * to get confused under certain conditions and 1147 * constantly write over the same frame, leading 1148 * the RX driver code here to get heavily confused. 1149 */ 1150 /* 1151 * XXX Has RX DMA stopped enough here to just call 1152 * ath_startrecv()? 1153 * XXX Do we need to use the holding buffer to restart 1154 * RX DMA by appending entries to the final 1155 * descriptor? Quite likely. 1156 */ 1157 #if 1 1158 ath_startrecv(sc); 1159 #else 1160 /* 1161 * Disabled for now - it'd be nice to be able to do 1162 * this in order to limit the amount of CPU time spent 1163 * reinitialising the RX side (and thus minimise RX 1164 * drops) however there's a hardware issue that 1165 * causes things to get too far out of whack. 1166 */ 1167 /* 1168 * XXX can we hold the PCU lock here? 1169 * Are there any net80211 buffer calls involved? 1170 */ 1171 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1172 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1173 ath_hal_rxena(ah); /* enable recv descriptors */ 1174 ath_mode_init(sc); /* set filters, etc. */ 1175 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1176 #endif 1177 1178 ath_hal_intrset(ah, sc->sc_imask); 1179 sc->sc_kickpcu = 0; 1180 ATH_PCU_UNLOCK(sc); 1181 } 1182 1183 #ifdef IEEE80211_SUPPORT_SUPERG 1184 if (resched) 1185 ieee80211_ff_age_all(ic, 100); 1186 #endif 1187 1188 /* 1189 * Put the hardware to sleep again if we're done with it. 1190 */ 1191 ATH_LOCK(sc); 1192 ath_power_restore_power_state(sc); 1193 ATH_UNLOCK(sc); 1194 1195 /* 1196 * If we hit the maximum number of frames in this round, 1197 * reschedule for another immediate pass. This gives 1198 * the TX and TX completion routines time to run, which 1199 * will reduce latency. 1200 */ 1201 if (npkts >= ATH_RX_MAX) 1202 sc->sc_rx.recv_sched(sc, resched); 1203 1204 ATH_PCU_LOCK(sc); 1205 sc->sc_rxproc_cnt--; 1206 ATH_PCU_UNLOCK(sc); 1207 } 1208 #undef PA2DESC 1209 #undef ATH_RX_MAX 1210 1211 /* 1212 * Only run the RX proc if it's not already running. 1213 * Since this may get run as part of the reset/flush path, 1214 * the task can't clash with an existing, running tasklet. 1215 */ 1216 static void 1217 ath_legacy_rx_tasklet(void *arg, int npending) 1218 { 1219 struct ath_softc *sc = arg; 1220 1221 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1222 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1223 ATH_PCU_LOCK(sc); 1224 if (sc->sc_inreset_cnt > 0) { 1225 device_printf(sc->sc_dev, 1226 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1227 ATH_PCU_UNLOCK(sc); 1228 return; 1229 } 1230 ATH_PCU_UNLOCK(sc); 1231 1232 ath_rx_proc(sc, 1); 1233 } 1234 1235 static void 1236 ath_legacy_flushrecv(struct ath_softc *sc) 1237 { 1238 1239 ath_rx_proc(sc, 0); 1240 } 1241 1242 static void 1243 ath_legacy_flush_rxpending(struct ath_softc *sc) 1244 { 1245 1246 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1247 1248 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1249 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1250 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1251 } 1252 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1253 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1254 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1255 } 1256 } 1257 1258 static int 1259 ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1260 { 1261 struct ath_buf *bf; 1262 1263 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1264 /* 1265 * If there are RX holding buffers, free them here and return 1266 * them to the list. 1267 * 1268 * XXX should just verify that bf->bf_m is NULL, as it must 1269 * be at this point! 1270 */ 1271 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1272 if (bf != NULL) { 1273 if (bf->bf_m != NULL) 1274 m_freem(bf->bf_m); 1275 bf->bf_m = NULL; 1276 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1277 (void) ath_rxbuf_init(sc, bf); 1278 } 1279 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1280 1281 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1282 if (bf != NULL) { 1283 if (bf->bf_m != NULL) 1284 m_freem(bf->bf_m); 1285 bf->bf_m = NULL; 1286 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1287 (void) ath_rxbuf_init(sc, bf); 1288 } 1289 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1290 1291 return (0); 1292 } 1293 1294 /* 1295 * Disable the receive h/w in preparation for a reset. 1296 */ 1297 static void 1298 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1299 { 1300 #define PA2DESC(_sc, _pa) \ 1301 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1302 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1303 struct ath_hal *ah = sc->sc_ah; 1304 1305 ATH_RX_LOCK(sc); 1306 1307 ath_hal_stoppcurecv(ah); /* disable PCU */ 1308 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1309 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1310 /* 1311 * TODO: see if this particular DELAY() is required; it may be 1312 * masking some missing FIFO flush or DMA sync. 1313 */ 1314 #if 0 1315 if (dodelay) 1316 #endif 1317 DELAY(3000); /* 3ms is long enough for 1 frame */ 1318 #ifdef ATH_DEBUG 1319 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1320 struct ath_buf *bf; 1321 u_int ix; 1322 1323 device_printf(sc->sc_dev, 1324 "%s: rx queue %p, link %p\n", 1325 __func__, 1326 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1327 sc->sc_rxlink); 1328 ix = 0; 1329 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1330 struct ath_desc *ds = bf->bf_desc; 1331 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1332 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1333 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1334 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1335 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1336 ix++; 1337 } 1338 } 1339 #endif 1340 1341 (void) ath_legacy_flush_rxpending(sc); 1342 (void) ath_legacy_flush_rxholdbf(sc); 1343 1344 sc->sc_rxlink = NULL; /* just in case */ 1345 1346 ATH_RX_UNLOCK(sc); 1347 #undef PA2DESC 1348 } 1349 1350 /* 1351 * XXX TODO: something was calling startrecv without calling 1352 * stoprecv. Let's figure out what/why. It was showing up 1353 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1354 */ 1355 1356 /* 1357 * Enable the receive h/w following a reset. 1358 */ 1359 static int 1360 ath_legacy_startrecv(struct ath_softc *sc) 1361 { 1362 struct ath_hal *ah = sc->sc_ah; 1363 struct ath_buf *bf; 1364 1365 ATH_RX_LOCK(sc); 1366 1367 /* 1368 * XXX should verify these are already all NULL! 1369 */ 1370 sc->sc_rxlink = NULL; 1371 (void) ath_legacy_flush_rxpending(sc); 1372 (void) ath_legacy_flush_rxholdbf(sc); 1373 1374 /* 1375 * Re-chain all of the buffers in the RX buffer list. 1376 */ 1377 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1378 int error = ath_rxbuf_init(sc, bf); 1379 if (error != 0) { 1380 DPRINTF(sc, ATH_DEBUG_RECV, 1381 "%s: ath_rxbuf_init failed %d\n", 1382 __func__, error); 1383 return error; 1384 } 1385 } 1386 1387 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1388 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1389 ath_hal_rxena(ah); /* enable recv descriptors */ 1390 ath_mode_init(sc); /* set filters, etc. */ 1391 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1392 1393 ATH_RX_UNLOCK(sc); 1394 return 0; 1395 } 1396 1397 static int 1398 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1399 { 1400 int error; 1401 1402 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1403 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1404 if (error != 0) 1405 return (error); 1406 1407 return (0); 1408 } 1409 1410 static int 1411 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1412 { 1413 1414 if (sc->sc_rxdma.dd_desc_len != 0) 1415 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1416 return (0); 1417 } 1418 1419 static void 1420 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1421 { 1422 1423 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1424 } 1425 1426 static void 1427 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1428 int dosched) 1429 { 1430 1431 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1432 } 1433 1434 void 1435 ath_recv_setup_legacy(struct ath_softc *sc) 1436 { 1437 1438 /* Sensible legacy defaults */ 1439 /* 1440 * XXX this should be changed to properly support the 1441 * exact RX descriptor size for each HAL. 1442 */ 1443 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1444 1445 sc->sc_rx.recv_start = ath_legacy_startrecv; 1446 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1447 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1448 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1449 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1450 1451 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1452 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1453 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1454 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1455 } 1456