1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_var.h> 77 #include <net/if_dl.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_arp.h> 81 #include <net/ethernet.h> 82 #include <net/if_llc.h> 83 84 #include <net80211/ieee80211_var.h> 85 #include <net80211/ieee80211_regdomain.h> 86 #ifdef IEEE80211_SUPPORT_SUPERG 87 #include <net80211/ieee80211_superg.h> 88 #endif 89 #ifdef IEEE80211_SUPPORT_TDMA 90 #include <net80211/ieee80211_tdma.h> 91 #endif 92 93 #include <net/bpf.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #include <dev/ath/if_athvar.h> 101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 102 #include <dev/ath/ath_hal/ah_diagcodes.h> 103 104 #include <dev/ath/if_ath_debug.h> 105 #include <dev/ath/if_ath_misc.h> 106 #include <dev/ath/if_ath_tsf.h> 107 #include <dev/ath/if_ath_tx.h> 108 #include <dev/ath/if_ath_sysctl.h> 109 #include <dev/ath/if_ath_led.h> 110 #include <dev/ath/if_ath_keycache.h> 111 #include <dev/ath/if_ath_rx.h> 112 #include <dev/ath/if_ath_beacon.h> 113 #include <dev/ath/if_athdfs.h> 114 115 #ifdef ATH_TX99_DIAG 116 #include <dev/ath/ath_tx99/ath_tx99.h> 117 #endif 118 119 #ifdef ATH_DEBUG_ALQ 120 #include <dev/ath/if_ath_alq.h> 121 #endif 122 123 #include <dev/ath/if_ath_lna_div.h> 124 125 /* 126 * Calculate the receive filter according to the 127 * operating mode and state: 128 * 129 * o always accept unicast, broadcast, and multicast traffic 130 * o accept PHY error frames when hardware doesn't have MIB support 131 * to count and we need them for ANI (sta mode only until recently) 132 * and we are not scanning (ANI is disabled) 133 * NB: older hal's add rx filter bits out of sight and we need to 134 * blindly preserve them 135 * o probe request frames are accepted only when operating in 136 * hostap, adhoc, mesh, or monitor modes 137 * o enable promiscuous mode 138 * - when in monitor mode 139 * - if interface marked PROMISC (assumes bridge setting is filtered) 140 * o accept beacons: 141 * - when operating in station mode for collecting rssi data when 142 * the station is otherwise quiet, or 143 * - when operating in adhoc mode so the 802.11 layer creates 144 * node table entries for peers, 145 * - when scanning 146 * - when doing s/w beacon miss (e.g. for ap+sta) 147 * - when operating in ap mode in 11g to detect overlapping bss that 148 * require protection 149 * - when operating in mesh mode to detect neighbors 150 * o accept control frames: 151 * - when in monitor mode 152 * XXX HT protection for 11n 153 */ 154 u_int32_t 155 ath_calcrxfilter(struct ath_softc *sc) 156 { 157 struct ifnet *ifp = sc->sc_ifp; 158 struct ieee80211com *ic = ifp->if_l2com; 159 u_int32_t rfilt; 160 161 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 162 if (!sc->sc_needmib && !sc->sc_scanning) 163 rfilt |= HAL_RX_FILTER_PHYERR; 164 if (ic->ic_opmode != IEEE80211_M_STA) 165 rfilt |= HAL_RX_FILTER_PROBEREQ; 166 /* XXX ic->ic_monvaps != 0? */ 167 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 168 rfilt |= HAL_RX_FILTER_PROM; 169 170 /* 171 * Only listen to all beacons if we're scanning. 172 * 173 * Otherwise we only really need to hear beacons from 174 * our own BSSID. 175 */ 176 if (ic->ic_opmode == IEEE80211_M_STA || 177 ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 178 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 179 rfilt |= HAL_RX_FILTER_MYBEACON; 180 } else { /* scanning, non-mybeacon chips */ 181 rfilt |= HAL_RX_FILTER_BEACON; 182 } 183 } 184 185 /* 186 * NB: We don't recalculate the rx filter when 187 * ic_protmode changes; otherwise we could do 188 * this only when ic_protmode != NONE. 189 */ 190 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 191 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 192 rfilt |= HAL_RX_FILTER_BEACON; 193 194 /* 195 * Enable hardware PS-POLL RX only for hostap mode; 196 * STA mode sends PS-POLL frames but never 197 * receives them. 198 */ 199 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 200 0, NULL) == HAL_OK && 201 ic->ic_opmode == IEEE80211_M_HOSTAP) 202 rfilt |= HAL_RX_FILTER_PSPOLL; 203 204 if (sc->sc_nmeshvaps) { 205 rfilt |= HAL_RX_FILTER_BEACON; 206 if (sc->sc_hasbmatch) 207 rfilt |= HAL_RX_FILTER_BSSID; 208 else 209 rfilt |= HAL_RX_FILTER_PROM; 210 } 211 if (ic->ic_opmode == IEEE80211_M_MONITOR) 212 rfilt |= HAL_RX_FILTER_CONTROL; 213 214 /* 215 * Enable RX of compressed BAR frames only when doing 216 * 802.11n. Required for A-MPDU. 217 */ 218 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 219 rfilt |= HAL_RX_FILTER_COMPBAR; 220 221 /* 222 * Enable radar PHY errors if requested by the 223 * DFS module. 224 */ 225 if (sc->sc_dodfs) 226 rfilt |= HAL_RX_FILTER_PHYRADAR; 227 228 /* 229 * Enable spectral PHY errors if requested by the 230 * spectral module. 231 */ 232 if (sc->sc_dospectral) 233 rfilt |= HAL_RX_FILTER_PHYRADAR; 234 235 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 236 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 237 return rfilt; 238 } 239 240 static int 241 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 242 { 243 struct ath_hal *ah = sc->sc_ah; 244 int error; 245 struct mbuf *m; 246 struct ath_desc *ds; 247 248 m = bf->bf_m; 249 if (m == NULL) { 250 /* 251 * NB: by assigning a page to the rx dma buffer we 252 * implicitly satisfy the Atheros requirement that 253 * this buffer be cache-line-aligned and sized to be 254 * multiple of the cache line size. Not doing this 255 * causes weird stuff to happen (for the 5210 at least). 256 */ 257 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 258 if (m == NULL) { 259 DPRINTF(sc, ATH_DEBUG_ANY, 260 "%s: no mbuf/cluster\n", __func__); 261 sc->sc_stats.ast_rx_nombuf++; 262 return ENOMEM; 263 } 264 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 265 266 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 267 bf->bf_dmamap, m, 268 bf->bf_segs, &bf->bf_nseg, 269 BUS_DMA_NOWAIT); 270 if (error != 0) { 271 DPRINTF(sc, ATH_DEBUG_ANY, 272 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 273 __func__, error); 274 sc->sc_stats.ast_rx_busdma++; 275 m_freem(m); 276 return error; 277 } 278 KASSERT(bf->bf_nseg == 1, 279 ("multi-segment packet; nseg %u", bf->bf_nseg)); 280 bf->bf_m = m; 281 } 282 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 283 284 /* 285 * Setup descriptors. For receive we always terminate 286 * the descriptor list with a self-linked entry so we'll 287 * not get overrun under high load (as can happen with a 288 * 5212 when ANI processing enables PHY error frames). 289 * 290 * To insure the last descriptor is self-linked we create 291 * each descriptor as self-linked and add it to the end. As 292 * each additional descriptor is added the previous self-linked 293 * entry is ``fixed'' naturally. This should be safe even 294 * if DMA is happening. When processing RX interrupts we 295 * never remove/process the last, self-linked, entry on the 296 * descriptor list. This insures the hardware always has 297 * someplace to write a new frame. 298 */ 299 /* 300 * 11N: we can no longer afford to self link the last descriptor. 301 * MAC acknowledges BA status as long as it copies frames to host 302 * buffer (or rx fifo). This can incorrectly acknowledge packets 303 * to a sender if last desc is self-linked. 304 */ 305 ds = bf->bf_desc; 306 if (sc->sc_rxslink) 307 ds->ds_link = bf->bf_daddr; /* link to self */ 308 else 309 ds->ds_link = 0; /* terminate the list */ 310 ds->ds_data = bf->bf_segs[0].ds_addr; 311 ath_hal_setuprxdesc(ah, ds 312 , m->m_len /* buffer size */ 313 , 0 314 ); 315 316 if (sc->sc_rxlink != NULL) 317 *sc->sc_rxlink = bf->bf_daddr; 318 sc->sc_rxlink = &ds->ds_link; 319 return 0; 320 } 321 322 /* 323 * Intercept management frames to collect beacon rssi data 324 * and to do ibss merges. 325 */ 326 void 327 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 328 int subtype, int rssi, int nf) 329 { 330 struct ieee80211vap *vap = ni->ni_vap; 331 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 332 uint64_t tsf_beacon_old, tsf_beacon; 333 uint64_t nexttbtt; 334 int64_t tsf_delta; 335 int32_t tsf_delta_bmiss; 336 int32_t tsf_remainder; 337 uint64_t tsf_beacon_target; 338 int tsf_intval; 339 340 tsf_beacon_old = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 341 tsf_beacon_old |= LE_READ_4(ni->ni_tstamp.data); 342 343 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 344 tsf_intval = 1; 345 if (ni != NULL && ni->ni_intval > 0) { 346 tsf_intval = TU_TO_TSF(ni->ni_intval); 347 } 348 #undef TU_TO_TSF 349 350 /* 351 * Call up first so subsequent work can use information 352 * potentially stored in the node (e.g. for ibss merge). 353 */ 354 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 355 switch (subtype) { 356 case IEEE80211_FC0_SUBTYPE_BEACON: 357 /* update rssi statistics for use by the hal */ 358 /* XXX unlocked check against vap->iv_bss? */ 359 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 360 361 tsf_beacon = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 362 tsf_beacon |= LE_READ_4(ni->ni_tstamp.data); 363 364 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 365 366 /* 367 * Let's calculate the delta and remainder, so we can see 368 * if the beacon timer from the AP is varying by more than 369 * a few TU. (Which would be a huge, huge problem.) 370 */ 371 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 372 373 tsf_delta_bmiss = tsf_delta / tsf_intval; 374 375 /* 376 * If our delta is greater than half the beacon interval, 377 * let's round the bmiss value up to the next beacon 378 * interval. Ie, we're running really, really early 379 * on the next beacon. 380 */ 381 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 382 tsf_delta_bmiss ++; 383 384 tsf_beacon_target = tsf_beacon_old + 385 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 386 387 /* 388 * The remainder using '%' is between 0 .. intval-1. 389 * If we're actually running too fast, then the remainder 390 * will be some large number just under intval-1. 391 * So we need to look at whether we're running 392 * before or after the target beacon interval 393 * and if we are, modify how we do the remainder 394 * calculation. 395 */ 396 if (tsf_beacon < tsf_beacon_target) { 397 tsf_remainder = 398 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 399 } else { 400 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 401 } 402 403 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu, new_tsf=%llu, target_tsf=%llu, delta=%lld, bmiss=%d, remainder=%d\n", 404 __func__, 405 (unsigned long long) tsf_beacon_old, 406 (unsigned long long) tsf_beacon, 407 (unsigned long long) tsf_beacon_target, 408 (long long) tsf_delta, 409 tsf_delta_bmiss, 410 tsf_remainder); 411 412 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu, nexttbtt=%llu, delta=%d\n", 413 __func__, 414 (unsigned long long) tsf_beacon, 415 (unsigned long long) nexttbtt, 416 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 417 418 if (sc->sc_syncbeacon && 419 ni == vap->iv_bss && 420 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 421 DPRINTF(sc, ATH_DEBUG_BEACON, 422 "%s: syncbeacon=1; syncing\n", 423 __func__); 424 /* 425 * Resync beacon timers using the tsf of the beacon 426 * frame we just received. 427 */ 428 ath_beacon_config(sc, vap); 429 sc->sc_syncbeacon = 0; 430 } 431 432 433 /* fall thru... */ 434 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 435 if (vap->iv_opmode == IEEE80211_M_IBSS && 436 vap->iv_state == IEEE80211_S_RUN) { 437 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 438 uint64_t tsf = ath_extend_tsf(sc, rstamp, 439 ath_hal_gettsf64(sc->sc_ah)); 440 /* 441 * Handle ibss merge as needed; check the tsf on the 442 * frame before attempting the merge. The 802.11 spec 443 * says the station should change it's bssid to match 444 * the oldest station with the same ssid, where oldest 445 * is determined by the tsf. Note that hardware 446 * reconfiguration happens through callback to 447 * ath_newstate as the state machine will go from 448 * RUN -> RUN when this happens. 449 */ 450 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 451 DPRINTF(sc, ATH_DEBUG_STATE, 452 "ibss merge, rstamp %u tsf %ju " 453 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 454 (uintmax_t)ni->ni_tstamp.tsf); 455 (void) ieee80211_ibss_merge(ni); 456 } 457 } 458 break; 459 } 460 } 461 462 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 463 static void 464 ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m, 465 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 466 { 467 struct ath_softc *sc = ifp->if_softc; 468 469 /* Fill in the extension bitmap */ 470 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 471 472 /* Fill in the vendor header */ 473 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 474 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 475 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 476 477 /* XXX what should this be? */ 478 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 479 sc->sc_rx_th.wr_vh.vh_skip_len = 480 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 481 482 /* General version info */ 483 sc->sc_rx_th.wr_v.vh_version = 1; 484 485 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 486 487 /* rssi */ 488 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 489 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 490 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 491 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 492 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 493 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 494 495 /* evm */ 496 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 497 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 498 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 499 /* These are only populated from the AR9300 or later */ 500 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 501 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 502 503 /* direction */ 504 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 505 506 /* RX rate */ 507 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 508 509 /* RX flags */ 510 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 511 512 if (rs->rs_isaggr) 513 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 514 if (rs->rs_moreaggr) 515 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 516 517 /* phyerr info */ 518 if (rs->rs_status & HAL_RXERR_PHY) { 519 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 520 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 521 } else { 522 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 523 } 524 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 525 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 526 } 527 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 528 529 static void 530 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 531 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 532 { 533 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 534 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 535 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 536 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 537 struct ath_softc *sc = ifp->if_softc; 538 const HAL_RATE_TABLE *rt; 539 uint8_t rix; 540 541 rt = sc->sc_currates; 542 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 543 rix = rt->rateCodeToIndex[rs->rs_rate]; 544 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 545 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 546 #ifdef AH_SUPPORT_AR5416 547 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 548 if (rs->rs_status & HAL_RXERR_PHY) { 549 /* 550 * PHY error - make sure the channel flags 551 * reflect the actual channel configuration, 552 * not the received frame. 553 */ 554 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 555 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 556 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 557 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 558 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 559 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 560 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 561 struct ieee80211com *ic = ifp->if_l2com; 562 563 if ((rs->rs_flags & HAL_RX_2040) == 0) 564 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 565 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 566 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 567 else 568 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 569 if ((rs->rs_flags & HAL_RX_GI) == 0) 570 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 571 } 572 573 #endif 574 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 575 if (rs->rs_status & HAL_RXERR_CRC) 576 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 577 /* XXX propagate other error flags from descriptor */ 578 sc->sc_rx_th.wr_antnoise = nf; 579 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 580 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 581 #undef CHAN_HT 582 #undef CHAN_HT20 583 #undef CHAN_HT40U 584 #undef CHAN_HT40D 585 } 586 587 static void 588 ath_handle_micerror(struct ieee80211com *ic, 589 struct ieee80211_frame *wh, int keyix) 590 { 591 struct ieee80211_node *ni; 592 593 /* XXX recheck MIC to deal w/ chips that lie */ 594 /* XXX discard MIC errors on !data frames */ 595 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 596 if (ni != NULL) { 597 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 598 ieee80211_free_node(ni); 599 } 600 } 601 602 /* 603 * Process a single packet. 604 * 605 * The mbuf must already be synced, unmapped and removed from bf->bf_m 606 * by this stage. 607 * 608 * The mbuf must be consumed by this routine - either passed up the 609 * net80211 stack, put on the holding queue, or freed. 610 */ 611 int 612 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 613 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 614 struct mbuf *m) 615 { 616 uint64_t rstamp; 617 int len, type; 618 struct ifnet *ifp = sc->sc_ifp; 619 struct ieee80211com *ic = ifp->if_l2com; 620 struct ieee80211_node *ni; 621 int is_good = 0; 622 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 623 624 /* 625 * Calculate the correct 64 bit TSF given 626 * the TSF64 register value and rs_tstamp. 627 */ 628 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 629 630 /* These aren't specifically errors */ 631 #ifdef AH_SUPPORT_AR5416 632 if (rs->rs_flags & HAL_RX_GI) 633 sc->sc_stats.ast_rx_halfgi++; 634 if (rs->rs_flags & HAL_RX_2040) 635 sc->sc_stats.ast_rx_2040++; 636 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 637 sc->sc_stats.ast_rx_pre_crc_err++; 638 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 639 sc->sc_stats.ast_rx_post_crc_err++; 640 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 641 sc->sc_stats.ast_rx_decrypt_busy_err++; 642 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 643 sc->sc_stats.ast_rx_hi_rx_chain++; 644 if (rs->rs_flags & HAL_RX_STBC) 645 sc->sc_stats.ast_rx_stbc++; 646 #endif /* AH_SUPPORT_AR5416 */ 647 648 if (rs->rs_status != 0) { 649 if (rs->rs_status & HAL_RXERR_CRC) 650 sc->sc_stats.ast_rx_crcerr++; 651 if (rs->rs_status & HAL_RXERR_FIFO) 652 sc->sc_stats.ast_rx_fifoerr++; 653 if (rs->rs_status & HAL_RXERR_PHY) { 654 sc->sc_stats.ast_rx_phyerr++; 655 /* Process DFS radar events */ 656 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 657 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 658 /* Now pass it to the radar processing code */ 659 ath_dfs_process_phy_err(sc, m, rstamp, rs); 660 } 661 662 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 663 if (rs->rs_phyerr < 64) 664 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 665 goto rx_error; /* NB: don't count in ierrors */ 666 } 667 if (rs->rs_status & HAL_RXERR_DECRYPT) { 668 /* 669 * Decrypt error. If the error occurred 670 * because there was no hardware key, then 671 * let the frame through so the upper layers 672 * can process it. This is necessary for 5210 673 * parts which have no way to setup a ``clear'' 674 * key cache entry. 675 * 676 * XXX do key cache faulting 677 */ 678 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 679 goto rx_accept; 680 sc->sc_stats.ast_rx_badcrypt++; 681 } 682 /* 683 * Similar as above - if the failure was a keymiss 684 * just punt it up to the upper layers for now. 685 */ 686 if (rs->rs_status & HAL_RXERR_KEYMISS) { 687 sc->sc_stats.ast_rx_keymiss++; 688 goto rx_accept; 689 } 690 if (rs->rs_status & HAL_RXERR_MIC) { 691 sc->sc_stats.ast_rx_badmic++; 692 /* 693 * Do minimal work required to hand off 694 * the 802.11 header for notification. 695 */ 696 /* XXX frag's and qos frames */ 697 len = rs->rs_datalen; 698 if (len >= sizeof (struct ieee80211_frame)) { 699 ath_handle_micerror(ic, 700 mtod(m, struct ieee80211_frame *), 701 sc->sc_splitmic ? 702 rs->rs_keyix-32 : rs->rs_keyix); 703 } 704 } 705 ifp->if_ierrors++; 706 rx_error: 707 /* 708 * Cleanup any pending partial frame. 709 */ 710 if (re->m_rxpending != NULL) { 711 m_freem(re->m_rxpending); 712 re->m_rxpending = NULL; 713 } 714 /* 715 * When a tap is present pass error frames 716 * that have been requested. By default we 717 * pass decrypt+mic errors but others may be 718 * interesting (e.g. crc). 719 */ 720 if (ieee80211_radiotap_active(ic) && 721 (rs->rs_status & sc->sc_monpass)) { 722 /* NB: bpf needs the mbuf length setup */ 723 len = rs->rs_datalen; 724 m->m_pkthdr.len = m->m_len = len; 725 ath_rx_tap(ifp, m, rs, rstamp, nf); 726 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 727 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 728 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 729 ieee80211_radiotap_rx_all(ic, m); 730 } 731 /* XXX pass MIC errors up for s/w reclaculation */ 732 m_freem(m); m = NULL; 733 goto rx_next; 734 } 735 rx_accept: 736 len = rs->rs_datalen; 737 m->m_len = len; 738 739 if (rs->rs_more) { 740 /* 741 * Frame spans multiple descriptors; save 742 * it for the next completed descriptor, it 743 * will be used to construct a jumbogram. 744 */ 745 if (re->m_rxpending != NULL) { 746 /* NB: max frame size is currently 2 clusters */ 747 sc->sc_stats.ast_rx_toobig++; 748 m_freem(re->m_rxpending); 749 } 750 m->m_pkthdr.rcvif = ifp; 751 m->m_pkthdr.len = len; 752 re->m_rxpending = m; 753 m = NULL; 754 goto rx_next; 755 } else if (re->m_rxpending != NULL) { 756 /* 757 * This is the second part of a jumbogram, 758 * chain it to the first mbuf, adjust the 759 * frame length, and clear the rxpending state. 760 */ 761 re->m_rxpending->m_next = m; 762 re->m_rxpending->m_pkthdr.len += len; 763 m = re->m_rxpending; 764 re->m_rxpending = NULL; 765 } else { 766 /* 767 * Normal single-descriptor receive; setup 768 * the rcvif and packet length. 769 */ 770 m->m_pkthdr.rcvif = ifp; 771 m->m_pkthdr.len = len; 772 } 773 774 /* 775 * Validate rs->rs_antenna. 776 * 777 * Some users w/ AR9285 NICs have reported crashes 778 * here because rs_antenna field is bogusly large. 779 * Let's enforce the maximum antenna limit of 8 780 * (and it shouldn't be hard coded, but that's a 781 * separate problem) and if there's an issue, print 782 * out an error and adjust rs_antenna to something 783 * sensible. 784 * 785 * This code should be removed once the actual 786 * root cause of the issue has been identified. 787 * For example, it may be that the rs_antenna 788 * field is only valid for the lsat frame of 789 * an aggregate and it just happens that it is 790 * "mostly" right. (This is a general statement - 791 * the majority of the statistics are only valid 792 * for the last frame in an aggregate. 793 */ 794 if (rs->rs_antenna > 7) { 795 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 796 __func__, rs->rs_antenna); 797 #ifdef ATH_DEBUG 798 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 799 #endif /* ATH_DEBUG */ 800 rs->rs_antenna = 0; /* XXX better than nothing */ 801 } 802 803 /* 804 * If this is an AR9285/AR9485, then the receive and LNA 805 * configuration is stored in RSSI[2] / EXTRSSI[2]. 806 * We can extract this out to build a much better 807 * receive antenna profile. 808 * 809 * Yes, this just blurts over the above RX antenna field 810 * for now. It's fine, the AR9285 doesn't really use 811 * that. 812 * 813 * Later on we should store away the fine grained LNA 814 * information and keep separate counters just for 815 * that. It'll help when debugging the AR9285/AR9485 816 * combined diversity code. 817 */ 818 if (sc->sc_rx_lnamixer) { 819 rs->rs_antenna = 0; 820 821 /* Bits 0:1 - the LNA configuration used */ 822 rs->rs_antenna |= 823 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 824 >> HAL_RX_LNA_CFG_USED_S); 825 826 /* Bit 2 - the external RX antenna switch */ 827 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 828 rs->rs_antenna |= 0x4; 829 } 830 831 ifp->if_ipackets++; 832 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 833 834 /* 835 * Populate the rx status block. When there are bpf 836 * listeners we do the additional work to provide 837 * complete status. Otherwise we fill in only the 838 * material required by ieee80211_input. Note that 839 * noise setting is filled in above. 840 */ 841 if (ieee80211_radiotap_active(ic)) { 842 ath_rx_tap(ifp, m, rs, rstamp, nf); 843 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 844 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 845 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 846 } 847 848 /* 849 * From this point on we assume the frame is at least 850 * as large as ieee80211_frame_min; verify that. 851 */ 852 if (len < IEEE80211_MIN_LEN) { 853 if (!ieee80211_radiotap_active(ic)) { 854 DPRINTF(sc, ATH_DEBUG_RECV, 855 "%s: short packet %d\n", __func__, len); 856 sc->sc_stats.ast_rx_tooshort++; 857 } else { 858 /* NB: in particular this captures ack's */ 859 ieee80211_radiotap_rx_all(ic, m); 860 } 861 m_freem(m); m = NULL; 862 goto rx_next; 863 } 864 865 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 866 const HAL_RATE_TABLE *rt = sc->sc_currates; 867 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 868 869 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 870 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 871 } 872 873 m_adj(m, -IEEE80211_CRC_LEN); 874 875 /* 876 * Locate the node for sender, track state, and then 877 * pass the (referenced) node up to the 802.11 layer 878 * for its use. 879 */ 880 ni = ieee80211_find_rxnode_withkey(ic, 881 mtod(m, const struct ieee80211_frame_min *), 882 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 883 IEEE80211_KEYIX_NONE : rs->rs_keyix); 884 sc->sc_lastrs = rs; 885 886 #ifdef AH_SUPPORT_AR5416 887 if (rs->rs_isaggr) 888 sc->sc_stats.ast_rx_agg++; 889 #endif /* AH_SUPPORT_AR5416 */ 890 891 if (ni != NULL) { 892 /* 893 * Only punt packets for ampdu reorder processing for 894 * 11n nodes; net80211 enforces that M_AMPDU is only 895 * set for 11n nodes. 896 */ 897 if (ni->ni_flags & IEEE80211_NODE_HT) 898 m->m_flags |= M_AMPDU; 899 900 /* 901 * Sending station is known, dispatch directly. 902 */ 903 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 904 ieee80211_free_node(ni); 905 m = NULL; 906 /* 907 * Arrange to update the last rx timestamp only for 908 * frames from our ap when operating in station mode. 909 * This assumes the rx key is always setup when 910 * associated. 911 */ 912 if (ic->ic_opmode == IEEE80211_M_STA && 913 rs->rs_keyix != HAL_RXKEYIX_INVALID) 914 is_good = 1; 915 } else { 916 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 917 m = NULL; 918 } 919 920 /* 921 * At this point we have passed the frame up the stack; thus 922 * the mbuf is no longer ours. 923 */ 924 925 /* 926 * Track rx rssi and do any rx antenna management. 927 */ 928 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 929 if (sc->sc_diversity) { 930 /* 931 * When using fast diversity, change the default rx 932 * antenna if diversity chooses the other antenna 3 933 * times in a row. 934 */ 935 if (sc->sc_defant != rs->rs_antenna) { 936 if (++sc->sc_rxotherant >= 3) 937 ath_setdefantenna(sc, rs->rs_antenna); 938 } else 939 sc->sc_rxotherant = 0; 940 } 941 942 /* Handle slow diversity if enabled */ 943 if (sc->sc_dolnadiv) { 944 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 945 } 946 947 if (sc->sc_softled) { 948 /* 949 * Blink for any data frame. Otherwise do a 950 * heartbeat-style blink when idle. The latter 951 * is mainly for station mode where we depend on 952 * periodic beacon frames to trigger the poll event. 953 */ 954 if (type == IEEE80211_FC0_TYPE_DATA) { 955 const HAL_RATE_TABLE *rt = sc->sc_currates; 956 ath_led_event(sc, 957 rt->rateCodeToIndex[rs->rs_rate]); 958 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 959 ath_led_event(sc, 0); 960 } 961 rx_next: 962 /* 963 * Debugging - complain if we didn't NULL the mbuf pointer 964 * here. 965 */ 966 if (m != NULL) { 967 device_printf(sc->sc_dev, 968 "%s: mbuf %p should've been freed!\n", 969 __func__, 970 m); 971 } 972 return (is_good); 973 } 974 975 #define ATH_RX_MAX 128 976 977 static void 978 ath_rx_proc(struct ath_softc *sc, int resched) 979 { 980 #define PA2DESC(_sc, _pa) \ 981 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 982 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 983 struct ath_buf *bf; 984 struct ifnet *ifp = sc->sc_ifp; 985 struct ath_hal *ah = sc->sc_ah; 986 #ifdef IEEE80211_SUPPORT_SUPERG 987 struct ieee80211com *ic = ifp->if_l2com; 988 #endif 989 struct ath_desc *ds; 990 struct ath_rx_status *rs; 991 struct mbuf *m; 992 int ngood; 993 HAL_STATUS status; 994 int16_t nf; 995 u_int64_t tsf; 996 int npkts = 0; 997 int kickpcu = 0; 998 999 /* XXX we must not hold the ATH_LOCK here */ 1000 ATH_UNLOCK_ASSERT(sc); 1001 ATH_PCU_UNLOCK_ASSERT(sc); 1002 1003 ATH_PCU_LOCK(sc); 1004 sc->sc_rxproc_cnt++; 1005 kickpcu = sc->sc_kickpcu; 1006 ATH_PCU_UNLOCK(sc); 1007 1008 ATH_LOCK(sc); 1009 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1010 ATH_UNLOCK(sc); 1011 1012 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1013 ngood = 0; 1014 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1015 sc->sc_stats.ast_rx_noise = nf; 1016 tsf = ath_hal_gettsf64(ah); 1017 do { 1018 /* 1019 * Don't process too many packets at a time; give the 1020 * TX thread time to also run - otherwise the TX 1021 * latency can jump by quite a bit, causing throughput 1022 * degredation. 1023 */ 1024 if (!kickpcu && npkts >= ATH_RX_MAX) 1025 break; 1026 1027 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1028 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1029 if_printf(ifp, "%s: no buffer!\n", __func__); 1030 break; 1031 } else if (bf == NULL) { 1032 /* 1033 * End of List: 1034 * this can happen for non-self-linked RX chains 1035 */ 1036 sc->sc_stats.ast_rx_hitqueueend++; 1037 break; 1038 } 1039 m = bf->bf_m; 1040 if (m == NULL) { /* NB: shouldn't happen */ 1041 /* 1042 * If mbuf allocation failed previously there 1043 * will be no mbuf; try again to re-populate it. 1044 */ 1045 /* XXX make debug msg */ 1046 if_printf(ifp, "%s: no mbuf!\n", __func__); 1047 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1048 goto rx_proc_next; 1049 } 1050 ds = bf->bf_desc; 1051 if (ds->ds_link == bf->bf_daddr) { 1052 /* NB: never process the self-linked entry at the end */ 1053 sc->sc_stats.ast_rx_hitqueueend++; 1054 break; 1055 } 1056 /* XXX sync descriptor memory */ 1057 /* 1058 * Must provide the virtual address of the current 1059 * descriptor, the physical address, and the virtual 1060 * address of the next descriptor in the h/w chain. 1061 * This allows the HAL to look ahead to see if the 1062 * hardware is done with a descriptor by checking the 1063 * done bit in the following descriptor and the address 1064 * of the current descriptor the DMA engine is working 1065 * on. All this is necessary because of our use of 1066 * a self-linked list to avoid rx overruns. 1067 */ 1068 rs = &bf->bf_status.ds_rxstat; 1069 status = ath_hal_rxprocdesc(ah, ds, 1070 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1071 #ifdef ATH_DEBUG 1072 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1073 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1074 #endif 1075 1076 #ifdef ATH_DEBUG_ALQ 1077 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1078 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1079 sc->sc_rx_statuslen, (char *) ds); 1080 #endif /* ATH_DEBUG_ALQ */ 1081 1082 if (status == HAL_EINPROGRESS) 1083 break; 1084 1085 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1086 npkts++; 1087 1088 /* 1089 * Process a single frame. 1090 */ 1091 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1092 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1093 bf->bf_m = NULL; 1094 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1095 ngood++; 1096 rx_proc_next: 1097 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1098 } while (ath_rxbuf_init(sc, bf) == 0); 1099 1100 /* rx signal state monitoring */ 1101 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1102 if (ngood) 1103 sc->sc_lastrx = tsf; 1104 1105 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1106 /* Queue DFS tasklet if needed */ 1107 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1108 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1109 1110 /* 1111 * Now that all the RX frames were handled that 1112 * need to be handled, kick the PCU if there's 1113 * been an RXEOL condition. 1114 */ 1115 if (resched && kickpcu) { 1116 ATH_PCU_LOCK(sc); 1117 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1118 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1119 __func__, npkts); 1120 1121 /* 1122 * Go through the process of fully tearing down 1123 * the RX buffers and reinitialising them. 1124 * 1125 * There's a hardware bug that causes the RX FIFO 1126 * to get confused under certain conditions and 1127 * constantly write over the same frame, leading 1128 * the RX driver code here to get heavily confused. 1129 */ 1130 #if 1 1131 ath_startrecv(sc); 1132 #else 1133 /* 1134 * Disabled for now - it'd be nice to be able to do 1135 * this in order to limit the amount of CPU time spent 1136 * reinitialising the RX side (and thus minimise RX 1137 * drops) however there's a hardware issue that 1138 * causes things to get too far out of whack. 1139 */ 1140 /* 1141 * XXX can we hold the PCU lock here? 1142 * Are there any net80211 buffer calls involved? 1143 */ 1144 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1145 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1146 ath_hal_rxena(ah); /* enable recv descriptors */ 1147 ath_mode_init(sc); /* set filters, etc. */ 1148 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1149 #endif 1150 1151 ath_hal_intrset(ah, sc->sc_imask); 1152 sc->sc_kickpcu = 0; 1153 ATH_PCU_UNLOCK(sc); 1154 } 1155 1156 /* XXX check this inside of IF_LOCK? */ 1157 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 1158 #ifdef IEEE80211_SUPPORT_SUPERG 1159 ieee80211_ff_age_all(ic, 100); 1160 #endif 1161 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1162 ath_tx_kick(sc); 1163 } 1164 #undef PA2DESC 1165 1166 /* 1167 * Put the hardware to sleep again if we're done with it. 1168 */ 1169 ATH_LOCK(sc); 1170 ath_power_restore_power_state(sc); 1171 ATH_UNLOCK(sc); 1172 1173 /* 1174 * If we hit the maximum number of frames in this round, 1175 * reschedule for another immediate pass. This gives 1176 * the TX and TX completion routines time to run, which 1177 * will reduce latency. 1178 */ 1179 if (npkts >= ATH_RX_MAX) 1180 sc->sc_rx.recv_sched(sc, resched); 1181 1182 ATH_PCU_LOCK(sc); 1183 sc->sc_rxproc_cnt--; 1184 ATH_PCU_UNLOCK(sc); 1185 } 1186 1187 #undef ATH_RX_MAX 1188 1189 /* 1190 * Only run the RX proc if it's not already running. 1191 * Since this may get run as part of the reset/flush path, 1192 * the task can't clash with an existing, running tasklet. 1193 */ 1194 static void 1195 ath_legacy_rx_tasklet(void *arg, int npending) 1196 { 1197 struct ath_softc *sc = arg; 1198 1199 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1200 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1201 ATH_PCU_LOCK(sc); 1202 if (sc->sc_inreset_cnt > 0) { 1203 device_printf(sc->sc_dev, 1204 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1205 ATH_PCU_UNLOCK(sc); 1206 return; 1207 } 1208 ATH_PCU_UNLOCK(sc); 1209 1210 ath_rx_proc(sc, 1); 1211 } 1212 1213 static void 1214 ath_legacy_flushrecv(struct ath_softc *sc) 1215 { 1216 1217 ath_rx_proc(sc, 0); 1218 } 1219 1220 /* 1221 * Disable the receive h/w in preparation for a reset. 1222 */ 1223 static void 1224 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1225 { 1226 #define PA2DESC(_sc, _pa) \ 1227 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1228 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1229 struct ath_hal *ah = sc->sc_ah; 1230 1231 ath_hal_stoppcurecv(ah); /* disable PCU */ 1232 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1233 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1234 /* 1235 * TODO: see if this particular DELAY() is required; it may be 1236 * masking some missing FIFO flush or DMA sync. 1237 */ 1238 #if 0 1239 if (dodelay) 1240 #endif 1241 DELAY(3000); /* 3ms is long enough for 1 frame */ 1242 #ifdef ATH_DEBUG 1243 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1244 struct ath_buf *bf; 1245 u_int ix; 1246 1247 device_printf(sc->sc_dev, 1248 "%s: rx queue %p, link %p\n", 1249 __func__, 1250 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1251 sc->sc_rxlink); 1252 ix = 0; 1253 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1254 struct ath_desc *ds = bf->bf_desc; 1255 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1256 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1257 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1258 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1259 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1260 ix++; 1261 } 1262 } 1263 #endif 1264 /* 1265 * Free both high/low RX pending, just in case. 1266 */ 1267 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1268 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1269 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1270 } 1271 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1272 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1273 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1274 } 1275 sc->sc_rxlink = NULL; /* just in case */ 1276 #undef PA2DESC 1277 } 1278 1279 /* 1280 * Enable the receive h/w following a reset. 1281 */ 1282 static int 1283 ath_legacy_startrecv(struct ath_softc *sc) 1284 { 1285 struct ath_hal *ah = sc->sc_ah; 1286 struct ath_buf *bf; 1287 1288 sc->sc_rxlink = NULL; 1289 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1290 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1291 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1292 int error = ath_rxbuf_init(sc, bf); 1293 if (error != 0) { 1294 DPRINTF(sc, ATH_DEBUG_RECV, 1295 "%s: ath_rxbuf_init failed %d\n", 1296 __func__, error); 1297 return error; 1298 } 1299 } 1300 1301 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1302 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1303 ath_hal_rxena(ah); /* enable recv descriptors */ 1304 ath_mode_init(sc); /* set filters, etc. */ 1305 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1306 return 0; 1307 } 1308 1309 static int 1310 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1311 { 1312 int error; 1313 1314 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1315 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1316 if (error != 0) 1317 return (error); 1318 1319 return (0); 1320 } 1321 1322 static int 1323 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1324 { 1325 1326 if (sc->sc_rxdma.dd_desc_len != 0) 1327 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1328 return (0); 1329 } 1330 1331 static void 1332 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1333 { 1334 1335 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1336 } 1337 1338 static void 1339 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1340 int dosched) 1341 { 1342 1343 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1344 } 1345 1346 void 1347 ath_recv_setup_legacy(struct ath_softc *sc) 1348 { 1349 1350 /* Sensible legacy defaults */ 1351 /* 1352 * XXX this should be changed to properly support the 1353 * exact RX descriptor size for each HAL. 1354 */ 1355 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1356 1357 sc->sc_rx.recv_start = ath_legacy_startrecv; 1358 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1359 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1360 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1361 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1362 1363 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1364 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1365 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1366 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1367 } 1368