1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_var.h> 77 #include <net/if_dl.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_arp.h> 81 #include <net/ethernet.h> 82 #include <net/if_llc.h> 83 84 #include <net80211/ieee80211_var.h> 85 #include <net80211/ieee80211_regdomain.h> 86 #ifdef IEEE80211_SUPPORT_SUPERG 87 #include <net80211/ieee80211_superg.h> 88 #endif 89 #ifdef IEEE80211_SUPPORT_TDMA 90 #include <net80211/ieee80211_tdma.h> 91 #endif 92 93 #include <net/bpf.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #include <dev/ath/if_athvar.h> 101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 102 #include <dev/ath/ath_hal/ah_diagcodes.h> 103 104 #include <dev/ath/if_ath_debug.h> 105 #include <dev/ath/if_ath_misc.h> 106 #include <dev/ath/if_ath_tsf.h> 107 #include <dev/ath/if_ath_tx.h> 108 #include <dev/ath/if_ath_sysctl.h> 109 #include <dev/ath/if_ath_led.h> 110 #include <dev/ath/if_ath_keycache.h> 111 #include <dev/ath/if_ath_rx.h> 112 #include <dev/ath/if_ath_beacon.h> 113 #include <dev/ath/if_athdfs.h> 114 115 #ifdef ATH_TX99_DIAG 116 #include <dev/ath/ath_tx99/ath_tx99.h> 117 #endif 118 119 #ifdef ATH_DEBUG_ALQ 120 #include <dev/ath/if_ath_alq.h> 121 #endif 122 123 #include <dev/ath/if_ath_lna_div.h> 124 125 /* 126 * Calculate the receive filter according to the 127 * operating mode and state: 128 * 129 * o always accept unicast, broadcast, and multicast traffic 130 * o accept PHY error frames when hardware doesn't have MIB support 131 * to count and we need them for ANI (sta mode only until recently) 132 * and we are not scanning (ANI is disabled) 133 * NB: older hal's add rx filter bits out of sight and we need to 134 * blindly preserve them 135 * o probe request frames are accepted only when operating in 136 * hostap, adhoc, mesh, or monitor modes 137 * o enable promiscuous mode 138 * - when in monitor mode 139 * - if interface marked PROMISC (assumes bridge setting is filtered) 140 * o accept beacons: 141 * - when operating in station mode for collecting rssi data when 142 * the station is otherwise quiet, or 143 * - when operating in adhoc mode so the 802.11 layer creates 144 * node table entries for peers, 145 * - when scanning 146 * - when doing s/w beacon miss (e.g. for ap+sta) 147 * - when operating in ap mode in 11g to detect overlapping bss that 148 * require protection 149 * - when operating in mesh mode to detect neighbors 150 * o accept control frames: 151 * - when in monitor mode 152 * XXX HT protection for 11n 153 */ 154 u_int32_t 155 ath_calcrxfilter(struct ath_softc *sc) 156 { 157 struct ifnet *ifp = sc->sc_ifp; 158 struct ieee80211com *ic = ifp->if_l2com; 159 u_int32_t rfilt; 160 161 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 162 if (!sc->sc_needmib && !sc->sc_scanning) 163 rfilt |= HAL_RX_FILTER_PHYERR; 164 if (ic->ic_opmode != IEEE80211_M_STA) 165 rfilt |= HAL_RX_FILTER_PROBEREQ; 166 /* XXX ic->ic_monvaps != 0? */ 167 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 168 rfilt |= HAL_RX_FILTER_PROM; 169 if (ic->ic_opmode == IEEE80211_M_STA || 170 ic->ic_opmode == IEEE80211_M_IBSS || 171 sc->sc_swbmiss || sc->sc_scanning) 172 rfilt |= HAL_RX_FILTER_BEACON; 173 /* 174 * NB: We don't recalculate the rx filter when 175 * ic_protmode changes; otherwise we could do 176 * this only when ic_protmode != NONE. 177 */ 178 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 179 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 180 rfilt |= HAL_RX_FILTER_BEACON; 181 182 /* 183 * Enable hardware PS-POLL RX only for hostap mode; 184 * STA mode sends PS-POLL frames but never 185 * receives them. 186 */ 187 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 188 0, NULL) == HAL_OK && 189 ic->ic_opmode == IEEE80211_M_HOSTAP) 190 rfilt |= HAL_RX_FILTER_PSPOLL; 191 192 if (sc->sc_nmeshvaps) { 193 rfilt |= HAL_RX_FILTER_BEACON; 194 if (sc->sc_hasbmatch) 195 rfilt |= HAL_RX_FILTER_BSSID; 196 else 197 rfilt |= HAL_RX_FILTER_PROM; 198 } 199 if (ic->ic_opmode == IEEE80211_M_MONITOR) 200 rfilt |= HAL_RX_FILTER_CONTROL; 201 202 /* 203 * Enable RX of compressed BAR frames only when doing 204 * 802.11n. Required for A-MPDU. 205 */ 206 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 207 rfilt |= HAL_RX_FILTER_COMPBAR; 208 209 /* 210 * Enable radar PHY errors if requested by the 211 * DFS module. 212 */ 213 if (sc->sc_dodfs) 214 rfilt |= HAL_RX_FILTER_PHYRADAR; 215 216 /* 217 * Enable spectral PHY errors if requested by the 218 * spectral module. 219 */ 220 if (sc->sc_dospectral) 221 rfilt |= HAL_RX_FILTER_PHYRADAR; 222 223 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 224 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 225 return rfilt; 226 } 227 228 static int 229 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 230 { 231 struct ath_hal *ah = sc->sc_ah; 232 int error; 233 struct mbuf *m; 234 struct ath_desc *ds; 235 236 m = bf->bf_m; 237 if (m == NULL) { 238 /* 239 * NB: by assigning a page to the rx dma buffer we 240 * implicitly satisfy the Atheros requirement that 241 * this buffer be cache-line-aligned and sized to be 242 * multiple of the cache line size. Not doing this 243 * causes weird stuff to happen (for the 5210 at least). 244 */ 245 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 246 if (m == NULL) { 247 DPRINTF(sc, ATH_DEBUG_ANY, 248 "%s: no mbuf/cluster\n", __func__); 249 sc->sc_stats.ast_rx_nombuf++; 250 return ENOMEM; 251 } 252 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 253 254 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 255 bf->bf_dmamap, m, 256 bf->bf_segs, &bf->bf_nseg, 257 BUS_DMA_NOWAIT); 258 if (error != 0) { 259 DPRINTF(sc, ATH_DEBUG_ANY, 260 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 261 __func__, error); 262 sc->sc_stats.ast_rx_busdma++; 263 m_freem(m); 264 return error; 265 } 266 KASSERT(bf->bf_nseg == 1, 267 ("multi-segment packet; nseg %u", bf->bf_nseg)); 268 bf->bf_m = m; 269 } 270 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 271 272 /* 273 * Setup descriptors. For receive we always terminate 274 * the descriptor list with a self-linked entry so we'll 275 * not get overrun under high load (as can happen with a 276 * 5212 when ANI processing enables PHY error frames). 277 * 278 * To insure the last descriptor is self-linked we create 279 * each descriptor as self-linked and add it to the end. As 280 * each additional descriptor is added the previous self-linked 281 * entry is ``fixed'' naturally. This should be safe even 282 * if DMA is happening. When processing RX interrupts we 283 * never remove/process the last, self-linked, entry on the 284 * descriptor list. This insures the hardware always has 285 * someplace to write a new frame. 286 */ 287 /* 288 * 11N: we can no longer afford to self link the last descriptor. 289 * MAC acknowledges BA status as long as it copies frames to host 290 * buffer (or rx fifo). This can incorrectly acknowledge packets 291 * to a sender if last desc is self-linked. 292 */ 293 ds = bf->bf_desc; 294 if (sc->sc_rxslink) 295 ds->ds_link = bf->bf_daddr; /* link to self */ 296 else 297 ds->ds_link = 0; /* terminate the list */ 298 ds->ds_data = bf->bf_segs[0].ds_addr; 299 ath_hal_setuprxdesc(ah, ds 300 , m->m_len /* buffer size */ 301 , 0 302 ); 303 304 if (sc->sc_rxlink != NULL) 305 *sc->sc_rxlink = bf->bf_daddr; 306 sc->sc_rxlink = &ds->ds_link; 307 return 0; 308 } 309 310 /* 311 * Intercept management frames to collect beacon rssi data 312 * and to do ibss merges. 313 */ 314 void 315 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 316 int subtype, int rssi, int nf) 317 { 318 struct ieee80211vap *vap = ni->ni_vap; 319 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 320 321 /* 322 * Call up first so subsequent work can use information 323 * potentially stored in the node (e.g. for ibss merge). 324 */ 325 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 326 switch (subtype) { 327 case IEEE80211_FC0_SUBTYPE_BEACON: 328 /* update rssi statistics for use by the hal */ 329 /* XXX unlocked check against vap->iv_bss? */ 330 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 331 if (sc->sc_syncbeacon && 332 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 333 /* 334 * Resync beacon timers using the tsf of the beacon 335 * frame we just received. 336 */ 337 ath_beacon_config(sc, vap); 338 } 339 /* fall thru... */ 340 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 341 if (vap->iv_opmode == IEEE80211_M_IBSS && 342 vap->iv_state == IEEE80211_S_RUN) { 343 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 344 uint64_t tsf = ath_extend_tsf(sc, rstamp, 345 ath_hal_gettsf64(sc->sc_ah)); 346 /* 347 * Handle ibss merge as needed; check the tsf on the 348 * frame before attempting the merge. The 802.11 spec 349 * says the station should change it's bssid to match 350 * the oldest station with the same ssid, where oldest 351 * is determined by the tsf. Note that hardware 352 * reconfiguration happens through callback to 353 * ath_newstate as the state machine will go from 354 * RUN -> RUN when this happens. 355 */ 356 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 357 DPRINTF(sc, ATH_DEBUG_STATE, 358 "ibss merge, rstamp %u tsf %ju " 359 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 360 (uintmax_t)ni->ni_tstamp.tsf); 361 (void) ieee80211_ibss_merge(ni); 362 } 363 } 364 break; 365 } 366 } 367 368 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 369 static void 370 ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m, 371 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 372 { 373 struct ath_softc *sc = ifp->if_softc; 374 375 /* Fill in the extension bitmap */ 376 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 377 378 /* Fill in the vendor header */ 379 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 380 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 381 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 382 383 /* XXX what should this be? */ 384 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 385 sc->sc_rx_th.wr_vh.vh_skip_len = 386 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 387 388 /* General version info */ 389 sc->sc_rx_th.wr_v.vh_version = 1; 390 391 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 392 393 /* rssi */ 394 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 395 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 396 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 397 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 398 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 399 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 400 401 /* evm */ 402 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 403 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 404 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 405 /* These are only populated from the AR9300 or later */ 406 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 407 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 408 409 /* direction */ 410 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 411 412 /* RX rate */ 413 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 414 415 /* RX flags */ 416 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 417 418 if (rs->rs_isaggr) 419 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 420 if (rs->rs_moreaggr) 421 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 422 423 /* phyerr info */ 424 if (rs->rs_status & HAL_RXERR_PHY) { 425 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 426 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 427 } else { 428 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 429 } 430 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 431 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 432 } 433 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 434 435 static void 436 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 437 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 438 { 439 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 440 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 441 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 442 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 443 struct ath_softc *sc = ifp->if_softc; 444 const HAL_RATE_TABLE *rt; 445 uint8_t rix; 446 447 rt = sc->sc_currates; 448 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 449 rix = rt->rateCodeToIndex[rs->rs_rate]; 450 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 451 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 452 #ifdef AH_SUPPORT_AR5416 453 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 454 if (rs->rs_status & HAL_RXERR_PHY) { 455 /* 456 * PHY error - make sure the channel flags 457 * reflect the actual channel configuration, 458 * not the received frame. 459 */ 460 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 461 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 462 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 463 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 464 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 465 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 466 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 467 struct ieee80211com *ic = ifp->if_l2com; 468 469 if ((rs->rs_flags & HAL_RX_2040) == 0) 470 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 471 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 472 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 473 else 474 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 475 if ((rs->rs_flags & HAL_RX_GI) == 0) 476 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 477 } 478 479 #endif 480 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 481 if (rs->rs_status & HAL_RXERR_CRC) 482 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 483 /* XXX propagate other error flags from descriptor */ 484 sc->sc_rx_th.wr_antnoise = nf; 485 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 486 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 487 #undef CHAN_HT 488 #undef CHAN_HT20 489 #undef CHAN_HT40U 490 #undef CHAN_HT40D 491 } 492 493 static void 494 ath_handle_micerror(struct ieee80211com *ic, 495 struct ieee80211_frame *wh, int keyix) 496 { 497 struct ieee80211_node *ni; 498 499 /* XXX recheck MIC to deal w/ chips that lie */ 500 /* XXX discard MIC errors on !data frames */ 501 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 502 if (ni != NULL) { 503 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 504 ieee80211_free_node(ni); 505 } 506 } 507 508 /* 509 * Process a single packet. 510 * 511 * The mbuf must already be synced, unmapped and removed from bf->bf_m 512 * by this stage. 513 * 514 * The mbuf must be consumed by this routine - either passed up the 515 * net80211 stack, put on the holding queue, or freed. 516 */ 517 int 518 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 519 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 520 struct mbuf *m) 521 { 522 uint64_t rstamp; 523 int len, type; 524 struct ifnet *ifp = sc->sc_ifp; 525 struct ieee80211com *ic = ifp->if_l2com; 526 struct ieee80211_node *ni; 527 int is_good = 0; 528 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 529 530 /* 531 * Calculate the correct 64 bit TSF given 532 * the TSF64 register value and rs_tstamp. 533 */ 534 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 535 536 /* These aren't specifically errors */ 537 #ifdef AH_SUPPORT_AR5416 538 if (rs->rs_flags & HAL_RX_GI) 539 sc->sc_stats.ast_rx_halfgi++; 540 if (rs->rs_flags & HAL_RX_2040) 541 sc->sc_stats.ast_rx_2040++; 542 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 543 sc->sc_stats.ast_rx_pre_crc_err++; 544 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 545 sc->sc_stats.ast_rx_post_crc_err++; 546 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 547 sc->sc_stats.ast_rx_decrypt_busy_err++; 548 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 549 sc->sc_stats.ast_rx_hi_rx_chain++; 550 if (rs->rs_flags & HAL_RX_STBC) 551 sc->sc_stats.ast_rx_stbc++; 552 #endif /* AH_SUPPORT_AR5416 */ 553 554 if (rs->rs_status != 0) { 555 if (rs->rs_status & HAL_RXERR_CRC) 556 sc->sc_stats.ast_rx_crcerr++; 557 if (rs->rs_status & HAL_RXERR_FIFO) 558 sc->sc_stats.ast_rx_fifoerr++; 559 if (rs->rs_status & HAL_RXERR_PHY) { 560 sc->sc_stats.ast_rx_phyerr++; 561 /* Process DFS radar events */ 562 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 563 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 564 /* Now pass it to the radar processing code */ 565 ath_dfs_process_phy_err(sc, m, rstamp, rs); 566 } 567 568 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 569 if (rs->rs_phyerr < 64) 570 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 571 goto rx_error; /* NB: don't count in ierrors */ 572 } 573 if (rs->rs_status & HAL_RXERR_DECRYPT) { 574 /* 575 * Decrypt error. If the error occurred 576 * because there was no hardware key, then 577 * let the frame through so the upper layers 578 * can process it. This is necessary for 5210 579 * parts which have no way to setup a ``clear'' 580 * key cache entry. 581 * 582 * XXX do key cache faulting 583 */ 584 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 585 goto rx_accept; 586 sc->sc_stats.ast_rx_badcrypt++; 587 } 588 /* 589 * Similar as above - if the failure was a keymiss 590 * just punt it up to the upper layers for now. 591 */ 592 if (rs->rs_status & HAL_RXERR_KEYMISS) { 593 sc->sc_stats.ast_rx_keymiss++; 594 goto rx_accept; 595 } 596 if (rs->rs_status & HAL_RXERR_MIC) { 597 sc->sc_stats.ast_rx_badmic++; 598 /* 599 * Do minimal work required to hand off 600 * the 802.11 header for notification. 601 */ 602 /* XXX frag's and qos frames */ 603 len = rs->rs_datalen; 604 if (len >= sizeof (struct ieee80211_frame)) { 605 ath_handle_micerror(ic, 606 mtod(m, struct ieee80211_frame *), 607 sc->sc_splitmic ? 608 rs->rs_keyix-32 : rs->rs_keyix); 609 } 610 } 611 ifp->if_ierrors++; 612 rx_error: 613 /* 614 * Cleanup any pending partial frame. 615 */ 616 if (re->m_rxpending != NULL) { 617 m_freem(re->m_rxpending); 618 re->m_rxpending = NULL; 619 } 620 /* 621 * When a tap is present pass error frames 622 * that have been requested. By default we 623 * pass decrypt+mic errors but others may be 624 * interesting (e.g. crc). 625 */ 626 if (ieee80211_radiotap_active(ic) && 627 (rs->rs_status & sc->sc_monpass)) { 628 /* NB: bpf needs the mbuf length setup */ 629 len = rs->rs_datalen; 630 m->m_pkthdr.len = m->m_len = len; 631 ath_rx_tap(ifp, m, rs, rstamp, nf); 632 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 633 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 634 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 635 ieee80211_radiotap_rx_all(ic, m); 636 } 637 /* XXX pass MIC errors up for s/w reclaculation */ 638 m_freem(m); m = NULL; 639 goto rx_next; 640 } 641 rx_accept: 642 len = rs->rs_datalen; 643 m->m_len = len; 644 645 if (rs->rs_more) { 646 /* 647 * Frame spans multiple descriptors; save 648 * it for the next completed descriptor, it 649 * will be used to construct a jumbogram. 650 */ 651 if (re->m_rxpending != NULL) { 652 /* NB: max frame size is currently 2 clusters */ 653 sc->sc_stats.ast_rx_toobig++; 654 m_freem(re->m_rxpending); 655 } 656 m->m_pkthdr.rcvif = ifp; 657 m->m_pkthdr.len = len; 658 re->m_rxpending = m; 659 m = NULL; 660 goto rx_next; 661 } else if (re->m_rxpending != NULL) { 662 /* 663 * This is the second part of a jumbogram, 664 * chain it to the first mbuf, adjust the 665 * frame length, and clear the rxpending state. 666 */ 667 re->m_rxpending->m_next = m; 668 re->m_rxpending->m_pkthdr.len += len; 669 m = re->m_rxpending; 670 re->m_rxpending = NULL; 671 } else { 672 /* 673 * Normal single-descriptor receive; setup 674 * the rcvif and packet length. 675 */ 676 m->m_pkthdr.rcvif = ifp; 677 m->m_pkthdr.len = len; 678 } 679 680 /* 681 * Validate rs->rs_antenna. 682 * 683 * Some users w/ AR9285 NICs have reported crashes 684 * here because rs_antenna field is bogusly large. 685 * Let's enforce the maximum antenna limit of 8 686 * (and it shouldn't be hard coded, but that's a 687 * separate problem) and if there's an issue, print 688 * out an error and adjust rs_antenna to something 689 * sensible. 690 * 691 * This code should be removed once the actual 692 * root cause of the issue has been identified. 693 * For example, it may be that the rs_antenna 694 * field is only valid for the lsat frame of 695 * an aggregate and it just happens that it is 696 * "mostly" right. (This is a general statement - 697 * the majority of the statistics are only valid 698 * for the last frame in an aggregate. 699 */ 700 if (rs->rs_antenna > 7) { 701 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 702 __func__, rs->rs_antenna); 703 #ifdef ATH_DEBUG 704 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 705 #endif /* ATH_DEBUG */ 706 rs->rs_antenna = 0; /* XXX better than nothing */ 707 } 708 709 /* 710 * If this is an AR9285/AR9485, then the receive and LNA 711 * configuration is stored in RSSI[2] / EXTRSSI[2]. 712 * We can extract this out to build a much better 713 * receive antenna profile. 714 * 715 * Yes, this just blurts over the above RX antenna field 716 * for now. It's fine, the AR9285 doesn't really use 717 * that. 718 * 719 * Later on we should store away the fine grained LNA 720 * information and keep separate counters just for 721 * that. It'll help when debugging the AR9285/AR9485 722 * combined diversity code. 723 */ 724 if (sc->sc_rx_lnamixer) { 725 rs->rs_antenna = 0; 726 727 /* Bits 0:1 - the LNA configuration used */ 728 rs->rs_antenna |= 729 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 730 >> HAL_RX_LNA_CFG_USED_S); 731 732 /* Bit 2 - the external RX antenna switch */ 733 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 734 rs->rs_antenna |= 0x4; 735 } 736 737 ifp->if_ipackets++; 738 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 739 740 /* 741 * Populate the rx status block. When there are bpf 742 * listeners we do the additional work to provide 743 * complete status. Otherwise we fill in only the 744 * material required by ieee80211_input. Note that 745 * noise setting is filled in above. 746 */ 747 if (ieee80211_radiotap_active(ic)) { 748 ath_rx_tap(ifp, m, rs, rstamp, nf); 749 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 750 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 751 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 752 } 753 754 /* 755 * From this point on we assume the frame is at least 756 * as large as ieee80211_frame_min; verify that. 757 */ 758 if (len < IEEE80211_MIN_LEN) { 759 if (!ieee80211_radiotap_active(ic)) { 760 DPRINTF(sc, ATH_DEBUG_RECV, 761 "%s: short packet %d\n", __func__, len); 762 sc->sc_stats.ast_rx_tooshort++; 763 } else { 764 /* NB: in particular this captures ack's */ 765 ieee80211_radiotap_rx_all(ic, m); 766 } 767 m_freem(m); m = NULL; 768 goto rx_next; 769 } 770 771 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 772 const HAL_RATE_TABLE *rt = sc->sc_currates; 773 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 774 775 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 776 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 777 } 778 779 m_adj(m, -IEEE80211_CRC_LEN); 780 781 /* 782 * Locate the node for sender, track state, and then 783 * pass the (referenced) node up to the 802.11 layer 784 * for its use. 785 */ 786 ni = ieee80211_find_rxnode_withkey(ic, 787 mtod(m, const struct ieee80211_frame_min *), 788 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 789 IEEE80211_KEYIX_NONE : rs->rs_keyix); 790 sc->sc_lastrs = rs; 791 792 #ifdef AH_SUPPORT_AR5416 793 if (rs->rs_isaggr) 794 sc->sc_stats.ast_rx_agg++; 795 #endif /* AH_SUPPORT_AR5416 */ 796 797 if (ni != NULL) { 798 /* 799 * Only punt packets for ampdu reorder processing for 800 * 11n nodes; net80211 enforces that M_AMPDU is only 801 * set for 11n nodes. 802 */ 803 if (ni->ni_flags & IEEE80211_NODE_HT) 804 m->m_flags |= M_AMPDU; 805 806 /* 807 * Sending station is known, dispatch directly. 808 */ 809 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 810 ieee80211_free_node(ni); 811 m = NULL; 812 /* 813 * Arrange to update the last rx timestamp only for 814 * frames from our ap when operating in station mode. 815 * This assumes the rx key is always setup when 816 * associated. 817 */ 818 if (ic->ic_opmode == IEEE80211_M_STA && 819 rs->rs_keyix != HAL_RXKEYIX_INVALID) 820 is_good = 1; 821 } else { 822 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 823 m = NULL; 824 } 825 826 /* 827 * At this point we have passed the frame up the stack; thus 828 * the mbuf is no longer ours. 829 */ 830 831 /* 832 * Track rx rssi and do any rx antenna management. 833 */ 834 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 835 if (sc->sc_diversity) { 836 /* 837 * When using fast diversity, change the default rx 838 * antenna if diversity chooses the other antenna 3 839 * times in a row. 840 */ 841 if (sc->sc_defant != rs->rs_antenna) { 842 if (++sc->sc_rxotherant >= 3) 843 ath_setdefantenna(sc, rs->rs_antenna); 844 } else 845 sc->sc_rxotherant = 0; 846 } 847 848 /* Handle slow diversity if enabled */ 849 if (sc->sc_dolnadiv) { 850 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 851 } 852 853 if (sc->sc_softled) { 854 /* 855 * Blink for any data frame. Otherwise do a 856 * heartbeat-style blink when idle. The latter 857 * is mainly for station mode where we depend on 858 * periodic beacon frames to trigger the poll event. 859 */ 860 if (type == IEEE80211_FC0_TYPE_DATA) { 861 const HAL_RATE_TABLE *rt = sc->sc_currates; 862 ath_led_event(sc, 863 rt->rateCodeToIndex[rs->rs_rate]); 864 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 865 ath_led_event(sc, 0); 866 } 867 rx_next: 868 /* 869 * Debugging - complain if we didn't NULL the mbuf pointer 870 * here. 871 */ 872 if (m != NULL) { 873 device_printf(sc->sc_dev, 874 "%s: mbuf %p should've been freed!\n", 875 __func__, 876 m); 877 } 878 return (is_good); 879 } 880 881 #define ATH_RX_MAX 128 882 883 static void 884 ath_rx_proc(struct ath_softc *sc, int resched) 885 { 886 #define PA2DESC(_sc, _pa) \ 887 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 888 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 889 struct ath_buf *bf; 890 struct ifnet *ifp = sc->sc_ifp; 891 struct ath_hal *ah = sc->sc_ah; 892 #ifdef IEEE80211_SUPPORT_SUPERG 893 struct ieee80211com *ic = ifp->if_l2com; 894 #endif 895 struct ath_desc *ds; 896 struct ath_rx_status *rs; 897 struct mbuf *m; 898 int ngood; 899 HAL_STATUS status; 900 int16_t nf; 901 u_int64_t tsf; 902 int npkts = 0; 903 int kickpcu = 0; 904 905 /* XXX we must not hold the ATH_LOCK here */ 906 ATH_UNLOCK_ASSERT(sc); 907 ATH_PCU_UNLOCK_ASSERT(sc); 908 909 ATH_PCU_LOCK(sc); 910 sc->sc_rxproc_cnt++; 911 kickpcu = sc->sc_kickpcu; 912 ATH_PCU_UNLOCK(sc); 913 914 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 915 ngood = 0; 916 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 917 sc->sc_stats.ast_rx_noise = nf; 918 tsf = ath_hal_gettsf64(ah); 919 do { 920 /* 921 * Don't process too many packets at a time; give the 922 * TX thread time to also run - otherwise the TX 923 * latency can jump by quite a bit, causing throughput 924 * degredation. 925 */ 926 if (!kickpcu && npkts >= ATH_RX_MAX) 927 break; 928 929 bf = TAILQ_FIRST(&sc->sc_rxbuf); 930 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 931 if_printf(ifp, "%s: no buffer!\n", __func__); 932 break; 933 } else if (bf == NULL) { 934 /* 935 * End of List: 936 * this can happen for non-self-linked RX chains 937 */ 938 sc->sc_stats.ast_rx_hitqueueend++; 939 break; 940 } 941 m = bf->bf_m; 942 if (m == NULL) { /* NB: shouldn't happen */ 943 /* 944 * If mbuf allocation failed previously there 945 * will be no mbuf; try again to re-populate it. 946 */ 947 /* XXX make debug msg */ 948 if_printf(ifp, "%s: no mbuf!\n", __func__); 949 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 950 goto rx_proc_next; 951 } 952 ds = bf->bf_desc; 953 if (ds->ds_link == bf->bf_daddr) { 954 /* NB: never process the self-linked entry at the end */ 955 sc->sc_stats.ast_rx_hitqueueend++; 956 break; 957 } 958 /* XXX sync descriptor memory */ 959 /* 960 * Must provide the virtual address of the current 961 * descriptor, the physical address, and the virtual 962 * address of the next descriptor in the h/w chain. 963 * This allows the HAL to look ahead to see if the 964 * hardware is done with a descriptor by checking the 965 * done bit in the following descriptor and the address 966 * of the current descriptor the DMA engine is working 967 * on. All this is necessary because of our use of 968 * a self-linked list to avoid rx overruns. 969 */ 970 rs = &bf->bf_status.ds_rxstat; 971 status = ath_hal_rxprocdesc(ah, ds, 972 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 973 #ifdef ATH_DEBUG 974 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 975 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 976 #endif 977 978 #ifdef ATH_DEBUG_ALQ 979 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 980 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 981 sc->sc_rx_statuslen, (char *) ds); 982 #endif /* ATH_DEBUG_ALQ */ 983 984 if (status == HAL_EINPROGRESS) 985 break; 986 987 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 988 npkts++; 989 990 /* 991 * Process a single frame. 992 */ 993 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 994 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 995 bf->bf_m = NULL; 996 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 997 ngood++; 998 rx_proc_next: 999 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1000 } while (ath_rxbuf_init(sc, bf) == 0); 1001 1002 /* rx signal state monitoring */ 1003 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1004 if (ngood) 1005 sc->sc_lastrx = tsf; 1006 1007 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1008 /* Queue DFS tasklet if needed */ 1009 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1010 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1011 1012 /* 1013 * Now that all the RX frames were handled that 1014 * need to be handled, kick the PCU if there's 1015 * been an RXEOL condition. 1016 */ 1017 if (resched && kickpcu) { 1018 ATH_PCU_LOCK(sc); 1019 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1020 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1021 __func__, npkts); 1022 1023 /* 1024 * Go through the process of fully tearing down 1025 * the RX buffers and reinitialising them. 1026 * 1027 * There's a hardware bug that causes the RX FIFO 1028 * to get confused under certain conditions and 1029 * constantly write over the same frame, leading 1030 * the RX driver code here to get heavily confused. 1031 */ 1032 #if 1 1033 ath_startrecv(sc); 1034 #else 1035 /* 1036 * Disabled for now - it'd be nice to be able to do 1037 * this in order to limit the amount of CPU time spent 1038 * reinitialising the RX side (and thus minimise RX 1039 * drops) however there's a hardware issue that 1040 * causes things to get too far out of whack. 1041 */ 1042 /* 1043 * XXX can we hold the PCU lock here? 1044 * Are there any net80211 buffer calls involved? 1045 */ 1046 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1047 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1048 ath_hal_rxena(ah); /* enable recv descriptors */ 1049 ath_mode_init(sc); /* set filters, etc. */ 1050 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1051 #endif 1052 1053 ath_hal_intrset(ah, sc->sc_imask); 1054 sc->sc_kickpcu = 0; 1055 ATH_PCU_UNLOCK(sc); 1056 } 1057 1058 /* XXX check this inside of IF_LOCK? */ 1059 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 1060 #ifdef IEEE80211_SUPPORT_SUPERG 1061 ieee80211_ff_age_all(ic, 100); 1062 #endif 1063 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1064 ath_tx_kick(sc); 1065 } 1066 #undef PA2DESC 1067 1068 /* 1069 * If we hit the maximum number of frames in this round, 1070 * reschedule for another immediate pass. This gives 1071 * the TX and TX completion routines time to run, which 1072 * will reduce latency. 1073 */ 1074 if (npkts >= ATH_RX_MAX) 1075 sc->sc_rx.recv_sched(sc, resched); 1076 1077 ATH_PCU_LOCK(sc); 1078 sc->sc_rxproc_cnt--; 1079 ATH_PCU_UNLOCK(sc); 1080 } 1081 1082 #undef ATH_RX_MAX 1083 1084 /* 1085 * Only run the RX proc if it's not already running. 1086 * Since this may get run as part of the reset/flush path, 1087 * the task can't clash with an existing, running tasklet. 1088 */ 1089 static void 1090 ath_legacy_rx_tasklet(void *arg, int npending) 1091 { 1092 struct ath_softc *sc = arg; 1093 1094 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1095 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1096 ATH_PCU_LOCK(sc); 1097 if (sc->sc_inreset_cnt > 0) { 1098 device_printf(sc->sc_dev, 1099 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1100 ATH_PCU_UNLOCK(sc); 1101 return; 1102 } 1103 ATH_PCU_UNLOCK(sc); 1104 1105 ath_rx_proc(sc, 1); 1106 } 1107 1108 static void 1109 ath_legacy_flushrecv(struct ath_softc *sc) 1110 { 1111 1112 ath_rx_proc(sc, 0); 1113 } 1114 1115 /* 1116 * Disable the receive h/w in preparation for a reset. 1117 */ 1118 static void 1119 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1120 { 1121 #define PA2DESC(_sc, _pa) \ 1122 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1123 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1124 struct ath_hal *ah = sc->sc_ah; 1125 1126 ath_hal_stoppcurecv(ah); /* disable PCU */ 1127 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1128 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1129 /* 1130 * TODO: see if this particular DELAY() is required; it may be 1131 * masking some missing FIFO flush or DMA sync. 1132 */ 1133 #if 0 1134 if (dodelay) 1135 #endif 1136 DELAY(3000); /* 3ms is long enough for 1 frame */ 1137 #ifdef ATH_DEBUG 1138 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1139 struct ath_buf *bf; 1140 u_int ix; 1141 1142 device_printf(sc->sc_dev, 1143 "%s: rx queue %p, link %p\n", 1144 __func__, 1145 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1146 sc->sc_rxlink); 1147 ix = 0; 1148 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1149 struct ath_desc *ds = bf->bf_desc; 1150 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1151 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1152 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1153 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1154 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1155 ix++; 1156 } 1157 } 1158 #endif 1159 /* 1160 * Free both high/low RX pending, just in case. 1161 */ 1162 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1163 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1164 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1165 } 1166 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1167 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1168 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1169 } 1170 sc->sc_rxlink = NULL; /* just in case */ 1171 #undef PA2DESC 1172 } 1173 1174 /* 1175 * Enable the receive h/w following a reset. 1176 */ 1177 static int 1178 ath_legacy_startrecv(struct ath_softc *sc) 1179 { 1180 struct ath_hal *ah = sc->sc_ah; 1181 struct ath_buf *bf; 1182 1183 sc->sc_rxlink = NULL; 1184 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1185 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1186 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1187 int error = ath_rxbuf_init(sc, bf); 1188 if (error != 0) { 1189 DPRINTF(sc, ATH_DEBUG_RECV, 1190 "%s: ath_rxbuf_init failed %d\n", 1191 __func__, error); 1192 return error; 1193 } 1194 } 1195 1196 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1197 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1198 ath_hal_rxena(ah); /* enable recv descriptors */ 1199 ath_mode_init(sc); /* set filters, etc. */ 1200 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1201 return 0; 1202 } 1203 1204 static int 1205 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1206 { 1207 int error; 1208 1209 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1210 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1211 if (error != 0) 1212 return (error); 1213 1214 return (0); 1215 } 1216 1217 static int 1218 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1219 { 1220 1221 if (sc->sc_rxdma.dd_desc_len != 0) 1222 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1223 return (0); 1224 } 1225 1226 static void 1227 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1228 { 1229 1230 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1231 } 1232 1233 static void 1234 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1235 int dosched) 1236 { 1237 1238 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1239 } 1240 1241 void 1242 ath_recv_setup_legacy(struct ath_softc *sc) 1243 { 1244 1245 /* Sensible legacy defaults */ 1246 /* 1247 * XXX this should be changed to properly support the 1248 * exact RX descriptor size for each HAL. 1249 */ 1250 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1251 1252 sc->sc_rx.recv_start = ath_legacy_startrecv; 1253 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1254 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1255 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1256 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1257 1258 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1259 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1260 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1261 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1262 } 1263