1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42 #include "opt_inet.h" 43 #include "opt_ath.h" 44 /* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51 #include "opt_ah.h" 52 #include "opt_wlan.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysctl.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/kernel.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 #include <sys/errno.h> 65 #include <sys/callout.h> 66 #include <sys/bus.h> 67 #include <sys/endian.h> 68 #include <sys/kthread.h> 69 #include <sys/taskqueue.h> 70 #include <sys/priv.h> 71 #include <sys/module.h> 72 #include <sys/ktr.h> 73 #include <sys/smp.h> /* for mp_ncpus */ 74 75 #include <machine/bus.h> 76 77 #include <net/if.h> 78 #include <net/if_var.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_var.h> 87 #include <net80211/ieee80211_regdomain.h> 88 #ifdef IEEE80211_SUPPORT_SUPERG 89 #include <net80211/ieee80211_superg.h> 90 #endif 91 #ifdef IEEE80211_SUPPORT_TDMA 92 #include <net80211/ieee80211_tdma.h> 93 #endif 94 95 #include <net/bpf.h> 96 97 #ifdef INET 98 #include <netinet/in.h> 99 #include <netinet/if_ether.h> 100 #endif 101 102 #include <dev/ath/if_athvar.h> 103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 104 #include <dev/ath/ath_hal/ah_diagcodes.h> 105 106 #include <dev/ath/if_ath_debug.h> 107 #include <dev/ath/if_ath_misc.h> 108 #include <dev/ath/if_ath_tsf.h> 109 #include <dev/ath/if_ath_tx.h> 110 #include <dev/ath/if_ath_sysctl.h> 111 #include <dev/ath/if_ath_led.h> 112 #include <dev/ath/if_ath_keycache.h> 113 #include <dev/ath/if_ath_rx.h> 114 #include <dev/ath/if_ath_beacon.h> 115 #include <dev/ath/if_athdfs.h> 116 #include <dev/ath/if_ath_descdma.h> 117 118 #ifdef ATH_TX99_DIAG 119 #include <dev/ath/ath_tx99/ath_tx99.h> 120 #endif 121 122 #ifdef ATH_DEBUG_ALQ 123 #include <dev/ath/if_ath_alq.h> 124 #endif 125 126 #include <dev/ath/if_ath_lna_div.h> 127 128 /* 129 * Calculate the receive filter according to the 130 * operating mode and state: 131 * 132 * o always accept unicast, broadcast, and multicast traffic 133 * o accept PHY error frames when hardware doesn't have MIB support 134 * to count and we need them for ANI (sta mode only until recently) 135 * and we are not scanning (ANI is disabled) 136 * NB: older hal's add rx filter bits out of sight and we need to 137 * blindly preserve them 138 * o probe request frames are accepted only when operating in 139 * hostap, adhoc, mesh, or monitor modes 140 * o enable promiscuous mode 141 * - when in monitor mode 142 * - if interface marked PROMISC (assumes bridge setting is filtered) 143 * o accept beacons: 144 * - when operating in station mode for collecting rssi data when 145 * the station is otherwise quiet, or 146 * - when operating in adhoc mode so the 802.11 layer creates 147 * node table entries for peers, 148 * - when scanning 149 * - when doing s/w beacon miss (e.g. for ap+sta) 150 * - when operating in ap mode in 11g to detect overlapping bss that 151 * require protection 152 * - when operating in mesh mode to detect neighbors 153 * o accept control frames: 154 * - when in monitor mode 155 * XXX HT protection for 11n 156 */ 157 u_int32_t 158 ath_calcrxfilter(struct ath_softc *sc) 159 { 160 struct ieee80211com *ic = &sc->sc_ic; 161 u_int32_t rfilt; 162 163 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 164 if (!sc->sc_needmib && !sc->sc_scanning) 165 rfilt |= HAL_RX_FILTER_PHYERR; 166 if (ic->ic_opmode != IEEE80211_M_STA) 167 rfilt |= HAL_RX_FILTER_PROBEREQ; 168 /* XXX ic->ic_monvaps != 0? */ 169 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0) 170 rfilt |= HAL_RX_FILTER_PROM; 171 172 /* 173 * Only listen to all beacons if we're scanning. 174 * 175 * Otherwise we only really need to hear beacons from 176 * our own BSSID. 177 * 178 * IBSS? software beacon miss? Just receive all beacons. 179 * We need to hear beacons/probe requests from everyone so 180 * we can merge ibss. 181 */ 182 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 183 rfilt |= HAL_RX_FILTER_BEACON; 184 } else if (ic->ic_opmode == IEEE80211_M_STA) { 185 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 186 rfilt |= HAL_RX_FILTER_MYBEACON; 187 } else { /* scanning, non-mybeacon chips */ 188 rfilt |= HAL_RX_FILTER_BEACON; 189 } 190 } 191 192 /* 193 * NB: We don't recalculate the rx filter when 194 * ic_protmode changes; otherwise we could do 195 * this only when ic_protmode != NONE. 196 */ 197 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 198 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 199 rfilt |= HAL_RX_FILTER_BEACON; 200 201 /* 202 * Enable hardware PS-POLL RX only for hostap mode; 203 * STA mode sends PS-POLL frames but never 204 * receives them. 205 */ 206 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 207 0, NULL) == HAL_OK && 208 ic->ic_opmode == IEEE80211_M_HOSTAP) 209 rfilt |= HAL_RX_FILTER_PSPOLL; 210 211 if (sc->sc_nmeshvaps) { 212 rfilt |= HAL_RX_FILTER_BEACON; 213 if (sc->sc_hasbmatch) 214 rfilt |= HAL_RX_FILTER_BSSID; 215 else 216 rfilt |= HAL_RX_FILTER_PROM; 217 } 218 if (ic->ic_opmode == IEEE80211_M_MONITOR) 219 rfilt |= HAL_RX_FILTER_CONTROL; 220 221 /* 222 * Enable RX of compressed BAR frames only when doing 223 * 802.11n. Required for A-MPDU. 224 */ 225 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 226 rfilt |= HAL_RX_FILTER_COMPBAR; 227 228 /* 229 * Enable radar PHY errors if requested by the 230 * DFS module. 231 */ 232 if (sc->sc_dodfs) 233 rfilt |= HAL_RX_FILTER_PHYRADAR; 234 235 /* 236 * Enable spectral PHY errors if requested by the 237 * spectral module. 238 */ 239 if (sc->sc_dospectral) 240 rfilt |= HAL_RX_FILTER_PHYRADAR; 241 242 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n", 243 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]); 244 return rfilt; 245 } 246 247 static int 248 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 249 { 250 struct ath_hal *ah = sc->sc_ah; 251 int error; 252 struct mbuf *m; 253 struct ath_desc *ds; 254 255 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 256 257 m = bf->bf_m; 258 if (m == NULL) { 259 /* 260 * NB: by assigning a page to the rx dma buffer we 261 * implicitly satisfy the Atheros requirement that 262 * this buffer be cache-line-aligned and sized to be 263 * multiple of the cache line size. Not doing this 264 * causes weird stuff to happen (for the 5210 at least). 265 */ 266 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 267 if (m == NULL) { 268 DPRINTF(sc, ATH_DEBUG_ANY, 269 "%s: no mbuf/cluster\n", __func__); 270 sc->sc_stats.ast_rx_nombuf++; 271 return ENOMEM; 272 } 273 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 274 275 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 276 bf->bf_dmamap, m, 277 bf->bf_segs, &bf->bf_nseg, 278 BUS_DMA_NOWAIT); 279 if (error != 0) { 280 DPRINTF(sc, ATH_DEBUG_ANY, 281 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 282 __func__, error); 283 sc->sc_stats.ast_rx_busdma++; 284 m_freem(m); 285 return error; 286 } 287 KASSERT(bf->bf_nseg == 1, 288 ("multi-segment packet; nseg %u", bf->bf_nseg)); 289 bf->bf_m = m; 290 } 291 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 292 293 /* 294 * Setup descriptors. For receive we always terminate 295 * the descriptor list with a self-linked entry so we'll 296 * not get overrun under high load (as can happen with a 297 * 5212 when ANI processing enables PHY error frames). 298 * 299 * To insure the last descriptor is self-linked we create 300 * each descriptor as self-linked and add it to the end. As 301 * each additional descriptor is added the previous self-linked 302 * entry is ``fixed'' naturally. This should be safe even 303 * if DMA is happening. When processing RX interrupts we 304 * never remove/process the last, self-linked, entry on the 305 * descriptor list. This insures the hardware always has 306 * someplace to write a new frame. 307 */ 308 /* 309 * 11N: we can no longer afford to self link the last descriptor. 310 * MAC acknowledges BA status as long as it copies frames to host 311 * buffer (or rx fifo). This can incorrectly acknowledge packets 312 * to a sender if last desc is self-linked. 313 */ 314 ds = bf->bf_desc; 315 if (sc->sc_rxslink) 316 ds->ds_link = bf->bf_daddr; /* link to self */ 317 else 318 ds->ds_link = 0; /* terminate the list */ 319 ds->ds_data = bf->bf_segs[0].ds_addr; 320 ath_hal_setuprxdesc(ah, ds 321 , m->m_len /* buffer size */ 322 , 0 323 ); 324 325 if (sc->sc_rxlink != NULL) 326 *sc->sc_rxlink = bf->bf_daddr; 327 sc->sc_rxlink = &ds->ds_link; 328 return 0; 329 } 330 331 /* 332 * Intercept management frames to collect beacon rssi data 333 * and to do ibss merges. 334 */ 335 void 336 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 337 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) 338 { 339 struct ieee80211vap *vap = ni->ni_vap; 340 struct ath_softc *sc = vap->iv_ic->ic_softc; 341 uint64_t tsf_beacon_old, tsf_beacon; 342 uint64_t nexttbtt; 343 int64_t tsf_delta; 344 int32_t tsf_delta_bmiss; 345 int32_t tsf_remainder; 346 uint64_t tsf_beacon_target; 347 int tsf_intval; 348 349 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 350 tsf_beacon_old |= le32dec(ni->ni_tstamp.data); 351 352 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 353 tsf_intval = 1; 354 if (ni->ni_intval > 0) { 355 tsf_intval = TU_TO_TSF(ni->ni_intval); 356 } 357 #undef TU_TO_TSF 358 359 /* 360 * Call up first so subsequent work can use information 361 * potentially stored in the node (e.g. for ibss merge). 362 */ 363 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf); 364 switch (subtype) { 365 case IEEE80211_FC0_SUBTYPE_BEACON: 366 367 /* 368 * Only do the following processing if it's for 369 * the current BSS. 370 * 371 * In scan and IBSS mode we receive all beacons, 372 * which means we need to filter out stuff 373 * that isn't for us or we'll end up constantly 374 * trying to sync / merge to BSSes that aren't 375 * actually us. 376 */ 377 if (IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) { 378 /* update rssi statistics for use by the hal */ 379 /* XXX unlocked check against vap->iv_bss? */ 380 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 381 382 383 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 384 tsf_beacon |= le32dec(ni->ni_tstamp.data); 385 386 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 387 388 /* 389 * Let's calculate the delta and remainder, so we can see 390 * if the beacon timer from the AP is varying by more than 391 * a few TU. (Which would be a huge, huge problem.) 392 */ 393 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 394 395 tsf_delta_bmiss = tsf_delta / tsf_intval; 396 397 /* 398 * If our delta is greater than half the beacon interval, 399 * let's round the bmiss value up to the next beacon 400 * interval. Ie, we're running really, really early 401 * on the next beacon. 402 */ 403 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 404 tsf_delta_bmiss ++; 405 406 tsf_beacon_target = tsf_beacon_old + 407 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 408 409 /* 410 * The remainder using '%' is between 0 .. intval-1. 411 * If we're actually running too fast, then the remainder 412 * will be some large number just under intval-1. 413 * So we need to look at whether we're running 414 * before or after the target beacon interval 415 * and if we are, modify how we do the remainder 416 * calculation. 417 */ 418 if (tsf_beacon < tsf_beacon_target) { 419 tsf_remainder = 420 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 421 } else { 422 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 423 } 424 425 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu (%u), new_tsf=%llu (%u), target_tsf=%llu (%u), delta=%lld, bmiss=%d, remainder=%d\n", 426 __func__, 427 (unsigned long long) tsf_beacon_old, 428 (unsigned int) (tsf_beacon_old >> 10), 429 (unsigned long long) tsf_beacon, 430 (unsigned int ) (tsf_beacon >> 10), 431 (unsigned long long) tsf_beacon_target, 432 (unsigned int) (tsf_beacon_target >> 10), 433 (long long) tsf_delta, 434 tsf_delta_bmiss, 435 tsf_remainder); 436 437 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu (%u), nexttbtt=%llu (%u), delta=%d\n", 438 __func__, 439 (unsigned long long) tsf_beacon, 440 (unsigned int) (tsf_beacon >> 10), 441 (unsigned long long) nexttbtt, 442 (unsigned int) (nexttbtt >> 10), 443 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 444 445 /* We only do syncbeacon on STA VAPs; not on IBSS */ 446 if (vap->iv_opmode == IEEE80211_M_STA && 447 sc->sc_syncbeacon && 448 ni == vap->iv_bss && 449 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 450 DPRINTF(sc, ATH_DEBUG_BEACON, 451 "%s: syncbeacon=1; syncing\n", 452 __func__); 453 /* 454 * Resync beacon timers using the tsf of the beacon 455 * frame we just received. 456 */ 457 ath_beacon_config(sc, vap); 458 sc->sc_syncbeacon = 0; 459 } 460 } 461 462 /* fall thru... */ 463 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 464 if (vap->iv_opmode == IEEE80211_M_IBSS && 465 vap->iv_state == IEEE80211_S_RUN && 466 ieee80211_ibss_merge_check(ni)) { 467 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 468 uint64_t tsf = ath_extend_tsf(sc, rstamp, 469 ath_hal_gettsf64(sc->sc_ah)); 470 /* 471 * Handle ibss merge as needed; check the tsf on the 472 * frame before attempting the merge. The 802.11 spec 473 * says the station should change it's bssid to match 474 * the oldest station with the same ssid, where oldest 475 * is determined by the tsf. Note that hardware 476 * reconfiguration happens through callback to 477 * ath_newstate as the state machine will go from 478 * RUN -> RUN when this happens. 479 */ 480 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 481 DPRINTF(sc, ATH_DEBUG_STATE, 482 "ibss merge, rstamp %u tsf %ju " 483 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 484 (uintmax_t)ni->ni_tstamp.tsf); 485 (void) ieee80211_ibss_merge(ni); 486 } 487 } 488 break; 489 } 490 } 491 492 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 493 static void 494 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m, 495 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 496 { 497 498 /* Fill in the extension bitmap */ 499 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 500 501 /* Fill in the vendor header */ 502 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 503 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 504 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 505 506 /* XXX what should this be? */ 507 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 508 sc->sc_rx_th.wr_vh.vh_skip_len = 509 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 510 511 /* General version info */ 512 sc->sc_rx_th.wr_v.vh_version = 1; 513 514 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 515 516 /* rssi */ 517 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 518 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 519 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 520 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 521 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 522 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 523 524 /* evm */ 525 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 526 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 527 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 528 /* These are only populated from the AR9300 or later */ 529 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 530 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 531 532 /* direction */ 533 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 534 535 /* RX rate */ 536 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 537 538 /* RX flags */ 539 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 540 541 if (rs->rs_isaggr) 542 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 543 if (rs->rs_moreaggr) 544 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 545 546 /* phyerr info */ 547 if (rs->rs_status & HAL_RXERR_PHY) { 548 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 549 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 550 } else { 551 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 552 } 553 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 554 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 555 } 556 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 557 558 static void 559 ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 560 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 561 { 562 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 563 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 564 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 565 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 566 const HAL_RATE_TABLE *rt; 567 uint8_t rix; 568 569 rt = sc->sc_currates; 570 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 571 rix = rt->rateCodeToIndex[rs->rs_rate]; 572 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 573 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 574 575 /* 802.11 specific flags */ 576 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 577 if (rs->rs_status & HAL_RXERR_PHY) { 578 /* 579 * PHY error - make sure the channel flags 580 * reflect the actual channel configuration, 581 * not the received frame. 582 */ 583 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 584 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 585 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 586 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 587 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 588 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 589 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 590 struct ieee80211com *ic = &sc->sc_ic; 591 592 if ((rs->rs_flags & HAL_RX_2040) == 0) 593 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 594 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 595 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 596 else 597 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 598 599 if (rs->rs_flags & HAL_RX_GI) 600 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 601 } 602 603 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 604 if (rs->rs_status & HAL_RXERR_CRC) 605 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 606 /* XXX propagate other error flags from descriptor */ 607 sc->sc_rx_th.wr_antnoise = nf; 608 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 609 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 610 #undef CHAN_HT 611 #undef CHAN_HT20 612 #undef CHAN_HT40U 613 #undef CHAN_HT40D 614 } 615 616 static void 617 ath_handle_micerror(struct ieee80211com *ic, 618 struct ieee80211_frame *wh, int keyix) 619 { 620 struct ieee80211_node *ni; 621 622 /* XXX recheck MIC to deal w/ chips that lie */ 623 /* XXX discard MIC errors on !data frames */ 624 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 625 if (ni != NULL) { 626 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 627 ieee80211_free_node(ni); 628 } 629 } 630 631 /* 632 * Process a single packet. 633 * 634 * The mbuf must already be synced, unmapped and removed from bf->bf_m 635 * by this stage. 636 * 637 * The mbuf must be consumed by this routine - either passed up the 638 * net80211 stack, put on the holding queue, or freed. 639 */ 640 int 641 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 642 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 643 struct mbuf *m) 644 { 645 uint64_t rstamp; 646 /* XXX TODO: make this an mbuf tag? */ 647 struct ieee80211_rx_stats rxs; 648 int len, type, i; 649 struct ieee80211com *ic = &sc->sc_ic; 650 struct ieee80211_node *ni; 651 int is_good = 0; 652 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 653 654 /* 655 * Calculate the correct 64 bit TSF given 656 * the TSF64 register value and rs_tstamp. 657 */ 658 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 659 660 /* 802.11 return codes - These aren't specifically errors */ 661 if (rs->rs_flags & HAL_RX_GI) 662 sc->sc_stats.ast_rx_halfgi++; 663 if (rs->rs_flags & HAL_RX_2040) 664 sc->sc_stats.ast_rx_2040++; 665 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 666 sc->sc_stats.ast_rx_pre_crc_err++; 667 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 668 sc->sc_stats.ast_rx_post_crc_err++; 669 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 670 sc->sc_stats.ast_rx_decrypt_busy_err++; 671 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 672 sc->sc_stats.ast_rx_hi_rx_chain++; 673 if (rs->rs_flags & HAL_RX_STBC) 674 sc->sc_stats.ast_rx_stbc++; 675 676 if (rs->rs_status != 0) { 677 if (rs->rs_status & HAL_RXERR_CRC) 678 sc->sc_stats.ast_rx_crcerr++; 679 if (rs->rs_status & HAL_RXERR_FIFO) 680 sc->sc_stats.ast_rx_fifoerr++; 681 if (rs->rs_status & HAL_RXERR_PHY) { 682 sc->sc_stats.ast_rx_phyerr++; 683 /* Process DFS radar events */ 684 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 685 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 686 /* Now pass it to the radar processing code */ 687 ath_dfs_process_phy_err(sc, m, rstamp, rs); 688 } 689 690 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 691 if (rs->rs_phyerr < 64) 692 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 693 goto rx_error; /* NB: don't count in ierrors */ 694 } 695 if (rs->rs_status & HAL_RXERR_DECRYPT) { 696 /* 697 * Decrypt error. If the error occurred 698 * because there was no hardware key, then 699 * let the frame through so the upper layers 700 * can process it. This is necessary for 5210 701 * parts which have no way to setup a ``clear'' 702 * key cache entry. 703 * 704 * XXX do key cache faulting 705 */ 706 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 707 goto rx_accept; 708 sc->sc_stats.ast_rx_badcrypt++; 709 } 710 /* 711 * Similar as above - if the failure was a keymiss 712 * just punt it up to the upper layers for now. 713 */ 714 if (rs->rs_status & HAL_RXERR_KEYMISS) { 715 sc->sc_stats.ast_rx_keymiss++; 716 goto rx_accept; 717 } 718 if (rs->rs_status & HAL_RXERR_MIC) { 719 sc->sc_stats.ast_rx_badmic++; 720 /* 721 * Do minimal work required to hand off 722 * the 802.11 header for notification. 723 */ 724 /* XXX frag's and qos frames */ 725 len = rs->rs_datalen; 726 if (len >= sizeof (struct ieee80211_frame)) { 727 ath_handle_micerror(ic, 728 mtod(m, struct ieee80211_frame *), 729 sc->sc_splitmic ? 730 rs->rs_keyix-32 : rs->rs_keyix); 731 } 732 } 733 counter_u64_add(ic->ic_ierrors, 1); 734 rx_error: 735 /* 736 * Cleanup any pending partial frame. 737 */ 738 if (re->m_rxpending != NULL) { 739 m_freem(re->m_rxpending); 740 re->m_rxpending = NULL; 741 } 742 /* 743 * When a tap is present pass error frames 744 * that have been requested. By default we 745 * pass decrypt+mic errors but others may be 746 * interesting (e.g. crc). 747 */ 748 if (ieee80211_radiotap_active(ic) && 749 (rs->rs_status & sc->sc_monpass)) { 750 /* NB: bpf needs the mbuf length setup */ 751 len = rs->rs_datalen; 752 m->m_pkthdr.len = m->m_len = len; 753 ath_rx_tap(sc, m, rs, rstamp, nf); 754 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 755 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 756 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 757 ieee80211_radiotap_rx_all(ic, m); 758 } 759 /* XXX pass MIC errors up for s/w reclaculation */ 760 m_freem(m); m = NULL; 761 goto rx_next; 762 } 763 rx_accept: 764 len = rs->rs_datalen; 765 m->m_len = len; 766 767 if (rs->rs_more) { 768 /* 769 * Frame spans multiple descriptors; save 770 * it for the next completed descriptor, it 771 * will be used to construct a jumbogram. 772 */ 773 if (re->m_rxpending != NULL) { 774 /* NB: max frame size is currently 2 clusters */ 775 sc->sc_stats.ast_rx_toobig++; 776 m_freem(re->m_rxpending); 777 } 778 m->m_pkthdr.len = len; 779 re->m_rxpending = m; 780 m = NULL; 781 goto rx_next; 782 } else if (re->m_rxpending != NULL) { 783 /* 784 * This is the second part of a jumbogram, 785 * chain it to the first mbuf, adjust the 786 * frame length, and clear the rxpending state. 787 */ 788 re->m_rxpending->m_next = m; 789 re->m_rxpending->m_pkthdr.len += len; 790 m = re->m_rxpending; 791 re->m_rxpending = NULL; 792 } else { 793 /* 794 * Normal single-descriptor receive; setup packet length. 795 */ 796 m->m_pkthdr.len = len; 797 } 798 799 /* 800 * Validate rs->rs_antenna. 801 * 802 * Some users w/ AR9285 NICs have reported crashes 803 * here because rs_antenna field is bogusly large. 804 * Let's enforce the maximum antenna limit of 8 805 * (and it shouldn't be hard coded, but that's a 806 * separate problem) and if there's an issue, print 807 * out an error and adjust rs_antenna to something 808 * sensible. 809 * 810 * This code should be removed once the actual 811 * root cause of the issue has been identified. 812 * For example, it may be that the rs_antenna 813 * field is only valid for the last frame of 814 * an aggregate and it just happens that it is 815 * "mostly" right. (This is a general statement - 816 * the majority of the statistics are only valid 817 * for the last frame in an aggregate. 818 */ 819 if (rs->rs_antenna > 7) { 820 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 821 __func__, rs->rs_antenna); 822 #ifdef ATH_DEBUG 823 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 824 #endif /* ATH_DEBUG */ 825 rs->rs_antenna = 0; /* XXX better than nothing */ 826 } 827 828 /* 829 * If this is an AR9285/AR9485, then the receive and LNA 830 * configuration is stored in RSSI[2] / EXTRSSI[2]. 831 * We can extract this out to build a much better 832 * receive antenna profile. 833 * 834 * Yes, this just blurts over the above RX antenna field 835 * for now. It's fine, the AR9285 doesn't really use 836 * that. 837 * 838 * Later on we should store away the fine grained LNA 839 * information and keep separate counters just for 840 * that. It'll help when debugging the AR9285/AR9485 841 * combined diversity code. 842 */ 843 if (sc->sc_rx_lnamixer) { 844 rs->rs_antenna = 0; 845 846 /* Bits 0:1 - the LNA configuration used */ 847 rs->rs_antenna |= 848 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 849 >> HAL_RX_LNA_CFG_USED_S); 850 851 /* Bit 2 - the external RX antenna switch */ 852 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 853 rs->rs_antenna |= 0x4; 854 } 855 856 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 857 858 /* 859 * Populate the rx status block. When there are bpf 860 * listeners we do the additional work to provide 861 * complete status. Otherwise we fill in only the 862 * material required by ieee80211_input. Note that 863 * noise setting is filled in above. 864 */ 865 if (ieee80211_radiotap_active(ic)) { 866 ath_rx_tap(sc, m, rs, rstamp, nf); 867 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 868 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 869 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 870 } 871 872 /* 873 * From this point on we assume the frame is at least 874 * as large as ieee80211_frame_min; verify that. 875 */ 876 if (len < IEEE80211_MIN_LEN) { 877 if (!ieee80211_radiotap_active(ic)) { 878 DPRINTF(sc, ATH_DEBUG_RECV, 879 "%s: short packet %d\n", __func__, len); 880 sc->sc_stats.ast_rx_tooshort++; 881 } else { 882 /* NB: in particular this captures ack's */ 883 ieee80211_radiotap_rx_all(ic, m); 884 } 885 m_freem(m); m = NULL; 886 goto rx_next; 887 } 888 889 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 890 const HAL_RATE_TABLE *rt = sc->sc_currates; 891 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 892 893 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 894 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 895 } 896 897 m_adj(m, -IEEE80211_CRC_LEN); 898 899 /* 900 * Locate the node for sender, track state, and then 901 * pass the (referenced) node up to the 802.11 layer 902 * for its use. 903 */ 904 ni = ieee80211_find_rxnode_withkey(ic, 905 mtod(m, const struct ieee80211_frame_min *), 906 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 907 IEEE80211_KEYIX_NONE : rs->rs_keyix); 908 sc->sc_lastrs = rs; 909 910 if (rs->rs_isaggr) 911 sc->sc_stats.ast_rx_agg++; 912 913 /* 914 * Populate the per-chain RSSI values where appropriate. 915 */ 916 bzero(&rxs, sizeof(rxs)); 917 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI | 918 IEEE80211_R_C_CHAIN | 919 IEEE80211_R_C_NF | 920 IEEE80211_R_C_RSSI | 921 IEEE80211_R_TSF64 | 922 IEEE80211_R_TSF_START; /* XXX TODO: validate */ 923 rxs.c_rssi = rs->rs_rssi; 924 rxs.c_nf = nf; 925 rxs.c_chain = 3; /* XXX TODO: check */ 926 rxs.c_rx_tsf = rstamp; 927 928 for (i = 0; i < 3; i++) { 929 rxs.c_rssi_ctl[i] = rs->rs_rssi_ctl[i]; 930 rxs.c_rssi_ext[i] = rs->rs_rssi_ext[i]; 931 /* 932 * XXX note: we currently don't track 933 * per-chain noisefloor. 934 */ 935 rxs.c_nf_ctl[i] = nf; 936 rxs.c_nf_ext[i] = nf; 937 } 938 939 if (ni != NULL) { 940 /* 941 * Only punt packets for ampdu reorder processing for 942 * 11n nodes; net80211 enforces that M_AMPDU is only 943 * set for 11n nodes. 944 */ 945 if (ni->ni_flags & IEEE80211_NODE_HT) 946 m->m_flags |= M_AMPDU; 947 948 /* 949 * Sending station is known, dispatch directly. 950 */ 951 (void) ieee80211_add_rx_params(m, &rxs); 952 type = ieee80211_input_mimo(ni, m); 953 ieee80211_free_node(ni); 954 m = NULL; 955 /* 956 * Arrange to update the last rx timestamp only for 957 * frames from our ap when operating in station mode. 958 * This assumes the rx key is always setup when 959 * associated. 960 */ 961 if (ic->ic_opmode == IEEE80211_M_STA && 962 rs->rs_keyix != HAL_RXKEYIX_INVALID) 963 is_good = 1; 964 } else { 965 (void) ieee80211_add_rx_params(m, &rxs); 966 type = ieee80211_input_mimo_all(ic, m); 967 m = NULL; 968 } 969 970 /* 971 * At this point we have passed the frame up the stack; thus 972 * the mbuf is no longer ours. 973 */ 974 975 /* 976 * Track rx rssi and do any rx antenna management. 977 */ 978 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 979 if (sc->sc_diversity) { 980 /* 981 * When using fast diversity, change the default rx 982 * antenna if diversity chooses the other antenna 3 983 * times in a row. 984 */ 985 if (sc->sc_defant != rs->rs_antenna) { 986 if (++sc->sc_rxotherant >= 3) 987 ath_setdefantenna(sc, rs->rs_antenna); 988 } else 989 sc->sc_rxotherant = 0; 990 } 991 992 /* Handle slow diversity if enabled */ 993 if (sc->sc_dolnadiv) { 994 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 995 } 996 997 if (sc->sc_softled) { 998 /* 999 * Blink for any data frame. Otherwise do a 1000 * heartbeat-style blink when idle. The latter 1001 * is mainly for station mode where we depend on 1002 * periodic beacon frames to trigger the poll event. 1003 */ 1004 if (type == IEEE80211_FC0_TYPE_DATA) { 1005 const HAL_RATE_TABLE *rt = sc->sc_currates; 1006 ath_led_event(sc, 1007 rt->rateCodeToIndex[rs->rs_rate]); 1008 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 1009 ath_led_event(sc, 0); 1010 } 1011 rx_next: 1012 /* 1013 * Debugging - complain if we didn't NULL the mbuf pointer 1014 * here. 1015 */ 1016 if (m != NULL) { 1017 device_printf(sc->sc_dev, 1018 "%s: mbuf %p should've been freed!\n", 1019 __func__, 1020 m); 1021 } 1022 return (is_good); 1023 } 1024 1025 #define ATH_RX_MAX 128 1026 1027 /* 1028 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 1029 * the EDMA code does. 1030 * 1031 * XXX TODO: then, do all of the RX list management stuff inside 1032 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 1033 * code is doing it right. 1034 */ 1035 static void 1036 ath_rx_proc(struct ath_softc *sc, int resched) 1037 { 1038 #define PA2DESC(_sc, _pa) \ 1039 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1040 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1041 struct ath_buf *bf; 1042 struct ath_hal *ah = sc->sc_ah; 1043 #ifdef IEEE80211_SUPPORT_SUPERG 1044 struct ieee80211com *ic = &sc->sc_ic; 1045 #endif 1046 struct ath_desc *ds; 1047 struct ath_rx_status *rs; 1048 struct mbuf *m; 1049 int ngood; 1050 HAL_STATUS status; 1051 int16_t nf; 1052 u_int64_t tsf; 1053 int npkts = 0; 1054 int kickpcu = 0; 1055 int ret; 1056 1057 /* XXX we must not hold the ATH_LOCK here */ 1058 ATH_UNLOCK_ASSERT(sc); 1059 ATH_PCU_UNLOCK_ASSERT(sc); 1060 1061 ATH_PCU_LOCK(sc); 1062 sc->sc_rxproc_cnt++; 1063 kickpcu = sc->sc_kickpcu; 1064 ATH_PCU_UNLOCK(sc); 1065 1066 ATH_LOCK(sc); 1067 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1068 ATH_UNLOCK(sc); 1069 1070 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1071 ngood = 0; 1072 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1073 sc->sc_stats.ast_rx_noise = nf; 1074 tsf = ath_hal_gettsf64(ah); 1075 do { 1076 /* 1077 * Don't process too many packets at a time; give the 1078 * TX thread time to also run - otherwise the TX 1079 * latency can jump by quite a bit, causing throughput 1080 * degredation. 1081 */ 1082 if (!kickpcu && npkts >= ATH_RX_MAX) 1083 break; 1084 1085 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1086 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1087 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__); 1088 break; 1089 } else if (bf == NULL) { 1090 /* 1091 * End of List: 1092 * this can happen for non-self-linked RX chains 1093 */ 1094 sc->sc_stats.ast_rx_hitqueueend++; 1095 break; 1096 } 1097 m = bf->bf_m; 1098 if (m == NULL) { /* NB: shouldn't happen */ 1099 /* 1100 * If mbuf allocation failed previously there 1101 * will be no mbuf; try again to re-populate it. 1102 */ 1103 /* XXX make debug msg */ 1104 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__); 1105 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1106 goto rx_proc_next; 1107 } 1108 ds = bf->bf_desc; 1109 if (ds->ds_link == bf->bf_daddr) { 1110 /* NB: never process the self-linked entry at the end */ 1111 sc->sc_stats.ast_rx_hitqueueend++; 1112 break; 1113 } 1114 /* XXX sync descriptor memory */ 1115 /* 1116 * Must provide the virtual address of the current 1117 * descriptor, the physical address, and the virtual 1118 * address of the next descriptor in the h/w chain. 1119 * This allows the HAL to look ahead to see if the 1120 * hardware is done with a descriptor by checking the 1121 * done bit in the following descriptor and the address 1122 * of the current descriptor the DMA engine is working 1123 * on. All this is necessary because of our use of 1124 * a self-linked list to avoid rx overruns. 1125 */ 1126 rs = &bf->bf_status.ds_rxstat; 1127 status = ath_hal_rxprocdesc(ah, ds, 1128 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1129 #ifdef ATH_DEBUG 1130 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1131 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1132 #endif 1133 1134 #ifdef ATH_DEBUG_ALQ 1135 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1136 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1137 sc->sc_rx_statuslen, (char *) ds); 1138 #endif /* ATH_DEBUG_ALQ */ 1139 1140 if (status == HAL_EINPROGRESS) 1141 break; 1142 1143 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1144 npkts++; 1145 1146 /* 1147 * Process a single frame. 1148 */ 1149 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1150 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1151 bf->bf_m = NULL; 1152 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1153 ngood++; 1154 rx_proc_next: 1155 /* 1156 * If there's a holding buffer, insert that onto 1157 * the RX list; the hardware is now definitely not pointing 1158 * to it now. 1159 */ 1160 ret = 0; 1161 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1162 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1163 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1164 bf_list); 1165 ret = ath_rxbuf_init(sc, 1166 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1167 } 1168 /* 1169 * Next, throw our buffer into the holding entry. The hardware 1170 * may use the descriptor to read the link pointer before 1171 * DMAing the next descriptor in to write out a packet. 1172 */ 1173 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1174 } while (ret == 0); 1175 1176 /* rx signal state monitoring */ 1177 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1178 if (ngood) 1179 sc->sc_lastrx = tsf; 1180 1181 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1182 /* Queue DFS tasklet if needed */ 1183 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1184 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1185 1186 /* 1187 * Now that all the RX frames were handled that 1188 * need to be handled, kick the PCU if there's 1189 * been an RXEOL condition. 1190 */ 1191 if (resched && kickpcu) { 1192 ATH_PCU_LOCK(sc); 1193 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1194 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1195 __func__, npkts); 1196 1197 /* 1198 * Go through the process of fully tearing down 1199 * the RX buffers and reinitialising them. 1200 * 1201 * There's a hardware bug that causes the RX FIFO 1202 * to get confused under certain conditions and 1203 * constantly write over the same frame, leading 1204 * the RX driver code here to get heavily confused. 1205 */ 1206 /* 1207 * XXX Has RX DMA stopped enough here to just call 1208 * ath_startrecv()? 1209 * XXX Do we need to use the holding buffer to restart 1210 * RX DMA by appending entries to the final 1211 * descriptor? Quite likely. 1212 */ 1213 #if 1 1214 ath_startrecv(sc); 1215 #else 1216 /* 1217 * Disabled for now - it'd be nice to be able to do 1218 * this in order to limit the amount of CPU time spent 1219 * reinitialising the RX side (and thus minimise RX 1220 * drops) however there's a hardware issue that 1221 * causes things to get too far out of whack. 1222 */ 1223 /* 1224 * XXX can we hold the PCU lock here? 1225 * Are there any net80211 buffer calls involved? 1226 */ 1227 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1228 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1229 ath_hal_rxena(ah); /* enable recv descriptors */ 1230 ath_mode_init(sc); /* set filters, etc. */ 1231 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1232 #endif 1233 1234 ath_hal_intrset(ah, sc->sc_imask); 1235 sc->sc_kickpcu = 0; 1236 ATH_PCU_UNLOCK(sc); 1237 } 1238 1239 #ifdef IEEE80211_SUPPORT_SUPERG 1240 if (resched) 1241 ieee80211_ff_age_all(ic, 100); 1242 #endif 1243 1244 /* 1245 * Put the hardware to sleep again if we're done with it. 1246 */ 1247 ATH_LOCK(sc); 1248 ath_power_restore_power_state(sc); 1249 ATH_UNLOCK(sc); 1250 1251 /* 1252 * If we hit the maximum number of frames in this round, 1253 * reschedule for another immediate pass. This gives 1254 * the TX and TX completion routines time to run, which 1255 * will reduce latency. 1256 */ 1257 if (npkts >= ATH_RX_MAX) 1258 sc->sc_rx.recv_sched(sc, resched); 1259 1260 ATH_PCU_LOCK(sc); 1261 sc->sc_rxproc_cnt--; 1262 ATH_PCU_UNLOCK(sc); 1263 } 1264 #undef PA2DESC 1265 #undef ATH_RX_MAX 1266 1267 /* 1268 * Only run the RX proc if it's not already running. 1269 * Since this may get run as part of the reset/flush path, 1270 * the task can't clash with an existing, running tasklet. 1271 */ 1272 static void 1273 ath_legacy_rx_tasklet(void *arg, int npending) 1274 { 1275 struct ath_softc *sc = arg; 1276 1277 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1278 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1279 ATH_PCU_LOCK(sc); 1280 if (sc->sc_inreset_cnt > 0) { 1281 device_printf(sc->sc_dev, 1282 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1283 ATH_PCU_UNLOCK(sc); 1284 return; 1285 } 1286 ATH_PCU_UNLOCK(sc); 1287 1288 ath_rx_proc(sc, 1); 1289 } 1290 1291 static void 1292 ath_legacy_flushrecv(struct ath_softc *sc) 1293 { 1294 1295 ath_rx_proc(sc, 0); 1296 } 1297 1298 static void 1299 ath_legacy_flush_rxpending(struct ath_softc *sc) 1300 { 1301 1302 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1303 1304 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1305 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1306 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1307 } 1308 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1309 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1310 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1311 } 1312 } 1313 1314 static int 1315 ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1316 { 1317 struct ath_buf *bf; 1318 1319 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1320 /* 1321 * If there are RX holding buffers, free them here and return 1322 * them to the list. 1323 * 1324 * XXX should just verify that bf->bf_m is NULL, as it must 1325 * be at this point! 1326 */ 1327 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1328 if (bf != NULL) { 1329 if (bf->bf_m != NULL) 1330 m_freem(bf->bf_m); 1331 bf->bf_m = NULL; 1332 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1333 (void) ath_rxbuf_init(sc, bf); 1334 } 1335 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1336 1337 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1338 if (bf != NULL) { 1339 if (bf->bf_m != NULL) 1340 m_freem(bf->bf_m); 1341 bf->bf_m = NULL; 1342 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1343 (void) ath_rxbuf_init(sc, bf); 1344 } 1345 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1346 1347 return (0); 1348 } 1349 1350 /* 1351 * Disable the receive h/w in preparation for a reset. 1352 */ 1353 static void 1354 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1355 { 1356 #define PA2DESC(_sc, _pa) \ 1357 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1358 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1359 struct ath_hal *ah = sc->sc_ah; 1360 1361 ATH_RX_LOCK(sc); 1362 1363 ath_hal_stoppcurecv(ah); /* disable PCU */ 1364 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1365 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1366 /* 1367 * TODO: see if this particular DELAY() is required; it may be 1368 * masking some missing FIFO flush or DMA sync. 1369 */ 1370 #if 0 1371 if (dodelay) 1372 #endif 1373 DELAY(3000); /* 3ms is long enough for 1 frame */ 1374 #ifdef ATH_DEBUG 1375 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1376 struct ath_buf *bf; 1377 u_int ix; 1378 1379 device_printf(sc->sc_dev, 1380 "%s: rx queue %p, link %p\n", 1381 __func__, 1382 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1383 sc->sc_rxlink); 1384 ix = 0; 1385 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1386 struct ath_desc *ds = bf->bf_desc; 1387 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1388 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1389 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1390 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1391 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1392 ix++; 1393 } 1394 } 1395 #endif 1396 1397 (void) ath_legacy_flush_rxpending(sc); 1398 (void) ath_legacy_flush_rxholdbf(sc); 1399 1400 sc->sc_rxlink = NULL; /* just in case */ 1401 1402 ATH_RX_UNLOCK(sc); 1403 #undef PA2DESC 1404 } 1405 1406 /* 1407 * XXX TODO: something was calling startrecv without calling 1408 * stoprecv. Let's figure out what/why. It was showing up 1409 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1410 */ 1411 1412 /* 1413 * Enable the receive h/w following a reset. 1414 */ 1415 static int 1416 ath_legacy_startrecv(struct ath_softc *sc) 1417 { 1418 struct ath_hal *ah = sc->sc_ah; 1419 struct ath_buf *bf; 1420 1421 ATH_RX_LOCK(sc); 1422 1423 /* 1424 * XXX should verify these are already all NULL! 1425 */ 1426 sc->sc_rxlink = NULL; 1427 (void) ath_legacy_flush_rxpending(sc); 1428 (void) ath_legacy_flush_rxholdbf(sc); 1429 1430 /* 1431 * Re-chain all of the buffers in the RX buffer list. 1432 */ 1433 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1434 int error = ath_rxbuf_init(sc, bf); 1435 if (error != 0) { 1436 DPRINTF(sc, ATH_DEBUG_RECV, 1437 "%s: ath_rxbuf_init failed %d\n", 1438 __func__, error); 1439 return error; 1440 } 1441 } 1442 1443 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1444 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1445 ath_hal_rxena(ah); /* enable recv descriptors */ 1446 ath_mode_init(sc); /* set filters, etc. */ 1447 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1448 1449 ATH_RX_UNLOCK(sc); 1450 return 0; 1451 } 1452 1453 static int 1454 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1455 { 1456 int error; 1457 1458 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1459 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1460 if (error != 0) 1461 return (error); 1462 1463 return (0); 1464 } 1465 1466 static int 1467 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1468 { 1469 1470 if (sc->sc_rxdma.dd_desc_len != 0) 1471 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1472 return (0); 1473 } 1474 1475 static void 1476 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1477 { 1478 1479 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1480 } 1481 1482 static void 1483 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1484 int dosched) 1485 { 1486 1487 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1488 } 1489 1490 void 1491 ath_recv_setup_legacy(struct ath_softc *sc) 1492 { 1493 1494 /* Sensible legacy defaults */ 1495 /* 1496 * XXX this should be changed to properly support the 1497 * exact RX descriptor size for each HAL. 1498 */ 1499 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1500 1501 sc->sc_rx.recv_start = ath_legacy_startrecv; 1502 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1503 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1504 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1505 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1506 1507 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1508 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1509 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1510 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1511 } 1512