1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42 #include "opt_inet.h" 43 #include "opt_ath.h" 44 /* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51 #include "opt_ah.h" 52 #include "opt_wlan.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysctl.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/kernel.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 #include <sys/errno.h> 65 #include <sys/callout.h> 66 #include <sys/bus.h> 67 #include <sys/endian.h> 68 #include <sys/kthread.h> 69 #include <sys/taskqueue.h> 70 #include <sys/priv.h> 71 #include <sys/module.h> 72 #include <sys/ktr.h> 73 #include <sys/smp.h> /* for mp_ncpus */ 74 75 #include <machine/bus.h> 76 77 #include <net/if.h> 78 #include <net/if_var.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_var.h> 87 #include <net80211/ieee80211_regdomain.h> 88 #ifdef IEEE80211_SUPPORT_SUPERG 89 #include <net80211/ieee80211_superg.h> 90 #endif 91 #ifdef IEEE80211_SUPPORT_TDMA 92 #include <net80211/ieee80211_tdma.h> 93 #endif 94 95 #include <net/bpf.h> 96 97 #ifdef INET 98 #include <netinet/in.h> 99 #include <netinet/if_ether.h> 100 #endif 101 102 #include <dev/ath/if_athvar.h> 103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 104 #include <dev/ath/ath_hal/ah_diagcodes.h> 105 106 #include <dev/ath/if_ath_debug.h> 107 #include <dev/ath/if_ath_misc.h> 108 #include <dev/ath/if_ath_tsf.h> 109 #include <dev/ath/if_ath_tx.h> 110 #include <dev/ath/if_ath_sysctl.h> 111 #include <dev/ath/if_ath_led.h> 112 #include <dev/ath/if_ath_keycache.h> 113 #include <dev/ath/if_ath_rx.h> 114 #include <dev/ath/if_ath_beacon.h> 115 #include <dev/ath/if_athdfs.h> 116 #include <dev/ath/if_ath_descdma.h> 117 118 #ifdef ATH_TX99_DIAG 119 #include <dev/ath/ath_tx99/ath_tx99.h> 120 #endif 121 122 #ifdef ATH_DEBUG_ALQ 123 #include <dev/ath/if_ath_alq.h> 124 #endif 125 126 #include <dev/ath/if_ath_lna_div.h> 127 128 /* 129 * Calculate the receive filter according to the 130 * operating mode and state: 131 * 132 * o always accept unicast, broadcast, and multicast traffic 133 * o accept PHY error frames when hardware doesn't have MIB support 134 * to count and we need them for ANI (sta mode only until recently) 135 * and we are not scanning (ANI is disabled) 136 * NB: older hal's add rx filter bits out of sight and we need to 137 * blindly preserve them 138 * o probe request frames are accepted only when operating in 139 * hostap, adhoc, mesh, or monitor modes 140 * o enable promiscuous mode 141 * - when in monitor mode 142 * - if interface marked PROMISC (assumes bridge setting is filtered) 143 * o accept beacons: 144 * - when operating in station mode for collecting rssi data when 145 * the station is otherwise quiet, or 146 * - when operating in adhoc mode so the 802.11 layer creates 147 * node table entries for peers, 148 * - when scanning 149 * - when doing s/w beacon miss (e.g. for ap+sta) 150 * - when operating in ap mode in 11g to detect overlapping bss that 151 * require protection 152 * - when operating in mesh mode to detect neighbors 153 * o accept control frames: 154 * - when in monitor mode 155 * XXX HT protection for 11n 156 */ 157 u_int32_t 158 ath_calcrxfilter(struct ath_softc *sc) 159 { 160 struct ieee80211com *ic = &sc->sc_ic; 161 u_int32_t rfilt; 162 163 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 164 if (!sc->sc_needmib && !sc->sc_scanning) 165 rfilt |= HAL_RX_FILTER_PHYERR; 166 if (ic->ic_opmode != IEEE80211_M_STA) 167 rfilt |= HAL_RX_FILTER_PROBEREQ; 168 /* XXX ic->ic_monvaps != 0? */ 169 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0) 170 rfilt |= HAL_RX_FILTER_PROM; 171 172 /* 173 * Only listen to all beacons if we're scanning. 174 * 175 * Otherwise we only really need to hear beacons from 176 * our own BSSID. 177 * 178 * IBSS? software beacon miss? Just receive all beacons. 179 * We need to hear beacons/probe requests from everyone so 180 * we can merge ibss. 181 */ 182 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 183 rfilt |= HAL_RX_FILTER_BEACON; 184 } else if (ic->ic_opmode == IEEE80211_M_STA) { 185 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 186 rfilt |= HAL_RX_FILTER_MYBEACON; 187 } else { /* scanning, non-mybeacon chips */ 188 rfilt |= HAL_RX_FILTER_BEACON; 189 } 190 } 191 192 /* 193 * NB: We don't recalculate the rx filter when 194 * ic_protmode changes; otherwise we could do 195 * this only when ic_protmode != NONE. 196 */ 197 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 198 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 199 rfilt |= HAL_RX_FILTER_BEACON; 200 201 /* 202 * Enable hardware PS-POLL RX only for hostap mode; 203 * STA mode sends PS-POLL frames but never 204 * receives them. 205 */ 206 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 207 0, NULL) == HAL_OK && 208 ic->ic_opmode == IEEE80211_M_HOSTAP) 209 rfilt |= HAL_RX_FILTER_PSPOLL; 210 211 if (sc->sc_nmeshvaps) { 212 rfilt |= HAL_RX_FILTER_BEACON; 213 if (sc->sc_hasbmatch) 214 rfilt |= HAL_RX_FILTER_BSSID; 215 else 216 rfilt |= HAL_RX_FILTER_PROM; 217 } 218 if (ic->ic_opmode == IEEE80211_M_MONITOR) 219 rfilt |= HAL_RX_FILTER_CONTROL; 220 221 /* 222 * Enable RX of compressed BAR frames only when doing 223 * 802.11n. Required for A-MPDU. 224 */ 225 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 226 rfilt |= HAL_RX_FILTER_COMPBAR; 227 228 /* 229 * Enable radar PHY errors if requested by the 230 * DFS module. 231 */ 232 if (sc->sc_dodfs) 233 rfilt |= HAL_RX_FILTER_PHYRADAR; 234 235 /* 236 * Enable spectral PHY errors if requested by the 237 * spectral module. 238 */ 239 if (sc->sc_dospectral) 240 rfilt |= HAL_RX_FILTER_PHYRADAR; 241 242 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n", 243 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]); 244 return rfilt; 245 } 246 247 static int 248 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 249 { 250 struct ath_hal *ah = sc->sc_ah; 251 int error; 252 struct mbuf *m; 253 struct ath_desc *ds; 254 255 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 256 257 m = bf->bf_m; 258 if (m == NULL) { 259 /* 260 * NB: by assigning a page to the rx dma buffer we 261 * implicitly satisfy the Atheros requirement that 262 * this buffer be cache-line-aligned and sized to be 263 * multiple of the cache line size. Not doing this 264 * causes weird stuff to happen (for the 5210 at least). 265 */ 266 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 267 if (m == NULL) { 268 DPRINTF(sc, ATH_DEBUG_ANY, 269 "%s: no mbuf/cluster\n", __func__); 270 sc->sc_stats.ast_rx_nombuf++; 271 return ENOMEM; 272 } 273 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 274 275 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 276 bf->bf_dmamap, m, 277 bf->bf_segs, &bf->bf_nseg, 278 BUS_DMA_NOWAIT); 279 if (error != 0) { 280 DPRINTF(sc, ATH_DEBUG_ANY, 281 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 282 __func__, error); 283 sc->sc_stats.ast_rx_busdma++; 284 m_freem(m); 285 return error; 286 } 287 KASSERT(bf->bf_nseg == 1, 288 ("multi-segment packet; nseg %u", bf->bf_nseg)); 289 bf->bf_m = m; 290 } 291 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 292 293 /* 294 * Setup descriptors. For receive we always terminate 295 * the descriptor list with a self-linked entry so we'll 296 * not get overrun under high load (as can happen with a 297 * 5212 when ANI processing enables PHY error frames). 298 * 299 * To insure the last descriptor is self-linked we create 300 * each descriptor as self-linked and add it to the end. As 301 * each additional descriptor is added the previous self-linked 302 * entry is ``fixed'' naturally. This should be safe even 303 * if DMA is happening. When processing RX interrupts we 304 * never remove/process the last, self-linked, entry on the 305 * descriptor list. This insures the hardware always has 306 * someplace to write a new frame. 307 */ 308 /* 309 * 11N: we can no longer afford to self link the last descriptor. 310 * MAC acknowledges BA status as long as it copies frames to host 311 * buffer (or rx fifo). This can incorrectly acknowledge packets 312 * to a sender if last desc is self-linked. 313 */ 314 ds = bf->bf_desc; 315 if (sc->sc_rxslink) 316 ds->ds_link = bf->bf_daddr; /* link to self */ 317 else 318 ds->ds_link = 0; /* terminate the list */ 319 ds->ds_data = bf->bf_segs[0].ds_addr; 320 ath_hal_setuprxdesc(ah, ds 321 , m->m_len /* buffer size */ 322 , 0 323 ); 324 325 if (sc->sc_rxlink != NULL) 326 *sc->sc_rxlink = bf->bf_daddr; 327 sc->sc_rxlink = &ds->ds_link; 328 return 0; 329 } 330 331 /* 332 * Intercept management frames to collect beacon rssi data 333 * and to do ibss merges. 334 */ 335 void 336 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 337 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) 338 { 339 struct ieee80211vap *vap = ni->ni_vap; 340 struct ath_softc *sc = vap->iv_ic->ic_softc; 341 uint64_t tsf_beacon_old, tsf_beacon; 342 uint64_t nexttbtt; 343 int64_t tsf_delta; 344 int32_t tsf_delta_bmiss; 345 int32_t tsf_remainder; 346 uint64_t tsf_beacon_target; 347 int tsf_intval; 348 349 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 350 tsf_beacon_old |= le32dec(ni->ni_tstamp.data); 351 352 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 353 tsf_intval = 1; 354 if (ni->ni_intval > 0) { 355 tsf_intval = TU_TO_TSF(ni->ni_intval); 356 } 357 #undef TU_TO_TSF 358 359 /* 360 * Call up first so subsequent work can use information 361 * potentially stored in the node (e.g. for ibss merge). 362 */ 363 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf); 364 switch (subtype) { 365 case IEEE80211_FC0_SUBTYPE_BEACON: 366 /* 367 * Always update the per-node beacon RSSI if we're hearing 368 * beacons from that node. 369 */ 370 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgbrssi, rssi); 371 372 /* 373 * Only do the following processing if it's for 374 * the current BSS. 375 * 376 * In scan and IBSS mode we receive all beacons, 377 * which means we need to filter out stuff 378 * that isn't for us or we'll end up constantly 379 * trying to sync / merge to BSSes that aren't 380 * actually us. 381 */ 382 if (IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) { 383 /* update rssi statistics for use by the hal */ 384 /* XXX unlocked check against vap->iv_bss? */ 385 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 386 387 388 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 389 tsf_beacon |= le32dec(ni->ni_tstamp.data); 390 391 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 392 393 /* 394 * Let's calculate the delta and remainder, so we can see 395 * if the beacon timer from the AP is varying by more than 396 * a few TU. (Which would be a huge, huge problem.) 397 */ 398 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 399 400 tsf_delta_bmiss = tsf_delta / tsf_intval; 401 402 /* 403 * If our delta is greater than half the beacon interval, 404 * let's round the bmiss value up to the next beacon 405 * interval. Ie, we're running really, really early 406 * on the next beacon. 407 */ 408 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 409 tsf_delta_bmiss ++; 410 411 tsf_beacon_target = tsf_beacon_old + 412 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 413 414 /* 415 * The remainder using '%' is between 0 .. intval-1. 416 * If we're actually running too fast, then the remainder 417 * will be some large number just under intval-1. 418 * So we need to look at whether we're running 419 * before or after the target beacon interval 420 * and if we are, modify how we do the remainder 421 * calculation. 422 */ 423 if (tsf_beacon < tsf_beacon_target) { 424 tsf_remainder = 425 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 426 } else { 427 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 428 } 429 430 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu (%u), new_tsf=%llu (%u), target_tsf=%llu (%u), delta=%lld, bmiss=%d, remainder=%d\n", 431 __func__, 432 (unsigned long long) tsf_beacon_old, 433 (unsigned int) (tsf_beacon_old >> 10), 434 (unsigned long long) tsf_beacon, 435 (unsigned int ) (tsf_beacon >> 10), 436 (unsigned long long) tsf_beacon_target, 437 (unsigned int) (tsf_beacon_target >> 10), 438 (long long) tsf_delta, 439 tsf_delta_bmiss, 440 tsf_remainder); 441 442 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu (%u), nexttbtt=%llu (%u), delta=%d\n", 443 __func__, 444 (unsigned long long) tsf_beacon, 445 (unsigned int) (tsf_beacon >> 10), 446 (unsigned long long) nexttbtt, 447 (unsigned int) (nexttbtt >> 10), 448 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 449 450 /* 451 * We only do syncbeacon on STA VAPs; not on IBSS; 452 * but don't do it with swbmiss enabled or we 453 * may end up overwriting AP mode beacon config. 454 * 455 * The driver (and net80211) should be smarter about 456 * this.. 457 */ 458 if (vap->iv_opmode == IEEE80211_M_STA && 459 sc->sc_syncbeacon && 460 (!sc->sc_swbmiss) && 461 ni == vap->iv_bss && 462 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 463 DPRINTF(sc, ATH_DEBUG_BEACON, 464 "%s: syncbeacon=1; syncing\n", 465 __func__); 466 /* 467 * Resync beacon timers using the tsf of the beacon 468 * frame we just received. 469 */ 470 ath_beacon_config(sc, vap); 471 sc->sc_syncbeacon = 0; 472 } 473 } 474 475 /* fall thru... */ 476 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 477 if (vap->iv_opmode == IEEE80211_M_IBSS && 478 vap->iv_state == IEEE80211_S_RUN && 479 ieee80211_ibss_merge_check(ni)) { 480 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 481 uint64_t tsf = ath_extend_tsf(sc, rstamp, 482 ath_hal_gettsf64(sc->sc_ah)); 483 /* 484 * Handle ibss merge as needed; check the tsf on the 485 * frame before attempting the merge. The 802.11 spec 486 * says the station should change it's bssid to match 487 * the oldest station with the same ssid, where oldest 488 * is determined by the tsf. Note that hardware 489 * reconfiguration happens through callback to 490 * ath_newstate as the state machine will go from 491 * RUN -> RUN when this happens. 492 */ 493 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 494 DPRINTF(sc, ATH_DEBUG_STATE, 495 "ibss merge, rstamp %u tsf %ju " 496 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 497 (uintmax_t)ni->ni_tstamp.tsf); 498 (void) ieee80211_ibss_merge(ni); 499 } 500 } 501 break; 502 } 503 } 504 505 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 506 static void 507 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m, 508 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 509 { 510 511 /* Fill in the extension bitmap */ 512 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 513 514 /* Fill in the vendor header */ 515 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 516 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 517 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 518 519 /* XXX what should this be? */ 520 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 521 sc->sc_rx_th.wr_vh.vh_skip_len = 522 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 523 524 /* General version info */ 525 sc->sc_rx_th.wr_v.vh_version = 1; 526 527 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 528 529 /* rssi */ 530 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 531 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 532 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 533 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 534 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 535 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 536 537 /* evm */ 538 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 539 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 540 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 541 /* These are only populated from the AR9300 or later */ 542 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 543 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 544 545 /* direction */ 546 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 547 548 /* RX rate */ 549 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 550 551 /* RX flags */ 552 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 553 554 if (rs->rs_isaggr) 555 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 556 if (rs->rs_moreaggr) 557 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 558 559 /* phyerr info */ 560 if (rs->rs_status & HAL_RXERR_PHY) { 561 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 562 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 563 } else { 564 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 565 } 566 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 567 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 568 } 569 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 570 571 static void 572 ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 573 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 574 { 575 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 576 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 577 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 578 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 579 const HAL_RATE_TABLE *rt; 580 uint8_t rix; 581 582 rt = sc->sc_currates; 583 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 584 rix = rt->rateCodeToIndex[rs->rs_rate]; 585 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 586 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 587 588 /* 802.11 specific flags */ 589 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 590 if (rs->rs_status & HAL_RXERR_PHY) { 591 /* 592 * PHY error - make sure the channel flags 593 * reflect the actual channel configuration, 594 * not the received frame. 595 */ 596 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 597 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 598 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 599 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 600 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 601 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 602 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 603 struct ieee80211com *ic = &sc->sc_ic; 604 605 if ((rs->rs_flags & HAL_RX_2040) == 0) 606 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 607 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 608 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 609 else 610 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 611 612 if (rs->rs_flags & HAL_RX_GI) 613 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 614 } 615 616 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 617 if (rs->rs_status & HAL_RXERR_CRC) 618 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 619 /* XXX propagate other error flags from descriptor */ 620 sc->sc_rx_th.wr_antnoise = nf; 621 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 622 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 623 #undef CHAN_HT 624 #undef CHAN_HT20 625 #undef CHAN_HT40U 626 #undef CHAN_HT40D 627 } 628 629 static void 630 ath_handle_micerror(struct ieee80211com *ic, 631 struct ieee80211_frame *wh, int keyix) 632 { 633 struct ieee80211_node *ni; 634 635 /* XXX recheck MIC to deal w/ chips that lie */ 636 /* XXX discard MIC errors on !data frames */ 637 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 638 if (ni != NULL) { 639 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 640 ieee80211_free_node(ni); 641 } 642 } 643 644 /* 645 * Process a single packet. 646 * 647 * The mbuf must already be synced, unmapped and removed from bf->bf_m 648 * by this stage. 649 * 650 * The mbuf must be consumed by this routine - either passed up the 651 * net80211 stack, put on the holding queue, or freed. 652 */ 653 int 654 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 655 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 656 struct mbuf *m) 657 { 658 uint64_t rstamp; 659 /* XXX TODO: make this an mbuf tag? */ 660 struct ieee80211_rx_stats rxs; 661 int len, type, i; 662 struct ieee80211com *ic = &sc->sc_ic; 663 struct ieee80211_node *ni; 664 int is_good = 0; 665 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 666 667 NET_EPOCH_ASSERT(); 668 669 /* 670 * Calculate the correct 64 bit TSF given 671 * the TSF64 register value and rs_tstamp. 672 */ 673 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 674 675 /* 802.11 return codes - These aren't specifically errors */ 676 if (rs->rs_flags & HAL_RX_GI) 677 sc->sc_stats.ast_rx_halfgi++; 678 if (rs->rs_flags & HAL_RX_2040) 679 sc->sc_stats.ast_rx_2040++; 680 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 681 sc->sc_stats.ast_rx_pre_crc_err++; 682 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 683 sc->sc_stats.ast_rx_post_crc_err++; 684 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 685 sc->sc_stats.ast_rx_decrypt_busy_err++; 686 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 687 sc->sc_stats.ast_rx_hi_rx_chain++; 688 if (rs->rs_flags & HAL_RX_STBC) 689 sc->sc_stats.ast_rx_stbc++; 690 691 if (rs->rs_status != 0) { 692 if (rs->rs_status & HAL_RXERR_CRC) 693 sc->sc_stats.ast_rx_crcerr++; 694 if (rs->rs_status & HAL_RXERR_FIFO) 695 sc->sc_stats.ast_rx_fifoerr++; 696 if (rs->rs_status & HAL_RXERR_PHY) { 697 sc->sc_stats.ast_rx_phyerr++; 698 /* Process DFS radar events */ 699 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 700 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 701 /* Now pass it to the radar processing code */ 702 ath_dfs_process_phy_err(sc, m, rstamp, rs); 703 } 704 705 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 706 if (rs->rs_phyerr < 64) 707 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 708 goto rx_error; /* NB: don't count in ierrors */ 709 } 710 if (rs->rs_status & HAL_RXERR_DECRYPT) { 711 /* 712 * Decrypt error. If the error occurred 713 * because there was no hardware key, then 714 * let the frame through so the upper layers 715 * can process it. This is necessary for 5210 716 * parts which have no way to setup a ``clear'' 717 * key cache entry. 718 * 719 * XXX do key cache faulting 720 */ 721 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 722 goto rx_accept; 723 sc->sc_stats.ast_rx_badcrypt++; 724 } 725 /* 726 * Similar as above - if the failure was a keymiss 727 * just punt it up to the upper layers for now. 728 */ 729 if (rs->rs_status & HAL_RXERR_KEYMISS) { 730 sc->sc_stats.ast_rx_keymiss++; 731 goto rx_accept; 732 } 733 if (rs->rs_status & HAL_RXERR_MIC) { 734 sc->sc_stats.ast_rx_badmic++; 735 /* 736 * Do minimal work required to hand off 737 * the 802.11 header for notification. 738 */ 739 /* XXX frag's and qos frames */ 740 len = rs->rs_datalen; 741 if (len >= sizeof (struct ieee80211_frame)) { 742 ath_handle_micerror(ic, 743 mtod(m, struct ieee80211_frame *), 744 sc->sc_splitmic ? 745 rs->rs_keyix-32 : rs->rs_keyix); 746 } 747 } 748 counter_u64_add(ic->ic_ierrors, 1); 749 rx_error: 750 /* 751 * Cleanup any pending partial frame. 752 */ 753 if (re->m_rxpending != NULL) { 754 m_freem(re->m_rxpending); 755 re->m_rxpending = NULL; 756 } 757 /* 758 * When a tap is present pass error frames 759 * that have been requested. By default we 760 * pass decrypt+mic errors but others may be 761 * interesting (e.g. crc). 762 */ 763 if (ieee80211_radiotap_active(ic) && 764 (rs->rs_status & sc->sc_monpass)) { 765 /* NB: bpf needs the mbuf length setup */ 766 len = rs->rs_datalen; 767 m->m_pkthdr.len = m->m_len = len; 768 ath_rx_tap(sc, m, rs, rstamp, nf); 769 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 770 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 771 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 772 ieee80211_radiotap_rx_all(ic, m); 773 } 774 /* XXX pass MIC errors up for s/w reclaculation */ 775 m_freem(m); m = NULL; 776 goto rx_next; 777 } 778 rx_accept: 779 len = rs->rs_datalen; 780 m->m_len = len; 781 782 if (rs->rs_more) { 783 /* 784 * Frame spans multiple descriptors; save 785 * it for the next completed descriptor, it 786 * will be used to construct a jumbogram. 787 */ 788 if (re->m_rxpending != NULL) { 789 /* NB: max frame size is currently 2 clusters */ 790 sc->sc_stats.ast_rx_toobig++; 791 m_freem(re->m_rxpending); 792 } 793 m->m_pkthdr.len = len; 794 re->m_rxpending = m; 795 m = NULL; 796 goto rx_next; 797 } else if (re->m_rxpending != NULL) { 798 /* 799 * This is the second part of a jumbogram, 800 * chain it to the first mbuf, adjust the 801 * frame length, and clear the rxpending state. 802 */ 803 re->m_rxpending->m_next = m; 804 re->m_rxpending->m_pkthdr.len += len; 805 m = re->m_rxpending; 806 re->m_rxpending = NULL; 807 } else { 808 /* 809 * Normal single-descriptor receive; setup packet length. 810 */ 811 m->m_pkthdr.len = len; 812 } 813 814 /* 815 * Validate rs->rs_antenna. 816 * 817 * Some users w/ AR9285 NICs have reported crashes 818 * here because rs_antenna field is bogusly large. 819 * Let's enforce the maximum antenna limit of 8 820 * (and it shouldn't be hard coded, but that's a 821 * separate problem) and if there's an issue, print 822 * out an error and adjust rs_antenna to something 823 * sensible. 824 * 825 * This code should be removed once the actual 826 * root cause of the issue has been identified. 827 * For example, it may be that the rs_antenna 828 * field is only valid for the last frame of 829 * an aggregate and it just happens that it is 830 * "mostly" right. (This is a general statement - 831 * the majority of the statistics are only valid 832 * for the last frame in an aggregate. 833 */ 834 if (rs->rs_antenna > 7) { 835 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 836 __func__, rs->rs_antenna); 837 #ifdef ATH_DEBUG 838 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 839 #endif /* ATH_DEBUG */ 840 rs->rs_antenna = 0; /* XXX better than nothing */ 841 } 842 843 /* 844 * If this is an AR9285/AR9485, then the receive and LNA 845 * configuration is stored in RSSI[2] / EXTRSSI[2]. 846 * We can extract this out to build a much better 847 * receive antenna profile. 848 * 849 * Yes, this just blurts over the above RX antenna field 850 * for now. It's fine, the AR9285 doesn't really use 851 * that. 852 * 853 * Later on we should store away the fine grained LNA 854 * information and keep separate counters just for 855 * that. It'll help when debugging the AR9285/AR9485 856 * combined diversity code. 857 */ 858 if (sc->sc_rx_lnamixer) { 859 rs->rs_antenna = 0; 860 861 /* Bits 0:1 - the LNA configuration used */ 862 rs->rs_antenna |= 863 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 864 >> HAL_RX_LNA_CFG_USED_S); 865 866 /* Bit 2 - the external RX antenna switch */ 867 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 868 rs->rs_antenna |= 0x4; 869 } 870 871 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 872 873 /* 874 * Populate the rx status block. When there are bpf 875 * listeners we do the additional work to provide 876 * complete status. Otherwise we fill in only the 877 * material required by ieee80211_input. Note that 878 * noise setting is filled in above. 879 */ 880 if (ieee80211_radiotap_active(ic)) { 881 ath_rx_tap(sc, m, rs, rstamp, nf); 882 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 883 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 884 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 885 } 886 887 /* 888 * From this point on we assume the frame is at least 889 * as large as ieee80211_frame_min; verify that. 890 */ 891 if (len < IEEE80211_MIN_LEN) { 892 if (!ieee80211_radiotap_active(ic)) { 893 DPRINTF(sc, ATH_DEBUG_RECV, 894 "%s: short packet %d\n", __func__, len); 895 sc->sc_stats.ast_rx_tooshort++; 896 } else { 897 /* NB: in particular this captures ack's */ 898 ieee80211_radiotap_rx_all(ic, m); 899 } 900 m_freem(m); m = NULL; 901 goto rx_next; 902 } 903 904 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 905 const HAL_RATE_TABLE *rt = sc->sc_currates; 906 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 907 908 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 909 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 910 } 911 912 m_adj(m, -IEEE80211_CRC_LEN); 913 914 /* 915 * Locate the node for sender, track state, and then 916 * pass the (referenced) node up to the 802.11 layer 917 * for its use. 918 */ 919 ni = ieee80211_find_rxnode_withkey(ic, 920 mtod(m, const struct ieee80211_frame_min *), 921 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 922 IEEE80211_KEYIX_NONE : rs->rs_keyix); 923 sc->sc_lastrs = rs; 924 925 if (rs->rs_isaggr) 926 sc->sc_stats.ast_rx_agg++; 927 928 /* 929 * Populate the per-chain RSSI values where appropriate. 930 */ 931 bzero(&rxs, sizeof(rxs)); 932 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI | 933 IEEE80211_R_C_CHAIN | 934 IEEE80211_R_C_NF | 935 IEEE80211_R_C_RSSI | 936 IEEE80211_R_TSF64 | 937 IEEE80211_R_TSF_START; /* XXX TODO: validate */ 938 rxs.c_rssi = rs->rs_rssi; 939 rxs.c_nf = nf; 940 rxs.c_chain = 3; /* XXX TODO: check */ 941 rxs.c_rx_tsf = rstamp; 942 943 for (i = 0; i < 3; i++) { 944 rxs.c_rssi_ctl[i] = rs->rs_rssi_ctl[i]; 945 rxs.c_rssi_ext[i] = rs->rs_rssi_ext[i]; 946 /* 947 * XXX note: we currently don't track 948 * per-chain noisefloor. 949 */ 950 rxs.c_nf_ctl[i] = nf; 951 rxs.c_nf_ext[i] = nf; 952 } 953 954 if (ni != NULL) { 955 /* 956 * Only punt packets for ampdu reorder processing for 957 * 11n nodes; net80211 enforces that M_AMPDU is only 958 * set for 11n nodes. 959 */ 960 if (ni->ni_flags & IEEE80211_NODE_HT) 961 m->m_flags |= M_AMPDU; 962 963 /* 964 * Inform rate control about the received RSSI. 965 * It can then use this information to potentially drastically 966 * alter the available rate based on the RSSI estimate. 967 * 968 * This is super important when associating to a far away station; 969 * you don't want to waste time trying higher rates at some low 970 * packet exchange rate (like during DHCP) just to establish 971 * that higher MCS rates aren't available. 972 */ 973 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgrssi, 974 rs->rs_rssi); 975 ath_rate_update_rx_rssi(sc, ATH_NODE(ni), 976 ATH_RSSI(ATH_NODE(ni)->an_node_stats.ns_avgrssi)); 977 978 /* 979 * Sending station is known, dispatch directly. 980 */ 981 (void) ieee80211_add_rx_params(m, &rxs); 982 type = ieee80211_input_mimo(ni, m); 983 ieee80211_free_node(ni); 984 m = NULL; 985 /* 986 * Arrange to update the last rx timestamp only for 987 * frames from our ap when operating in station mode. 988 * This assumes the rx key is always setup when 989 * associated. 990 */ 991 if (ic->ic_opmode == IEEE80211_M_STA && 992 rs->rs_keyix != HAL_RXKEYIX_INVALID) 993 is_good = 1; 994 } else { 995 (void) ieee80211_add_rx_params(m, &rxs); 996 type = ieee80211_input_mimo_all(ic, m); 997 m = NULL; 998 } 999 1000 /* 1001 * At this point we have passed the frame up the stack; thus 1002 * the mbuf is no longer ours. 1003 */ 1004 1005 /* 1006 * Track legacy station RX rssi and do any rx antenna management. 1007 */ 1008 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 1009 if (sc->sc_diversity) { 1010 /* 1011 * When using fast diversity, change the default rx 1012 * antenna if diversity chooses the other antenna 3 1013 * times in a row. 1014 */ 1015 if (sc->sc_defant != rs->rs_antenna) { 1016 if (++sc->sc_rxotherant >= 3) 1017 ath_setdefantenna(sc, rs->rs_antenna); 1018 } else 1019 sc->sc_rxotherant = 0; 1020 } 1021 1022 /* Handle slow diversity if enabled */ 1023 if (sc->sc_dolnadiv) { 1024 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 1025 } 1026 1027 if (sc->sc_softled) { 1028 /* 1029 * Blink for any data frame. Otherwise do a 1030 * heartbeat-style blink when idle. The latter 1031 * is mainly for station mode where we depend on 1032 * periodic beacon frames to trigger the poll event. 1033 */ 1034 if (type == IEEE80211_FC0_TYPE_DATA) { 1035 const HAL_RATE_TABLE *rt = sc->sc_currates; 1036 ath_led_event(sc, 1037 rt->rateCodeToIndex[rs->rs_rate]); 1038 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 1039 ath_led_event(sc, 0); 1040 } 1041 rx_next: 1042 /* 1043 * Debugging - complain if we didn't NULL the mbuf pointer 1044 * here. 1045 */ 1046 if (m != NULL) { 1047 device_printf(sc->sc_dev, 1048 "%s: mbuf %p should've been freed!\n", 1049 __func__, 1050 m); 1051 } 1052 return (is_good); 1053 } 1054 1055 #define ATH_RX_MAX 128 1056 1057 /* 1058 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 1059 * the EDMA code does. 1060 * 1061 * XXX TODO: then, do all of the RX list management stuff inside 1062 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 1063 * code is doing it right. 1064 */ 1065 static void 1066 ath_rx_proc(struct ath_softc *sc, int resched) 1067 { 1068 #define PA2DESC(_sc, _pa) \ 1069 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1070 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1071 struct ath_buf *bf; 1072 struct ath_hal *ah = sc->sc_ah; 1073 #ifdef IEEE80211_SUPPORT_SUPERG 1074 struct ieee80211com *ic = &sc->sc_ic; 1075 #endif 1076 struct ath_desc *ds; 1077 struct ath_rx_status *rs; 1078 struct mbuf *m; 1079 int ngood; 1080 HAL_STATUS status; 1081 int16_t nf; 1082 u_int64_t tsf; 1083 int npkts = 0; 1084 int kickpcu = 0; 1085 int ret; 1086 1087 NET_EPOCH_ASSERT(); 1088 1089 /* XXX we must not hold the ATH_LOCK here */ 1090 ATH_UNLOCK_ASSERT(sc); 1091 ATH_PCU_UNLOCK_ASSERT(sc); 1092 1093 ATH_PCU_LOCK(sc); 1094 sc->sc_rxproc_cnt++; 1095 kickpcu = sc->sc_kickpcu; 1096 ATH_PCU_UNLOCK(sc); 1097 1098 ATH_LOCK(sc); 1099 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1100 ATH_UNLOCK(sc); 1101 1102 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1103 ngood = 0; 1104 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1105 sc->sc_stats.ast_rx_noise = nf; 1106 tsf = ath_hal_gettsf64(ah); 1107 do { 1108 /* 1109 * Don't process too many packets at a time; give the 1110 * TX thread time to also run - otherwise the TX 1111 * latency can jump by quite a bit, causing throughput 1112 * degredation. 1113 */ 1114 if (!kickpcu && npkts >= ATH_RX_MAX) 1115 break; 1116 1117 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1118 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1119 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__); 1120 break; 1121 } else if (bf == NULL) { 1122 /* 1123 * End of List: 1124 * this can happen for non-self-linked RX chains 1125 */ 1126 sc->sc_stats.ast_rx_hitqueueend++; 1127 break; 1128 } 1129 m = bf->bf_m; 1130 if (m == NULL) { /* NB: shouldn't happen */ 1131 /* 1132 * If mbuf allocation failed previously there 1133 * will be no mbuf; try again to re-populate it. 1134 */ 1135 /* XXX make debug msg */ 1136 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__); 1137 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1138 goto rx_proc_next; 1139 } 1140 ds = bf->bf_desc; 1141 if (ds->ds_link == bf->bf_daddr) { 1142 /* NB: never process the self-linked entry at the end */ 1143 sc->sc_stats.ast_rx_hitqueueend++; 1144 break; 1145 } 1146 /* XXX sync descriptor memory */ 1147 /* 1148 * Must provide the virtual address of the current 1149 * descriptor, the physical address, and the virtual 1150 * address of the next descriptor in the h/w chain. 1151 * This allows the HAL to look ahead to see if the 1152 * hardware is done with a descriptor by checking the 1153 * done bit in the following descriptor and the address 1154 * of the current descriptor the DMA engine is working 1155 * on. All this is necessary because of our use of 1156 * a self-linked list to avoid rx overruns. 1157 */ 1158 rs = &bf->bf_status.ds_rxstat; 1159 status = ath_hal_rxprocdesc(ah, ds, 1160 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1161 #ifdef ATH_DEBUG 1162 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1163 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1164 #endif 1165 1166 #ifdef ATH_DEBUG_ALQ 1167 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1168 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1169 sc->sc_rx_statuslen, (char *) ds); 1170 #endif /* ATH_DEBUG_ALQ */ 1171 1172 if (status == HAL_EINPROGRESS) 1173 break; 1174 1175 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1176 npkts++; 1177 1178 /* 1179 * Process a single frame. 1180 */ 1181 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1182 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1183 bf->bf_m = NULL; 1184 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1185 ngood++; 1186 rx_proc_next: 1187 /* 1188 * If there's a holding buffer, insert that onto 1189 * the RX list; the hardware is now definitely not pointing 1190 * to it now. 1191 */ 1192 ret = 0; 1193 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1194 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1195 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1196 bf_list); 1197 ret = ath_rxbuf_init(sc, 1198 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1199 } 1200 /* 1201 * Next, throw our buffer into the holding entry. The hardware 1202 * may use the descriptor to read the link pointer before 1203 * DMAing the next descriptor in to write out a packet. 1204 */ 1205 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1206 } while (ret == 0); 1207 1208 /* rx signal state monitoring */ 1209 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1210 if (ngood) 1211 sc->sc_lastrx = tsf; 1212 1213 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1214 /* Queue DFS tasklet if needed */ 1215 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1216 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1217 1218 /* 1219 * Now that all the RX frames were handled that 1220 * need to be handled, kick the PCU if there's 1221 * been an RXEOL condition. 1222 */ 1223 if (resched && kickpcu) { 1224 ATH_PCU_LOCK(sc); 1225 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1226 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1227 __func__, npkts); 1228 1229 /* 1230 * Go through the process of fully tearing down 1231 * the RX buffers and reinitialising them. 1232 * 1233 * There's a hardware bug that causes the RX FIFO 1234 * to get confused under certain conditions and 1235 * constantly write over the same frame, leading 1236 * the RX driver code here to get heavily confused. 1237 */ 1238 /* 1239 * XXX Has RX DMA stopped enough here to just call 1240 * ath_startrecv()? 1241 * XXX Do we need to use the holding buffer to restart 1242 * RX DMA by appending entries to the final 1243 * descriptor? Quite likely. 1244 */ 1245 #if 1 1246 ath_startrecv(sc); 1247 #else 1248 /* 1249 * Disabled for now - it'd be nice to be able to do 1250 * this in order to limit the amount of CPU time spent 1251 * reinitialising the RX side (and thus minimise RX 1252 * drops) however there's a hardware issue that 1253 * causes things to get too far out of whack. 1254 */ 1255 /* 1256 * XXX can we hold the PCU lock here? 1257 * Are there any net80211 buffer calls involved? 1258 */ 1259 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1260 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1261 ath_hal_rxena(ah); /* enable recv descriptors */ 1262 ath_mode_init(sc); /* set filters, etc. */ 1263 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */ 1264 #endif 1265 1266 ath_hal_intrset(ah, sc->sc_imask); 1267 sc->sc_kickpcu = 0; 1268 ATH_PCU_UNLOCK(sc); 1269 } 1270 1271 #ifdef IEEE80211_SUPPORT_SUPERG 1272 if (resched) 1273 ieee80211_ff_age_all(ic, 100); 1274 #endif 1275 1276 /* 1277 * Put the hardware to sleep again if we're done with it. 1278 */ 1279 ATH_LOCK(sc); 1280 ath_power_restore_power_state(sc); 1281 ATH_UNLOCK(sc); 1282 1283 /* 1284 * If we hit the maximum number of frames in this round, 1285 * reschedule for another immediate pass. This gives 1286 * the TX and TX completion routines time to run, which 1287 * will reduce latency. 1288 */ 1289 if (npkts >= ATH_RX_MAX) 1290 sc->sc_rx.recv_sched(sc, resched); 1291 1292 ATH_PCU_LOCK(sc); 1293 sc->sc_rxproc_cnt--; 1294 ATH_PCU_UNLOCK(sc); 1295 } 1296 #undef PA2DESC 1297 #undef ATH_RX_MAX 1298 1299 /* 1300 * Only run the RX proc if it's not already running. 1301 * Since this may get run as part of the reset/flush path, 1302 * the task can't clash with an existing, running tasklet. 1303 */ 1304 static void 1305 ath_legacy_rx_tasklet(void *arg, int npending) 1306 { 1307 struct ath_softc *sc = arg; 1308 struct epoch_tracker et; 1309 1310 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1311 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1312 ATH_PCU_LOCK(sc); 1313 if (sc->sc_inreset_cnt > 0) { 1314 device_printf(sc->sc_dev, 1315 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1316 ATH_PCU_UNLOCK(sc); 1317 return; 1318 } 1319 ATH_PCU_UNLOCK(sc); 1320 1321 NET_EPOCH_ENTER(et); 1322 ath_rx_proc(sc, 1); 1323 NET_EPOCH_EXIT(et); 1324 } 1325 1326 static void 1327 ath_legacy_flushrecv(struct ath_softc *sc) 1328 { 1329 struct epoch_tracker et; 1330 NET_EPOCH_ENTER(et); 1331 ath_rx_proc(sc, 0); 1332 NET_EPOCH_EXIT(et); 1333 } 1334 1335 static void 1336 ath_legacy_flush_rxpending(struct ath_softc *sc) 1337 { 1338 1339 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1340 1341 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1342 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1343 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1344 } 1345 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1346 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1347 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1348 } 1349 } 1350 1351 static int 1352 ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1353 { 1354 struct ath_buf *bf; 1355 1356 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1357 /* 1358 * If there are RX holding buffers, free them here and return 1359 * them to the list. 1360 * 1361 * XXX should just verify that bf->bf_m is NULL, as it must 1362 * be at this point! 1363 */ 1364 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1365 if (bf != NULL) { 1366 if (bf->bf_m != NULL) 1367 m_freem(bf->bf_m); 1368 bf->bf_m = NULL; 1369 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1370 (void) ath_rxbuf_init(sc, bf); 1371 } 1372 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1373 1374 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1375 if (bf != NULL) { 1376 if (bf->bf_m != NULL) 1377 m_freem(bf->bf_m); 1378 bf->bf_m = NULL; 1379 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1380 (void) ath_rxbuf_init(sc, bf); 1381 } 1382 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1383 1384 return (0); 1385 } 1386 1387 /* 1388 * Disable the receive h/w in preparation for a reset. 1389 */ 1390 static void 1391 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1392 { 1393 #define PA2DESC(_sc, _pa) \ 1394 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1395 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1396 struct ath_hal *ah = sc->sc_ah; 1397 1398 ATH_RX_LOCK(sc); 1399 1400 ath_hal_stoppcurecv(ah); /* disable PCU */ 1401 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1402 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1403 /* 1404 * TODO: see if this particular DELAY() is required; it may be 1405 * masking some missing FIFO flush or DMA sync. 1406 */ 1407 #if 0 1408 if (dodelay) 1409 #endif 1410 DELAY(3000); /* 3ms is long enough for 1 frame */ 1411 #ifdef ATH_DEBUG 1412 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1413 struct ath_buf *bf; 1414 u_int ix; 1415 1416 device_printf(sc->sc_dev, 1417 "%s: rx queue %p, link %p\n", 1418 __func__, 1419 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1420 sc->sc_rxlink); 1421 ix = 0; 1422 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1423 struct ath_desc *ds = bf->bf_desc; 1424 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1425 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1426 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1427 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1428 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1429 ix++; 1430 } 1431 } 1432 #endif 1433 1434 (void) ath_legacy_flush_rxpending(sc); 1435 (void) ath_legacy_flush_rxholdbf(sc); 1436 1437 sc->sc_rxlink = NULL; /* just in case */ 1438 1439 ATH_RX_UNLOCK(sc); 1440 #undef PA2DESC 1441 } 1442 1443 /* 1444 * XXX TODO: something was calling startrecv without calling 1445 * stoprecv. Let's figure out what/why. It was showing up 1446 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1447 */ 1448 1449 /* 1450 * Enable the receive h/w following a reset. 1451 */ 1452 static int 1453 ath_legacy_startrecv(struct ath_softc *sc) 1454 { 1455 struct ath_hal *ah = sc->sc_ah; 1456 struct ath_buf *bf; 1457 1458 ATH_RX_LOCK(sc); 1459 1460 /* 1461 * XXX should verify these are already all NULL! 1462 */ 1463 sc->sc_rxlink = NULL; 1464 (void) ath_legacy_flush_rxpending(sc); 1465 (void) ath_legacy_flush_rxholdbf(sc); 1466 1467 /* 1468 * Re-chain all of the buffers in the RX buffer list. 1469 */ 1470 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1471 int error = ath_rxbuf_init(sc, bf); 1472 if (error != 0) { 1473 DPRINTF(sc, ATH_DEBUG_RECV, 1474 "%s: ath_rxbuf_init failed %d\n", 1475 __func__, error); 1476 return error; 1477 } 1478 } 1479 1480 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1481 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1482 ath_hal_rxena(ah); /* enable recv descriptors */ 1483 ath_mode_init(sc); /* set filters, etc. */ 1484 ath_hal_startpcurecv(ah, (!! sc->sc_scanning)); /* re-enable PCU/DMA engine */ 1485 1486 ATH_RX_UNLOCK(sc); 1487 return 0; 1488 } 1489 1490 static int 1491 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1492 { 1493 int error; 1494 1495 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1496 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1497 if (error != 0) 1498 return (error); 1499 1500 return (0); 1501 } 1502 1503 static int 1504 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1505 { 1506 1507 if (sc->sc_rxdma.dd_desc_len != 0) 1508 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1509 return (0); 1510 } 1511 1512 static void 1513 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1514 { 1515 1516 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1517 } 1518 1519 static void 1520 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1521 int dosched) 1522 { 1523 1524 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1525 } 1526 1527 void 1528 ath_recv_setup_legacy(struct ath_softc *sc) 1529 { 1530 1531 /* Sensible legacy defaults */ 1532 /* 1533 * XXX this should be changed to properly support the 1534 * exact RX descriptor size for each HAL. 1535 */ 1536 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1537 1538 sc->sc_rx.recv_start = ath_legacy_startrecv; 1539 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1540 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1541 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1542 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1543 1544 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1545 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1546 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1547 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1548 } 1549