1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_var.h> 77 #include <net/if_dl.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_arp.h> 81 #include <net/ethernet.h> 82 #include <net/if_llc.h> 83 84 #include <net80211/ieee80211_var.h> 85 #include <net80211/ieee80211_regdomain.h> 86 #ifdef IEEE80211_SUPPORT_SUPERG 87 #include <net80211/ieee80211_superg.h> 88 #endif 89 #ifdef IEEE80211_SUPPORT_TDMA 90 #include <net80211/ieee80211_tdma.h> 91 #endif 92 93 #include <net/bpf.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #include <dev/ath/if_athvar.h> 101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 102 #include <dev/ath/ath_hal/ah_diagcodes.h> 103 104 #include <dev/ath/if_ath_debug.h> 105 #include <dev/ath/if_ath_misc.h> 106 #include <dev/ath/if_ath_tsf.h> 107 #include <dev/ath/if_ath_tx.h> 108 #include <dev/ath/if_ath_sysctl.h> 109 #include <dev/ath/if_ath_led.h> 110 #include <dev/ath/if_ath_keycache.h> 111 #include <dev/ath/if_ath_rx.h> 112 #include <dev/ath/if_ath_beacon.h> 113 #include <dev/ath/if_athdfs.h> 114 #include <dev/ath/if_ath_descdma.h> 115 116 #ifdef ATH_TX99_DIAG 117 #include <dev/ath/ath_tx99/ath_tx99.h> 118 #endif 119 120 #ifdef ATH_DEBUG_ALQ 121 #include <dev/ath/if_ath_alq.h> 122 #endif 123 124 #include <dev/ath/if_ath_lna_div.h> 125 126 /* 127 * Calculate the receive filter according to the 128 * operating mode and state: 129 * 130 * o always accept unicast, broadcast, and multicast traffic 131 * o accept PHY error frames when hardware doesn't have MIB support 132 * to count and we need them for ANI (sta mode only until recently) 133 * and we are not scanning (ANI is disabled) 134 * NB: older hal's add rx filter bits out of sight and we need to 135 * blindly preserve them 136 * o probe request frames are accepted only when operating in 137 * hostap, adhoc, mesh, or monitor modes 138 * o enable promiscuous mode 139 * - when in monitor mode 140 * - if interface marked PROMISC (assumes bridge setting is filtered) 141 * o accept beacons: 142 * - when operating in station mode for collecting rssi data when 143 * the station is otherwise quiet, or 144 * - when operating in adhoc mode so the 802.11 layer creates 145 * node table entries for peers, 146 * - when scanning 147 * - when doing s/w beacon miss (e.g. for ap+sta) 148 * - when operating in ap mode in 11g to detect overlapping bss that 149 * require protection 150 * - when operating in mesh mode to detect neighbors 151 * o accept control frames: 152 * - when in monitor mode 153 * XXX HT protection for 11n 154 */ 155 u_int32_t 156 ath_calcrxfilter(struct ath_softc *sc) 157 { 158 struct ieee80211com *ic = &sc->sc_ic; 159 u_int32_t rfilt; 160 161 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 162 if (!sc->sc_needmib && !sc->sc_scanning) 163 rfilt |= HAL_RX_FILTER_PHYERR; 164 if (ic->ic_opmode != IEEE80211_M_STA) 165 rfilt |= HAL_RX_FILTER_PROBEREQ; 166 /* XXX ic->ic_monvaps != 0? */ 167 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0) 168 rfilt |= HAL_RX_FILTER_PROM; 169 170 /* 171 * Only listen to all beacons if we're scanning. 172 * 173 * Otherwise we only really need to hear beacons from 174 * our own BSSID. 175 * 176 * IBSS? software beacon miss? Just receive all beacons. 177 * We need to hear beacons/probe requests from everyone so 178 * we can merge ibss. 179 */ 180 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 181 rfilt |= HAL_RX_FILTER_BEACON; 182 } else if (ic->ic_opmode == IEEE80211_M_STA) { 183 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 184 rfilt |= HAL_RX_FILTER_MYBEACON; 185 } else { /* scanning, non-mybeacon chips */ 186 rfilt |= HAL_RX_FILTER_BEACON; 187 } 188 } 189 190 /* 191 * NB: We don't recalculate the rx filter when 192 * ic_protmode changes; otherwise we could do 193 * this only when ic_protmode != NONE. 194 */ 195 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 196 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 197 rfilt |= HAL_RX_FILTER_BEACON; 198 199 /* 200 * Enable hardware PS-POLL RX only for hostap mode; 201 * STA mode sends PS-POLL frames but never 202 * receives them. 203 */ 204 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 205 0, NULL) == HAL_OK && 206 ic->ic_opmode == IEEE80211_M_HOSTAP) 207 rfilt |= HAL_RX_FILTER_PSPOLL; 208 209 if (sc->sc_nmeshvaps) { 210 rfilt |= HAL_RX_FILTER_BEACON; 211 if (sc->sc_hasbmatch) 212 rfilt |= HAL_RX_FILTER_BSSID; 213 else 214 rfilt |= HAL_RX_FILTER_PROM; 215 } 216 if (ic->ic_opmode == IEEE80211_M_MONITOR) 217 rfilt |= HAL_RX_FILTER_CONTROL; 218 219 /* 220 * Enable RX of compressed BAR frames only when doing 221 * 802.11n. Required for A-MPDU. 222 */ 223 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 224 rfilt |= HAL_RX_FILTER_COMPBAR; 225 226 /* 227 * Enable radar PHY errors if requested by the 228 * DFS module. 229 */ 230 if (sc->sc_dodfs) 231 rfilt |= HAL_RX_FILTER_PHYRADAR; 232 233 /* 234 * Enable spectral PHY errors if requested by the 235 * spectral module. 236 */ 237 if (sc->sc_dospectral) 238 rfilt |= HAL_RX_FILTER_PHYRADAR; 239 240 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n", 241 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]); 242 return rfilt; 243 } 244 245 static int 246 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 247 { 248 struct ath_hal *ah = sc->sc_ah; 249 int error; 250 struct mbuf *m; 251 struct ath_desc *ds; 252 253 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 254 255 m = bf->bf_m; 256 if (m == NULL) { 257 /* 258 * NB: by assigning a page to the rx dma buffer we 259 * implicitly satisfy the Atheros requirement that 260 * this buffer be cache-line-aligned and sized to be 261 * multiple of the cache line size. Not doing this 262 * causes weird stuff to happen (for the 5210 at least). 263 */ 264 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 265 if (m == NULL) { 266 DPRINTF(sc, ATH_DEBUG_ANY, 267 "%s: no mbuf/cluster\n", __func__); 268 sc->sc_stats.ast_rx_nombuf++; 269 return ENOMEM; 270 } 271 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 272 273 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 274 bf->bf_dmamap, m, 275 bf->bf_segs, &bf->bf_nseg, 276 BUS_DMA_NOWAIT); 277 if (error != 0) { 278 DPRINTF(sc, ATH_DEBUG_ANY, 279 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 280 __func__, error); 281 sc->sc_stats.ast_rx_busdma++; 282 m_freem(m); 283 return error; 284 } 285 KASSERT(bf->bf_nseg == 1, 286 ("multi-segment packet; nseg %u", bf->bf_nseg)); 287 bf->bf_m = m; 288 } 289 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 290 291 /* 292 * Setup descriptors. For receive we always terminate 293 * the descriptor list with a self-linked entry so we'll 294 * not get overrun under high load (as can happen with a 295 * 5212 when ANI processing enables PHY error frames). 296 * 297 * To insure the last descriptor is self-linked we create 298 * each descriptor as self-linked and add it to the end. As 299 * each additional descriptor is added the previous self-linked 300 * entry is ``fixed'' naturally. This should be safe even 301 * if DMA is happening. When processing RX interrupts we 302 * never remove/process the last, self-linked, entry on the 303 * descriptor list. This insures the hardware always has 304 * someplace to write a new frame. 305 */ 306 /* 307 * 11N: we can no longer afford to self link the last descriptor. 308 * MAC acknowledges BA status as long as it copies frames to host 309 * buffer (or rx fifo). This can incorrectly acknowledge packets 310 * to a sender if last desc is self-linked. 311 */ 312 ds = bf->bf_desc; 313 if (sc->sc_rxslink) 314 ds->ds_link = bf->bf_daddr; /* link to self */ 315 else 316 ds->ds_link = 0; /* terminate the list */ 317 ds->ds_data = bf->bf_segs[0].ds_addr; 318 ath_hal_setuprxdesc(ah, ds 319 , m->m_len /* buffer size */ 320 , 0 321 ); 322 323 if (sc->sc_rxlink != NULL) 324 *sc->sc_rxlink = bf->bf_daddr; 325 sc->sc_rxlink = &ds->ds_link; 326 return 0; 327 } 328 329 /* 330 * Intercept management frames to collect beacon rssi data 331 * and to do ibss merges. 332 */ 333 void 334 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 335 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) 336 { 337 struct ieee80211vap *vap = ni->ni_vap; 338 struct ath_softc *sc = vap->iv_ic->ic_softc; 339 uint64_t tsf_beacon_old, tsf_beacon; 340 uint64_t nexttbtt; 341 int64_t tsf_delta; 342 int32_t tsf_delta_bmiss; 343 int32_t tsf_remainder; 344 uint64_t tsf_beacon_target; 345 int tsf_intval; 346 347 tsf_beacon_old = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 348 tsf_beacon_old |= LE_READ_4(ni->ni_tstamp.data); 349 350 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 351 tsf_intval = 1; 352 if (ni->ni_intval > 0) { 353 tsf_intval = TU_TO_TSF(ni->ni_intval); 354 } 355 #undef TU_TO_TSF 356 357 /* 358 * Call up first so subsequent work can use information 359 * potentially stored in the node (e.g. for ibss merge). 360 */ 361 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf); 362 switch (subtype) { 363 case IEEE80211_FC0_SUBTYPE_BEACON: 364 /* update rssi statistics for use by the hal */ 365 /* XXX unlocked check against vap->iv_bss? */ 366 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 367 368 tsf_beacon = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 369 tsf_beacon |= LE_READ_4(ni->ni_tstamp.data); 370 371 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 372 373 /* 374 * Let's calculate the delta and remainder, so we can see 375 * if the beacon timer from the AP is varying by more than 376 * a few TU. (Which would be a huge, huge problem.) 377 */ 378 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 379 380 tsf_delta_bmiss = tsf_delta / tsf_intval; 381 382 /* 383 * If our delta is greater than half the beacon interval, 384 * let's round the bmiss value up to the next beacon 385 * interval. Ie, we're running really, really early 386 * on the next beacon. 387 */ 388 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 389 tsf_delta_bmiss ++; 390 391 tsf_beacon_target = tsf_beacon_old + 392 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 393 394 /* 395 * The remainder using '%' is between 0 .. intval-1. 396 * If we're actually running too fast, then the remainder 397 * will be some large number just under intval-1. 398 * So we need to look at whether we're running 399 * before or after the target beacon interval 400 * and if we are, modify how we do the remainder 401 * calculation. 402 */ 403 if (tsf_beacon < tsf_beacon_target) { 404 tsf_remainder = 405 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 406 } else { 407 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 408 } 409 410 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu, new_tsf=%llu, target_tsf=%llu, delta=%lld, bmiss=%d, remainder=%d\n", 411 __func__, 412 (unsigned long long) tsf_beacon_old, 413 (unsigned long long) tsf_beacon, 414 (unsigned long long) tsf_beacon_target, 415 (long long) tsf_delta, 416 tsf_delta_bmiss, 417 tsf_remainder); 418 419 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu, nexttbtt=%llu, delta=%d\n", 420 __func__, 421 (unsigned long long) tsf_beacon, 422 (unsigned long long) nexttbtt, 423 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 424 425 if (sc->sc_syncbeacon && 426 ni == vap->iv_bss && 427 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 428 DPRINTF(sc, ATH_DEBUG_BEACON, 429 "%s: syncbeacon=1; syncing\n", 430 __func__); 431 /* 432 * Resync beacon timers using the tsf of the beacon 433 * frame we just received. 434 */ 435 ath_beacon_config(sc, vap); 436 sc->sc_syncbeacon = 0; 437 } 438 439 /* fall thru... */ 440 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 441 if (vap->iv_opmode == IEEE80211_M_IBSS && 442 vap->iv_state == IEEE80211_S_RUN) { 443 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 444 uint64_t tsf = ath_extend_tsf(sc, rstamp, 445 ath_hal_gettsf64(sc->sc_ah)); 446 /* 447 * Handle ibss merge as needed; check the tsf on the 448 * frame before attempting the merge. The 802.11 spec 449 * says the station should change it's bssid to match 450 * the oldest station with the same ssid, where oldest 451 * is determined by the tsf. Note that hardware 452 * reconfiguration happens through callback to 453 * ath_newstate as the state machine will go from 454 * RUN -> RUN when this happens. 455 */ 456 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 457 DPRINTF(sc, ATH_DEBUG_STATE, 458 "ibss merge, rstamp %u tsf %ju " 459 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 460 (uintmax_t)ni->ni_tstamp.tsf); 461 (void) ieee80211_ibss_merge(ni); 462 } 463 } 464 break; 465 } 466 } 467 468 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 469 static void 470 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m, 471 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 472 { 473 474 /* Fill in the extension bitmap */ 475 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 476 477 /* Fill in the vendor header */ 478 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 479 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 480 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 481 482 /* XXX what should this be? */ 483 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 484 sc->sc_rx_th.wr_vh.vh_skip_len = 485 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 486 487 /* General version info */ 488 sc->sc_rx_th.wr_v.vh_version = 1; 489 490 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 491 492 /* rssi */ 493 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 494 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 495 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 496 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 497 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 498 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 499 500 /* evm */ 501 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 502 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 503 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 504 /* These are only populated from the AR9300 or later */ 505 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 506 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 507 508 /* direction */ 509 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 510 511 /* RX rate */ 512 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 513 514 /* RX flags */ 515 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 516 517 if (rs->rs_isaggr) 518 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 519 if (rs->rs_moreaggr) 520 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 521 522 /* phyerr info */ 523 if (rs->rs_status & HAL_RXERR_PHY) { 524 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 525 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 526 } else { 527 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 528 } 529 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 530 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 531 } 532 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 533 534 static void 535 ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 536 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 537 { 538 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 539 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 540 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 541 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 542 const HAL_RATE_TABLE *rt; 543 uint8_t rix; 544 545 rt = sc->sc_currates; 546 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 547 rix = rt->rateCodeToIndex[rs->rs_rate]; 548 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 549 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 550 #ifdef AH_SUPPORT_AR5416 551 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 552 if (rs->rs_status & HAL_RXERR_PHY) { 553 /* 554 * PHY error - make sure the channel flags 555 * reflect the actual channel configuration, 556 * not the received frame. 557 */ 558 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 559 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 560 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 561 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 562 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 563 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 564 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 565 struct ieee80211com *ic = &sc->sc_ic; 566 567 if ((rs->rs_flags & HAL_RX_2040) == 0) 568 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 569 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 570 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 571 else 572 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 573 if ((rs->rs_flags & HAL_RX_GI) == 0) 574 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 575 } 576 577 #endif 578 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 579 if (rs->rs_status & HAL_RXERR_CRC) 580 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 581 /* XXX propagate other error flags from descriptor */ 582 sc->sc_rx_th.wr_antnoise = nf; 583 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 584 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 585 #undef CHAN_HT 586 #undef CHAN_HT20 587 #undef CHAN_HT40U 588 #undef CHAN_HT40D 589 } 590 591 static void 592 ath_handle_micerror(struct ieee80211com *ic, 593 struct ieee80211_frame *wh, int keyix) 594 { 595 struct ieee80211_node *ni; 596 597 /* XXX recheck MIC to deal w/ chips that lie */ 598 /* XXX discard MIC errors on !data frames */ 599 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 600 if (ni != NULL) { 601 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 602 ieee80211_free_node(ni); 603 } 604 } 605 606 /* 607 * Process a single packet. 608 * 609 * The mbuf must already be synced, unmapped and removed from bf->bf_m 610 * by this stage. 611 * 612 * The mbuf must be consumed by this routine - either passed up the 613 * net80211 stack, put on the holding queue, or freed. 614 */ 615 int 616 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 617 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 618 struct mbuf *m) 619 { 620 uint64_t rstamp; 621 int len, type; 622 struct ieee80211com *ic = &sc->sc_ic; 623 struct ieee80211_node *ni; 624 int is_good = 0; 625 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 626 627 /* 628 * Calculate the correct 64 bit TSF given 629 * the TSF64 register value and rs_tstamp. 630 */ 631 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 632 633 /* These aren't specifically errors */ 634 #ifdef AH_SUPPORT_AR5416 635 if (rs->rs_flags & HAL_RX_GI) 636 sc->sc_stats.ast_rx_halfgi++; 637 if (rs->rs_flags & HAL_RX_2040) 638 sc->sc_stats.ast_rx_2040++; 639 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 640 sc->sc_stats.ast_rx_pre_crc_err++; 641 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 642 sc->sc_stats.ast_rx_post_crc_err++; 643 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 644 sc->sc_stats.ast_rx_decrypt_busy_err++; 645 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 646 sc->sc_stats.ast_rx_hi_rx_chain++; 647 if (rs->rs_flags & HAL_RX_STBC) 648 sc->sc_stats.ast_rx_stbc++; 649 #endif /* AH_SUPPORT_AR5416 */ 650 651 if (rs->rs_status != 0) { 652 if (rs->rs_status & HAL_RXERR_CRC) 653 sc->sc_stats.ast_rx_crcerr++; 654 if (rs->rs_status & HAL_RXERR_FIFO) 655 sc->sc_stats.ast_rx_fifoerr++; 656 if (rs->rs_status & HAL_RXERR_PHY) { 657 sc->sc_stats.ast_rx_phyerr++; 658 /* Process DFS radar events */ 659 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 660 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 661 /* Now pass it to the radar processing code */ 662 ath_dfs_process_phy_err(sc, m, rstamp, rs); 663 } 664 665 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 666 if (rs->rs_phyerr < 64) 667 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 668 goto rx_error; /* NB: don't count in ierrors */ 669 } 670 if (rs->rs_status & HAL_RXERR_DECRYPT) { 671 /* 672 * Decrypt error. If the error occurred 673 * because there was no hardware key, then 674 * let the frame through so the upper layers 675 * can process it. This is necessary for 5210 676 * parts which have no way to setup a ``clear'' 677 * key cache entry. 678 * 679 * XXX do key cache faulting 680 */ 681 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 682 goto rx_accept; 683 sc->sc_stats.ast_rx_badcrypt++; 684 } 685 /* 686 * Similar as above - if the failure was a keymiss 687 * just punt it up to the upper layers for now. 688 */ 689 if (rs->rs_status & HAL_RXERR_KEYMISS) { 690 sc->sc_stats.ast_rx_keymiss++; 691 goto rx_accept; 692 } 693 if (rs->rs_status & HAL_RXERR_MIC) { 694 sc->sc_stats.ast_rx_badmic++; 695 /* 696 * Do minimal work required to hand off 697 * the 802.11 header for notification. 698 */ 699 /* XXX frag's and qos frames */ 700 len = rs->rs_datalen; 701 if (len >= sizeof (struct ieee80211_frame)) { 702 ath_handle_micerror(ic, 703 mtod(m, struct ieee80211_frame *), 704 sc->sc_splitmic ? 705 rs->rs_keyix-32 : rs->rs_keyix); 706 } 707 } 708 counter_u64_add(ic->ic_ierrors, 1); 709 rx_error: 710 /* 711 * Cleanup any pending partial frame. 712 */ 713 if (re->m_rxpending != NULL) { 714 m_freem(re->m_rxpending); 715 re->m_rxpending = NULL; 716 } 717 /* 718 * When a tap is present pass error frames 719 * that have been requested. By default we 720 * pass decrypt+mic errors but others may be 721 * interesting (e.g. crc). 722 */ 723 if (ieee80211_radiotap_active(ic) && 724 (rs->rs_status & sc->sc_monpass)) { 725 /* NB: bpf needs the mbuf length setup */ 726 len = rs->rs_datalen; 727 m->m_pkthdr.len = m->m_len = len; 728 ath_rx_tap(sc, m, rs, rstamp, nf); 729 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 730 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 731 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 732 ieee80211_radiotap_rx_all(ic, m); 733 } 734 /* XXX pass MIC errors up for s/w reclaculation */ 735 m_freem(m); m = NULL; 736 goto rx_next; 737 } 738 rx_accept: 739 len = rs->rs_datalen; 740 m->m_len = len; 741 742 if (rs->rs_more) { 743 /* 744 * Frame spans multiple descriptors; save 745 * it for the next completed descriptor, it 746 * will be used to construct a jumbogram. 747 */ 748 if (re->m_rxpending != NULL) { 749 /* NB: max frame size is currently 2 clusters */ 750 sc->sc_stats.ast_rx_toobig++; 751 m_freem(re->m_rxpending); 752 } 753 m->m_pkthdr.len = len; 754 re->m_rxpending = m; 755 m = NULL; 756 goto rx_next; 757 } else if (re->m_rxpending != NULL) { 758 /* 759 * This is the second part of a jumbogram, 760 * chain it to the first mbuf, adjust the 761 * frame length, and clear the rxpending state. 762 */ 763 re->m_rxpending->m_next = m; 764 re->m_rxpending->m_pkthdr.len += len; 765 m = re->m_rxpending; 766 re->m_rxpending = NULL; 767 } else { 768 /* 769 * Normal single-descriptor receive; setup packet length. 770 */ 771 m->m_pkthdr.len = len; 772 } 773 774 /* 775 * Validate rs->rs_antenna. 776 * 777 * Some users w/ AR9285 NICs have reported crashes 778 * here because rs_antenna field is bogusly large. 779 * Let's enforce the maximum antenna limit of 8 780 * (and it shouldn't be hard coded, but that's a 781 * separate problem) and if there's an issue, print 782 * out an error and adjust rs_antenna to something 783 * sensible. 784 * 785 * This code should be removed once the actual 786 * root cause of the issue has been identified. 787 * For example, it may be that the rs_antenna 788 * field is only valid for the lsat frame of 789 * an aggregate and it just happens that it is 790 * "mostly" right. (This is a general statement - 791 * the majority of the statistics are only valid 792 * for the last frame in an aggregate. 793 */ 794 if (rs->rs_antenna > 7) { 795 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 796 __func__, rs->rs_antenna); 797 #ifdef ATH_DEBUG 798 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 799 #endif /* ATH_DEBUG */ 800 rs->rs_antenna = 0; /* XXX better than nothing */ 801 } 802 803 /* 804 * If this is an AR9285/AR9485, then the receive and LNA 805 * configuration is stored in RSSI[2] / EXTRSSI[2]. 806 * We can extract this out to build a much better 807 * receive antenna profile. 808 * 809 * Yes, this just blurts over the above RX antenna field 810 * for now. It's fine, the AR9285 doesn't really use 811 * that. 812 * 813 * Later on we should store away the fine grained LNA 814 * information and keep separate counters just for 815 * that. It'll help when debugging the AR9285/AR9485 816 * combined diversity code. 817 */ 818 if (sc->sc_rx_lnamixer) { 819 rs->rs_antenna = 0; 820 821 /* Bits 0:1 - the LNA configuration used */ 822 rs->rs_antenna |= 823 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 824 >> HAL_RX_LNA_CFG_USED_S); 825 826 /* Bit 2 - the external RX antenna switch */ 827 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 828 rs->rs_antenna |= 0x4; 829 } 830 831 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 832 833 /* 834 * Populate the rx status block. When there are bpf 835 * listeners we do the additional work to provide 836 * complete status. Otherwise we fill in only the 837 * material required by ieee80211_input. Note that 838 * noise setting is filled in above. 839 */ 840 if (ieee80211_radiotap_active(ic)) { 841 ath_rx_tap(sc, m, rs, rstamp, nf); 842 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 843 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 844 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 845 } 846 847 /* 848 * From this point on we assume the frame is at least 849 * as large as ieee80211_frame_min; verify that. 850 */ 851 if (len < IEEE80211_MIN_LEN) { 852 if (!ieee80211_radiotap_active(ic)) { 853 DPRINTF(sc, ATH_DEBUG_RECV, 854 "%s: short packet %d\n", __func__, len); 855 sc->sc_stats.ast_rx_tooshort++; 856 } else { 857 /* NB: in particular this captures ack's */ 858 ieee80211_radiotap_rx_all(ic, m); 859 } 860 m_freem(m); m = NULL; 861 goto rx_next; 862 } 863 864 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 865 const HAL_RATE_TABLE *rt = sc->sc_currates; 866 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 867 868 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 869 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 870 } 871 872 m_adj(m, -IEEE80211_CRC_LEN); 873 874 /* 875 * Locate the node for sender, track state, and then 876 * pass the (referenced) node up to the 802.11 layer 877 * for its use. 878 */ 879 ni = ieee80211_find_rxnode_withkey(ic, 880 mtod(m, const struct ieee80211_frame_min *), 881 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 882 IEEE80211_KEYIX_NONE : rs->rs_keyix); 883 sc->sc_lastrs = rs; 884 885 #ifdef AH_SUPPORT_AR5416 886 if (rs->rs_isaggr) 887 sc->sc_stats.ast_rx_agg++; 888 #endif /* AH_SUPPORT_AR5416 */ 889 890 if (ni != NULL) { 891 /* 892 * Only punt packets for ampdu reorder processing for 893 * 11n nodes; net80211 enforces that M_AMPDU is only 894 * set for 11n nodes. 895 */ 896 if (ni->ni_flags & IEEE80211_NODE_HT) 897 m->m_flags |= M_AMPDU; 898 899 /* 900 * Sending station is known, dispatch directly. 901 */ 902 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 903 ieee80211_free_node(ni); 904 m = NULL; 905 /* 906 * Arrange to update the last rx timestamp only for 907 * frames from our ap when operating in station mode. 908 * This assumes the rx key is always setup when 909 * associated. 910 */ 911 if (ic->ic_opmode == IEEE80211_M_STA && 912 rs->rs_keyix != HAL_RXKEYIX_INVALID) 913 is_good = 1; 914 } else { 915 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 916 m = NULL; 917 } 918 919 /* 920 * At this point we have passed the frame up the stack; thus 921 * the mbuf is no longer ours. 922 */ 923 924 /* 925 * Track rx rssi and do any rx antenna management. 926 */ 927 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 928 if (sc->sc_diversity) { 929 /* 930 * When using fast diversity, change the default rx 931 * antenna if diversity chooses the other antenna 3 932 * times in a row. 933 */ 934 if (sc->sc_defant != rs->rs_antenna) { 935 if (++sc->sc_rxotherant >= 3) 936 ath_setdefantenna(sc, rs->rs_antenna); 937 } else 938 sc->sc_rxotherant = 0; 939 } 940 941 /* Handle slow diversity if enabled */ 942 if (sc->sc_dolnadiv) { 943 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 944 } 945 946 if (sc->sc_softled) { 947 /* 948 * Blink for any data frame. Otherwise do a 949 * heartbeat-style blink when idle. The latter 950 * is mainly for station mode where we depend on 951 * periodic beacon frames to trigger the poll event. 952 */ 953 if (type == IEEE80211_FC0_TYPE_DATA) { 954 const HAL_RATE_TABLE *rt = sc->sc_currates; 955 ath_led_event(sc, 956 rt->rateCodeToIndex[rs->rs_rate]); 957 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 958 ath_led_event(sc, 0); 959 } 960 rx_next: 961 /* 962 * Debugging - complain if we didn't NULL the mbuf pointer 963 * here. 964 */ 965 if (m != NULL) { 966 device_printf(sc->sc_dev, 967 "%s: mbuf %p should've been freed!\n", 968 __func__, 969 m); 970 } 971 return (is_good); 972 } 973 974 #define ATH_RX_MAX 128 975 976 /* 977 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 978 * the EDMA code does. 979 * 980 * XXX TODO: then, do all of the RX list management stuff inside 981 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 982 * code is doing it right. 983 */ 984 static void 985 ath_rx_proc(struct ath_softc *sc, int resched) 986 { 987 #define PA2DESC(_sc, _pa) \ 988 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 989 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 990 struct ath_buf *bf; 991 struct ath_hal *ah = sc->sc_ah; 992 #ifdef IEEE80211_SUPPORT_SUPERG 993 struct ieee80211com *ic = &sc->sc_ic; 994 #endif 995 struct ath_desc *ds; 996 struct ath_rx_status *rs; 997 struct mbuf *m; 998 int ngood; 999 HAL_STATUS status; 1000 int16_t nf; 1001 u_int64_t tsf; 1002 int npkts = 0; 1003 int kickpcu = 0; 1004 int ret; 1005 1006 /* XXX we must not hold the ATH_LOCK here */ 1007 ATH_UNLOCK_ASSERT(sc); 1008 ATH_PCU_UNLOCK_ASSERT(sc); 1009 1010 ATH_PCU_LOCK(sc); 1011 sc->sc_rxproc_cnt++; 1012 kickpcu = sc->sc_kickpcu; 1013 ATH_PCU_UNLOCK(sc); 1014 1015 ATH_LOCK(sc); 1016 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1017 ATH_UNLOCK(sc); 1018 1019 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1020 ngood = 0; 1021 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1022 sc->sc_stats.ast_rx_noise = nf; 1023 tsf = ath_hal_gettsf64(ah); 1024 do { 1025 /* 1026 * Don't process too many packets at a time; give the 1027 * TX thread time to also run - otherwise the TX 1028 * latency can jump by quite a bit, causing throughput 1029 * degredation. 1030 */ 1031 if (!kickpcu && npkts >= ATH_RX_MAX) 1032 break; 1033 1034 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1035 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1036 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__); 1037 break; 1038 } else if (bf == NULL) { 1039 /* 1040 * End of List: 1041 * this can happen for non-self-linked RX chains 1042 */ 1043 sc->sc_stats.ast_rx_hitqueueend++; 1044 break; 1045 } 1046 m = bf->bf_m; 1047 if (m == NULL) { /* NB: shouldn't happen */ 1048 /* 1049 * If mbuf allocation failed previously there 1050 * will be no mbuf; try again to re-populate it. 1051 */ 1052 /* XXX make debug msg */ 1053 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__); 1054 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1055 goto rx_proc_next; 1056 } 1057 ds = bf->bf_desc; 1058 if (ds->ds_link == bf->bf_daddr) { 1059 /* NB: never process the self-linked entry at the end */ 1060 sc->sc_stats.ast_rx_hitqueueend++; 1061 break; 1062 } 1063 /* XXX sync descriptor memory */ 1064 /* 1065 * Must provide the virtual address of the current 1066 * descriptor, the physical address, and the virtual 1067 * address of the next descriptor in the h/w chain. 1068 * This allows the HAL to look ahead to see if the 1069 * hardware is done with a descriptor by checking the 1070 * done bit in the following descriptor and the address 1071 * of the current descriptor the DMA engine is working 1072 * on. All this is necessary because of our use of 1073 * a self-linked list to avoid rx overruns. 1074 */ 1075 rs = &bf->bf_status.ds_rxstat; 1076 status = ath_hal_rxprocdesc(ah, ds, 1077 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1078 #ifdef ATH_DEBUG 1079 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1080 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1081 #endif 1082 1083 #ifdef ATH_DEBUG_ALQ 1084 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1085 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1086 sc->sc_rx_statuslen, (char *) ds); 1087 #endif /* ATH_DEBUG_ALQ */ 1088 1089 if (status == HAL_EINPROGRESS) 1090 break; 1091 1092 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1093 npkts++; 1094 1095 /* 1096 * Process a single frame. 1097 */ 1098 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1099 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1100 bf->bf_m = NULL; 1101 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1102 ngood++; 1103 rx_proc_next: 1104 /* 1105 * If there's a holding buffer, insert that onto 1106 * the RX list; the hardware is now definitely not pointing 1107 * to it now. 1108 */ 1109 ret = 0; 1110 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1111 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1112 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1113 bf_list); 1114 ret = ath_rxbuf_init(sc, 1115 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1116 } 1117 /* 1118 * Next, throw our buffer into the holding entry. The hardware 1119 * may use the descriptor to read the link pointer before 1120 * DMAing the next descriptor in to write out a packet. 1121 */ 1122 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1123 } while (ret == 0); 1124 1125 /* rx signal state monitoring */ 1126 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1127 if (ngood) 1128 sc->sc_lastrx = tsf; 1129 1130 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1131 /* Queue DFS tasklet if needed */ 1132 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1133 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1134 1135 /* 1136 * Now that all the RX frames were handled that 1137 * need to be handled, kick the PCU if there's 1138 * been an RXEOL condition. 1139 */ 1140 if (resched && kickpcu) { 1141 ATH_PCU_LOCK(sc); 1142 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1143 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1144 __func__, npkts); 1145 1146 /* 1147 * Go through the process of fully tearing down 1148 * the RX buffers and reinitialising them. 1149 * 1150 * There's a hardware bug that causes the RX FIFO 1151 * to get confused under certain conditions and 1152 * constantly write over the same frame, leading 1153 * the RX driver code here to get heavily confused. 1154 */ 1155 /* 1156 * XXX Has RX DMA stopped enough here to just call 1157 * ath_startrecv()? 1158 * XXX Do we need to use the holding buffer to restart 1159 * RX DMA by appending entries to the final 1160 * descriptor? Quite likely. 1161 */ 1162 #if 1 1163 ath_startrecv(sc); 1164 #else 1165 /* 1166 * Disabled for now - it'd be nice to be able to do 1167 * this in order to limit the amount of CPU time spent 1168 * reinitialising the RX side (and thus minimise RX 1169 * drops) however there's a hardware issue that 1170 * causes things to get too far out of whack. 1171 */ 1172 /* 1173 * XXX can we hold the PCU lock here? 1174 * Are there any net80211 buffer calls involved? 1175 */ 1176 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1177 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1178 ath_hal_rxena(ah); /* enable recv descriptors */ 1179 ath_mode_init(sc); /* set filters, etc. */ 1180 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1181 #endif 1182 1183 ath_hal_intrset(ah, sc->sc_imask); 1184 sc->sc_kickpcu = 0; 1185 ATH_PCU_UNLOCK(sc); 1186 } 1187 1188 #ifdef IEEE80211_SUPPORT_SUPERG 1189 if (resched) 1190 ieee80211_ff_age_all(ic, 100); 1191 #endif 1192 1193 /* 1194 * Put the hardware to sleep again if we're done with it. 1195 */ 1196 ATH_LOCK(sc); 1197 ath_power_restore_power_state(sc); 1198 ATH_UNLOCK(sc); 1199 1200 /* 1201 * If we hit the maximum number of frames in this round, 1202 * reschedule for another immediate pass. This gives 1203 * the TX and TX completion routines time to run, which 1204 * will reduce latency. 1205 */ 1206 if (npkts >= ATH_RX_MAX) 1207 sc->sc_rx.recv_sched(sc, resched); 1208 1209 ATH_PCU_LOCK(sc); 1210 sc->sc_rxproc_cnt--; 1211 ATH_PCU_UNLOCK(sc); 1212 } 1213 #undef PA2DESC 1214 #undef ATH_RX_MAX 1215 1216 /* 1217 * Only run the RX proc if it's not already running. 1218 * Since this may get run as part of the reset/flush path, 1219 * the task can't clash with an existing, running tasklet. 1220 */ 1221 static void 1222 ath_legacy_rx_tasklet(void *arg, int npending) 1223 { 1224 struct ath_softc *sc = arg; 1225 1226 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1227 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1228 ATH_PCU_LOCK(sc); 1229 if (sc->sc_inreset_cnt > 0) { 1230 device_printf(sc->sc_dev, 1231 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1232 ATH_PCU_UNLOCK(sc); 1233 return; 1234 } 1235 ATH_PCU_UNLOCK(sc); 1236 1237 ath_rx_proc(sc, 1); 1238 } 1239 1240 static void 1241 ath_legacy_flushrecv(struct ath_softc *sc) 1242 { 1243 1244 ath_rx_proc(sc, 0); 1245 } 1246 1247 static void 1248 ath_legacy_flush_rxpending(struct ath_softc *sc) 1249 { 1250 1251 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1252 1253 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1254 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1255 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1256 } 1257 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1258 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1259 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1260 } 1261 } 1262 1263 static int 1264 ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1265 { 1266 struct ath_buf *bf; 1267 1268 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1269 /* 1270 * If there are RX holding buffers, free them here and return 1271 * them to the list. 1272 * 1273 * XXX should just verify that bf->bf_m is NULL, as it must 1274 * be at this point! 1275 */ 1276 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1277 if (bf != NULL) { 1278 if (bf->bf_m != NULL) 1279 m_freem(bf->bf_m); 1280 bf->bf_m = NULL; 1281 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1282 (void) ath_rxbuf_init(sc, bf); 1283 } 1284 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1285 1286 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1287 if (bf != NULL) { 1288 if (bf->bf_m != NULL) 1289 m_freem(bf->bf_m); 1290 bf->bf_m = NULL; 1291 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1292 (void) ath_rxbuf_init(sc, bf); 1293 } 1294 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1295 1296 return (0); 1297 } 1298 1299 /* 1300 * Disable the receive h/w in preparation for a reset. 1301 */ 1302 static void 1303 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1304 { 1305 #define PA2DESC(_sc, _pa) \ 1306 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1307 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1308 struct ath_hal *ah = sc->sc_ah; 1309 1310 ATH_RX_LOCK(sc); 1311 1312 ath_hal_stoppcurecv(ah); /* disable PCU */ 1313 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1314 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1315 /* 1316 * TODO: see if this particular DELAY() is required; it may be 1317 * masking some missing FIFO flush or DMA sync. 1318 */ 1319 #if 0 1320 if (dodelay) 1321 #endif 1322 DELAY(3000); /* 3ms is long enough for 1 frame */ 1323 #ifdef ATH_DEBUG 1324 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1325 struct ath_buf *bf; 1326 u_int ix; 1327 1328 device_printf(sc->sc_dev, 1329 "%s: rx queue %p, link %p\n", 1330 __func__, 1331 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1332 sc->sc_rxlink); 1333 ix = 0; 1334 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1335 struct ath_desc *ds = bf->bf_desc; 1336 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1337 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1338 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1339 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1340 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1341 ix++; 1342 } 1343 } 1344 #endif 1345 1346 (void) ath_legacy_flush_rxpending(sc); 1347 (void) ath_legacy_flush_rxholdbf(sc); 1348 1349 sc->sc_rxlink = NULL; /* just in case */ 1350 1351 ATH_RX_UNLOCK(sc); 1352 #undef PA2DESC 1353 } 1354 1355 /* 1356 * XXX TODO: something was calling startrecv without calling 1357 * stoprecv. Let's figure out what/why. It was showing up 1358 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1359 */ 1360 1361 /* 1362 * Enable the receive h/w following a reset. 1363 */ 1364 static int 1365 ath_legacy_startrecv(struct ath_softc *sc) 1366 { 1367 struct ath_hal *ah = sc->sc_ah; 1368 struct ath_buf *bf; 1369 1370 ATH_RX_LOCK(sc); 1371 1372 /* 1373 * XXX should verify these are already all NULL! 1374 */ 1375 sc->sc_rxlink = NULL; 1376 (void) ath_legacy_flush_rxpending(sc); 1377 (void) ath_legacy_flush_rxholdbf(sc); 1378 1379 /* 1380 * Re-chain all of the buffers in the RX buffer list. 1381 */ 1382 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1383 int error = ath_rxbuf_init(sc, bf); 1384 if (error != 0) { 1385 DPRINTF(sc, ATH_DEBUG_RECV, 1386 "%s: ath_rxbuf_init failed %d\n", 1387 __func__, error); 1388 return error; 1389 } 1390 } 1391 1392 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1393 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1394 ath_hal_rxena(ah); /* enable recv descriptors */ 1395 ath_mode_init(sc); /* set filters, etc. */ 1396 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1397 1398 ATH_RX_UNLOCK(sc); 1399 return 0; 1400 } 1401 1402 static int 1403 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1404 { 1405 int error; 1406 1407 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1408 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1409 if (error != 0) 1410 return (error); 1411 1412 return (0); 1413 } 1414 1415 static int 1416 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1417 { 1418 1419 if (sc->sc_rxdma.dd_desc_len != 0) 1420 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1421 return (0); 1422 } 1423 1424 static void 1425 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1426 { 1427 1428 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1429 } 1430 1431 static void 1432 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1433 int dosched) 1434 { 1435 1436 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1437 } 1438 1439 void 1440 ath_recv_setup_legacy(struct ath_softc *sc) 1441 { 1442 1443 /* Sensible legacy defaults */ 1444 /* 1445 * XXX this should be changed to properly support the 1446 * exact RX descriptor size for each HAL. 1447 */ 1448 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1449 1450 sc->sc_rx.recv_start = ath_legacy_startrecv; 1451 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1452 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1453 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1454 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1455 1456 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1457 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1458 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1459 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1460 } 1461