1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 35 */ 36 #include "opt_ath.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 #include <sys/errno.h> 46 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 #include <sys/bus.h> 50 #include <sys/rman.h> 51 52 #include <sys/socket.h> 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 #include <net/if_arp.h> 57 #include <net/ethernet.h> 58 59 #include <net80211/ieee80211_var.h> 60 61 #include <dev/ath/if_athvar.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 66 /* For EEPROM firmware */ 67 #ifdef ATH_EEPROM_FIRMWARE 68 #include <sys/linker.h> 69 #include <sys/firmware.h> 70 #endif /* ATH_EEPROM_FIRMWARE */ 71 72 /* 73 * PCI glue. 74 */ 75 76 struct ath_pci_softc { 77 struct ath_softc sc_sc; 78 struct resource *sc_sr; /* memory resource */ 79 struct resource *sc_irq; /* irq resource */ 80 void *sc_ih; /* interrupt handler */ 81 }; 82 83 #define BS_BAR 0x10 84 #define PCIR_RETRY_TIMEOUT 0x41 85 #define PCIR_CFG_PMCSR 0x48 86 87 #define DEFAULT_CACHESIZE 32 88 89 static void 90 ath_pci_setup(device_t dev) 91 { 92 uint8_t cz; 93 94 /* XXX TODO: need to override the _system_ saved copies of this */ 95 96 /* 97 * If the cache line size is 0, force it to a reasonable 98 * value. 99 */ 100 cz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 101 if (cz == 0) { 102 pci_write_config(dev, PCIR_CACHELNSZ, 103 DEFAULT_CACHESIZE / 4, 1); 104 } 105 106 /* Override the system latency timer */ 107 pci_write_config(dev, PCIR_LATTIMER, 0xa8, 1); 108 109 /* If a PCI NIC, force wakeup */ 110 #ifdef ATH_PCI_WAKEUP_WAR 111 /* XXX TODO: don't do this for non-PCI (ie, PCIe, Cardbus!) */ 112 if (1) { 113 uint16_t pmcsr; 114 pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2); 115 pmcsr |= 3; 116 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 117 pmcsr &= ~3; 118 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 119 } 120 #endif 121 122 /* 123 * Disable retry timeout to keep PCI Tx retries from 124 * interfering with C3 CPU state. 125 */ 126 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1); 127 } 128 129 static int 130 ath_pci_probe(device_t dev) 131 { 132 const char* devname; 133 134 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev)); 135 if (devname != NULL) { 136 device_set_desc(dev, devname); 137 return BUS_PROBE_DEFAULT; 138 } 139 return ENXIO; 140 } 141 142 static int 143 ath_pci_attach(device_t dev) 144 { 145 struct ath_pci_softc *psc = device_get_softc(dev); 146 struct ath_softc *sc = &psc->sc_sc; 147 int error = ENXIO; 148 int rid; 149 #ifdef ATH_EEPROM_FIRMWARE 150 const struct firmware *fw = NULL; 151 const char *buf; 152 #endif 153 154 sc->sc_dev = dev; 155 156 /* 157 * Enable bus mastering. 158 */ 159 pci_enable_busmaster(dev); 160 161 /* 162 * Setup other PCI bus configuration parameters. 163 */ 164 ath_pci_setup(dev); 165 166 /* 167 * Setup memory-mapping of PCI registers. 168 */ 169 rid = BS_BAR; 170 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 171 RF_ACTIVE); 172 if (psc->sc_sr == NULL) { 173 device_printf(dev, "cannot map register space\n"); 174 goto bad; 175 } 176 sc->sc_st = (HAL_BUS_TAG) rman_get_bustag(psc->sc_sr); 177 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr); 178 /* 179 * Mark device invalid so any interrupts (shared or otherwise) 180 * that arrive before the HAL is setup are discarded. 181 */ 182 sc->sc_invalid = 1; 183 184 /* 185 * Arrange interrupt line. 186 */ 187 rid = 0; 188 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 189 RF_SHAREABLE|RF_ACTIVE); 190 if (psc->sc_irq == NULL) { 191 device_printf(dev, "could not map interrupt\n"); 192 goto bad1; 193 } 194 if (bus_setup_intr(dev, psc->sc_irq, 195 INTR_TYPE_NET | INTR_MPSAFE, 196 NULL, ath_intr, sc, &psc->sc_ih)) { 197 device_printf(dev, "could not establish interrupt\n"); 198 goto bad2; 199 } 200 201 /* 202 * Setup DMA descriptor area. 203 */ 204 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 205 1, 0, /* alignment, bounds */ 206 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 207 BUS_SPACE_MAXADDR, /* highaddr */ 208 NULL, NULL, /* filter, filterarg */ 209 0x3ffff, /* maxsize XXX */ 210 ATH_MAX_SCATTER, /* nsegments */ 211 0x3ffff, /* maxsegsize XXX */ 212 BUS_DMA_ALLOCNOW, /* flags */ 213 NULL, /* lockfunc */ 214 NULL, /* lockarg */ 215 &sc->sc_dmat)) { 216 device_printf(dev, "cannot allocate DMA tag\n"); 217 goto bad3; 218 } 219 220 #ifdef ATH_EEPROM_FIRMWARE 221 /* 222 * If there's an EEPROM firmware image, load that in. 223 */ 224 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 225 "eeprom_firmware", &buf) == 0) { 226 if (bootverbose) 227 device_printf(dev, "%s: looking up firmware @ '%s'\n", 228 __func__, buf); 229 230 fw = firmware_get(buf); 231 if (fw == NULL) { 232 device_printf(dev, "%s: couldn't find firmware\n", 233 __func__); 234 goto bad3; 235 } 236 237 device_printf(dev, "%s: EEPROM firmware @ %p\n", 238 __func__, fw->data); 239 sc->sc_eepromdata = 240 malloc(fw->datasize, M_TEMP, M_WAITOK | M_ZERO); 241 if (! sc->sc_eepromdata) { 242 device_printf(dev, "%s: can't malloc eepromdata\n", 243 __func__); 244 goto bad3; 245 } 246 memcpy(sc->sc_eepromdata, fw->data, fw->datasize); 247 firmware_put(fw, 0); 248 } 249 #endif /* ATH_EEPROM_FIRMWARE */ 250 251 ATH_LOCK_INIT(sc); 252 ATH_PCU_LOCK_INIT(sc); 253 ATH_RX_LOCK_INIT(sc); 254 ATH_TX_LOCK_INIT(sc); 255 ATH_TX_IC_LOCK_INIT(sc); 256 ATH_TXSTATUS_LOCK_INIT(sc); 257 258 error = ath_attach(pci_get_device(dev), sc); 259 if (error == 0) /* success */ 260 return 0; 261 262 ATH_TXSTATUS_LOCK_DESTROY(sc); 263 ATH_PCU_LOCK_DESTROY(sc); 264 ATH_RX_LOCK_DESTROY(sc); 265 ATH_TX_IC_LOCK_DESTROY(sc); 266 ATH_TX_LOCK_DESTROY(sc); 267 ATH_LOCK_DESTROY(sc); 268 bus_dma_tag_destroy(sc->sc_dmat); 269 bad3: 270 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 271 bad2: 272 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 273 bad1: 274 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 275 bad: 276 return (error); 277 } 278 279 static int 280 ath_pci_detach(device_t dev) 281 { 282 struct ath_pci_softc *psc = device_get_softc(dev); 283 struct ath_softc *sc = &psc->sc_sc; 284 285 /* check if device was removed */ 286 sc->sc_invalid = !bus_child_present(dev); 287 288 /* 289 * Do a config read to clear pre-existing pci error status. 290 */ 291 (void) pci_read_config(dev, PCIR_COMMAND, 4); 292 293 ath_detach(sc); 294 295 bus_generic_detach(dev); 296 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 297 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 298 299 bus_dma_tag_destroy(sc->sc_dmat); 300 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 301 302 if (sc->sc_eepromdata) 303 free(sc->sc_eepromdata, M_TEMP); 304 305 ATH_TXSTATUS_LOCK_DESTROY(sc); 306 ATH_PCU_LOCK_DESTROY(sc); 307 ATH_RX_LOCK_DESTROY(sc); 308 ATH_TX_IC_LOCK_DESTROY(sc); 309 ATH_TX_LOCK_DESTROY(sc); 310 ATH_LOCK_DESTROY(sc); 311 312 return (0); 313 } 314 315 static int 316 ath_pci_shutdown(device_t dev) 317 { 318 struct ath_pci_softc *psc = device_get_softc(dev); 319 320 ath_shutdown(&psc->sc_sc); 321 return (0); 322 } 323 324 static int 325 ath_pci_suspend(device_t dev) 326 { 327 struct ath_pci_softc *psc = device_get_softc(dev); 328 329 ath_suspend(&psc->sc_sc); 330 331 return (0); 332 } 333 334 static int 335 ath_pci_resume(device_t dev) 336 { 337 struct ath_pci_softc *psc = device_get_softc(dev); 338 339 /* 340 * Suspend/resume resets the PCI configuration space. 341 */ 342 ath_pci_setup(dev); 343 344 ath_resume(&psc->sc_sc); 345 346 return (0); 347 } 348 349 static device_method_t ath_pci_methods[] = { 350 /* Device interface */ 351 DEVMETHOD(device_probe, ath_pci_probe), 352 DEVMETHOD(device_attach, ath_pci_attach), 353 DEVMETHOD(device_detach, ath_pci_detach), 354 DEVMETHOD(device_shutdown, ath_pci_shutdown), 355 DEVMETHOD(device_suspend, ath_pci_suspend), 356 DEVMETHOD(device_resume, ath_pci_resume), 357 358 { 0,0 } 359 }; 360 static driver_t ath_pci_driver = { 361 "ath", 362 ath_pci_methods, 363 sizeof (struct ath_pci_softc) 364 }; 365 static devclass_t ath_devclass; 366 DRIVER_MODULE(ath_pci, pci, ath_pci_driver, ath_devclass, 0, 0); 367 MODULE_VERSION(ath_pci, 1); 368 MODULE_DEPEND(ath_pci, wlan, 1, 1, 1); /* 802.11 media layer */ 369 MODULE_DEPEND(ath_pci, if_ath, 1, 1, 1); /* if_ath driver */ 370