1 /*- 2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 /* 41 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 42 */ 43 44 #include "opt_inet.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/module.h> 51 #include <sys/kernel.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/socket.h> 55 #include <sys/sockio.h> 56 #include <sys/errno.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/bus.h> 61 #include <sys/rman.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/ethernet.h> 67 #include <net/if_llc.h> 68 #include <net/if_arp.h> 69 70 #include <net80211/ieee80211.h> 71 #include <net80211/ieee80211_crypto.h> 72 #include <net80211/ieee80211_node.h> 73 #include <net80211/ieee80211_proto.h> 74 #include <net80211/ieee80211_var.h> 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/if_ether.h> 79 #endif 80 81 #include <dev/ath/if_athvar.h> 82 #include <contrib/dev/ath/ah.h> 83 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcireg.h> 86 87 /* 88 * PCI glue. 89 */ 90 91 struct ath_pci_softc { 92 struct ath_softc sc_sc; 93 struct resource *sc_sr; /* memory resource */ 94 struct resource *sc_irq; /* irq resource */ 95 void *sc_ih; /* intererupt handler */ 96 u_int8_t sc_saved_intline; 97 u_int8_t sc_saved_cachelinesz; 98 u_int8_t sc_saved_lattimer; 99 }; 100 101 #define BS_BAR 0x10 102 103 static int 104 ath_pci_probe(device_t dev) 105 { 106 const char* devname; 107 108 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev)); 109 if (devname) { 110 device_set_desc(dev, devname); 111 return 0; 112 } 113 return ENXIO; 114 } 115 116 static int 117 ath_pci_attach(device_t dev) 118 { 119 struct ath_pci_softc *psc = device_get_softc(dev); 120 struct ath_softc *sc = &psc->sc_sc; 121 u_int32_t cmd; 122 int error = ENXIO; 123 int rid; 124 125 bzero(psc, sizeof (*psc)); 126 sc->sc_dev = dev; 127 128 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 129 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 130 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 131 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 132 133 if ((cmd & PCIM_CMD_MEMEN) == 0) { 134 device_printf(dev, "failed to enable memory mapping\n"); 135 goto bad; 136 } 137 138 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) { 139 device_printf(dev, "failed to enable bus mastering\n"); 140 goto bad; 141 } 142 143 /* 144 * Setup memory-mapping of PCI registers. 145 */ 146 rid = BS_BAR; 147 psc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 148 0, ~0, 1, RF_ACTIVE); 149 if (psc->sc_sr == NULL) { 150 device_printf(dev, "cannot map register space\n"); 151 goto bad; 152 } 153 sc->sc_st = rman_get_bustag(psc->sc_sr); 154 sc->sc_sh = rman_get_bushandle(psc->sc_sr); 155 156 /* 157 * Arrange interrupt line. 158 */ 159 rid = 0; 160 psc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 161 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 162 if (psc->sc_irq == NULL) { 163 device_printf(dev, "could not map interrupt\n"); 164 goto bad1; 165 } 166 if (bus_setup_intr(dev, psc->sc_irq, 167 INTR_TYPE_NET | INTR_MPSAFE, 168 ath_intr, sc, &psc->sc_ih)) { 169 device_printf(dev, "could not establish interrupt\n"); 170 goto bad2; 171 } 172 173 /* 174 * Setup DMA descriptor area. 175 */ 176 if (bus_dma_tag_create(NULL, /* parent */ 177 1, 0, /* alignment, bounds */ 178 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 179 BUS_SPACE_MAXADDR, /* highaddr */ 180 NULL, NULL, /* filter, filterarg */ 181 0x3ffff, /* maxsize XXX */ 182 ATH_MAX_SCATTER, /* nsegments */ 183 0xffff, /* maxsegsize XXX */ 184 BUS_DMA_ALLOCNOW, /* flags */ 185 NULL, /* lockfunc */ 186 NULL, /* lockarg */ 187 &sc->sc_dmat)) { 188 device_printf(dev, "cannot allocate DMA tag\n"); 189 goto bad3; 190 } 191 192 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), 193 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE); 194 195 error = ath_attach(pci_get_device(dev), sc); 196 if (error == 0) 197 return error; 198 199 mtx_destroy(&sc->sc_mtx); 200 bus_dma_tag_destroy(sc->sc_dmat); 201 bad3: 202 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 203 bad2: 204 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 205 bad1: 206 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 207 bad: 208 return (error); 209 } 210 211 static int 212 ath_pci_detach(device_t dev) 213 { 214 struct ath_pci_softc *psc = device_get_softc(dev); 215 struct ath_softc *sc = &psc->sc_sc; 216 217 /* check if device was removed */ 218 sc->sc_invalid = !bus_child_present(dev); 219 220 ath_detach(sc); 221 222 bus_generic_detach(dev); 223 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 224 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 225 226 bus_dma_tag_destroy(sc->sc_dmat); 227 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 228 229 mtx_destroy(&sc->sc_mtx); 230 231 return (0); 232 } 233 234 static int 235 ath_pci_shutdown(device_t dev) 236 { 237 struct ath_pci_softc *psc = device_get_softc(dev); 238 239 ath_shutdown(&psc->sc_sc); 240 return (0); 241 } 242 243 static int 244 ath_pci_suspend(device_t dev) 245 { 246 struct ath_pci_softc *psc = device_get_softc(dev); 247 248 ath_suspend(&psc->sc_sc); 249 250 psc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 251 psc->sc_saved_cachelinesz= pci_read_config(dev, PCIR_CACHELNSZ, 1); 252 psc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 253 254 return (0); 255 } 256 257 static int 258 ath_pci_resume(device_t dev) 259 { 260 struct ath_pci_softc *psc = device_get_softc(dev); 261 u_int16_t cmd; 262 263 pci_write_config(dev, PCIR_INTLINE, psc->sc_saved_intline, 1); 264 pci_write_config(dev, PCIR_CACHELNSZ, psc->sc_saved_cachelinesz, 1); 265 pci_write_config(dev, PCIR_LATTIMER, psc->sc_saved_lattimer, 1); 266 267 /* re-enable mem-map and busmastering */ 268 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 269 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 270 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 271 272 ath_resume(&psc->sc_sc); 273 274 return (0); 275 } 276 277 static device_method_t ath_pci_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, ath_pci_probe), 280 DEVMETHOD(device_attach, ath_pci_attach), 281 DEVMETHOD(device_detach, ath_pci_detach), 282 DEVMETHOD(device_shutdown, ath_pci_shutdown), 283 DEVMETHOD(device_suspend, ath_pci_suspend), 284 DEVMETHOD(device_resume, ath_pci_resume), 285 286 { 0,0 } 287 }; 288 static driver_t ath_pci_driver = { 289 "ath", 290 ath_pci_methods, 291 sizeof (struct ath_pci_softc) 292 }; 293 static devclass_t ath_devclass; 294 DRIVER_MODULE(if_ath, pci, ath_pci_driver, ath_devclass, 0, 0); 295 DRIVER_MODULE(if_ath, cardbus, ath_pci_driver, ath_devclass, 0, 0); 296 MODULE_VERSION(if_ath, 1); 297 MODULE_DEPEND(if_ath, ath_hal, 1, 1, 1); /* Atheros HAL */ 298 MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */ 299