1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/module.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/errno.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <sys/bus.h> 48 #include <sys/rman.h> 49 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_media.h> 54 #include <net/if_arp.h> 55 56 #include <net80211/ieee80211_var.h> 57 58 #include <dev/ath/if_athvar.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 63 /* 64 * PCI glue. 65 */ 66 67 struct ath_pci_softc { 68 struct ath_softc sc_sc; 69 struct resource *sc_sr; /* memory resource */ 70 struct resource *sc_irq; /* irq resource */ 71 void *sc_ih; /* interrupt handler */ 72 }; 73 74 #define BS_BAR 0x10 75 #define PCIR_RETRY_TIMEOUT 0x41 76 #define PCIR_CFG_PMCSR 0x48 77 78 static void 79 ath_pci_setup(device_t dev) 80 { 81 #ifdef ATH_PCI_LATENCY_WAR 82 /* Override the system latency timer */ 83 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 84 #endif 85 86 /* If a PCI NIC, force wakeup */ 87 #ifdef ATH_PCI_WAKEUP_WAR 88 /* XXX TODO: don't do this for non-PCI (ie, PCIe, Cardbus!) */ 89 if (1) { 90 uint16_t pmcsr; 91 pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2); 92 pmcsr |= 3; 93 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 94 pmcsr &= ~3; 95 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 96 } 97 #endif 98 99 /* 100 * Disable retry timeout to keep PCI Tx retries from 101 * interfering with C3 CPU state. 102 */ 103 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1); 104 } 105 106 static int 107 ath_pci_probe(device_t dev) 108 { 109 const char* devname; 110 111 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev)); 112 if (devname != NULL) { 113 device_set_desc(dev, devname); 114 return BUS_PROBE_DEFAULT; 115 } 116 return ENXIO; 117 } 118 119 static int 120 ath_pci_attach(device_t dev) 121 { 122 struct ath_pci_softc *psc = device_get_softc(dev); 123 struct ath_softc *sc = &psc->sc_sc; 124 int error = ENXIO; 125 int rid; 126 127 sc->sc_dev = dev; 128 129 /* 130 * Enable bus mastering. 131 */ 132 pci_enable_busmaster(dev); 133 134 /* 135 * Setup other PCI bus configuration parameters. 136 */ 137 ath_pci_setup(dev); 138 139 /* 140 * Setup memory-mapping of PCI registers. 141 */ 142 rid = BS_BAR; 143 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 144 RF_ACTIVE); 145 if (psc->sc_sr == NULL) { 146 device_printf(dev, "cannot map register space\n"); 147 goto bad; 148 } 149 /* XXX uintptr_t is a bandaid for ia64; to be fixed */ 150 sc->sc_st = (HAL_BUS_TAG)(uintptr_t) rman_get_bustag(psc->sc_sr); 151 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr); 152 /* 153 * Mark device invalid so any interrupts (shared or otherwise) 154 * that arrive before the HAL is setup are discarded. 155 */ 156 sc->sc_invalid = 1; 157 158 /* 159 * Arrange interrupt line. 160 */ 161 rid = 0; 162 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 163 RF_SHAREABLE|RF_ACTIVE); 164 if (psc->sc_irq == NULL) { 165 device_printf(dev, "could not map interrupt\n"); 166 goto bad1; 167 } 168 if (bus_setup_intr(dev, psc->sc_irq, 169 INTR_TYPE_NET | INTR_MPSAFE, 170 NULL, ath_intr, sc, &psc->sc_ih)) { 171 device_printf(dev, "could not establish interrupt\n"); 172 goto bad2; 173 } 174 175 /* 176 * Setup DMA descriptor area. 177 */ 178 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 179 1, 0, /* alignment, bounds */ 180 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 181 BUS_SPACE_MAXADDR, /* highaddr */ 182 NULL, NULL, /* filter, filterarg */ 183 0x3ffff, /* maxsize XXX */ 184 ATH_MAX_SCATTER, /* nsegments */ 185 0x3ffff, /* maxsegsize XXX */ 186 BUS_DMA_ALLOCNOW, /* flags */ 187 NULL, /* lockfunc */ 188 NULL, /* lockarg */ 189 &sc->sc_dmat)) { 190 device_printf(dev, "cannot allocate DMA tag\n"); 191 goto bad3; 192 } 193 194 ATH_LOCK_INIT(sc); 195 ATH_PCU_LOCK_INIT(sc); 196 197 error = ath_attach(pci_get_device(dev), sc); 198 if (error == 0) /* success */ 199 return 0; 200 201 ATH_PCU_LOCK_DESTROY(sc); 202 ATH_LOCK_DESTROY(sc); 203 bus_dma_tag_destroy(sc->sc_dmat); 204 bad3: 205 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 206 bad2: 207 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 208 bad1: 209 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 210 bad: 211 return (error); 212 } 213 214 static int 215 ath_pci_detach(device_t dev) 216 { 217 struct ath_pci_softc *psc = device_get_softc(dev); 218 struct ath_softc *sc = &psc->sc_sc; 219 220 /* check if device was removed */ 221 sc->sc_invalid = !bus_child_present(dev); 222 223 /* 224 * Do a config read to clear pre-existing pci error status. 225 */ 226 (void) pci_read_config(dev, PCIR_COMMAND, 4); 227 228 ath_detach(sc); 229 230 bus_generic_detach(dev); 231 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 232 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 233 234 bus_dma_tag_destroy(sc->sc_dmat); 235 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 236 237 ATH_PCU_LOCK_DESTROY(sc); 238 ATH_LOCK_DESTROY(sc); 239 240 return (0); 241 } 242 243 static int 244 ath_pci_shutdown(device_t dev) 245 { 246 struct ath_pci_softc *psc = device_get_softc(dev); 247 248 ath_shutdown(&psc->sc_sc); 249 return (0); 250 } 251 252 static int 253 ath_pci_suspend(device_t dev) 254 { 255 struct ath_pci_softc *psc = device_get_softc(dev); 256 257 ath_suspend(&psc->sc_sc); 258 259 return (0); 260 } 261 262 static int 263 ath_pci_resume(device_t dev) 264 { 265 struct ath_pci_softc *psc = device_get_softc(dev); 266 267 /* 268 * Suspend/resume resets the PCI configuration space. 269 */ 270 ath_pci_setup(dev); 271 272 ath_resume(&psc->sc_sc); 273 274 return (0); 275 } 276 277 static device_method_t ath_pci_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, ath_pci_probe), 280 DEVMETHOD(device_attach, ath_pci_attach), 281 DEVMETHOD(device_detach, ath_pci_detach), 282 DEVMETHOD(device_shutdown, ath_pci_shutdown), 283 DEVMETHOD(device_suspend, ath_pci_suspend), 284 DEVMETHOD(device_resume, ath_pci_resume), 285 286 { 0,0 } 287 }; 288 static driver_t ath_pci_driver = { 289 "ath", 290 ath_pci_methods, 291 sizeof (struct ath_pci_softc) 292 }; 293 static devclass_t ath_devclass; 294 DRIVER_MODULE(ath_pci, pci, ath_pci_driver, ath_devclass, 0, 0); 295 MODULE_VERSION(ath_pci, 1); 296 MODULE_DEPEND(ath_pci, wlan, 1, 1, 1); /* 802.11 media layer */ 297 MODULE_DEPEND(ath_pci, if_ath, 1, 1, 1); /* if_ath driver */ 298