1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 35 */ 36 #include "opt_ath.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/module.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/errno.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <sys/bus.h> 49 #include <sys/rman.h> 50 51 #include <sys/socket.h> 52 53 #include <net/if.h> 54 #include <net/if_media.h> 55 #include <net/if_arp.h> 56 57 #include <net80211/ieee80211_var.h> 58 59 #include <dev/ath/if_athvar.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 64 /* For EEPROM firmware */ 65 #ifdef ATH_EEPROM_FIRMWARE 66 #include <sys/linker.h> 67 #include <sys/firmware.h> 68 #endif /* ATH_EEPROM_FIRMWARE */ 69 70 /* 71 * PCI glue. 72 */ 73 74 struct ath_pci_softc { 75 struct ath_softc sc_sc; 76 struct resource *sc_sr; /* memory resource */ 77 struct resource *sc_irq; /* irq resource */ 78 void *sc_ih; /* interrupt handler */ 79 }; 80 81 #define BS_BAR 0x10 82 #define PCIR_RETRY_TIMEOUT 0x41 83 #define PCIR_CFG_PMCSR 0x48 84 85 #define DEFAULT_CACHESIZE 32 86 87 static void 88 ath_pci_setup(device_t dev) 89 { 90 uint8_t cz; 91 92 /* XXX TODO: need to override the _system_ saved copies of this */ 93 94 /* 95 * If the cache line size is 0, force it to a reasonable 96 * value. 97 */ 98 cz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 99 if (cz == 0) { 100 pci_write_config(dev, PCIR_CACHELNSZ, 101 DEFAULT_CACHESIZE / 4, 1); 102 } 103 104 /* Override the system latency timer */ 105 pci_write_config(dev, PCIR_LATTIMER, 0xa8, 1); 106 107 /* If a PCI NIC, force wakeup */ 108 #ifdef ATH_PCI_WAKEUP_WAR 109 /* XXX TODO: don't do this for non-PCI (ie, PCIe, Cardbus!) */ 110 if (1) { 111 uint16_t pmcsr; 112 pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2); 113 pmcsr |= 3; 114 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 115 pmcsr &= ~3; 116 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 117 } 118 #endif 119 120 /* 121 * Disable retry timeout to keep PCI Tx retries from 122 * interfering with C3 CPU state. 123 */ 124 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1); 125 } 126 127 static int 128 ath_pci_probe(device_t dev) 129 { 130 const char* devname; 131 132 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev)); 133 if (devname != NULL) { 134 device_set_desc(dev, devname); 135 return BUS_PROBE_DEFAULT; 136 } 137 return ENXIO; 138 } 139 140 static int 141 ath_pci_attach(device_t dev) 142 { 143 struct ath_pci_softc *psc = device_get_softc(dev); 144 struct ath_softc *sc = &psc->sc_sc; 145 int error = ENXIO; 146 int rid; 147 #ifdef ATH_EEPROM_FIRMWARE 148 const struct firmware *fw = NULL; 149 const char *buf; 150 #endif 151 152 sc->sc_dev = dev; 153 154 /* 155 * Enable bus mastering. 156 */ 157 pci_enable_busmaster(dev); 158 159 /* 160 * Setup other PCI bus configuration parameters. 161 */ 162 ath_pci_setup(dev); 163 164 /* 165 * Setup memory-mapping of PCI registers. 166 */ 167 rid = BS_BAR; 168 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 169 RF_ACTIVE); 170 if (psc->sc_sr == NULL) { 171 device_printf(dev, "cannot map register space\n"); 172 goto bad; 173 } 174 /* XXX uintptr_t is a bandaid for ia64; to be fixed */ 175 sc->sc_st = (HAL_BUS_TAG)(uintptr_t) rman_get_bustag(psc->sc_sr); 176 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr); 177 /* 178 * Mark device invalid so any interrupts (shared or otherwise) 179 * that arrive before the HAL is setup are discarded. 180 */ 181 sc->sc_invalid = 1; 182 183 /* 184 * Arrange interrupt line. 185 */ 186 rid = 0; 187 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 188 RF_SHAREABLE|RF_ACTIVE); 189 if (psc->sc_irq == NULL) { 190 device_printf(dev, "could not map interrupt\n"); 191 goto bad1; 192 } 193 if (bus_setup_intr(dev, psc->sc_irq, 194 INTR_TYPE_NET | INTR_MPSAFE, 195 NULL, ath_intr, sc, &psc->sc_ih)) { 196 device_printf(dev, "could not establish interrupt\n"); 197 goto bad2; 198 } 199 200 /* 201 * Setup DMA descriptor area. 202 */ 203 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 204 1, 0, /* alignment, bounds */ 205 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 206 BUS_SPACE_MAXADDR, /* highaddr */ 207 NULL, NULL, /* filter, filterarg */ 208 0x3ffff, /* maxsize XXX */ 209 ATH_MAX_SCATTER, /* nsegments */ 210 0x3ffff, /* maxsegsize XXX */ 211 BUS_DMA_ALLOCNOW, /* flags */ 212 NULL, /* lockfunc */ 213 NULL, /* lockarg */ 214 &sc->sc_dmat)) { 215 device_printf(dev, "cannot allocate DMA tag\n"); 216 goto bad3; 217 } 218 219 #ifdef ATH_EEPROM_FIRMWARE 220 /* 221 * If there's an EEPROM firmware image, load that in. 222 */ 223 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 224 "eeprom_firmware", &buf) == 0) { 225 if (bootverbose) 226 device_printf(dev, "%s: looking up firmware @ '%s'\n", 227 __func__, buf); 228 229 fw = firmware_get(buf); 230 if (fw == NULL) { 231 device_printf(dev, "%s: couldn't find firmware\n", 232 __func__); 233 goto bad3; 234 } 235 236 device_printf(dev, "%s: EEPROM firmware @ %p\n", 237 __func__, fw->data); 238 sc->sc_eepromdata = 239 malloc(fw->datasize, M_TEMP, M_WAITOK | M_ZERO); 240 if (! sc->sc_eepromdata) { 241 device_printf(dev, "%s: can't malloc eepromdata\n", 242 __func__); 243 goto bad3; 244 } 245 memcpy(sc->sc_eepromdata, fw->data, fw->datasize); 246 firmware_put(fw, 0); 247 } 248 #endif /* ATH_EEPROM_FIRMWARE */ 249 250 ATH_LOCK_INIT(sc); 251 ATH_PCU_LOCK_INIT(sc); 252 ATH_RX_LOCK_INIT(sc); 253 ATH_TX_LOCK_INIT(sc); 254 ATH_TX_IC_LOCK_INIT(sc); 255 ATH_TXSTATUS_LOCK_INIT(sc); 256 257 error = ath_attach(pci_get_device(dev), sc); 258 if (error == 0) /* success */ 259 return 0; 260 261 ATH_TXSTATUS_LOCK_DESTROY(sc); 262 ATH_PCU_LOCK_DESTROY(sc); 263 ATH_RX_LOCK_DESTROY(sc); 264 ATH_TX_IC_LOCK_DESTROY(sc); 265 ATH_TX_LOCK_DESTROY(sc); 266 ATH_LOCK_DESTROY(sc); 267 bus_dma_tag_destroy(sc->sc_dmat); 268 bad3: 269 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 270 bad2: 271 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 272 bad1: 273 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 274 bad: 275 return (error); 276 } 277 278 static int 279 ath_pci_detach(device_t dev) 280 { 281 struct ath_pci_softc *psc = device_get_softc(dev); 282 struct ath_softc *sc = &psc->sc_sc; 283 284 /* check if device was removed */ 285 sc->sc_invalid = !bus_child_present(dev); 286 287 /* 288 * Do a config read to clear pre-existing pci error status. 289 */ 290 (void) pci_read_config(dev, PCIR_COMMAND, 4); 291 292 ath_detach(sc); 293 294 bus_generic_detach(dev); 295 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 296 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 297 298 bus_dma_tag_destroy(sc->sc_dmat); 299 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 300 301 if (sc->sc_eepromdata) 302 free(sc->sc_eepromdata, M_TEMP); 303 304 ATH_TXSTATUS_LOCK_DESTROY(sc); 305 ATH_PCU_LOCK_DESTROY(sc); 306 ATH_RX_LOCK_DESTROY(sc); 307 ATH_TX_IC_LOCK_DESTROY(sc); 308 ATH_TX_LOCK_DESTROY(sc); 309 ATH_LOCK_DESTROY(sc); 310 311 return (0); 312 } 313 314 static int 315 ath_pci_shutdown(device_t dev) 316 { 317 struct ath_pci_softc *psc = device_get_softc(dev); 318 319 ath_shutdown(&psc->sc_sc); 320 return (0); 321 } 322 323 static int 324 ath_pci_suspend(device_t dev) 325 { 326 struct ath_pci_softc *psc = device_get_softc(dev); 327 328 ath_suspend(&psc->sc_sc); 329 330 return (0); 331 } 332 333 static int 334 ath_pci_resume(device_t dev) 335 { 336 struct ath_pci_softc *psc = device_get_softc(dev); 337 338 /* 339 * Suspend/resume resets the PCI configuration space. 340 */ 341 ath_pci_setup(dev); 342 343 ath_resume(&psc->sc_sc); 344 345 return (0); 346 } 347 348 static device_method_t ath_pci_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, ath_pci_probe), 351 DEVMETHOD(device_attach, ath_pci_attach), 352 DEVMETHOD(device_detach, ath_pci_detach), 353 DEVMETHOD(device_shutdown, ath_pci_shutdown), 354 DEVMETHOD(device_suspend, ath_pci_suspend), 355 DEVMETHOD(device_resume, ath_pci_resume), 356 357 { 0,0 } 358 }; 359 static driver_t ath_pci_driver = { 360 "ath", 361 ath_pci_methods, 362 sizeof (struct ath_pci_softc) 363 }; 364 static devclass_t ath_devclass; 365 DRIVER_MODULE(ath_pci, pci, ath_pci_driver, ath_devclass, 0, 0); 366 MODULE_VERSION(ath_pci, 1); 367 MODULE_DEPEND(ath_pci, wlan, 1, 1, 1); /* 802.11 media layer */ 368 MODULE_DEPEND(ath_pci, if_ath, 1, 1, 1); /* if_ath driver */ 369