1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/module.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/errno.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <sys/bus.h> 48 #include <sys/rman.h> 49 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_media.h> 54 #include <net/if_arp.h> 55 56 #include <net80211/ieee80211_var.h> 57 58 #include <dev/ath/if_athvar.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 63 /* #define ATH_EEPROM_FIRMWARE */ 64 65 /* For EEPROM firmware */ 66 #ifdef ATH_EEPROM_FIRMWARE 67 #include <sys/linker.h> 68 #include <sys/firmware.h> 69 #endif /* ATH_EEPROM_FIRMWARE */ 70 71 /* 72 * PCI glue. 73 */ 74 75 struct ath_pci_softc { 76 struct ath_softc sc_sc; 77 struct resource *sc_sr; /* memory resource */ 78 struct resource *sc_irq; /* irq resource */ 79 void *sc_ih; /* interrupt handler */ 80 }; 81 82 #define BS_BAR 0x10 83 #define PCIR_RETRY_TIMEOUT 0x41 84 #define PCIR_CFG_PMCSR 0x48 85 86 static void 87 ath_pci_setup(device_t dev) 88 { 89 #ifdef ATH_PCI_LATENCY_WAR 90 /* Override the system latency timer */ 91 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 92 #endif 93 94 /* If a PCI NIC, force wakeup */ 95 #ifdef ATH_PCI_WAKEUP_WAR 96 /* XXX TODO: don't do this for non-PCI (ie, PCIe, Cardbus!) */ 97 if (1) { 98 uint16_t pmcsr; 99 pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2); 100 pmcsr |= 3; 101 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 102 pmcsr &= ~3; 103 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 104 } 105 #endif 106 107 /* 108 * Disable retry timeout to keep PCI Tx retries from 109 * interfering with C3 CPU state. 110 */ 111 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1); 112 } 113 114 static int 115 ath_pci_probe(device_t dev) 116 { 117 const char* devname; 118 119 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev)); 120 if (devname != NULL) { 121 device_set_desc(dev, devname); 122 return BUS_PROBE_DEFAULT; 123 } 124 return ENXIO; 125 } 126 127 static int 128 ath_pci_attach(device_t dev) 129 { 130 struct ath_pci_softc *psc = device_get_softc(dev); 131 struct ath_softc *sc = &psc->sc_sc; 132 int error = ENXIO; 133 int rid; 134 #ifdef ATH_EEPROM_FIRMWARE 135 const struct firmware *fw = NULL; 136 const char *buf; 137 #endif 138 139 sc->sc_dev = dev; 140 141 /* 142 * Enable bus mastering. 143 */ 144 pci_enable_busmaster(dev); 145 146 /* 147 * Setup other PCI bus configuration parameters. 148 */ 149 ath_pci_setup(dev); 150 151 /* 152 * Setup memory-mapping of PCI registers. 153 */ 154 rid = BS_BAR; 155 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 156 RF_ACTIVE); 157 if (psc->sc_sr == NULL) { 158 device_printf(dev, "cannot map register space\n"); 159 goto bad; 160 } 161 /* XXX uintptr_t is a bandaid for ia64; to be fixed */ 162 sc->sc_st = (HAL_BUS_TAG)(uintptr_t) rman_get_bustag(psc->sc_sr); 163 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr); 164 /* 165 * Mark device invalid so any interrupts (shared or otherwise) 166 * that arrive before the HAL is setup are discarded. 167 */ 168 sc->sc_invalid = 1; 169 170 /* 171 * Arrange interrupt line. 172 */ 173 rid = 0; 174 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 175 RF_SHAREABLE|RF_ACTIVE); 176 if (psc->sc_irq == NULL) { 177 device_printf(dev, "could not map interrupt\n"); 178 goto bad1; 179 } 180 if (bus_setup_intr(dev, psc->sc_irq, 181 INTR_TYPE_NET | INTR_MPSAFE, 182 NULL, ath_intr, sc, &psc->sc_ih)) { 183 device_printf(dev, "could not establish interrupt\n"); 184 goto bad2; 185 } 186 187 /* 188 * Setup DMA descriptor area. 189 */ 190 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 191 1, 0, /* alignment, bounds */ 192 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 193 BUS_SPACE_MAXADDR, /* highaddr */ 194 NULL, NULL, /* filter, filterarg */ 195 0x3ffff, /* maxsize XXX */ 196 ATH_MAX_SCATTER, /* nsegments */ 197 0x3ffff, /* maxsegsize XXX */ 198 BUS_DMA_ALLOCNOW, /* flags */ 199 NULL, /* lockfunc */ 200 NULL, /* lockarg */ 201 &sc->sc_dmat)) { 202 device_printf(dev, "cannot allocate DMA tag\n"); 203 goto bad3; 204 } 205 206 #ifdef ATH_EEPROM_FIRMWARE 207 /* 208 * If there's an EEPROM firmware image, load that in. 209 */ 210 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 211 "eeprom_firmware", &buf) == 0) { 212 if (bootverbose) 213 device_printf(dev, "%s: looking up firmware @ '%s'\n", 214 __func__, buf); 215 216 fw = firmware_get(buf); 217 if (fw == NULL) { 218 device_printf(dev, "%s: couldn't find firmware\n", 219 __func__); 220 goto bad3; 221 } 222 223 device_printf(dev, "%s: EEPROM firmware @ %p\n", 224 __func__, fw->data); 225 sc->sc_eepromdata = 226 malloc(fw->datasize, M_TEMP, M_WAITOK | M_ZERO); 227 if (! sc->sc_eepromdata) { 228 device_printf(dev, "%s: can't malloc eepromdata\n", 229 __func__); 230 goto bad3; 231 } 232 memcpy(sc->sc_eepromdata, fw->data, fw->datasize); 233 firmware_put(fw, 0); 234 } 235 #endif /* ATH_EEPROM_FIRMWARE */ 236 237 ATH_LOCK_INIT(sc); 238 ATH_PCU_LOCK_INIT(sc); 239 240 error = ath_attach(pci_get_device(dev), sc); 241 if (error == 0) /* success */ 242 return 0; 243 244 ATH_PCU_LOCK_DESTROY(sc); 245 ATH_LOCK_DESTROY(sc); 246 bus_dma_tag_destroy(sc->sc_dmat); 247 bad3: 248 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 249 bad2: 250 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 251 bad1: 252 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 253 bad: 254 return (error); 255 } 256 257 static int 258 ath_pci_detach(device_t dev) 259 { 260 struct ath_pci_softc *psc = device_get_softc(dev); 261 struct ath_softc *sc = &psc->sc_sc; 262 263 /* check if device was removed */ 264 sc->sc_invalid = !bus_child_present(dev); 265 266 /* 267 * Do a config read to clear pre-existing pci error status. 268 */ 269 (void) pci_read_config(dev, PCIR_COMMAND, 4); 270 271 ath_detach(sc); 272 273 bus_generic_detach(dev); 274 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 275 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 276 277 bus_dma_tag_destroy(sc->sc_dmat); 278 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 279 280 if (sc->sc_eepromdata) 281 free(sc->sc_eepromdata, M_TEMP); 282 283 ATH_PCU_LOCK_DESTROY(sc); 284 ATH_LOCK_DESTROY(sc); 285 286 return (0); 287 } 288 289 static int 290 ath_pci_shutdown(device_t dev) 291 { 292 struct ath_pci_softc *psc = device_get_softc(dev); 293 294 ath_shutdown(&psc->sc_sc); 295 return (0); 296 } 297 298 static int 299 ath_pci_suspend(device_t dev) 300 { 301 struct ath_pci_softc *psc = device_get_softc(dev); 302 303 ath_suspend(&psc->sc_sc); 304 305 return (0); 306 } 307 308 static int 309 ath_pci_resume(device_t dev) 310 { 311 struct ath_pci_softc *psc = device_get_softc(dev); 312 313 /* 314 * Suspend/resume resets the PCI configuration space. 315 */ 316 ath_pci_setup(dev); 317 318 ath_resume(&psc->sc_sc); 319 320 return (0); 321 } 322 323 static device_method_t ath_pci_methods[] = { 324 /* Device interface */ 325 DEVMETHOD(device_probe, ath_pci_probe), 326 DEVMETHOD(device_attach, ath_pci_attach), 327 DEVMETHOD(device_detach, ath_pci_detach), 328 DEVMETHOD(device_shutdown, ath_pci_shutdown), 329 DEVMETHOD(device_suspend, ath_pci_suspend), 330 DEVMETHOD(device_resume, ath_pci_resume), 331 332 { 0,0 } 333 }; 334 static driver_t ath_pci_driver = { 335 "ath", 336 ath_pci_methods, 337 sizeof (struct ath_pci_softc) 338 }; 339 static devclass_t ath_devclass; 340 DRIVER_MODULE(ath_pci, pci, ath_pci_driver, ath_devclass, 0, 0); 341 MODULE_VERSION(ath_pci, 1); 342 MODULE_DEPEND(ath_pci, wlan, 1, 1, 1); /* 802.11 media layer */ 343 MODULE_DEPEND(ath_pci, if_ath, 1, 1, 1); /* if_ath driver */ 344