1ba5c15d9SAdrian Chadd /*- 2ba5c15d9SAdrian Chadd * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3ba5c15d9SAdrian Chadd * All rights reserved. 4ba5c15d9SAdrian Chadd * 5ba5c15d9SAdrian Chadd * Redistribution and use in source and binary forms, with or without 6ba5c15d9SAdrian Chadd * modification, are permitted provided that the following conditions 7ba5c15d9SAdrian Chadd * are met: 8ba5c15d9SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 9ba5c15d9SAdrian Chadd * notice, this list of conditions and the following disclaimer, 10ba5c15d9SAdrian Chadd * without modification. 11ba5c15d9SAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12ba5c15d9SAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13ba5c15d9SAdrian Chadd * redistribution must be conditioned upon including a substantially 14ba5c15d9SAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 15ba5c15d9SAdrian Chadd * 16ba5c15d9SAdrian Chadd * NO WARRANTY 17ba5c15d9SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18ba5c15d9SAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19ba5c15d9SAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20ba5c15d9SAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21ba5c15d9SAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22ba5c15d9SAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23ba5c15d9SAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24ba5c15d9SAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25ba5c15d9SAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26ba5c15d9SAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27ba5c15d9SAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 28ba5c15d9SAdrian Chadd */ 29ba5c15d9SAdrian Chadd 30ba5c15d9SAdrian Chadd #include <sys/cdefs.h> 31ba5c15d9SAdrian Chadd __FBSDID("$FreeBSD$"); 32ba5c15d9SAdrian Chadd 33ba5c15d9SAdrian Chadd /* 34ba5c15d9SAdrian Chadd * Driver for the Atheros Wireless LAN controller. 35ba5c15d9SAdrian Chadd * 36ba5c15d9SAdrian Chadd * This software is derived from work of Atsushi Onoe; his contribution 37ba5c15d9SAdrian Chadd * is greatly appreciated. 38ba5c15d9SAdrian Chadd */ 39ba5c15d9SAdrian Chadd 40ba5c15d9SAdrian Chadd #include "opt_inet.h" 41ba5c15d9SAdrian Chadd #include "opt_ath.h" 42ba5c15d9SAdrian Chadd /* 43ba5c15d9SAdrian Chadd * This is needed for register operations which are performed 44ba5c15d9SAdrian Chadd * by the driver - eg, calls to ath_hal_gettsf32(). 45ba5c15d9SAdrian Chadd * 46ba5c15d9SAdrian Chadd * It's also required for any AH_DEBUG checks in here, eg the 47ba5c15d9SAdrian Chadd * module dependencies. 48ba5c15d9SAdrian Chadd */ 49ba5c15d9SAdrian Chadd #include "opt_ah.h" 50ba5c15d9SAdrian Chadd #include "opt_wlan.h" 51ba5c15d9SAdrian Chadd 52ba5c15d9SAdrian Chadd #include <sys/param.h> 53ba5c15d9SAdrian Chadd #include <sys/systm.h> 54ba5c15d9SAdrian Chadd #include <sys/sysctl.h> 55ba5c15d9SAdrian Chadd #include <sys/mbuf.h> 56ba5c15d9SAdrian Chadd #include <sys/malloc.h> 57ba5c15d9SAdrian Chadd #include <sys/lock.h> 58ba5c15d9SAdrian Chadd #include <sys/mutex.h> 59ba5c15d9SAdrian Chadd #include <sys/kernel.h> 60ba5c15d9SAdrian Chadd #include <sys/socket.h> 61ba5c15d9SAdrian Chadd #include <sys/sockio.h> 62ba5c15d9SAdrian Chadd #include <sys/errno.h> 63ba5c15d9SAdrian Chadd #include <sys/callout.h> 64ba5c15d9SAdrian Chadd #include <sys/bus.h> 65ba5c15d9SAdrian Chadd #include <sys/endian.h> 66ba5c15d9SAdrian Chadd #include <sys/kthread.h> 67ba5c15d9SAdrian Chadd #include <sys/taskqueue.h> 68ba5c15d9SAdrian Chadd #include <sys/priv.h> 69ba5c15d9SAdrian Chadd #include <sys/module.h> 70ba5c15d9SAdrian Chadd #include <sys/ktr.h> 71ba5c15d9SAdrian Chadd #include <sys/smp.h> /* for mp_ncpus */ 72ba5c15d9SAdrian Chadd 73ba5c15d9SAdrian Chadd #include <machine/bus.h> 74ba5c15d9SAdrian Chadd 75ba5c15d9SAdrian Chadd #include <net/if.h> 76ba5c15d9SAdrian Chadd #include <net/if_dl.h> 77ba5c15d9SAdrian Chadd #include <net/if_media.h> 78ba5c15d9SAdrian Chadd #include <net/if_types.h> 79ba5c15d9SAdrian Chadd #include <net/if_arp.h> 80ba5c15d9SAdrian Chadd #include <net/ethernet.h> 81ba5c15d9SAdrian Chadd #include <net/if_llc.h> 82ba5c15d9SAdrian Chadd 83ba5c15d9SAdrian Chadd #include <net80211/ieee80211_var.h> 84ba5c15d9SAdrian Chadd #include <net80211/ieee80211_regdomain.h> 85ba5c15d9SAdrian Chadd #ifdef IEEE80211_SUPPORT_SUPERG 86ba5c15d9SAdrian Chadd #include <net80211/ieee80211_superg.h> 87ba5c15d9SAdrian Chadd #endif 88ba5c15d9SAdrian Chadd 89ba5c15d9SAdrian Chadd #include <net/bpf.h> 90ba5c15d9SAdrian Chadd 91ba5c15d9SAdrian Chadd #ifdef INET 92ba5c15d9SAdrian Chadd #include <netinet/in.h> 93ba5c15d9SAdrian Chadd #include <netinet/if_ether.h> 94ba5c15d9SAdrian Chadd #endif 95ba5c15d9SAdrian Chadd 96ba5c15d9SAdrian Chadd #include <dev/ath/if_athvar.h> 97ba5c15d9SAdrian Chadd 98ba5c15d9SAdrian Chadd #include <dev/ath/if_ath_debug.h> 99ba5c15d9SAdrian Chadd #include <dev/ath/if_ath_misc.h> 100ba5c15d9SAdrian Chadd #include <dev/ath/if_ath_tx.h> 101ba5c15d9SAdrian Chadd #include <dev/ath/if_ath_beacon.h> 102ba5c15d9SAdrian Chadd 103ba5c15d9SAdrian Chadd #ifdef ATH_TX99_DIAG 104ba5c15d9SAdrian Chadd #include <dev/ath/ath_tx99/ath_tx99.h> 105ba5c15d9SAdrian Chadd #endif 106ba5c15d9SAdrian Chadd 107ba5c15d9SAdrian Chadd /* 108ba5c15d9SAdrian Chadd * Setup a h/w transmit queue for beacons. 109ba5c15d9SAdrian Chadd */ 110ba5c15d9SAdrian Chadd int 111*e1252ce1SAdrian Chadd ath_beaconq_setup(struct ath_softc *sc) 112ba5c15d9SAdrian Chadd { 113*e1252ce1SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 114ba5c15d9SAdrian Chadd HAL_TXQ_INFO qi; 115ba5c15d9SAdrian Chadd 116ba5c15d9SAdrian Chadd memset(&qi, 0, sizeof(qi)); 117ba5c15d9SAdrian Chadd qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 118ba5c15d9SAdrian Chadd qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 119ba5c15d9SAdrian Chadd qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 120ba5c15d9SAdrian Chadd /* NB: for dynamic turbo, don't enable any other interrupts */ 121ba5c15d9SAdrian Chadd qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 122*e1252ce1SAdrian Chadd if (sc->sc_isedma) 123*e1252ce1SAdrian Chadd qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE | 124*e1252ce1SAdrian Chadd HAL_TXQ_TXERRINT_ENABLE; 125*e1252ce1SAdrian Chadd 126ba5c15d9SAdrian Chadd return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 127ba5c15d9SAdrian Chadd } 128ba5c15d9SAdrian Chadd 129ba5c15d9SAdrian Chadd /* 130ba5c15d9SAdrian Chadd * Setup the transmit queue parameters for the beacon queue. 131ba5c15d9SAdrian Chadd */ 132ba5c15d9SAdrian Chadd int 133ba5c15d9SAdrian Chadd ath_beaconq_config(struct ath_softc *sc) 134ba5c15d9SAdrian Chadd { 135ba5c15d9SAdrian Chadd #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 136ba5c15d9SAdrian Chadd struct ieee80211com *ic = sc->sc_ifp->if_l2com; 137ba5c15d9SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 138ba5c15d9SAdrian Chadd HAL_TXQ_INFO qi; 139ba5c15d9SAdrian Chadd 140ba5c15d9SAdrian Chadd ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 141ba5c15d9SAdrian Chadd if (ic->ic_opmode == IEEE80211_M_HOSTAP || 142ba5c15d9SAdrian Chadd ic->ic_opmode == IEEE80211_M_MBSS) { 143ba5c15d9SAdrian Chadd /* 144ba5c15d9SAdrian Chadd * Always burst out beacon and CAB traffic. 145ba5c15d9SAdrian Chadd */ 146ba5c15d9SAdrian Chadd qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 147ba5c15d9SAdrian Chadd qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 148ba5c15d9SAdrian Chadd qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 149ba5c15d9SAdrian Chadd } else { 150ba5c15d9SAdrian Chadd struct wmeParams *wmep = 151ba5c15d9SAdrian Chadd &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 152ba5c15d9SAdrian Chadd /* 153ba5c15d9SAdrian Chadd * Adhoc mode; important thing is to use 2x cwmin. 154ba5c15d9SAdrian Chadd */ 155ba5c15d9SAdrian Chadd qi.tqi_aifs = wmep->wmep_aifsn; 156ba5c15d9SAdrian Chadd qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 157ba5c15d9SAdrian Chadd qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 158ba5c15d9SAdrian Chadd } 159ba5c15d9SAdrian Chadd 160ba5c15d9SAdrian Chadd if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 161ba5c15d9SAdrian Chadd device_printf(sc->sc_dev, "unable to update parameters for " 162ba5c15d9SAdrian Chadd "beacon hardware queue!\n"); 163ba5c15d9SAdrian Chadd return 0; 164ba5c15d9SAdrian Chadd } else { 165ba5c15d9SAdrian Chadd ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 166ba5c15d9SAdrian Chadd return 1; 167ba5c15d9SAdrian Chadd } 168ba5c15d9SAdrian Chadd #undef ATH_EXPONENT_TO_VALUE 169ba5c15d9SAdrian Chadd } 170ba5c15d9SAdrian Chadd 171ba5c15d9SAdrian Chadd /* 172ba5c15d9SAdrian Chadd * Allocate and setup an initial beacon frame. 173ba5c15d9SAdrian Chadd */ 174ba5c15d9SAdrian Chadd int 175ba5c15d9SAdrian Chadd ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 176ba5c15d9SAdrian Chadd { 177ba5c15d9SAdrian Chadd struct ieee80211vap *vap = ni->ni_vap; 178ba5c15d9SAdrian Chadd struct ath_vap *avp = ATH_VAP(vap); 179ba5c15d9SAdrian Chadd struct ath_buf *bf; 180ba5c15d9SAdrian Chadd struct mbuf *m; 181ba5c15d9SAdrian Chadd int error; 182ba5c15d9SAdrian Chadd 183ba5c15d9SAdrian Chadd bf = avp->av_bcbuf; 184ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n", 185ba5c15d9SAdrian Chadd __func__, bf->bf_m, bf->bf_node); 186ba5c15d9SAdrian Chadd if (bf->bf_m != NULL) { 187ba5c15d9SAdrian Chadd bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 188ba5c15d9SAdrian Chadd m_freem(bf->bf_m); 189ba5c15d9SAdrian Chadd bf->bf_m = NULL; 190ba5c15d9SAdrian Chadd } 191ba5c15d9SAdrian Chadd if (bf->bf_node != NULL) { 192ba5c15d9SAdrian Chadd ieee80211_free_node(bf->bf_node); 193ba5c15d9SAdrian Chadd bf->bf_node = NULL; 194ba5c15d9SAdrian Chadd } 195ba5c15d9SAdrian Chadd 196ba5c15d9SAdrian Chadd /* 197ba5c15d9SAdrian Chadd * NB: the beacon data buffer must be 32-bit aligned; 198ba5c15d9SAdrian Chadd * we assume the mbuf routines will return us something 199ba5c15d9SAdrian Chadd * with this alignment (perhaps should assert). 200ba5c15d9SAdrian Chadd */ 201ba5c15d9SAdrian Chadd m = ieee80211_beacon_alloc(ni, &avp->av_boff); 202ba5c15d9SAdrian Chadd if (m == NULL) { 203ba5c15d9SAdrian Chadd device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 204ba5c15d9SAdrian Chadd sc->sc_stats.ast_be_nombuf++; 205ba5c15d9SAdrian Chadd return ENOMEM; 206ba5c15d9SAdrian Chadd } 207ba5c15d9SAdrian Chadd error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 208ba5c15d9SAdrian Chadd bf->bf_segs, &bf->bf_nseg, 209ba5c15d9SAdrian Chadd BUS_DMA_NOWAIT); 210ba5c15d9SAdrian Chadd if (error != 0) { 211ba5c15d9SAdrian Chadd device_printf(sc->sc_dev, 212ba5c15d9SAdrian Chadd "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 213ba5c15d9SAdrian Chadd __func__, error); 214ba5c15d9SAdrian Chadd m_freem(m); 215ba5c15d9SAdrian Chadd return error; 216ba5c15d9SAdrian Chadd } 217ba5c15d9SAdrian Chadd 218ba5c15d9SAdrian Chadd /* 219ba5c15d9SAdrian Chadd * Calculate a TSF adjustment factor required for staggered 220ba5c15d9SAdrian Chadd * beacons. Note that we assume the format of the beacon 221ba5c15d9SAdrian Chadd * frame leaves the tstamp field immediately following the 222ba5c15d9SAdrian Chadd * header. 223ba5c15d9SAdrian Chadd */ 224ba5c15d9SAdrian Chadd if (sc->sc_stagbeacons && avp->av_bslot > 0) { 225ba5c15d9SAdrian Chadd uint64_t tsfadjust; 226ba5c15d9SAdrian Chadd struct ieee80211_frame *wh; 227ba5c15d9SAdrian Chadd 228ba5c15d9SAdrian Chadd /* 229ba5c15d9SAdrian Chadd * The beacon interval is in TU's; the TSF is in usecs. 230ba5c15d9SAdrian Chadd * We figure out how many TU's to add to align the timestamp 231ba5c15d9SAdrian Chadd * then convert to TSF units and handle byte swapping before 232ba5c15d9SAdrian Chadd * inserting it in the frame. The hardware will then add this 233ba5c15d9SAdrian Chadd * each time a beacon frame is sent. Note that we align vap's 234ba5c15d9SAdrian Chadd * 1..N and leave vap 0 untouched. This means vap 0 has a 235ba5c15d9SAdrian Chadd * timestamp in one beacon interval while the others get a 236ba5c15d9SAdrian Chadd * timstamp aligned to the next interval. 237ba5c15d9SAdrian Chadd */ 238ba5c15d9SAdrian Chadd tsfadjust = ni->ni_intval * 239ba5c15d9SAdrian Chadd (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 240ba5c15d9SAdrian Chadd tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 241ba5c15d9SAdrian Chadd 242ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON, 243ba5c15d9SAdrian Chadd "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 244ba5c15d9SAdrian Chadd __func__, sc->sc_stagbeacons ? "stagger" : "burst", 245ba5c15d9SAdrian Chadd avp->av_bslot, ni->ni_intval, 246ba5c15d9SAdrian Chadd (long long unsigned) le64toh(tsfadjust)); 247ba5c15d9SAdrian Chadd 248ba5c15d9SAdrian Chadd wh = mtod(m, struct ieee80211_frame *); 249ba5c15d9SAdrian Chadd memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 250ba5c15d9SAdrian Chadd } 251ba5c15d9SAdrian Chadd bf->bf_m = m; 252ba5c15d9SAdrian Chadd bf->bf_node = ieee80211_ref_node(ni); 253ba5c15d9SAdrian Chadd 254ba5c15d9SAdrian Chadd return 0; 255ba5c15d9SAdrian Chadd } 256ba5c15d9SAdrian Chadd 257ba5c15d9SAdrian Chadd /* 258ba5c15d9SAdrian Chadd * Setup the beacon frame for transmit. 259ba5c15d9SAdrian Chadd */ 260ba5c15d9SAdrian Chadd static void 261ba5c15d9SAdrian Chadd ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 262ba5c15d9SAdrian Chadd { 263ba5c15d9SAdrian Chadd #define USE_SHPREAMBLE(_ic) \ 264ba5c15d9SAdrian Chadd (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 265ba5c15d9SAdrian Chadd == IEEE80211_F_SHPREAMBLE) 266ba5c15d9SAdrian Chadd struct ieee80211_node *ni = bf->bf_node; 267ba5c15d9SAdrian Chadd struct ieee80211com *ic = ni->ni_ic; 268ba5c15d9SAdrian Chadd struct mbuf *m = bf->bf_m; 269ba5c15d9SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 270ba5c15d9SAdrian Chadd struct ath_desc *ds; 271ba5c15d9SAdrian Chadd int flags, antenna; 272ba5c15d9SAdrian Chadd const HAL_RATE_TABLE *rt; 273ba5c15d9SAdrian Chadd u_int8_t rix, rate; 27446634305SAdrian Chadd HAL_DMA_ADDR bufAddrList[4]; 27546634305SAdrian Chadd uint32_t segLenList[4]; 276*e1252ce1SAdrian Chadd HAL_11N_RATE_SERIES rc[4]; 277ba5c15d9SAdrian Chadd 278ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 279ba5c15d9SAdrian Chadd __func__, m, m->m_len); 280ba5c15d9SAdrian Chadd 281ba5c15d9SAdrian Chadd /* setup descriptors */ 282ba5c15d9SAdrian Chadd ds = bf->bf_desc; 283ba5c15d9SAdrian Chadd bf->bf_last = bf; 284ba5c15d9SAdrian Chadd bf->bf_lastds = ds; 285ba5c15d9SAdrian Chadd 286ba5c15d9SAdrian Chadd flags = HAL_TXDESC_NOACK; 287ba5c15d9SAdrian Chadd if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 288bb069955SAdrian Chadd /* self-linked descriptor */ 289bb069955SAdrian Chadd ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr); 290ba5c15d9SAdrian Chadd flags |= HAL_TXDESC_VEOL; 291ba5c15d9SAdrian Chadd /* 292ba5c15d9SAdrian Chadd * Let hardware handle antenna switching. 293ba5c15d9SAdrian Chadd */ 294ba5c15d9SAdrian Chadd antenna = sc->sc_txantenna; 295ba5c15d9SAdrian Chadd } else { 296bb069955SAdrian Chadd ath_hal_settxdesclink(sc->sc_ah, ds, 0); 297ba5c15d9SAdrian Chadd /* 298ba5c15d9SAdrian Chadd * Switch antenna every 4 beacons. 299ba5c15d9SAdrian Chadd * XXX assumes two antenna 300ba5c15d9SAdrian Chadd */ 301ba5c15d9SAdrian Chadd if (sc->sc_txantenna != 0) 302ba5c15d9SAdrian Chadd antenna = sc->sc_txantenna; 303ba5c15d9SAdrian Chadd else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 304ba5c15d9SAdrian Chadd antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 305ba5c15d9SAdrian Chadd else 306ba5c15d9SAdrian Chadd antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 307ba5c15d9SAdrian Chadd } 308ba5c15d9SAdrian Chadd 309ba5c15d9SAdrian Chadd KASSERT(bf->bf_nseg == 1, 310ba5c15d9SAdrian Chadd ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 31146634305SAdrian Chadd 312ba5c15d9SAdrian Chadd /* 313ba5c15d9SAdrian Chadd * Calculate rate code. 314ba5c15d9SAdrian Chadd * XXX everything at min xmit rate 315ba5c15d9SAdrian Chadd */ 316ba5c15d9SAdrian Chadd rix = 0; 317ba5c15d9SAdrian Chadd rt = sc->sc_currates; 318ba5c15d9SAdrian Chadd rate = rt->info[rix].rateCode; 319ba5c15d9SAdrian Chadd if (USE_SHPREAMBLE(ic)) 320ba5c15d9SAdrian Chadd rate |= rt->info[rix].shortPreamble; 321ba5c15d9SAdrian Chadd ath_hal_setuptxdesc(ah, ds 322ba5c15d9SAdrian Chadd , m->m_len + IEEE80211_CRC_LEN /* frame length */ 323ba5c15d9SAdrian Chadd , sizeof(struct ieee80211_frame)/* header length */ 324ba5c15d9SAdrian Chadd , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 325ba5c15d9SAdrian Chadd , ni->ni_txpower /* txpower XXX */ 326ba5c15d9SAdrian Chadd , rate, 1 /* series 0 rate/tries */ 327ba5c15d9SAdrian Chadd , HAL_TXKEYIX_INVALID /* no encryption */ 328ba5c15d9SAdrian Chadd , antenna /* antenna mode */ 329ba5c15d9SAdrian Chadd , flags /* no ack, veol for beacons */ 330ba5c15d9SAdrian Chadd , 0 /* rts/cts rate */ 331ba5c15d9SAdrian Chadd , 0 /* rts/cts duration */ 332ba5c15d9SAdrian Chadd ); 333*e1252ce1SAdrian Chadd 334*e1252ce1SAdrian Chadd /* 335*e1252ce1SAdrian Chadd * The EDMA HAL currently assumes that _all_ rate control 336*e1252ce1SAdrian Chadd * settings are done in ath_hal_set11nratescenario(), rather 337*e1252ce1SAdrian Chadd * than in ath_hal_setuptxdesc(). 338*e1252ce1SAdrian Chadd */ 339*e1252ce1SAdrian Chadd if (sc->sc_isedma) { 340*e1252ce1SAdrian Chadd memset(&rc, 0, sizeof(rc)); 341*e1252ce1SAdrian Chadd 342*e1252ce1SAdrian Chadd rc[0].ChSel = sc->sc_txchainmask; 343*e1252ce1SAdrian Chadd rc[0].Tries = 1; 344*e1252ce1SAdrian Chadd rc[0].Rate = rt->info[rix].rateCode; 345*e1252ce1SAdrian Chadd rc[0].RateIndex = rix; 346*e1252ce1SAdrian Chadd rc[0].tx_power_cap = 0x3f; 347*e1252ce1SAdrian Chadd rc[0].PktDuration = 348*e1252ce1SAdrian Chadd ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4), 349*e1252ce1SAdrian Chadd rix, 0); 350*e1252ce1SAdrian Chadd ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags); 351*e1252ce1SAdrian Chadd } 352*e1252ce1SAdrian Chadd 353ba5c15d9SAdrian Chadd /* NB: beacon's BufLen must be a multiple of 4 bytes */ 35446634305SAdrian Chadd segLenList[0] = roundup(m->m_len, 4); 35546634305SAdrian Chadd segLenList[1] = segLenList[2] = segLenList[3] = 0; 35646634305SAdrian Chadd bufAddrList[0] = bf->bf_segs[0].ds_addr; 35746634305SAdrian Chadd bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0; 358ba5c15d9SAdrian Chadd ath_hal_filltxdesc(ah, ds 35946634305SAdrian Chadd , bufAddrList 36046634305SAdrian Chadd , segLenList 36146634305SAdrian Chadd , 0 /* XXX desc id */ 36246634305SAdrian Chadd , sc->sc_bhalq /* hardware TXQ */ 363ba5c15d9SAdrian Chadd , AH_TRUE /* first segment */ 364ba5c15d9SAdrian Chadd , AH_TRUE /* last segment */ 365ba5c15d9SAdrian Chadd , ds /* first descriptor */ 366ba5c15d9SAdrian Chadd ); 367ba5c15d9SAdrian Chadd #if 0 368ba5c15d9SAdrian Chadd ath_desc_swap(ds); 369ba5c15d9SAdrian Chadd #endif 370ba5c15d9SAdrian Chadd #undef USE_SHPREAMBLE 371ba5c15d9SAdrian Chadd } 372ba5c15d9SAdrian Chadd 373ba5c15d9SAdrian Chadd void 374ba5c15d9SAdrian Chadd ath_beacon_update(struct ieee80211vap *vap, int item) 375ba5c15d9SAdrian Chadd { 376ba5c15d9SAdrian Chadd struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 377ba5c15d9SAdrian Chadd 378ba5c15d9SAdrian Chadd setbit(bo->bo_flags, item); 379ba5c15d9SAdrian Chadd } 380ba5c15d9SAdrian Chadd 381ba5c15d9SAdrian Chadd /* 382ba5c15d9SAdrian Chadd * Transmit a beacon frame at SWBA. Dynamic updates to the 383ba5c15d9SAdrian Chadd * frame contents are done as needed and the slot time is 384ba5c15d9SAdrian Chadd * also adjusted based on current state. 385ba5c15d9SAdrian Chadd */ 386ba5c15d9SAdrian Chadd void 387ba5c15d9SAdrian Chadd ath_beacon_proc(void *arg, int pending) 388ba5c15d9SAdrian Chadd { 389ba5c15d9SAdrian Chadd struct ath_softc *sc = arg; 390ba5c15d9SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 391ba5c15d9SAdrian Chadd struct ieee80211vap *vap; 392ba5c15d9SAdrian Chadd struct ath_buf *bf; 393ba5c15d9SAdrian Chadd int slot, otherant; 394ba5c15d9SAdrian Chadd uint32_t bfaddr; 395ba5c15d9SAdrian Chadd 396ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 397ba5c15d9SAdrian Chadd __func__, pending); 398ba5c15d9SAdrian Chadd /* 399ba5c15d9SAdrian Chadd * Check if the previous beacon has gone out. If 400ba5c15d9SAdrian Chadd * not don't try to post another, skip this period 401ba5c15d9SAdrian Chadd * and wait for the next. Missed beacons indicate 402ba5c15d9SAdrian Chadd * a problem and should not occur. If we miss too 403ba5c15d9SAdrian Chadd * many consecutive beacons reset the device. 404ba5c15d9SAdrian Chadd */ 405ba5c15d9SAdrian Chadd if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 406ba5c15d9SAdrian Chadd sc->sc_bmisscount++; 407ba5c15d9SAdrian Chadd sc->sc_stats.ast_be_missed++; 408ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON, 409ba5c15d9SAdrian Chadd "%s: missed %u consecutive beacons\n", 410ba5c15d9SAdrian Chadd __func__, sc->sc_bmisscount); 411ba5c15d9SAdrian Chadd if (sc->sc_bmisscount >= ath_bstuck_threshold) 412ba5c15d9SAdrian Chadd taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 413ba5c15d9SAdrian Chadd return; 414ba5c15d9SAdrian Chadd } 415ba5c15d9SAdrian Chadd if (sc->sc_bmisscount != 0) { 416ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON, 417ba5c15d9SAdrian Chadd "%s: resume beacon xmit after %u misses\n", 418ba5c15d9SAdrian Chadd __func__, sc->sc_bmisscount); 419ba5c15d9SAdrian Chadd sc->sc_bmisscount = 0; 420ba5c15d9SAdrian Chadd } 421ba5c15d9SAdrian Chadd 422ba5c15d9SAdrian Chadd if (sc->sc_stagbeacons) { /* staggered beacons */ 423ba5c15d9SAdrian Chadd struct ieee80211com *ic = sc->sc_ifp->if_l2com; 424ba5c15d9SAdrian Chadd uint32_t tsftu; 425ba5c15d9SAdrian Chadd 426ba5c15d9SAdrian Chadd tsftu = ath_hal_gettsf32(ah) >> 10; 427ba5c15d9SAdrian Chadd /* XXX lintval */ 428ba5c15d9SAdrian Chadd slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 429ba5c15d9SAdrian Chadd vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 430ba5c15d9SAdrian Chadd bfaddr = 0; 431ba5c15d9SAdrian Chadd if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 432ba5c15d9SAdrian Chadd bf = ath_beacon_generate(sc, vap); 433ba5c15d9SAdrian Chadd if (bf != NULL) 434ba5c15d9SAdrian Chadd bfaddr = bf->bf_daddr; 435ba5c15d9SAdrian Chadd } 436ba5c15d9SAdrian Chadd } else { /* burst'd beacons */ 437ba5c15d9SAdrian Chadd uint32_t *bflink = &bfaddr; 438ba5c15d9SAdrian Chadd 439ba5c15d9SAdrian Chadd for (slot = 0; slot < ATH_BCBUF; slot++) { 440ba5c15d9SAdrian Chadd vap = sc->sc_bslot[slot]; 441ba5c15d9SAdrian Chadd if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 442ba5c15d9SAdrian Chadd bf = ath_beacon_generate(sc, vap); 443ba5c15d9SAdrian Chadd if (bf != NULL) { 444bb069955SAdrian Chadd /* XXX should do this using the ds */ 445ba5c15d9SAdrian Chadd *bflink = bf->bf_daddr; 446bb069955SAdrian Chadd ath_hal_gettxdesclinkptr(sc->sc_ah, 447bb069955SAdrian Chadd bf->bf_desc, &bflink); 448ba5c15d9SAdrian Chadd } 449ba5c15d9SAdrian Chadd } 450ba5c15d9SAdrian Chadd } 451ba5c15d9SAdrian Chadd *bflink = 0; /* terminate list */ 452ba5c15d9SAdrian Chadd } 453ba5c15d9SAdrian Chadd 454ba5c15d9SAdrian Chadd /* 455ba5c15d9SAdrian Chadd * Handle slot time change when a non-ERP station joins/leaves 456ba5c15d9SAdrian Chadd * an 11g network. The 802.11 layer notifies us via callback, 457ba5c15d9SAdrian Chadd * we mark updateslot, then wait one beacon before effecting 458ba5c15d9SAdrian Chadd * the change. This gives associated stations at least one 459ba5c15d9SAdrian Chadd * beacon interval to note the state change. 460ba5c15d9SAdrian Chadd */ 461ba5c15d9SAdrian Chadd /* XXX locking */ 462ba5c15d9SAdrian Chadd if (sc->sc_updateslot == UPDATE) { 463ba5c15d9SAdrian Chadd sc->sc_updateslot = COMMIT; /* commit next beacon */ 464ba5c15d9SAdrian Chadd sc->sc_slotupdate = slot; 465ba5c15d9SAdrian Chadd } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 466ba5c15d9SAdrian Chadd ath_setslottime(sc); /* commit change to h/w */ 467ba5c15d9SAdrian Chadd 468ba5c15d9SAdrian Chadd /* 469ba5c15d9SAdrian Chadd * Check recent per-antenna transmit statistics and flip 470ba5c15d9SAdrian Chadd * the default antenna if noticeably more frames went out 471ba5c15d9SAdrian Chadd * on the non-default antenna. 472ba5c15d9SAdrian Chadd * XXX assumes 2 anntenae 473ba5c15d9SAdrian Chadd */ 474ba5c15d9SAdrian Chadd if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 475ba5c15d9SAdrian Chadd otherant = sc->sc_defant & 1 ? 2 : 1; 476ba5c15d9SAdrian Chadd if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 477ba5c15d9SAdrian Chadd ath_setdefantenna(sc, otherant); 478ba5c15d9SAdrian Chadd sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 479ba5c15d9SAdrian Chadd } 480ba5c15d9SAdrian Chadd 481ba5c15d9SAdrian Chadd if (bfaddr != 0) { 482ba5c15d9SAdrian Chadd /* 483ba5c15d9SAdrian Chadd * Stop any current dma and put the new frame on the queue. 484ba5c15d9SAdrian Chadd * This should never fail since we check above that no frames 485ba5c15d9SAdrian Chadd * are still pending on the queue. 486ba5c15d9SAdrian Chadd */ 487*e1252ce1SAdrian Chadd if (! sc->sc_isedma) { 488ba5c15d9SAdrian Chadd if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 489ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_ANY, 490ba5c15d9SAdrian Chadd "%s: beacon queue %u did not stop?\n", 491ba5c15d9SAdrian Chadd __func__, sc->sc_bhalq); 492ba5c15d9SAdrian Chadd } 493*e1252ce1SAdrian Chadd } 494ba5c15d9SAdrian Chadd /* NB: cabq traffic should already be queued and primed */ 495*e1252ce1SAdrian Chadd 496ba5c15d9SAdrian Chadd ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 497ba5c15d9SAdrian Chadd ath_hal_txstart(ah, sc->sc_bhalq); 498ba5c15d9SAdrian Chadd 499ba5c15d9SAdrian Chadd sc->sc_stats.ast_be_xmit++; 500ba5c15d9SAdrian Chadd } 501ba5c15d9SAdrian Chadd } 502ba5c15d9SAdrian Chadd 503ba5c15d9SAdrian Chadd struct ath_buf * 504ba5c15d9SAdrian Chadd ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 505ba5c15d9SAdrian Chadd { 506ba5c15d9SAdrian Chadd struct ath_vap *avp = ATH_VAP(vap); 507ba5c15d9SAdrian Chadd struct ath_txq *cabq = sc->sc_cabq; 508ba5c15d9SAdrian Chadd struct ath_buf *bf; 509ba5c15d9SAdrian Chadd struct mbuf *m; 510ba5c15d9SAdrian Chadd int nmcastq, error; 511ba5c15d9SAdrian Chadd 512ba5c15d9SAdrian Chadd KASSERT(vap->iv_state >= IEEE80211_S_RUN, 513ba5c15d9SAdrian Chadd ("not running, state %d", vap->iv_state)); 514ba5c15d9SAdrian Chadd KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 515ba5c15d9SAdrian Chadd 516ba5c15d9SAdrian Chadd /* 517ba5c15d9SAdrian Chadd * Update dynamic beacon contents. If this returns 518ba5c15d9SAdrian Chadd * non-zero then we need to remap the memory because 519ba5c15d9SAdrian Chadd * the beacon frame changed size (probably because 520ba5c15d9SAdrian Chadd * of the TIM bitmap). 521ba5c15d9SAdrian Chadd */ 522ba5c15d9SAdrian Chadd bf = avp->av_bcbuf; 523ba5c15d9SAdrian Chadd m = bf->bf_m; 524ba5c15d9SAdrian Chadd /* XXX lock mcastq? */ 525ba5c15d9SAdrian Chadd nmcastq = avp->av_mcastq.axq_depth; 526ba5c15d9SAdrian Chadd 527ba5c15d9SAdrian Chadd if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 528ba5c15d9SAdrian Chadd /* XXX too conservative? */ 529ba5c15d9SAdrian Chadd bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 530ba5c15d9SAdrian Chadd error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 531ba5c15d9SAdrian Chadd bf->bf_segs, &bf->bf_nseg, 532ba5c15d9SAdrian Chadd BUS_DMA_NOWAIT); 533ba5c15d9SAdrian Chadd if (error != 0) { 534ba5c15d9SAdrian Chadd if_printf(vap->iv_ifp, 535ba5c15d9SAdrian Chadd "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 536ba5c15d9SAdrian Chadd __func__, error); 537ba5c15d9SAdrian Chadd return NULL; 538ba5c15d9SAdrian Chadd } 539ba5c15d9SAdrian Chadd } 540ba5c15d9SAdrian Chadd if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 541ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON, 542ba5c15d9SAdrian Chadd "%s: cabq did not drain, mcastq %u cabq %u\n", 543ba5c15d9SAdrian Chadd __func__, nmcastq, cabq->axq_depth); 544ba5c15d9SAdrian Chadd sc->sc_stats.ast_cabq_busy++; 545ba5c15d9SAdrian Chadd if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 546ba5c15d9SAdrian Chadd /* 547ba5c15d9SAdrian Chadd * CABQ traffic from a previous vap is still pending. 548ba5c15d9SAdrian Chadd * We must drain the q before this beacon frame goes 549ba5c15d9SAdrian Chadd * out as otherwise this vap's stations will get cab 550ba5c15d9SAdrian Chadd * frames from a different vap. 551ba5c15d9SAdrian Chadd * XXX could be slow causing us to miss DBA 552ba5c15d9SAdrian Chadd */ 553ba5c15d9SAdrian Chadd ath_tx_draintxq(sc, cabq); 554ba5c15d9SAdrian Chadd } 555ba5c15d9SAdrian Chadd } 556ba5c15d9SAdrian Chadd ath_beacon_setup(sc, bf); 557ba5c15d9SAdrian Chadd bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 558ba5c15d9SAdrian Chadd 559ba5c15d9SAdrian Chadd /* 560ba5c15d9SAdrian Chadd * Enable the CAB queue before the beacon queue to 561ba5c15d9SAdrian Chadd * insure cab frames are triggered by this beacon. 562ba5c15d9SAdrian Chadd */ 563ba5c15d9SAdrian Chadd if (avp->av_boff.bo_tim[4] & 1) { 564ba5c15d9SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 565ba5c15d9SAdrian Chadd 566ba5c15d9SAdrian Chadd /* NB: only at DTIM */ 567ba5c15d9SAdrian Chadd ATH_TXQ_LOCK(cabq); 568ba5c15d9SAdrian Chadd ATH_TXQ_LOCK(&avp->av_mcastq); 569ba5c15d9SAdrian Chadd if (nmcastq) { 570ba5c15d9SAdrian Chadd struct ath_buf *bfm; 571ba5c15d9SAdrian Chadd 572ba5c15d9SAdrian Chadd /* 573ba5c15d9SAdrian Chadd * Move frames from the s/w mcast q to the h/w cab q. 574ba5c15d9SAdrian Chadd * XXX MORE_DATA bit 575ba5c15d9SAdrian Chadd */ 576ba5c15d9SAdrian Chadd bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q); 577ba5c15d9SAdrian Chadd if (cabq->axq_link != NULL) { 578ba5c15d9SAdrian Chadd *cabq->axq_link = bfm->bf_daddr; 579ba5c15d9SAdrian Chadd } else 580ba5c15d9SAdrian Chadd ath_hal_puttxbuf(ah, cabq->axq_qnum, 581ba5c15d9SAdrian Chadd bfm->bf_daddr); 582ba5c15d9SAdrian Chadd ath_txqmove(cabq, &avp->av_mcastq); 583ba5c15d9SAdrian Chadd 584ba5c15d9SAdrian Chadd sc->sc_stats.ast_cabq_xmit += nmcastq; 585ba5c15d9SAdrian Chadd } 586ba5c15d9SAdrian Chadd /* NB: gated by beacon so safe to start here */ 587ba5c15d9SAdrian Chadd if (! TAILQ_EMPTY(&(cabq->axq_q))) 588ba5c15d9SAdrian Chadd ath_hal_txstart(ah, cabq->axq_qnum); 589ba5c15d9SAdrian Chadd ATH_TXQ_UNLOCK(&avp->av_mcastq); 590ba5c15d9SAdrian Chadd ATH_TXQ_UNLOCK(cabq); 591ba5c15d9SAdrian Chadd } 592ba5c15d9SAdrian Chadd return bf; 593ba5c15d9SAdrian Chadd } 594ba5c15d9SAdrian Chadd 595ba5c15d9SAdrian Chadd void 596ba5c15d9SAdrian Chadd ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 597ba5c15d9SAdrian Chadd { 598ba5c15d9SAdrian Chadd struct ath_vap *avp = ATH_VAP(vap); 599ba5c15d9SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 600ba5c15d9SAdrian Chadd struct ath_buf *bf; 601ba5c15d9SAdrian Chadd struct mbuf *m; 602ba5c15d9SAdrian Chadd int error; 603ba5c15d9SAdrian Chadd 604ba5c15d9SAdrian Chadd KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 605ba5c15d9SAdrian Chadd 606ba5c15d9SAdrian Chadd /* 607ba5c15d9SAdrian Chadd * Update dynamic beacon contents. If this returns 608ba5c15d9SAdrian Chadd * non-zero then we need to remap the memory because 609ba5c15d9SAdrian Chadd * the beacon frame changed size (probably because 610ba5c15d9SAdrian Chadd * of the TIM bitmap). 611ba5c15d9SAdrian Chadd */ 612ba5c15d9SAdrian Chadd bf = avp->av_bcbuf; 613ba5c15d9SAdrian Chadd m = bf->bf_m; 614ba5c15d9SAdrian Chadd if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 615ba5c15d9SAdrian Chadd /* XXX too conservative? */ 616ba5c15d9SAdrian Chadd bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 617ba5c15d9SAdrian Chadd error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 618ba5c15d9SAdrian Chadd bf->bf_segs, &bf->bf_nseg, 619ba5c15d9SAdrian Chadd BUS_DMA_NOWAIT); 620ba5c15d9SAdrian Chadd if (error != 0) { 621ba5c15d9SAdrian Chadd if_printf(vap->iv_ifp, 622ba5c15d9SAdrian Chadd "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 623ba5c15d9SAdrian Chadd __func__, error); 624ba5c15d9SAdrian Chadd return; 625ba5c15d9SAdrian Chadd } 626ba5c15d9SAdrian Chadd } 627ba5c15d9SAdrian Chadd ath_beacon_setup(sc, bf); 628ba5c15d9SAdrian Chadd bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 629ba5c15d9SAdrian Chadd 630ba5c15d9SAdrian Chadd /* NB: caller is known to have already stopped tx dma */ 631ba5c15d9SAdrian Chadd ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 632ba5c15d9SAdrian Chadd ath_hal_txstart(ah, sc->sc_bhalq); 633ba5c15d9SAdrian Chadd } 634ba5c15d9SAdrian Chadd 635ba5c15d9SAdrian Chadd /* 636ba5c15d9SAdrian Chadd * Reclaim beacon resources and return buffer to the pool. 637ba5c15d9SAdrian Chadd */ 638ba5c15d9SAdrian Chadd void 639ba5c15d9SAdrian Chadd ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 640ba5c15d9SAdrian Chadd { 641ba5c15d9SAdrian Chadd 642ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 643ba5c15d9SAdrian Chadd __func__, bf, bf->bf_m, bf->bf_node); 644ba5c15d9SAdrian Chadd if (bf->bf_m != NULL) { 645ba5c15d9SAdrian Chadd bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 646ba5c15d9SAdrian Chadd m_freem(bf->bf_m); 647ba5c15d9SAdrian Chadd bf->bf_m = NULL; 648ba5c15d9SAdrian Chadd } 649ba5c15d9SAdrian Chadd if (bf->bf_node != NULL) { 650ba5c15d9SAdrian Chadd ieee80211_free_node(bf->bf_node); 651ba5c15d9SAdrian Chadd bf->bf_node = NULL; 652ba5c15d9SAdrian Chadd } 653ba5c15d9SAdrian Chadd TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 654ba5c15d9SAdrian Chadd } 655ba5c15d9SAdrian Chadd 656ba5c15d9SAdrian Chadd /* 657ba5c15d9SAdrian Chadd * Reclaim beacon resources. 658ba5c15d9SAdrian Chadd */ 659ba5c15d9SAdrian Chadd void 660ba5c15d9SAdrian Chadd ath_beacon_free(struct ath_softc *sc) 661ba5c15d9SAdrian Chadd { 662ba5c15d9SAdrian Chadd struct ath_buf *bf; 663ba5c15d9SAdrian Chadd 664ba5c15d9SAdrian Chadd TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 665ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_NODE, 666ba5c15d9SAdrian Chadd "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 667ba5c15d9SAdrian Chadd __func__, bf, bf->bf_m, bf->bf_node); 668ba5c15d9SAdrian Chadd if (bf->bf_m != NULL) { 669ba5c15d9SAdrian Chadd bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 670ba5c15d9SAdrian Chadd m_freem(bf->bf_m); 671ba5c15d9SAdrian Chadd bf->bf_m = NULL; 672ba5c15d9SAdrian Chadd } 673ba5c15d9SAdrian Chadd if (bf->bf_node != NULL) { 674ba5c15d9SAdrian Chadd ieee80211_free_node(bf->bf_node); 675ba5c15d9SAdrian Chadd bf->bf_node = NULL; 676ba5c15d9SAdrian Chadd } 677ba5c15d9SAdrian Chadd } 678ba5c15d9SAdrian Chadd } 679ba5c15d9SAdrian Chadd 680ba5c15d9SAdrian Chadd /* 681ba5c15d9SAdrian Chadd * Configure the beacon and sleep timers. 682ba5c15d9SAdrian Chadd * 683ba5c15d9SAdrian Chadd * When operating as an AP this resets the TSF and sets 684ba5c15d9SAdrian Chadd * up the hardware to notify us when we need to issue beacons. 685ba5c15d9SAdrian Chadd * 686ba5c15d9SAdrian Chadd * When operating in station mode this sets up the beacon 687ba5c15d9SAdrian Chadd * timers according to the timestamp of the last received 688ba5c15d9SAdrian Chadd * beacon and the current TSF, configures PCF and DTIM 689ba5c15d9SAdrian Chadd * handling, programs the sleep registers so the hardware 690ba5c15d9SAdrian Chadd * will wakeup in time to receive beacons, and configures 691ba5c15d9SAdrian Chadd * the beacon miss handling so we'll receive a BMISS 692ba5c15d9SAdrian Chadd * interrupt when we stop seeing beacons from the AP 693ba5c15d9SAdrian Chadd * we've associated with. 694ba5c15d9SAdrian Chadd */ 695ba5c15d9SAdrian Chadd void 696ba5c15d9SAdrian Chadd ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 697ba5c15d9SAdrian Chadd { 698ba5c15d9SAdrian Chadd #define TSF_TO_TU(_h,_l) \ 699ba5c15d9SAdrian Chadd ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 700ba5c15d9SAdrian Chadd #define FUDGE 2 701ba5c15d9SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 702ba5c15d9SAdrian Chadd struct ieee80211com *ic = sc->sc_ifp->if_l2com; 703ba5c15d9SAdrian Chadd struct ieee80211_node *ni; 704ba5c15d9SAdrian Chadd u_int32_t nexttbtt, intval, tsftu; 705*e1252ce1SAdrian Chadd u_int32_t nexttbtt_u8, intval_u8; 706ba5c15d9SAdrian Chadd u_int64_t tsf; 707ba5c15d9SAdrian Chadd 708ba5c15d9SAdrian Chadd if (vap == NULL) 709ba5c15d9SAdrian Chadd vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 710ba5c15d9SAdrian Chadd ni = ieee80211_ref_node(vap->iv_bss); 711ba5c15d9SAdrian Chadd 712ba5c15d9SAdrian Chadd /* extract tstamp from last beacon and convert to TU */ 713ba5c15d9SAdrian Chadd nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 714ba5c15d9SAdrian Chadd LE_READ_4(ni->ni_tstamp.data)); 715ba5c15d9SAdrian Chadd if (ic->ic_opmode == IEEE80211_M_HOSTAP || 716ba5c15d9SAdrian Chadd ic->ic_opmode == IEEE80211_M_MBSS) { 717ba5c15d9SAdrian Chadd /* 718ba5c15d9SAdrian Chadd * For multi-bss ap/mesh support beacons are either staggered 719ba5c15d9SAdrian Chadd * evenly over N slots or burst together. For the former 720ba5c15d9SAdrian Chadd * arrange for the SWBA to be delivered for each slot. 721ba5c15d9SAdrian Chadd * Slots that are not occupied will generate nothing. 722ba5c15d9SAdrian Chadd */ 723ba5c15d9SAdrian Chadd /* NB: the beacon interval is kept internally in TU's */ 724ba5c15d9SAdrian Chadd intval = ni->ni_intval & HAL_BEACON_PERIOD; 725ba5c15d9SAdrian Chadd if (sc->sc_stagbeacons) 726ba5c15d9SAdrian Chadd intval /= ATH_BCBUF; 727ba5c15d9SAdrian Chadd } else { 728ba5c15d9SAdrian Chadd /* NB: the beacon interval is kept internally in TU's */ 729ba5c15d9SAdrian Chadd intval = ni->ni_intval & HAL_BEACON_PERIOD; 730ba5c15d9SAdrian Chadd } 731ba5c15d9SAdrian Chadd if (nexttbtt == 0) /* e.g. for ap mode */ 732ba5c15d9SAdrian Chadd nexttbtt = intval; 733ba5c15d9SAdrian Chadd else if (intval) /* NB: can be 0 for monitor mode */ 734ba5c15d9SAdrian Chadd nexttbtt = roundup(nexttbtt, intval); 735ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 736ba5c15d9SAdrian Chadd __func__, nexttbtt, intval, ni->ni_intval); 737ba5c15d9SAdrian Chadd if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 738ba5c15d9SAdrian Chadd HAL_BEACON_STATE bs; 739ba5c15d9SAdrian Chadd int dtimperiod, dtimcount; 740ba5c15d9SAdrian Chadd int cfpperiod, cfpcount; 741ba5c15d9SAdrian Chadd 742ba5c15d9SAdrian Chadd /* 743ba5c15d9SAdrian Chadd * Setup dtim and cfp parameters according to 744ba5c15d9SAdrian Chadd * last beacon we received (which may be none). 745ba5c15d9SAdrian Chadd */ 746ba5c15d9SAdrian Chadd dtimperiod = ni->ni_dtim_period; 747ba5c15d9SAdrian Chadd if (dtimperiod <= 0) /* NB: 0 if not known */ 748ba5c15d9SAdrian Chadd dtimperiod = 1; 749ba5c15d9SAdrian Chadd dtimcount = ni->ni_dtim_count; 750ba5c15d9SAdrian Chadd if (dtimcount >= dtimperiod) /* NB: sanity check */ 751ba5c15d9SAdrian Chadd dtimcount = 0; /* XXX? */ 752ba5c15d9SAdrian Chadd cfpperiod = 1; /* NB: no PCF support yet */ 753ba5c15d9SAdrian Chadd cfpcount = 0; 754ba5c15d9SAdrian Chadd /* 755ba5c15d9SAdrian Chadd * Pull nexttbtt forward to reflect the current 756ba5c15d9SAdrian Chadd * TSF and calculate dtim+cfp state for the result. 757ba5c15d9SAdrian Chadd */ 758ba5c15d9SAdrian Chadd tsf = ath_hal_gettsf64(ah); 759ba5c15d9SAdrian Chadd tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 760ba5c15d9SAdrian Chadd do { 761ba5c15d9SAdrian Chadd nexttbtt += intval; 762ba5c15d9SAdrian Chadd if (--dtimcount < 0) { 763ba5c15d9SAdrian Chadd dtimcount = dtimperiod - 1; 764ba5c15d9SAdrian Chadd if (--cfpcount < 0) 765ba5c15d9SAdrian Chadd cfpcount = cfpperiod - 1; 766ba5c15d9SAdrian Chadd } 767ba5c15d9SAdrian Chadd } while (nexttbtt < tsftu); 768ba5c15d9SAdrian Chadd memset(&bs, 0, sizeof(bs)); 769ba5c15d9SAdrian Chadd bs.bs_intval = intval; 770ba5c15d9SAdrian Chadd bs.bs_nexttbtt = nexttbtt; 771ba5c15d9SAdrian Chadd bs.bs_dtimperiod = dtimperiod*intval; 772ba5c15d9SAdrian Chadd bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 773ba5c15d9SAdrian Chadd bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 774ba5c15d9SAdrian Chadd bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 775ba5c15d9SAdrian Chadd bs.bs_cfpmaxduration = 0; 776ba5c15d9SAdrian Chadd #if 0 777ba5c15d9SAdrian Chadd /* 778ba5c15d9SAdrian Chadd * The 802.11 layer records the offset to the DTIM 779ba5c15d9SAdrian Chadd * bitmap while receiving beacons; use it here to 780ba5c15d9SAdrian Chadd * enable h/w detection of our AID being marked in 781ba5c15d9SAdrian Chadd * the bitmap vector (to indicate frames for us are 782ba5c15d9SAdrian Chadd * pending at the AP). 783ba5c15d9SAdrian Chadd * XXX do DTIM handling in s/w to WAR old h/w bugs 784ba5c15d9SAdrian Chadd * XXX enable based on h/w rev for newer chips 785ba5c15d9SAdrian Chadd */ 786ba5c15d9SAdrian Chadd bs.bs_timoffset = ni->ni_timoff; 787ba5c15d9SAdrian Chadd #endif 788ba5c15d9SAdrian Chadd /* 789ba5c15d9SAdrian Chadd * Calculate the number of consecutive beacons to miss 790ba5c15d9SAdrian Chadd * before taking a BMISS interrupt. 791ba5c15d9SAdrian Chadd * Note that we clamp the result to at most 10 beacons. 792ba5c15d9SAdrian Chadd */ 793ba5c15d9SAdrian Chadd bs.bs_bmissthreshold = vap->iv_bmissthreshold; 794ba5c15d9SAdrian Chadd if (bs.bs_bmissthreshold > 10) 795ba5c15d9SAdrian Chadd bs.bs_bmissthreshold = 10; 796ba5c15d9SAdrian Chadd else if (bs.bs_bmissthreshold <= 0) 797ba5c15d9SAdrian Chadd bs.bs_bmissthreshold = 1; 798ba5c15d9SAdrian Chadd 799ba5c15d9SAdrian Chadd /* 800ba5c15d9SAdrian Chadd * Calculate sleep duration. The configuration is 801ba5c15d9SAdrian Chadd * given in ms. We insure a multiple of the beacon 802ba5c15d9SAdrian Chadd * period is used. Also, if the sleep duration is 803ba5c15d9SAdrian Chadd * greater than the DTIM period then it makes senses 804ba5c15d9SAdrian Chadd * to make it a multiple of that. 805ba5c15d9SAdrian Chadd * 806ba5c15d9SAdrian Chadd * XXX fixed at 100ms 807ba5c15d9SAdrian Chadd */ 808ba5c15d9SAdrian Chadd bs.bs_sleepduration = 809ba5c15d9SAdrian Chadd roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 810ba5c15d9SAdrian Chadd if (bs.bs_sleepduration > bs.bs_dtimperiod) 811ba5c15d9SAdrian Chadd bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 812ba5c15d9SAdrian Chadd 813ba5c15d9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON, 814ba5c15d9SAdrian Chadd "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 815ba5c15d9SAdrian Chadd , __func__ 816ba5c15d9SAdrian Chadd , tsf, tsftu 817ba5c15d9SAdrian Chadd , bs.bs_intval 818ba5c15d9SAdrian Chadd , bs.bs_nexttbtt 819ba5c15d9SAdrian Chadd , bs.bs_dtimperiod 820ba5c15d9SAdrian Chadd , bs.bs_nextdtim 821ba5c15d9SAdrian Chadd , bs.bs_bmissthreshold 822ba5c15d9SAdrian Chadd , bs.bs_sleepduration 823ba5c15d9SAdrian Chadd , bs.bs_cfpperiod 824ba5c15d9SAdrian Chadd , bs.bs_cfpmaxduration 825ba5c15d9SAdrian Chadd , bs.bs_cfpnext 826ba5c15d9SAdrian Chadd , bs.bs_timoffset 827ba5c15d9SAdrian Chadd ); 828ba5c15d9SAdrian Chadd ath_hal_intrset(ah, 0); 829ba5c15d9SAdrian Chadd ath_hal_beacontimers(ah, &bs); 830ba5c15d9SAdrian Chadd sc->sc_imask |= HAL_INT_BMISS; 831ba5c15d9SAdrian Chadd ath_hal_intrset(ah, sc->sc_imask); 832ba5c15d9SAdrian Chadd } else { 833ba5c15d9SAdrian Chadd ath_hal_intrset(ah, 0); 834ba5c15d9SAdrian Chadd if (nexttbtt == intval) 835ba5c15d9SAdrian Chadd intval |= HAL_BEACON_RESET_TSF; 836ba5c15d9SAdrian Chadd if (ic->ic_opmode == IEEE80211_M_IBSS) { 837ba5c15d9SAdrian Chadd /* 838ba5c15d9SAdrian Chadd * In IBSS mode enable the beacon timers but only 839ba5c15d9SAdrian Chadd * enable SWBA interrupts if we need to manually 840ba5c15d9SAdrian Chadd * prepare beacon frames. Otherwise we use a 841ba5c15d9SAdrian Chadd * self-linked tx descriptor and let the hardware 842ba5c15d9SAdrian Chadd * deal with things. 843ba5c15d9SAdrian Chadd */ 844ba5c15d9SAdrian Chadd intval |= HAL_BEACON_ENA; 845ba5c15d9SAdrian Chadd if (!sc->sc_hasveol) 846ba5c15d9SAdrian Chadd sc->sc_imask |= HAL_INT_SWBA; 847ba5c15d9SAdrian Chadd if ((intval & HAL_BEACON_RESET_TSF) == 0) { 848ba5c15d9SAdrian Chadd /* 849ba5c15d9SAdrian Chadd * Pull nexttbtt forward to reflect 850ba5c15d9SAdrian Chadd * the current TSF. 851ba5c15d9SAdrian Chadd */ 852ba5c15d9SAdrian Chadd tsf = ath_hal_gettsf64(ah); 853ba5c15d9SAdrian Chadd tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 854ba5c15d9SAdrian Chadd do { 855ba5c15d9SAdrian Chadd nexttbtt += intval; 856ba5c15d9SAdrian Chadd } while (nexttbtt < tsftu); 857ba5c15d9SAdrian Chadd } 858ba5c15d9SAdrian Chadd ath_beaconq_config(sc); 859ba5c15d9SAdrian Chadd } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 860ba5c15d9SAdrian Chadd ic->ic_opmode == IEEE80211_M_MBSS) { 861ba5c15d9SAdrian Chadd /* 862ba5c15d9SAdrian Chadd * In AP/mesh mode we enable the beacon timers 863ba5c15d9SAdrian Chadd * and SWBA interrupts to prepare beacon frames. 864ba5c15d9SAdrian Chadd */ 865ba5c15d9SAdrian Chadd intval |= HAL_BEACON_ENA; 866ba5c15d9SAdrian Chadd sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 867ba5c15d9SAdrian Chadd ath_beaconq_config(sc); 868ba5c15d9SAdrian Chadd } 869*e1252ce1SAdrian Chadd 870*e1252ce1SAdrian Chadd /* 871*e1252ce1SAdrian Chadd * Now dirty things because for now, the EDMA HAL has 872*e1252ce1SAdrian Chadd * nexttbtt and intval is TU/8. 873*e1252ce1SAdrian Chadd */ 874*e1252ce1SAdrian Chadd if (sc->sc_isedma) { 875*e1252ce1SAdrian Chadd nexttbtt_u8 = (nexttbtt << 3); 876*e1252ce1SAdrian Chadd intval_u8 = (intval << 3); 877*e1252ce1SAdrian Chadd if (intval & HAL_BEACON_ENA) 878*e1252ce1SAdrian Chadd intval_u8 |= HAL_BEACON_ENA; 879*e1252ce1SAdrian Chadd if (intval & HAL_BEACON_RESET_TSF) 880*e1252ce1SAdrian Chadd intval_u8 |= HAL_BEACON_RESET_TSF; 881*e1252ce1SAdrian Chadd ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8); 882*e1252ce1SAdrian Chadd } else 883ba5c15d9SAdrian Chadd ath_hal_beaconinit(ah, nexttbtt, intval); 884ba5c15d9SAdrian Chadd sc->sc_bmisscount = 0; 885ba5c15d9SAdrian Chadd ath_hal_intrset(ah, sc->sc_imask); 886ba5c15d9SAdrian Chadd /* 887ba5c15d9SAdrian Chadd * When using a self-linked beacon descriptor in 888ba5c15d9SAdrian Chadd * ibss mode load it once here. 889ba5c15d9SAdrian Chadd */ 890ba5c15d9SAdrian Chadd if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 891ba5c15d9SAdrian Chadd ath_beacon_start_adhoc(sc, vap); 892ba5c15d9SAdrian Chadd } 893ba5c15d9SAdrian Chadd sc->sc_syncbeacon = 0; 894ba5c15d9SAdrian Chadd ieee80211_free_node(ni); 895ba5c15d9SAdrian Chadd #undef FUDGE 896ba5c15d9SAdrian Chadd #undef TSF_TO_TU 897ba5c15d9SAdrian Chadd } 898