xref: /freebsd/sys/dev/ath/if_ath_beacon.c (revision b6ef0f8ac8983da0777fffffd92fa1713a1b221e)
1ba5c15d9SAdrian Chadd /*-
2ba5c15d9SAdrian Chadd  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3ba5c15d9SAdrian Chadd  * All rights reserved.
4ba5c15d9SAdrian Chadd  *
5ba5c15d9SAdrian Chadd  * Redistribution and use in source and binary forms, with or without
6ba5c15d9SAdrian Chadd  * modification, are permitted provided that the following conditions
7ba5c15d9SAdrian Chadd  * are met:
8ba5c15d9SAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
9ba5c15d9SAdrian Chadd  *    notice, this list of conditions and the following disclaimer,
10ba5c15d9SAdrian Chadd  *    without modification.
11ba5c15d9SAdrian Chadd  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12ba5c15d9SAdrian Chadd  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13ba5c15d9SAdrian Chadd  *    redistribution must be conditioned upon including a substantially
14ba5c15d9SAdrian Chadd  *    similar Disclaimer requirement for further binary redistribution.
15ba5c15d9SAdrian Chadd  *
16ba5c15d9SAdrian Chadd  * NO WARRANTY
17ba5c15d9SAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18ba5c15d9SAdrian Chadd  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19ba5c15d9SAdrian Chadd  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20ba5c15d9SAdrian Chadd  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21ba5c15d9SAdrian Chadd  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22ba5c15d9SAdrian Chadd  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23ba5c15d9SAdrian Chadd  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24ba5c15d9SAdrian Chadd  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25ba5c15d9SAdrian Chadd  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26ba5c15d9SAdrian Chadd  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27ba5c15d9SAdrian Chadd  * THE POSSIBILITY OF SUCH DAMAGES.
28ba5c15d9SAdrian Chadd  */
29ba5c15d9SAdrian Chadd 
30ba5c15d9SAdrian Chadd #include <sys/cdefs.h>
31ba5c15d9SAdrian Chadd __FBSDID("$FreeBSD$");
32ba5c15d9SAdrian Chadd 
33ba5c15d9SAdrian Chadd /*
34ba5c15d9SAdrian Chadd  * Driver for the Atheros Wireless LAN controller.
35ba5c15d9SAdrian Chadd  *
36ba5c15d9SAdrian Chadd  * This software is derived from work of Atsushi Onoe; his contribution
37ba5c15d9SAdrian Chadd  * is greatly appreciated.
38ba5c15d9SAdrian Chadd  */
39ba5c15d9SAdrian Chadd 
40ba5c15d9SAdrian Chadd #include "opt_inet.h"
41ba5c15d9SAdrian Chadd #include "opt_ath.h"
42ba5c15d9SAdrian Chadd /*
43ba5c15d9SAdrian Chadd  * This is needed for register operations which are performed
44ba5c15d9SAdrian Chadd  * by the driver - eg, calls to ath_hal_gettsf32().
45ba5c15d9SAdrian Chadd  *
46ba5c15d9SAdrian Chadd  * It's also required for any AH_DEBUG checks in here, eg the
47ba5c15d9SAdrian Chadd  * module dependencies.
48ba5c15d9SAdrian Chadd  */
49ba5c15d9SAdrian Chadd #include "opt_ah.h"
50ba5c15d9SAdrian Chadd #include "opt_wlan.h"
51ba5c15d9SAdrian Chadd 
52ba5c15d9SAdrian Chadd #include <sys/param.h>
53ba5c15d9SAdrian Chadd #include <sys/systm.h>
54ba5c15d9SAdrian Chadd #include <sys/sysctl.h>
55ba5c15d9SAdrian Chadd #include <sys/mbuf.h>
56ba5c15d9SAdrian Chadd #include <sys/malloc.h>
57ba5c15d9SAdrian Chadd #include <sys/lock.h>
58ba5c15d9SAdrian Chadd #include <sys/mutex.h>
59ba5c15d9SAdrian Chadd #include <sys/kernel.h>
60ba5c15d9SAdrian Chadd #include <sys/socket.h>
61ba5c15d9SAdrian Chadd #include <sys/sockio.h>
62ba5c15d9SAdrian Chadd #include <sys/errno.h>
63ba5c15d9SAdrian Chadd #include <sys/callout.h>
64ba5c15d9SAdrian Chadd #include <sys/bus.h>
65ba5c15d9SAdrian Chadd #include <sys/endian.h>
66ba5c15d9SAdrian Chadd #include <sys/kthread.h>
67ba5c15d9SAdrian Chadd #include <sys/taskqueue.h>
68ba5c15d9SAdrian Chadd #include <sys/priv.h>
69ba5c15d9SAdrian Chadd #include <sys/module.h>
70ba5c15d9SAdrian Chadd #include <sys/ktr.h>
71ba5c15d9SAdrian Chadd #include <sys/smp.h>	/* for mp_ncpus */
72ba5c15d9SAdrian Chadd 
73ba5c15d9SAdrian Chadd #include <machine/bus.h>
74ba5c15d9SAdrian Chadd 
75ba5c15d9SAdrian Chadd #include <net/if.h>
76ba5c15d9SAdrian Chadd #include <net/if_dl.h>
77ba5c15d9SAdrian Chadd #include <net/if_media.h>
78ba5c15d9SAdrian Chadd #include <net/if_types.h>
79ba5c15d9SAdrian Chadd #include <net/if_arp.h>
80ba5c15d9SAdrian Chadd #include <net/ethernet.h>
81ba5c15d9SAdrian Chadd #include <net/if_llc.h>
82ba5c15d9SAdrian Chadd 
83ba5c15d9SAdrian Chadd #include <net80211/ieee80211_var.h>
84ba5c15d9SAdrian Chadd #include <net80211/ieee80211_regdomain.h>
85ba5c15d9SAdrian Chadd #ifdef IEEE80211_SUPPORT_SUPERG
86ba5c15d9SAdrian Chadd #include <net80211/ieee80211_superg.h>
87ba5c15d9SAdrian Chadd #endif
88ba5c15d9SAdrian Chadd 
89ba5c15d9SAdrian Chadd #include <net/bpf.h>
90ba5c15d9SAdrian Chadd 
91ba5c15d9SAdrian Chadd #ifdef INET
92ba5c15d9SAdrian Chadd #include <netinet/in.h>
93ba5c15d9SAdrian Chadd #include <netinet/if_ether.h>
94ba5c15d9SAdrian Chadd #endif
95ba5c15d9SAdrian Chadd 
96ba5c15d9SAdrian Chadd #include <dev/ath/if_athvar.h>
97ba5c15d9SAdrian Chadd 
98ba5c15d9SAdrian Chadd #include <dev/ath/if_ath_debug.h>
99ba5c15d9SAdrian Chadd #include <dev/ath/if_ath_misc.h>
100ba5c15d9SAdrian Chadd #include <dev/ath/if_ath_tx.h>
101ba5c15d9SAdrian Chadd #include <dev/ath/if_ath_beacon.h>
102ba5c15d9SAdrian Chadd 
103ba5c15d9SAdrian Chadd #ifdef ATH_TX99_DIAG
104ba5c15d9SAdrian Chadd #include <dev/ath/ath_tx99/ath_tx99.h>
105ba5c15d9SAdrian Chadd #endif
106ba5c15d9SAdrian Chadd 
107ba5c15d9SAdrian Chadd /*
108ba5c15d9SAdrian Chadd  * Setup a h/w transmit queue for beacons.
109ba5c15d9SAdrian Chadd  */
110ba5c15d9SAdrian Chadd int
111e1252ce1SAdrian Chadd ath_beaconq_setup(struct ath_softc *sc)
112ba5c15d9SAdrian Chadd {
113e1252ce1SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
114ba5c15d9SAdrian Chadd 	HAL_TXQ_INFO qi;
115ba5c15d9SAdrian Chadd 
116ba5c15d9SAdrian Chadd 	memset(&qi, 0, sizeof(qi));
117ba5c15d9SAdrian Chadd 	qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
118ba5c15d9SAdrian Chadd 	qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
119ba5c15d9SAdrian Chadd 	qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
120ba5c15d9SAdrian Chadd 	/* NB: for dynamic turbo, don't enable any other interrupts */
121ba5c15d9SAdrian Chadd 	qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
122e1252ce1SAdrian Chadd 	if (sc->sc_isedma)
123e1252ce1SAdrian Chadd 		qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE |
124e1252ce1SAdrian Chadd 		    HAL_TXQ_TXERRINT_ENABLE;
125e1252ce1SAdrian Chadd 
126ba5c15d9SAdrian Chadd 	return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
127ba5c15d9SAdrian Chadd }
128ba5c15d9SAdrian Chadd 
129ba5c15d9SAdrian Chadd /*
130ba5c15d9SAdrian Chadd  * Setup the transmit queue parameters for the beacon queue.
131ba5c15d9SAdrian Chadd  */
132ba5c15d9SAdrian Chadd int
133ba5c15d9SAdrian Chadd ath_beaconq_config(struct ath_softc *sc)
134ba5c15d9SAdrian Chadd {
135ba5c15d9SAdrian Chadd #define	ATH_EXPONENT_TO_VALUE(v)	((1<<(v))-1)
136ba5c15d9SAdrian Chadd 	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
137ba5c15d9SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
138ba5c15d9SAdrian Chadd 	HAL_TXQ_INFO qi;
139ba5c15d9SAdrian Chadd 
140ba5c15d9SAdrian Chadd 	ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
141ba5c15d9SAdrian Chadd 	if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
142ba5c15d9SAdrian Chadd 	    ic->ic_opmode == IEEE80211_M_MBSS) {
143ba5c15d9SAdrian Chadd 		/*
144ba5c15d9SAdrian Chadd 		 * Always burst out beacon and CAB traffic.
145ba5c15d9SAdrian Chadd 		 */
146ba5c15d9SAdrian Chadd 		qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
147ba5c15d9SAdrian Chadd 		qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
148ba5c15d9SAdrian Chadd 		qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
149ba5c15d9SAdrian Chadd 	} else {
150ba5c15d9SAdrian Chadd 		struct wmeParams *wmep =
151ba5c15d9SAdrian Chadd 			&ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
152ba5c15d9SAdrian Chadd 		/*
153ba5c15d9SAdrian Chadd 		 * Adhoc mode; important thing is to use 2x cwmin.
154ba5c15d9SAdrian Chadd 		 */
155ba5c15d9SAdrian Chadd 		qi.tqi_aifs = wmep->wmep_aifsn;
156ba5c15d9SAdrian Chadd 		qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
157ba5c15d9SAdrian Chadd 		qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
158ba5c15d9SAdrian Chadd 	}
159ba5c15d9SAdrian Chadd 
160ba5c15d9SAdrian Chadd 	if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
161ba5c15d9SAdrian Chadd 		device_printf(sc->sc_dev, "unable to update parameters for "
162ba5c15d9SAdrian Chadd 			"beacon hardware queue!\n");
163ba5c15d9SAdrian Chadd 		return 0;
164ba5c15d9SAdrian Chadd 	} else {
165ba5c15d9SAdrian Chadd 		ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
166ba5c15d9SAdrian Chadd 		return 1;
167ba5c15d9SAdrian Chadd 	}
168ba5c15d9SAdrian Chadd #undef ATH_EXPONENT_TO_VALUE
169ba5c15d9SAdrian Chadd }
170ba5c15d9SAdrian Chadd 
171ba5c15d9SAdrian Chadd /*
172ba5c15d9SAdrian Chadd  * Allocate and setup an initial beacon frame.
173ba5c15d9SAdrian Chadd  */
174ba5c15d9SAdrian Chadd int
175ba5c15d9SAdrian Chadd ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
176ba5c15d9SAdrian Chadd {
177ba5c15d9SAdrian Chadd 	struct ieee80211vap *vap = ni->ni_vap;
178ba5c15d9SAdrian Chadd 	struct ath_vap *avp = ATH_VAP(vap);
179ba5c15d9SAdrian Chadd 	struct ath_buf *bf;
180ba5c15d9SAdrian Chadd 	struct mbuf *m;
181ba5c15d9SAdrian Chadd 	int error;
182ba5c15d9SAdrian Chadd 
183ba5c15d9SAdrian Chadd 	bf = avp->av_bcbuf;
184ba5c15d9SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n",
185ba5c15d9SAdrian Chadd 	    __func__, bf->bf_m, bf->bf_node);
186ba5c15d9SAdrian Chadd 	if (bf->bf_m != NULL) {
187ba5c15d9SAdrian Chadd 		bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
188ba5c15d9SAdrian Chadd 		m_freem(bf->bf_m);
189ba5c15d9SAdrian Chadd 		bf->bf_m = NULL;
190ba5c15d9SAdrian Chadd 	}
191ba5c15d9SAdrian Chadd 	if (bf->bf_node != NULL) {
192ba5c15d9SAdrian Chadd 		ieee80211_free_node(bf->bf_node);
193ba5c15d9SAdrian Chadd 		bf->bf_node = NULL;
194ba5c15d9SAdrian Chadd 	}
195ba5c15d9SAdrian Chadd 
196ba5c15d9SAdrian Chadd 	/*
197ba5c15d9SAdrian Chadd 	 * NB: the beacon data buffer must be 32-bit aligned;
198ba5c15d9SAdrian Chadd 	 * we assume the mbuf routines will return us something
199ba5c15d9SAdrian Chadd 	 * with this alignment (perhaps should assert).
200ba5c15d9SAdrian Chadd 	 */
201ba5c15d9SAdrian Chadd 	m = ieee80211_beacon_alloc(ni, &avp->av_boff);
202ba5c15d9SAdrian Chadd 	if (m == NULL) {
203ba5c15d9SAdrian Chadd 		device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__);
204ba5c15d9SAdrian Chadd 		sc->sc_stats.ast_be_nombuf++;
205ba5c15d9SAdrian Chadd 		return ENOMEM;
206ba5c15d9SAdrian Chadd 	}
207ba5c15d9SAdrian Chadd 	error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
208ba5c15d9SAdrian Chadd 				     bf->bf_segs, &bf->bf_nseg,
209ba5c15d9SAdrian Chadd 				     BUS_DMA_NOWAIT);
210ba5c15d9SAdrian Chadd 	if (error != 0) {
211ba5c15d9SAdrian Chadd 		device_printf(sc->sc_dev,
212ba5c15d9SAdrian Chadd 		    "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n",
213ba5c15d9SAdrian Chadd 		    __func__, error);
214ba5c15d9SAdrian Chadd 		m_freem(m);
215ba5c15d9SAdrian Chadd 		return error;
216ba5c15d9SAdrian Chadd 	}
217ba5c15d9SAdrian Chadd 
218ba5c15d9SAdrian Chadd 	/*
219ba5c15d9SAdrian Chadd 	 * Calculate a TSF adjustment factor required for staggered
220ba5c15d9SAdrian Chadd 	 * beacons.  Note that we assume the format of the beacon
221ba5c15d9SAdrian Chadd 	 * frame leaves the tstamp field immediately following the
222ba5c15d9SAdrian Chadd 	 * header.
223ba5c15d9SAdrian Chadd 	 */
224ba5c15d9SAdrian Chadd 	if (sc->sc_stagbeacons && avp->av_bslot > 0) {
225ba5c15d9SAdrian Chadd 		uint64_t tsfadjust;
226ba5c15d9SAdrian Chadd 		struct ieee80211_frame *wh;
227ba5c15d9SAdrian Chadd 
228ba5c15d9SAdrian Chadd 		/*
229ba5c15d9SAdrian Chadd 		 * The beacon interval is in TU's; the TSF is in usecs.
230ba5c15d9SAdrian Chadd 		 * We figure out how many TU's to add to align the timestamp
231ba5c15d9SAdrian Chadd 		 * then convert to TSF units and handle byte swapping before
232ba5c15d9SAdrian Chadd 		 * inserting it in the frame.  The hardware will then add this
233ba5c15d9SAdrian Chadd 		 * each time a beacon frame is sent.  Note that we align vap's
234ba5c15d9SAdrian Chadd 		 * 1..N and leave vap 0 untouched.  This means vap 0 has a
235ba5c15d9SAdrian Chadd 		 * timestamp in one beacon interval while the others get a
236ba5c15d9SAdrian Chadd 		 * timstamp aligned to the next interval.
237ba5c15d9SAdrian Chadd 		 */
238ba5c15d9SAdrian Chadd 		tsfadjust = ni->ni_intval *
239ba5c15d9SAdrian Chadd 		    (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF;
240ba5c15d9SAdrian Chadd 		tsfadjust = htole64(tsfadjust << 10);	/* TU -> TSF */
241ba5c15d9SAdrian Chadd 
242ba5c15d9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
243ba5c15d9SAdrian Chadd 		    "%s: %s beacons bslot %d intval %u tsfadjust %llu\n",
244ba5c15d9SAdrian Chadd 		    __func__, sc->sc_stagbeacons ? "stagger" : "burst",
245ba5c15d9SAdrian Chadd 		    avp->av_bslot, ni->ni_intval,
246ba5c15d9SAdrian Chadd 		    (long long unsigned) le64toh(tsfadjust));
247ba5c15d9SAdrian Chadd 
248ba5c15d9SAdrian Chadd 		wh = mtod(m, struct ieee80211_frame *);
249ba5c15d9SAdrian Chadd 		memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
250ba5c15d9SAdrian Chadd 	}
251ba5c15d9SAdrian Chadd 	bf->bf_m = m;
252ba5c15d9SAdrian Chadd 	bf->bf_node = ieee80211_ref_node(ni);
253ba5c15d9SAdrian Chadd 
254ba5c15d9SAdrian Chadd 	return 0;
255ba5c15d9SAdrian Chadd }
256ba5c15d9SAdrian Chadd 
257ba5c15d9SAdrian Chadd /*
258ba5c15d9SAdrian Chadd  * Setup the beacon frame for transmit.
259ba5c15d9SAdrian Chadd  */
260ba5c15d9SAdrian Chadd static void
261ba5c15d9SAdrian Chadd ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
262ba5c15d9SAdrian Chadd {
263ba5c15d9SAdrian Chadd #define	USE_SHPREAMBLE(_ic) \
264ba5c15d9SAdrian Chadd 	(((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
265ba5c15d9SAdrian Chadd 		== IEEE80211_F_SHPREAMBLE)
266ba5c15d9SAdrian Chadd 	struct ieee80211_node *ni = bf->bf_node;
267ba5c15d9SAdrian Chadd 	struct ieee80211com *ic = ni->ni_ic;
268ba5c15d9SAdrian Chadd 	struct mbuf *m = bf->bf_m;
269ba5c15d9SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
270ba5c15d9SAdrian Chadd 	struct ath_desc *ds;
271ba5c15d9SAdrian Chadd 	int flags, antenna;
272ba5c15d9SAdrian Chadd 	const HAL_RATE_TABLE *rt;
273ba5c15d9SAdrian Chadd 	u_int8_t rix, rate;
27446634305SAdrian Chadd 	HAL_DMA_ADDR bufAddrList[4];
27546634305SAdrian Chadd 	uint32_t segLenList[4];
276e1252ce1SAdrian Chadd 	HAL_11N_RATE_SERIES rc[4];
277ba5c15d9SAdrian Chadd 
278ba5c15d9SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
279ba5c15d9SAdrian Chadd 		__func__, m, m->m_len);
280ba5c15d9SAdrian Chadd 
281ba5c15d9SAdrian Chadd 	/* setup descriptors */
282ba5c15d9SAdrian Chadd 	ds = bf->bf_desc;
283ba5c15d9SAdrian Chadd 	bf->bf_last = bf;
284ba5c15d9SAdrian Chadd 	bf->bf_lastds = ds;
285ba5c15d9SAdrian Chadd 
286ba5c15d9SAdrian Chadd 	flags = HAL_TXDESC_NOACK;
287ba5c15d9SAdrian Chadd 	if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
288bb069955SAdrian Chadd 		/* self-linked descriptor */
289bb069955SAdrian Chadd 		ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr);
290ba5c15d9SAdrian Chadd 		flags |= HAL_TXDESC_VEOL;
291ba5c15d9SAdrian Chadd 		/*
292ba5c15d9SAdrian Chadd 		 * Let hardware handle antenna switching.
293ba5c15d9SAdrian Chadd 		 */
294ba5c15d9SAdrian Chadd 		antenna = sc->sc_txantenna;
295ba5c15d9SAdrian Chadd 	} else {
296bb069955SAdrian Chadd 		ath_hal_settxdesclink(sc->sc_ah, ds, 0);
297ba5c15d9SAdrian Chadd 		/*
298ba5c15d9SAdrian Chadd 		 * Switch antenna every 4 beacons.
299ba5c15d9SAdrian Chadd 		 * XXX assumes two antenna
300ba5c15d9SAdrian Chadd 		 */
301ba5c15d9SAdrian Chadd 		if (sc->sc_txantenna != 0)
302ba5c15d9SAdrian Chadd 			antenna = sc->sc_txantenna;
303ba5c15d9SAdrian Chadd 		else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0)
304ba5c15d9SAdrian Chadd 			antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1);
305ba5c15d9SAdrian Chadd 		else
306ba5c15d9SAdrian Chadd 			antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
307ba5c15d9SAdrian Chadd 	}
308ba5c15d9SAdrian Chadd 
309ba5c15d9SAdrian Chadd 	KASSERT(bf->bf_nseg == 1,
310ba5c15d9SAdrian Chadd 		("multi-segment beacon frame; nseg %u", bf->bf_nseg));
31146634305SAdrian Chadd 
312ba5c15d9SAdrian Chadd 	/*
313ba5c15d9SAdrian Chadd 	 * Calculate rate code.
314ba5c15d9SAdrian Chadd 	 * XXX everything at min xmit rate
315ba5c15d9SAdrian Chadd 	 */
316ba5c15d9SAdrian Chadd 	rix = 0;
317ba5c15d9SAdrian Chadd 	rt = sc->sc_currates;
318ba5c15d9SAdrian Chadd 	rate = rt->info[rix].rateCode;
319ba5c15d9SAdrian Chadd 	if (USE_SHPREAMBLE(ic))
320ba5c15d9SAdrian Chadd 		rate |= rt->info[rix].shortPreamble;
321ba5c15d9SAdrian Chadd 	ath_hal_setuptxdesc(ah, ds
322ba5c15d9SAdrian Chadd 		, m->m_len + IEEE80211_CRC_LEN	/* frame length */
323ba5c15d9SAdrian Chadd 		, sizeof(struct ieee80211_frame)/* header length */
324ba5c15d9SAdrian Chadd 		, HAL_PKT_TYPE_BEACON		/* Atheros packet type */
325ba5c15d9SAdrian Chadd 		, ni->ni_txpower		/* txpower XXX */
326ba5c15d9SAdrian Chadd 		, rate, 1			/* series 0 rate/tries */
327ba5c15d9SAdrian Chadd 		, HAL_TXKEYIX_INVALID		/* no encryption */
328ba5c15d9SAdrian Chadd 		, antenna			/* antenna mode */
329ba5c15d9SAdrian Chadd 		, flags				/* no ack, veol for beacons */
330ba5c15d9SAdrian Chadd 		, 0				/* rts/cts rate */
331ba5c15d9SAdrian Chadd 		, 0				/* rts/cts duration */
332ba5c15d9SAdrian Chadd 	);
333e1252ce1SAdrian Chadd 
334e1252ce1SAdrian Chadd 	/*
335e1252ce1SAdrian Chadd 	 * The EDMA HAL currently assumes that _all_ rate control
336e1252ce1SAdrian Chadd 	 * settings are done in ath_hal_set11nratescenario(), rather
337e1252ce1SAdrian Chadd 	 * than in ath_hal_setuptxdesc().
338e1252ce1SAdrian Chadd 	 */
339e1252ce1SAdrian Chadd 	if (sc->sc_isedma) {
340e1252ce1SAdrian Chadd 		memset(&rc, 0, sizeof(rc));
341e1252ce1SAdrian Chadd 
342e1252ce1SAdrian Chadd 		rc[0].ChSel = sc->sc_txchainmask;
343e1252ce1SAdrian Chadd 		rc[0].Tries = 1;
344e1252ce1SAdrian Chadd 		rc[0].Rate = rt->info[rix].rateCode;
345e1252ce1SAdrian Chadd 		rc[0].RateIndex = rix;
346e1252ce1SAdrian Chadd 		rc[0].tx_power_cap = 0x3f;
347e1252ce1SAdrian Chadd 		rc[0].PktDuration =
348e1252ce1SAdrian Chadd 		    ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4),
349e1252ce1SAdrian Chadd 		        rix, 0);
350e1252ce1SAdrian Chadd 		ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags);
351e1252ce1SAdrian Chadd 	}
352e1252ce1SAdrian Chadd 
353ba5c15d9SAdrian Chadd 	/* NB: beacon's BufLen must be a multiple of 4 bytes */
35446634305SAdrian Chadd 	segLenList[0] = roundup(m->m_len, 4);
35546634305SAdrian Chadd 	segLenList[1] = segLenList[2] = segLenList[3] = 0;
35646634305SAdrian Chadd 	bufAddrList[0] = bf->bf_segs[0].ds_addr;
35746634305SAdrian Chadd 	bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0;
358ba5c15d9SAdrian Chadd 	ath_hal_filltxdesc(ah, ds
35946634305SAdrian Chadd 		, bufAddrList
36046634305SAdrian Chadd 		, segLenList
36146634305SAdrian Chadd 		, 0				/* XXX desc id */
36246634305SAdrian Chadd 		, sc->sc_bhalq			/* hardware TXQ */
363ba5c15d9SAdrian Chadd 		, AH_TRUE			/* first segment */
364ba5c15d9SAdrian Chadd 		, AH_TRUE			/* last segment */
365ba5c15d9SAdrian Chadd 		, ds				/* first descriptor */
366ba5c15d9SAdrian Chadd 	);
367ba5c15d9SAdrian Chadd #if 0
368ba5c15d9SAdrian Chadd 	ath_desc_swap(ds);
369ba5c15d9SAdrian Chadd #endif
370ba5c15d9SAdrian Chadd #undef USE_SHPREAMBLE
371ba5c15d9SAdrian Chadd }
372ba5c15d9SAdrian Chadd 
373ba5c15d9SAdrian Chadd void
374ba5c15d9SAdrian Chadd ath_beacon_update(struct ieee80211vap *vap, int item)
375ba5c15d9SAdrian Chadd {
376ba5c15d9SAdrian Chadd 	struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff;
377ba5c15d9SAdrian Chadd 
378ba5c15d9SAdrian Chadd 	setbit(bo->bo_flags, item);
379ba5c15d9SAdrian Chadd }
380ba5c15d9SAdrian Chadd 
381ba5c15d9SAdrian Chadd /*
382b837332dSAdrian Chadd  * Handle a beacon miss.
383b837332dSAdrian Chadd  */
384b837332dSAdrian Chadd static void
385b837332dSAdrian Chadd ath_beacon_miss(struct ath_softc *sc)
386b837332dSAdrian Chadd {
387b837332dSAdrian Chadd 	HAL_SURVEY_SAMPLE hs;
388b837332dSAdrian Chadd 	HAL_BOOL ret;
389b837332dSAdrian Chadd 	uint32_t hangs;
390b837332dSAdrian Chadd 
391b837332dSAdrian Chadd 	bzero(&hs, sizeof(hs));
392b837332dSAdrian Chadd 
393b837332dSAdrian Chadd 	ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs);
394b837332dSAdrian Chadd 
395b837332dSAdrian Chadd 	if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) {
396b837332dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
397b837332dSAdrian Chadd 		    "%s: hang=0x%08x\n",
398b837332dSAdrian Chadd 		    __func__,
399b837332dSAdrian Chadd 		    hangs);
400b837332dSAdrian Chadd 	}
401b837332dSAdrian Chadd 
402b837332dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_BEACON,
403b837332dSAdrian Chadd 	    "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, "
404b837332dSAdrian Chadd 	    "extchanbusy=%u, cyclecount=%u\n",
405b837332dSAdrian Chadd 	    __func__,
406b837332dSAdrian Chadd 	    ret,
407b837332dSAdrian Chadd 	    hs.tx_busy,
408b837332dSAdrian Chadd 	    hs.rx_busy,
409b837332dSAdrian Chadd 	    hs.chan_busy,
410b837332dSAdrian Chadd 	    hs.ext_chan_busy,
411b837332dSAdrian Chadd 	    hs.cycle_count);
412b837332dSAdrian Chadd }
413b837332dSAdrian Chadd 
414b837332dSAdrian Chadd /*
415ba5c15d9SAdrian Chadd  * Transmit a beacon frame at SWBA.  Dynamic updates to the
416ba5c15d9SAdrian Chadd  * frame contents are done as needed and the slot time is
417ba5c15d9SAdrian Chadd  * also adjusted based on current state.
418ba5c15d9SAdrian Chadd  */
419ba5c15d9SAdrian Chadd void
420ba5c15d9SAdrian Chadd ath_beacon_proc(void *arg, int pending)
421ba5c15d9SAdrian Chadd {
422ba5c15d9SAdrian Chadd 	struct ath_softc *sc = arg;
423ba5c15d9SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
424ba5c15d9SAdrian Chadd 	struct ieee80211vap *vap;
425ba5c15d9SAdrian Chadd 	struct ath_buf *bf;
426ba5c15d9SAdrian Chadd 	int slot, otherant;
427ba5c15d9SAdrian Chadd 	uint32_t bfaddr;
428ba5c15d9SAdrian Chadd 
429ba5c15d9SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
430ba5c15d9SAdrian Chadd 		__func__, pending);
431ba5c15d9SAdrian Chadd 	/*
432ba5c15d9SAdrian Chadd 	 * Check if the previous beacon has gone out.  If
433ba5c15d9SAdrian Chadd 	 * not don't try to post another, skip this period
434ba5c15d9SAdrian Chadd 	 * and wait for the next.  Missed beacons indicate
435ba5c15d9SAdrian Chadd 	 * a problem and should not occur.  If we miss too
436ba5c15d9SAdrian Chadd 	 * many consecutive beacons reset the device.
437ba5c15d9SAdrian Chadd 	 */
438ba5c15d9SAdrian Chadd 	if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
439ba5c15d9SAdrian Chadd 		sc->sc_bmisscount++;
440ba5c15d9SAdrian Chadd 		sc->sc_stats.ast_be_missed++;
441b837332dSAdrian Chadd 		ath_beacon_miss(sc);
442ba5c15d9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
443ba5c15d9SAdrian Chadd 			"%s: missed %u consecutive beacons\n",
444ba5c15d9SAdrian Chadd 			__func__, sc->sc_bmisscount);
445ba5c15d9SAdrian Chadd 		if (sc->sc_bmisscount >= ath_bstuck_threshold)
446ba5c15d9SAdrian Chadd 			taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
447ba5c15d9SAdrian Chadd 		return;
448ba5c15d9SAdrian Chadd 	}
449ba5c15d9SAdrian Chadd 	if (sc->sc_bmisscount != 0) {
450ba5c15d9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
451ba5c15d9SAdrian Chadd 			"%s: resume beacon xmit after %u misses\n",
452ba5c15d9SAdrian Chadd 			__func__, sc->sc_bmisscount);
453ba5c15d9SAdrian Chadd 		sc->sc_bmisscount = 0;
454ba5c15d9SAdrian Chadd 	}
455ba5c15d9SAdrian Chadd 
456ba5c15d9SAdrian Chadd 	if (sc->sc_stagbeacons) {			/* staggered beacons */
457ba5c15d9SAdrian Chadd 		struct ieee80211com *ic = sc->sc_ifp->if_l2com;
458ba5c15d9SAdrian Chadd 		uint32_t tsftu;
459ba5c15d9SAdrian Chadd 
460ba5c15d9SAdrian Chadd 		tsftu = ath_hal_gettsf32(ah) >> 10;
461ba5c15d9SAdrian Chadd 		/* XXX lintval */
462ba5c15d9SAdrian Chadd 		slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval;
463ba5c15d9SAdrian Chadd 		vap = sc->sc_bslot[(slot+1) % ATH_BCBUF];
464ba5c15d9SAdrian Chadd 		bfaddr = 0;
465ba5c15d9SAdrian Chadd 		if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
466ba5c15d9SAdrian Chadd 			bf = ath_beacon_generate(sc, vap);
467ba5c15d9SAdrian Chadd 			if (bf != NULL)
468ba5c15d9SAdrian Chadd 				bfaddr = bf->bf_daddr;
469ba5c15d9SAdrian Chadd 		}
470ba5c15d9SAdrian Chadd 	} else {					/* burst'd beacons */
471ba5c15d9SAdrian Chadd 		uint32_t *bflink = &bfaddr;
472ba5c15d9SAdrian Chadd 
473ba5c15d9SAdrian Chadd 		for (slot = 0; slot < ATH_BCBUF; slot++) {
474ba5c15d9SAdrian Chadd 			vap = sc->sc_bslot[slot];
475ba5c15d9SAdrian Chadd 			if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
476ba5c15d9SAdrian Chadd 				bf = ath_beacon_generate(sc, vap);
477ba5c15d9SAdrian Chadd 				if (bf != NULL) {
478bb069955SAdrian Chadd 					/* XXX should do this using the ds */
479ba5c15d9SAdrian Chadd 					*bflink = bf->bf_daddr;
480bb069955SAdrian Chadd 					ath_hal_gettxdesclinkptr(sc->sc_ah,
481bb069955SAdrian Chadd 					    bf->bf_desc, &bflink);
482ba5c15d9SAdrian Chadd 				}
483ba5c15d9SAdrian Chadd 			}
484ba5c15d9SAdrian Chadd 		}
485ba5c15d9SAdrian Chadd 		*bflink = 0;				/* terminate list */
486ba5c15d9SAdrian Chadd 	}
487ba5c15d9SAdrian Chadd 
488ba5c15d9SAdrian Chadd 	/*
489ba5c15d9SAdrian Chadd 	 * Handle slot time change when a non-ERP station joins/leaves
490ba5c15d9SAdrian Chadd 	 * an 11g network.  The 802.11 layer notifies us via callback,
491ba5c15d9SAdrian Chadd 	 * we mark updateslot, then wait one beacon before effecting
492ba5c15d9SAdrian Chadd 	 * the change.  This gives associated stations at least one
493ba5c15d9SAdrian Chadd 	 * beacon interval to note the state change.
494ba5c15d9SAdrian Chadd 	 */
495ba5c15d9SAdrian Chadd 	/* XXX locking */
496ba5c15d9SAdrian Chadd 	if (sc->sc_updateslot == UPDATE) {
497ba5c15d9SAdrian Chadd 		sc->sc_updateslot = COMMIT;	/* commit next beacon */
498ba5c15d9SAdrian Chadd 		sc->sc_slotupdate = slot;
499ba5c15d9SAdrian Chadd 	} else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
500ba5c15d9SAdrian Chadd 		ath_setslottime(sc);		/* commit change to h/w */
501ba5c15d9SAdrian Chadd 
502ba5c15d9SAdrian Chadd 	/*
503ba5c15d9SAdrian Chadd 	 * Check recent per-antenna transmit statistics and flip
504ba5c15d9SAdrian Chadd 	 * the default antenna if noticeably more frames went out
505ba5c15d9SAdrian Chadd 	 * on the non-default antenna.
506ba5c15d9SAdrian Chadd 	 * XXX assumes 2 anntenae
507ba5c15d9SAdrian Chadd 	 */
508ba5c15d9SAdrian Chadd 	if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) {
509ba5c15d9SAdrian Chadd 		otherant = sc->sc_defant & 1 ? 2 : 1;
510ba5c15d9SAdrian Chadd 		if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
511ba5c15d9SAdrian Chadd 			ath_setdefantenna(sc, otherant);
512ba5c15d9SAdrian Chadd 		sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
513ba5c15d9SAdrian Chadd 	}
514ba5c15d9SAdrian Chadd 
515b837332dSAdrian Chadd 	/* Program the CABQ with the contents of the CABQ txq and start it */
516b837332dSAdrian Chadd 	ATH_TXQ_LOCK(sc->sc_cabq);
517b837332dSAdrian Chadd 	ath_beacon_cabq_start(sc);
518b837332dSAdrian Chadd 	ATH_TXQ_UNLOCK(sc->sc_cabq);
519b837332dSAdrian Chadd 
520b837332dSAdrian Chadd 	/* Program the new beacon frame if we have one for this interval */
521ba5c15d9SAdrian Chadd 	if (bfaddr != 0) {
522ba5c15d9SAdrian Chadd 		/*
523ba5c15d9SAdrian Chadd 		 * Stop any current dma and put the new frame on the queue.
524ba5c15d9SAdrian Chadd 		 * This should never fail since we check above that no frames
525ba5c15d9SAdrian Chadd 		 * are still pending on the queue.
526ba5c15d9SAdrian Chadd 		 */
527e1252ce1SAdrian Chadd 		if (! sc->sc_isedma) {
528ba5c15d9SAdrian Chadd 			if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
529ba5c15d9SAdrian Chadd 				DPRINTF(sc, ATH_DEBUG_ANY,
530ba5c15d9SAdrian Chadd 					"%s: beacon queue %u did not stop?\n",
531ba5c15d9SAdrian Chadd 					__func__, sc->sc_bhalq);
532ba5c15d9SAdrian Chadd 			}
533e1252ce1SAdrian Chadd 		}
534ba5c15d9SAdrian Chadd 		/* NB: cabq traffic should already be queued and primed */
535e1252ce1SAdrian Chadd 
536ba5c15d9SAdrian Chadd 		ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);
537ba5c15d9SAdrian Chadd 		ath_hal_txstart(ah, sc->sc_bhalq);
538ba5c15d9SAdrian Chadd 
539ba5c15d9SAdrian Chadd 		sc->sc_stats.ast_be_xmit++;
540ba5c15d9SAdrian Chadd 	}
541ba5c15d9SAdrian Chadd }
542ba5c15d9SAdrian Chadd 
543b837332dSAdrian Chadd /*
544b837332dSAdrian Chadd  * Start CABQ transmission - this assumes that all frames are prepped
545b837332dSAdrian Chadd  * and ready in the CABQ.
546b837332dSAdrian Chadd  *
547b837332dSAdrian Chadd  * XXX TODO: methodize this; for the EDMA case it should only push
548b837332dSAdrian Chadd  * into the hardware if the FIFO isn't full _AND_ then it should
549b837332dSAdrian Chadd  * tag the final buffer in the queue as ATH_BUF_FIFOEND so the FIFO
550b837332dSAdrian Chadd  * depth is correctly accounted for.
551b837332dSAdrian Chadd  */
552b837332dSAdrian Chadd void
553b837332dSAdrian Chadd ath_beacon_cabq_start(struct ath_softc *sc)
554b837332dSAdrian Chadd {
555b837332dSAdrian Chadd 	struct ath_buf *bf;
556b837332dSAdrian Chadd 	struct ath_txq *cabq = sc->sc_cabq;
557b837332dSAdrian Chadd 
558b837332dSAdrian Chadd 	ATH_TXQ_LOCK_ASSERT(cabq);
559b837332dSAdrian Chadd 	if (TAILQ_EMPTY(&cabq->axq_q))
560b837332dSAdrian Chadd 		return;
561b837332dSAdrian Chadd 	bf = TAILQ_FIRST(&cabq->axq_q);
562b837332dSAdrian Chadd 
563b837332dSAdrian Chadd 	/* Push the first entry into the hardware */
564b837332dSAdrian Chadd 	ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr);
565b837332dSAdrian Chadd 
566b837332dSAdrian Chadd 	/* NB: gated by beacon so safe to start here */
567b837332dSAdrian Chadd 	ath_hal_txstart(sc->sc_ah, cabq->axq_qnum);
568b837332dSAdrian Chadd }
569b837332dSAdrian Chadd 
570ba5c15d9SAdrian Chadd struct ath_buf *
571ba5c15d9SAdrian Chadd ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
572ba5c15d9SAdrian Chadd {
573ba5c15d9SAdrian Chadd 	struct ath_vap *avp = ATH_VAP(vap);
574ba5c15d9SAdrian Chadd 	struct ath_txq *cabq = sc->sc_cabq;
575ba5c15d9SAdrian Chadd 	struct ath_buf *bf;
576ba5c15d9SAdrian Chadd 	struct mbuf *m;
577ba5c15d9SAdrian Chadd 	int nmcastq, error;
578ba5c15d9SAdrian Chadd 
579ba5c15d9SAdrian Chadd 	KASSERT(vap->iv_state >= IEEE80211_S_RUN,
580ba5c15d9SAdrian Chadd 	    ("not running, state %d", vap->iv_state));
581ba5c15d9SAdrian Chadd 	KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
582ba5c15d9SAdrian Chadd 
583ba5c15d9SAdrian Chadd 	/*
584ba5c15d9SAdrian Chadd 	 * Update dynamic beacon contents.  If this returns
585ba5c15d9SAdrian Chadd 	 * non-zero then we need to remap the memory because
586ba5c15d9SAdrian Chadd 	 * the beacon frame changed size (probably because
587ba5c15d9SAdrian Chadd 	 * of the TIM bitmap).
588ba5c15d9SAdrian Chadd 	 */
589ba5c15d9SAdrian Chadd 	bf = avp->av_bcbuf;
590ba5c15d9SAdrian Chadd 	m = bf->bf_m;
591ba5c15d9SAdrian Chadd 	/* XXX lock mcastq? */
592ba5c15d9SAdrian Chadd 	nmcastq = avp->av_mcastq.axq_depth;
593ba5c15d9SAdrian Chadd 
594ba5c15d9SAdrian Chadd 	if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) {
595ba5c15d9SAdrian Chadd 		/* XXX too conservative? */
596ba5c15d9SAdrian Chadd 		bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
597ba5c15d9SAdrian Chadd 		error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
598ba5c15d9SAdrian Chadd 					     bf->bf_segs, &bf->bf_nseg,
599ba5c15d9SAdrian Chadd 					     BUS_DMA_NOWAIT);
600ba5c15d9SAdrian Chadd 		if (error != 0) {
601ba5c15d9SAdrian Chadd 			if_printf(vap->iv_ifp,
602ba5c15d9SAdrian Chadd 			    "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
603ba5c15d9SAdrian Chadd 			    __func__, error);
604ba5c15d9SAdrian Chadd 			return NULL;
605ba5c15d9SAdrian Chadd 		}
606ba5c15d9SAdrian Chadd 	}
607ba5c15d9SAdrian Chadd 	if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) {
608ba5c15d9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
609ba5c15d9SAdrian Chadd 		    "%s: cabq did not drain, mcastq %u cabq %u\n",
610ba5c15d9SAdrian Chadd 		    __func__, nmcastq, cabq->axq_depth);
611ba5c15d9SAdrian Chadd 		sc->sc_stats.ast_cabq_busy++;
612ba5c15d9SAdrian Chadd 		if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
613ba5c15d9SAdrian Chadd 			/*
614ba5c15d9SAdrian Chadd 			 * CABQ traffic from a previous vap is still pending.
615ba5c15d9SAdrian Chadd 			 * We must drain the q before this beacon frame goes
616ba5c15d9SAdrian Chadd 			 * out as otherwise this vap's stations will get cab
617ba5c15d9SAdrian Chadd 			 * frames from a different vap.
618ba5c15d9SAdrian Chadd 			 * XXX could be slow causing us to miss DBA
619ba5c15d9SAdrian Chadd 			 */
620ba5c15d9SAdrian Chadd 			ath_tx_draintxq(sc, cabq);
621ba5c15d9SAdrian Chadd 		}
622ba5c15d9SAdrian Chadd 	}
623ba5c15d9SAdrian Chadd 	ath_beacon_setup(sc, bf);
624ba5c15d9SAdrian Chadd 	bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
625ba5c15d9SAdrian Chadd 
626ba5c15d9SAdrian Chadd 	/*
627ba5c15d9SAdrian Chadd 	 * Enable the CAB queue before the beacon queue to
628ba5c15d9SAdrian Chadd 	 * insure cab frames are triggered by this beacon.
629ba5c15d9SAdrian Chadd 	 */
630ba5c15d9SAdrian Chadd 	if (avp->av_boff.bo_tim[4] & 1) {
631ba5c15d9SAdrian Chadd 
632ba5c15d9SAdrian Chadd 		/* NB: only at DTIM */
633b837332dSAdrian Chadd 		ATH_TXQ_LOCK(&avp->av_mcastq);
634ba5c15d9SAdrian Chadd 		if (nmcastq) {
635*b6ef0f8aSAdrian Chadd 			struct ath_buf *bfm, *bfc_last;
636ba5c15d9SAdrian Chadd 
637ba5c15d9SAdrian Chadd 			/*
638ba5c15d9SAdrian Chadd 			 * Move frames from the s/w mcast q to the h/w cab q.
63974ea88c3SAdrian Chadd 			 *
640b837332dSAdrian Chadd 			 * XXX TODO: This should be methodized - the EDMA
641b837332dSAdrian Chadd 			 * CABQ setup code may look different!
642b837332dSAdrian Chadd 			 *
643b837332dSAdrian Chadd 			 * XXX TODO: if we chain together multiple VAPs
644b837332dSAdrian Chadd 			 * worth of CABQ traffic, should we keep the
645b837332dSAdrian Chadd 			 * MORE data bit set on the last frame of each
646b837332dSAdrian Chadd 			 * intermediary VAP (ie, only clear the MORE
647b837332dSAdrian Chadd 			 * bit of the last frame on the last vap?)
648ba5c15d9SAdrian Chadd 			 */
649ba5c15d9SAdrian Chadd 			bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q);
650b837332dSAdrian Chadd 			ATH_TXQ_LOCK(cabq);
651*b6ef0f8aSAdrian Chadd 
652*b6ef0f8aSAdrian Chadd 			/*
653*b6ef0f8aSAdrian Chadd 			 * If there's already a frame on the CABQ, we
654*b6ef0f8aSAdrian Chadd 			 * need to link to the end of the last frame.
655*b6ef0f8aSAdrian Chadd 			 * We can't use axq_link here because
656*b6ef0f8aSAdrian Chadd 			 * EDMA descriptors require some recalculation
657*b6ef0f8aSAdrian Chadd 			 * (checksum) to occur.
658*b6ef0f8aSAdrian Chadd 			 */
659*b6ef0f8aSAdrian Chadd 			bfc_last = ATH_TXQ_LAST(cabq, axq_q_s);
660*b6ef0f8aSAdrian Chadd 			if (bfc_last != NULL) {
661*b6ef0f8aSAdrian Chadd 				ath_hal_settxdesclink(sc->sc_ah,
662*b6ef0f8aSAdrian Chadd 				    bfc_last->bf_lastds,
663*b6ef0f8aSAdrian Chadd 				    bfm->bf_daddr);
664*b6ef0f8aSAdrian Chadd 			}
665ba5c15d9SAdrian Chadd 			ath_txqmove(cabq, &avp->av_mcastq);
666b837332dSAdrian Chadd 			ATH_TXQ_UNLOCK(cabq);
667b837332dSAdrian Chadd 			/*
668b837332dSAdrian Chadd 			 * XXX not entirely accurate, in case a mcast
669b837332dSAdrian Chadd 			 * queue frame arrived before we grabbed the TX
670b837332dSAdrian Chadd 			 * lock.
671b837332dSAdrian Chadd 			 */
672ba5c15d9SAdrian Chadd 			sc->sc_stats.ast_cabq_xmit += nmcastq;
673ba5c15d9SAdrian Chadd 		}
674b837332dSAdrian Chadd 		ATH_TXQ_UNLOCK(&avp->av_mcastq);
675ba5c15d9SAdrian Chadd 	}
676ba5c15d9SAdrian Chadd 	return bf;
677ba5c15d9SAdrian Chadd }
678ba5c15d9SAdrian Chadd 
679ba5c15d9SAdrian Chadd void
680ba5c15d9SAdrian Chadd ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap)
681ba5c15d9SAdrian Chadd {
682ba5c15d9SAdrian Chadd 	struct ath_vap *avp = ATH_VAP(vap);
683ba5c15d9SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
684ba5c15d9SAdrian Chadd 	struct ath_buf *bf;
685ba5c15d9SAdrian Chadd 	struct mbuf *m;
686ba5c15d9SAdrian Chadd 	int error;
687ba5c15d9SAdrian Chadd 
688ba5c15d9SAdrian Chadd 	KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
689ba5c15d9SAdrian Chadd 
690ba5c15d9SAdrian Chadd 	/*
691ba5c15d9SAdrian Chadd 	 * Update dynamic beacon contents.  If this returns
692ba5c15d9SAdrian Chadd 	 * non-zero then we need to remap the memory because
693ba5c15d9SAdrian Chadd 	 * the beacon frame changed size (probably because
694ba5c15d9SAdrian Chadd 	 * of the TIM bitmap).
695ba5c15d9SAdrian Chadd 	 */
696ba5c15d9SAdrian Chadd 	bf = avp->av_bcbuf;
697ba5c15d9SAdrian Chadd 	m = bf->bf_m;
698ba5c15d9SAdrian Chadd 	if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) {
699ba5c15d9SAdrian Chadd 		/* XXX too conservative? */
700ba5c15d9SAdrian Chadd 		bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
701ba5c15d9SAdrian Chadd 		error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
702ba5c15d9SAdrian Chadd 					     bf->bf_segs, &bf->bf_nseg,
703ba5c15d9SAdrian Chadd 					     BUS_DMA_NOWAIT);
704ba5c15d9SAdrian Chadd 		if (error != 0) {
705ba5c15d9SAdrian Chadd 			if_printf(vap->iv_ifp,
706ba5c15d9SAdrian Chadd 			    "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
707ba5c15d9SAdrian Chadd 			    __func__, error);
708ba5c15d9SAdrian Chadd 			return;
709ba5c15d9SAdrian Chadd 		}
710ba5c15d9SAdrian Chadd 	}
711ba5c15d9SAdrian Chadd 	ath_beacon_setup(sc, bf);
712ba5c15d9SAdrian Chadd 	bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
713ba5c15d9SAdrian Chadd 
714ba5c15d9SAdrian Chadd 	/* NB: caller is known to have already stopped tx dma */
715ba5c15d9SAdrian Chadd 	ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
716ba5c15d9SAdrian Chadd 	ath_hal_txstart(ah, sc->sc_bhalq);
717ba5c15d9SAdrian Chadd }
718ba5c15d9SAdrian Chadd 
719ba5c15d9SAdrian Chadd /*
720ba5c15d9SAdrian Chadd  * Reclaim beacon resources and return buffer to the pool.
721ba5c15d9SAdrian Chadd  */
722ba5c15d9SAdrian Chadd void
723ba5c15d9SAdrian Chadd ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf)
724ba5c15d9SAdrian Chadd {
725ba5c15d9SAdrian Chadd 
726ba5c15d9SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
727ba5c15d9SAdrian Chadd 	    __func__, bf, bf->bf_m, bf->bf_node);
728ba5c15d9SAdrian Chadd 	if (bf->bf_m != NULL) {
729ba5c15d9SAdrian Chadd 		bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
730ba5c15d9SAdrian Chadd 		m_freem(bf->bf_m);
731ba5c15d9SAdrian Chadd 		bf->bf_m = NULL;
732ba5c15d9SAdrian Chadd 	}
733ba5c15d9SAdrian Chadd 	if (bf->bf_node != NULL) {
734ba5c15d9SAdrian Chadd 		ieee80211_free_node(bf->bf_node);
735ba5c15d9SAdrian Chadd 		bf->bf_node = NULL;
736ba5c15d9SAdrian Chadd 	}
737ba5c15d9SAdrian Chadd 	TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list);
738ba5c15d9SAdrian Chadd }
739ba5c15d9SAdrian Chadd 
740ba5c15d9SAdrian Chadd /*
741ba5c15d9SAdrian Chadd  * Reclaim beacon resources.
742ba5c15d9SAdrian Chadd  */
743ba5c15d9SAdrian Chadd void
744ba5c15d9SAdrian Chadd ath_beacon_free(struct ath_softc *sc)
745ba5c15d9SAdrian Chadd {
746ba5c15d9SAdrian Chadd 	struct ath_buf *bf;
747ba5c15d9SAdrian Chadd 
748ba5c15d9SAdrian Chadd 	TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
749ba5c15d9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_NODE,
750ba5c15d9SAdrian Chadd 		    "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
751ba5c15d9SAdrian Chadd 		        __func__, bf, bf->bf_m, bf->bf_node);
752ba5c15d9SAdrian Chadd 		if (bf->bf_m != NULL) {
753ba5c15d9SAdrian Chadd 			bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
754ba5c15d9SAdrian Chadd 			m_freem(bf->bf_m);
755ba5c15d9SAdrian Chadd 			bf->bf_m = NULL;
756ba5c15d9SAdrian Chadd 		}
757ba5c15d9SAdrian Chadd 		if (bf->bf_node != NULL) {
758ba5c15d9SAdrian Chadd 			ieee80211_free_node(bf->bf_node);
759ba5c15d9SAdrian Chadd 			bf->bf_node = NULL;
760ba5c15d9SAdrian Chadd 		}
761ba5c15d9SAdrian Chadd 	}
762ba5c15d9SAdrian Chadd }
763ba5c15d9SAdrian Chadd 
764ba5c15d9SAdrian Chadd /*
765ba5c15d9SAdrian Chadd  * Configure the beacon and sleep timers.
766ba5c15d9SAdrian Chadd  *
767ba5c15d9SAdrian Chadd  * When operating as an AP this resets the TSF and sets
768ba5c15d9SAdrian Chadd  * up the hardware to notify us when we need to issue beacons.
769ba5c15d9SAdrian Chadd  *
770ba5c15d9SAdrian Chadd  * When operating in station mode this sets up the beacon
771ba5c15d9SAdrian Chadd  * timers according to the timestamp of the last received
772ba5c15d9SAdrian Chadd  * beacon and the current TSF, configures PCF and DTIM
773ba5c15d9SAdrian Chadd  * handling, programs the sleep registers so the hardware
774ba5c15d9SAdrian Chadd  * will wakeup in time to receive beacons, and configures
775ba5c15d9SAdrian Chadd  * the beacon miss handling so we'll receive a BMISS
776ba5c15d9SAdrian Chadd  * interrupt when we stop seeing beacons from the AP
777ba5c15d9SAdrian Chadd  * we've associated with.
778ba5c15d9SAdrian Chadd  */
779ba5c15d9SAdrian Chadd void
780ba5c15d9SAdrian Chadd ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap)
781ba5c15d9SAdrian Chadd {
782ba5c15d9SAdrian Chadd #define	TSF_TO_TU(_h,_l) \
783ba5c15d9SAdrian Chadd 	((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
784ba5c15d9SAdrian Chadd #define	FUDGE	2
785ba5c15d9SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
786ba5c15d9SAdrian Chadd 	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
787ba5c15d9SAdrian Chadd 	struct ieee80211_node *ni;
788ba5c15d9SAdrian Chadd 	u_int32_t nexttbtt, intval, tsftu;
789e1252ce1SAdrian Chadd 	u_int32_t nexttbtt_u8, intval_u8;
790ba5c15d9SAdrian Chadd 	u_int64_t tsf;
791ba5c15d9SAdrian Chadd 
792ba5c15d9SAdrian Chadd 	if (vap == NULL)
793ba5c15d9SAdrian Chadd 		vap = TAILQ_FIRST(&ic->ic_vaps);	/* XXX */
79461cd9692SAdrian Chadd 	/*
79561cd9692SAdrian Chadd 	 * Just ensure that we aren't being called when the last
79661cd9692SAdrian Chadd 	 * VAP is destroyed.
79761cd9692SAdrian Chadd 	 */
79861cd9692SAdrian Chadd 	if (vap == NULL) {
79961cd9692SAdrian Chadd 		device_printf(sc->sc_dev, "%s: called with no VAPs\n",
80061cd9692SAdrian Chadd 		    __func__);
80161cd9692SAdrian Chadd 		return;
80261cd9692SAdrian Chadd 	}
80361cd9692SAdrian Chadd 
804ba5c15d9SAdrian Chadd 	ni = ieee80211_ref_node(vap->iv_bss);
805ba5c15d9SAdrian Chadd 
806ba5c15d9SAdrian Chadd 	/* extract tstamp from last beacon and convert to TU */
807ba5c15d9SAdrian Chadd 	nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
808ba5c15d9SAdrian Chadd 			     LE_READ_4(ni->ni_tstamp.data));
809ba5c15d9SAdrian Chadd 	if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
810ba5c15d9SAdrian Chadd 	    ic->ic_opmode == IEEE80211_M_MBSS) {
811ba5c15d9SAdrian Chadd 		/*
812ba5c15d9SAdrian Chadd 		 * For multi-bss ap/mesh support beacons are either staggered
813ba5c15d9SAdrian Chadd 		 * evenly over N slots or burst together.  For the former
814ba5c15d9SAdrian Chadd 		 * arrange for the SWBA to be delivered for each slot.
815ba5c15d9SAdrian Chadd 		 * Slots that are not occupied will generate nothing.
816ba5c15d9SAdrian Chadd 		 */
817ba5c15d9SAdrian Chadd 		/* NB: the beacon interval is kept internally in TU's */
818ba5c15d9SAdrian Chadd 		intval = ni->ni_intval & HAL_BEACON_PERIOD;
819ba5c15d9SAdrian Chadd 		if (sc->sc_stagbeacons)
820ba5c15d9SAdrian Chadd 			intval /= ATH_BCBUF;
821ba5c15d9SAdrian Chadd 	} else {
822ba5c15d9SAdrian Chadd 		/* NB: the beacon interval is kept internally in TU's */
823ba5c15d9SAdrian Chadd 		intval = ni->ni_intval & HAL_BEACON_PERIOD;
824ba5c15d9SAdrian Chadd 	}
825ba5c15d9SAdrian Chadd 	if (nexttbtt == 0)		/* e.g. for ap mode */
826ba5c15d9SAdrian Chadd 		nexttbtt = intval;
827ba5c15d9SAdrian Chadd 	else if (intval)		/* NB: can be 0 for monitor mode */
828ba5c15d9SAdrian Chadd 		nexttbtt = roundup(nexttbtt, intval);
829ba5c15d9SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
830ba5c15d9SAdrian Chadd 		__func__, nexttbtt, intval, ni->ni_intval);
831ba5c15d9SAdrian Chadd 	if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) {
832ba5c15d9SAdrian Chadd 		HAL_BEACON_STATE bs;
833ba5c15d9SAdrian Chadd 		int dtimperiod, dtimcount;
834ba5c15d9SAdrian Chadd 		int cfpperiod, cfpcount;
835ba5c15d9SAdrian Chadd 
836ba5c15d9SAdrian Chadd 		/*
837ba5c15d9SAdrian Chadd 		 * Setup dtim and cfp parameters according to
838ba5c15d9SAdrian Chadd 		 * last beacon we received (which may be none).
839ba5c15d9SAdrian Chadd 		 */
840ba5c15d9SAdrian Chadd 		dtimperiod = ni->ni_dtim_period;
841ba5c15d9SAdrian Chadd 		if (dtimperiod <= 0)		/* NB: 0 if not known */
842ba5c15d9SAdrian Chadd 			dtimperiod = 1;
843ba5c15d9SAdrian Chadd 		dtimcount = ni->ni_dtim_count;
844ba5c15d9SAdrian Chadd 		if (dtimcount >= dtimperiod)	/* NB: sanity check */
845ba5c15d9SAdrian Chadd 			dtimcount = 0;		/* XXX? */
846ba5c15d9SAdrian Chadd 		cfpperiod = 1;			/* NB: no PCF support yet */
847ba5c15d9SAdrian Chadd 		cfpcount = 0;
848ba5c15d9SAdrian Chadd 		/*
849ba5c15d9SAdrian Chadd 		 * Pull nexttbtt forward to reflect the current
850ba5c15d9SAdrian Chadd 		 * TSF and calculate dtim+cfp state for the result.
851ba5c15d9SAdrian Chadd 		 */
852ba5c15d9SAdrian Chadd 		tsf = ath_hal_gettsf64(ah);
853ba5c15d9SAdrian Chadd 		tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
854ba5c15d9SAdrian Chadd 		do {
855ba5c15d9SAdrian Chadd 			nexttbtt += intval;
856ba5c15d9SAdrian Chadd 			if (--dtimcount < 0) {
857ba5c15d9SAdrian Chadd 				dtimcount = dtimperiod - 1;
858ba5c15d9SAdrian Chadd 				if (--cfpcount < 0)
859ba5c15d9SAdrian Chadd 					cfpcount = cfpperiod - 1;
860ba5c15d9SAdrian Chadd 			}
861ba5c15d9SAdrian Chadd 		} while (nexttbtt < tsftu);
862ba5c15d9SAdrian Chadd 		memset(&bs, 0, sizeof(bs));
863ba5c15d9SAdrian Chadd 		bs.bs_intval = intval;
864ba5c15d9SAdrian Chadd 		bs.bs_nexttbtt = nexttbtt;
865ba5c15d9SAdrian Chadd 		bs.bs_dtimperiod = dtimperiod*intval;
866ba5c15d9SAdrian Chadd 		bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
867ba5c15d9SAdrian Chadd 		bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
868ba5c15d9SAdrian Chadd 		bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
869ba5c15d9SAdrian Chadd 		bs.bs_cfpmaxduration = 0;
870ba5c15d9SAdrian Chadd #if 0
871ba5c15d9SAdrian Chadd 		/*
872ba5c15d9SAdrian Chadd 		 * The 802.11 layer records the offset to the DTIM
873ba5c15d9SAdrian Chadd 		 * bitmap while receiving beacons; use it here to
874ba5c15d9SAdrian Chadd 		 * enable h/w detection of our AID being marked in
875ba5c15d9SAdrian Chadd 		 * the bitmap vector (to indicate frames for us are
876ba5c15d9SAdrian Chadd 		 * pending at the AP).
877ba5c15d9SAdrian Chadd 		 * XXX do DTIM handling in s/w to WAR old h/w bugs
878ba5c15d9SAdrian Chadd 		 * XXX enable based on h/w rev for newer chips
879ba5c15d9SAdrian Chadd 		 */
880ba5c15d9SAdrian Chadd 		bs.bs_timoffset = ni->ni_timoff;
881ba5c15d9SAdrian Chadd #endif
882ba5c15d9SAdrian Chadd 		/*
883ba5c15d9SAdrian Chadd 		 * Calculate the number of consecutive beacons to miss
884ba5c15d9SAdrian Chadd 		 * before taking a BMISS interrupt.
885ba5c15d9SAdrian Chadd 		 * Note that we clamp the result to at most 10 beacons.
886ba5c15d9SAdrian Chadd 		 */
887ba5c15d9SAdrian Chadd 		bs.bs_bmissthreshold = vap->iv_bmissthreshold;
888ba5c15d9SAdrian Chadd 		if (bs.bs_bmissthreshold > 10)
889ba5c15d9SAdrian Chadd 			bs.bs_bmissthreshold = 10;
890ba5c15d9SAdrian Chadd 		else if (bs.bs_bmissthreshold <= 0)
891ba5c15d9SAdrian Chadd 			bs.bs_bmissthreshold = 1;
892ba5c15d9SAdrian Chadd 
893ba5c15d9SAdrian Chadd 		/*
894ba5c15d9SAdrian Chadd 		 * Calculate sleep duration.  The configuration is
895ba5c15d9SAdrian Chadd 		 * given in ms.  We insure a multiple of the beacon
896ba5c15d9SAdrian Chadd 		 * period is used.  Also, if the sleep duration is
897ba5c15d9SAdrian Chadd 		 * greater than the DTIM period then it makes senses
898ba5c15d9SAdrian Chadd 		 * to make it a multiple of that.
899ba5c15d9SAdrian Chadd 		 *
900ba5c15d9SAdrian Chadd 		 * XXX fixed at 100ms
901ba5c15d9SAdrian Chadd 		 */
902ba5c15d9SAdrian Chadd 		bs.bs_sleepduration =
903ba5c15d9SAdrian Chadd 			roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
904ba5c15d9SAdrian Chadd 		if (bs.bs_sleepduration > bs.bs_dtimperiod)
905ba5c15d9SAdrian Chadd 			bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
906ba5c15d9SAdrian Chadd 
907ba5c15d9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
908ba5c15d9SAdrian Chadd 			"%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
909ba5c15d9SAdrian Chadd 			, __func__
910ba5c15d9SAdrian Chadd 			, tsf, tsftu
911ba5c15d9SAdrian Chadd 			, bs.bs_intval
912ba5c15d9SAdrian Chadd 			, bs.bs_nexttbtt
913ba5c15d9SAdrian Chadd 			, bs.bs_dtimperiod
914ba5c15d9SAdrian Chadd 			, bs.bs_nextdtim
915ba5c15d9SAdrian Chadd 			, bs.bs_bmissthreshold
916ba5c15d9SAdrian Chadd 			, bs.bs_sleepduration
917ba5c15d9SAdrian Chadd 			, bs.bs_cfpperiod
918ba5c15d9SAdrian Chadd 			, bs.bs_cfpmaxduration
919ba5c15d9SAdrian Chadd 			, bs.bs_cfpnext
920ba5c15d9SAdrian Chadd 			, bs.bs_timoffset
921ba5c15d9SAdrian Chadd 		);
922ba5c15d9SAdrian Chadd 		ath_hal_intrset(ah, 0);
923ba5c15d9SAdrian Chadd 		ath_hal_beacontimers(ah, &bs);
924ba5c15d9SAdrian Chadd 		sc->sc_imask |= HAL_INT_BMISS;
925ba5c15d9SAdrian Chadd 		ath_hal_intrset(ah, sc->sc_imask);
926ba5c15d9SAdrian Chadd 	} else {
927ba5c15d9SAdrian Chadd 		ath_hal_intrset(ah, 0);
928ba5c15d9SAdrian Chadd 		if (nexttbtt == intval)
929ba5c15d9SAdrian Chadd 			intval |= HAL_BEACON_RESET_TSF;
930ba5c15d9SAdrian Chadd 		if (ic->ic_opmode == IEEE80211_M_IBSS) {
931ba5c15d9SAdrian Chadd 			/*
932ba5c15d9SAdrian Chadd 			 * In IBSS mode enable the beacon timers but only
933ba5c15d9SAdrian Chadd 			 * enable SWBA interrupts if we need to manually
934ba5c15d9SAdrian Chadd 			 * prepare beacon frames.  Otherwise we use a
935ba5c15d9SAdrian Chadd 			 * self-linked tx descriptor and let the hardware
936ba5c15d9SAdrian Chadd 			 * deal with things.
937ba5c15d9SAdrian Chadd 			 */
938ba5c15d9SAdrian Chadd 			intval |= HAL_BEACON_ENA;
939ba5c15d9SAdrian Chadd 			if (!sc->sc_hasveol)
940ba5c15d9SAdrian Chadd 				sc->sc_imask |= HAL_INT_SWBA;
941ba5c15d9SAdrian Chadd 			if ((intval & HAL_BEACON_RESET_TSF) == 0) {
942ba5c15d9SAdrian Chadd 				/*
943ba5c15d9SAdrian Chadd 				 * Pull nexttbtt forward to reflect
944ba5c15d9SAdrian Chadd 				 * the current TSF.
945ba5c15d9SAdrian Chadd 				 */
946ba5c15d9SAdrian Chadd 				tsf = ath_hal_gettsf64(ah);
947ba5c15d9SAdrian Chadd 				tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
948ba5c15d9SAdrian Chadd 				do {
949ba5c15d9SAdrian Chadd 					nexttbtt += intval;
950ba5c15d9SAdrian Chadd 				} while (nexttbtt < tsftu);
951ba5c15d9SAdrian Chadd 			}
952ba5c15d9SAdrian Chadd 			ath_beaconq_config(sc);
953ba5c15d9SAdrian Chadd 		} else if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
954ba5c15d9SAdrian Chadd 		    ic->ic_opmode == IEEE80211_M_MBSS) {
955ba5c15d9SAdrian Chadd 			/*
956ba5c15d9SAdrian Chadd 			 * In AP/mesh mode we enable the beacon timers
957ba5c15d9SAdrian Chadd 			 * and SWBA interrupts to prepare beacon frames.
958ba5c15d9SAdrian Chadd 			 */
959ba5c15d9SAdrian Chadd 			intval |= HAL_BEACON_ENA;
960ba5c15d9SAdrian Chadd 			sc->sc_imask |= HAL_INT_SWBA;	/* beacon prepare */
961ba5c15d9SAdrian Chadd 			ath_beaconq_config(sc);
962ba5c15d9SAdrian Chadd 		}
963e1252ce1SAdrian Chadd 
964e1252ce1SAdrian Chadd 		/*
965e1252ce1SAdrian Chadd 		 * Now dirty things because for now, the EDMA HAL has
966e1252ce1SAdrian Chadd 		 * nexttbtt and intval is TU/8.
967e1252ce1SAdrian Chadd 		 */
968e1252ce1SAdrian Chadd 		if (sc->sc_isedma) {
969e1252ce1SAdrian Chadd 			nexttbtt_u8 = (nexttbtt << 3);
970e1252ce1SAdrian Chadd 			intval_u8 = (intval << 3);
971e1252ce1SAdrian Chadd 			if (intval & HAL_BEACON_ENA)
972e1252ce1SAdrian Chadd 				intval_u8 |= HAL_BEACON_ENA;
973e1252ce1SAdrian Chadd 			if (intval & HAL_BEACON_RESET_TSF)
974e1252ce1SAdrian Chadd 				intval_u8 |= HAL_BEACON_RESET_TSF;
975e1252ce1SAdrian Chadd 			ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8);
976e1252ce1SAdrian Chadd 		} else
977ba5c15d9SAdrian Chadd 			ath_hal_beaconinit(ah, nexttbtt, intval);
978ba5c15d9SAdrian Chadd 		sc->sc_bmisscount = 0;
979ba5c15d9SAdrian Chadd 		ath_hal_intrset(ah, sc->sc_imask);
980ba5c15d9SAdrian Chadd 		/*
981ba5c15d9SAdrian Chadd 		 * When using a self-linked beacon descriptor in
982ba5c15d9SAdrian Chadd 		 * ibss mode load it once here.
983ba5c15d9SAdrian Chadd 		 */
984ba5c15d9SAdrian Chadd 		if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
985ba5c15d9SAdrian Chadd 			ath_beacon_start_adhoc(sc, vap);
986ba5c15d9SAdrian Chadd 	}
987ba5c15d9SAdrian Chadd 	sc->sc_syncbeacon = 0;
988ba5c15d9SAdrian Chadd 	ieee80211_free_node(ni);
989ba5c15d9SAdrian Chadd #undef FUDGE
990ba5c15d9SAdrian Chadd #undef TSF_TO_TU
991ba5c15d9SAdrian Chadd }
992