1 /*- 2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 /* 41 * Driver for the Atheros Wireless LAN controller. 42 * 43 * This software is derived from work of Atsushi Onoe; his contribution 44 * is greatly appreciated. 45 */ 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/lock.h> 55 #include <sys/mutex.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/errno.h> 60 #include <sys/callout.h> 61 #include <sys/bus.h> 62 #include <sys/endian.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_arp.h> 70 #include <net/ethernet.h> 71 #include <net/if_llc.h> 72 73 #include <net80211/ieee80211_var.h> 74 75 #include <net/bpf.h> 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/if_ether.h> 80 #endif 81 82 #define AR_DEBUG 83 #include <dev/ath/if_athvar.h> 84 #include <contrib/dev/ath/ah_desc.h> 85 86 /* unalligned little endian access */ 87 #define LE_READ_2(p) \ 88 ((u_int16_t) \ 89 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 90 #define LE_READ_4(p) \ 91 ((u_int32_t) \ 92 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 93 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 94 95 static void ath_init(void *); 96 static void ath_stop(struct ifnet *); 97 static void ath_start(struct ifnet *); 98 static void ath_reset(struct ath_softc *); 99 static int ath_media_change(struct ifnet *); 100 static void ath_watchdog(struct ifnet *); 101 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 102 static void ath_fatal_proc(void *, int); 103 static void ath_rxorn_proc(void *, int); 104 static void ath_bmiss_proc(void *, int); 105 static void ath_initkeytable(struct ath_softc *); 106 static void ath_mode_init(struct ath_softc *); 107 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 108 static void ath_beacon_proc(void *, int); 109 static void ath_beacon_free(struct ath_softc *); 110 static void ath_beacon_config(struct ath_softc *); 111 static int ath_desc_alloc(struct ath_softc *); 112 static void ath_desc_free(struct ath_softc *); 113 static struct ieee80211_node *ath_node_alloc(struct ieee80211com *); 114 static void ath_node_free(struct ieee80211com *, struct ieee80211_node *); 115 static void ath_node_copy(struct ieee80211com *, 116 struct ieee80211_node *, const struct ieee80211_node *); 117 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 118 static void ath_rx_proc(void *, int); 119 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 120 struct ath_buf *, struct mbuf *); 121 static void ath_tx_proc(void *, int); 122 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 123 static void ath_draintxq(struct ath_softc *); 124 static void ath_stoprecv(struct ath_softc *); 125 static int ath_startrecv(struct ath_softc *); 126 static void ath_next_scan(void *); 127 static void ath_calibrate(void *); 128 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 129 static void ath_newassoc(struct ieee80211com *, 130 struct ieee80211_node *, int); 131 static int ath_getchannels(struct ath_softc *, u_int cc, HAL_BOOL outdoor); 132 133 static int ath_rate_setup(struct ath_softc *sc, u_int mode); 134 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 135 static void ath_rate_ctl_reset(struct ath_softc *, enum ieee80211_state); 136 static void ath_rate_ctl(void *, struct ieee80211_node *); 137 138 SYSCTL_DECL(_hw_ath); 139 140 /* XXX validate sysctl values */ 141 static int ath_dwelltime = 200; /* 5 channels/second */ 142 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 143 0, "channel dwell time (ms) for AP/station scanning"); 144 static int ath_calinterval = 30; /* calibrate every 30 secs */ 145 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 146 0, "chip calibration interval (secs)"); 147 static int ath_outdoor = AH_TRUE; /* outdoor operation */ 148 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 149 0, "enable/disable outdoor operation"); 150 static int ath_countrycode = CTRY_DEFAULT; /* country code */ 151 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 152 0, "country code"); 153 static int ath_regdomain = 0; /* regulatory domain */ 154 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 155 0, "regulatory domain"); 156 157 #ifdef AR_DEBUG 158 int ath_debug = 0; 159 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 160 0, "control debugging printfs"); 161 #define IFF_DUMPPKTS(_ifp) \ 162 (ath_debug || \ 163 ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 164 static void ath_printrxbuf(struct ath_buf *bf, int); 165 static void ath_printtxbuf(struct ath_buf *bf, int); 166 #define DPRINTF(X) if (ath_debug) printf X 167 #define DPRINTF2(X) if (ath_debug > 1) printf X 168 #else 169 #define IFF_DUMPPKTS(_ifp) \ 170 (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 171 #define DPRINTF(X) 172 #define DPRINTF2(X) 173 #endif 174 175 int 176 ath_attach(u_int16_t devid, struct ath_softc *sc) 177 { 178 struct ieee80211com *ic = &sc->sc_ic; 179 struct ifnet *ifp = &ic->ic_if; 180 struct ath_hal *ah; 181 HAL_STATUS status; 182 int error = 0; 183 184 DPRINTF(("ath_attach: devid 0x%x\n", devid)); 185 186 /* set these up early for if_printf use */ 187 ifp->if_unit = device_get_unit(sc->sc_dev); 188 ifp->if_name = "ath"; 189 190 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 191 if (ah == NULL) { 192 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 193 status); 194 error = ENXIO; 195 goto bad; 196 } 197 sc->sc_ah = ah; 198 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 199 200 /* 201 * Collect the channel list using the default country 202 * code and including outdoor channels. The 802.11 layer 203 * is resposible for filtering this list based on settings 204 * like the phy mode. 205 */ 206 error = ath_getchannels(sc, ath_countrycode, ath_outdoor); 207 if (error != 0) 208 goto bad; 209 /* 210 * Copy these back; they are set as a side effect 211 * of constructing the channel list. 212 */ 213 ath_regdomain = ath_hal_getregdomain(ah); 214 ath_countrycode = ath_hal_getcountrycode(ah); 215 216 /* 217 * Setup rate tables for all potential media types. 218 */ 219 ath_rate_setup(sc, IEEE80211_MODE_11A); 220 ath_rate_setup(sc, IEEE80211_MODE_11B); 221 ath_rate_setup(sc, IEEE80211_MODE_11G); 222 ath_rate_setup(sc, IEEE80211_MODE_TURBO); 223 224 error = ath_desc_alloc(sc); 225 if (error != 0) { 226 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 227 goto bad; 228 } 229 callout_init(&sc->sc_scan_ch, CALLOUT_MPSAFE); 230 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 231 232 mtx_init(&sc->sc_txbuflock, 233 device_get_nameunit(sc->sc_dev), "xmit buf q", MTX_DEF); 234 mtx_init(&sc->sc_txqlock, 235 device_get_nameunit(sc->sc_dev), "xmit q", MTX_DEF); 236 237 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 238 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 239 TASK_INIT(&sc->sc_swbatask, 0, ath_beacon_proc, sc); 240 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 241 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 242 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 243 244 /* 245 * For now just pre-allocate one data queue and one 246 * beacon queue. Note that the HAL handles resetting 247 * them at the needed time. Eventually we'll want to 248 * allocate more tx queues for splitting management 249 * frames and for QOS support. 250 */ 251 sc->sc_txhalq = ath_hal_setuptxqueue(ah, 252 HAL_TX_QUEUE_DATA, 253 AH_TRUE /* enable interrupts */ 254 ); 255 if (sc->sc_txhalq == (u_int) -1) { 256 if_printf(ifp, "unable to setup a data xmit queue!\n"); 257 goto bad; 258 } 259 sc->sc_bhalq = ath_hal_setuptxqueue(ah, 260 HAL_TX_QUEUE_BEACON, 261 AH_TRUE /* enable interrupts */ 262 ); 263 if (sc->sc_bhalq == (u_int) -1) { 264 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 265 goto bad; 266 } 267 268 ifp->if_softc = sc; 269 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 270 ifp->if_start = ath_start; 271 ifp->if_watchdog = ath_watchdog; 272 ifp->if_ioctl = ath_ioctl; 273 ifp->if_init = ath_init; 274 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 275 276 ic->ic_softc = sc; 277 ic->ic_newassoc = ath_newassoc; 278 /* XXX not right but it's not used anywhere important */ 279 ic->ic_phytype = IEEE80211_T_OFDM; 280 ic->ic_opmode = IEEE80211_M_STA; 281 ic->ic_caps = IEEE80211_C_WEP | IEEE80211_C_IBSS | IEEE80211_C_HOSTAP 282 | IEEE80211_C_MONITOR | IEEE80211_C_SHPREAMBLE; 283 284 /* get mac address from hardware */ 285 ath_hal_getmac(ah, ic->ic_myaddr); 286 287 /* call MI attach routine. */ 288 ieee80211_ifattach(ifp); 289 /* override default methods */ 290 ic->ic_node_alloc = ath_node_alloc; 291 ic->ic_node_free = ath_node_free; 292 ic->ic_node_copy = ath_node_copy; 293 sc->sc_newstate = ic->ic_newstate; 294 ic->ic_newstate = ath_newstate; 295 /* complete initialization */ 296 ieee80211_media_init(ifp, ath_media_change, ieee80211_media_status); 297 298 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 299 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 300 &sc->sc_drvbpf); 301 /* 302 * Initialize constant fields. 303 * 304 * NB: the channel is setup each time we transition to the 305 * RUN state to avoid filling it in for each frame. 306 */ 307 sc->sc_tx_th.wt_ihdr.it_len = sizeof(sc->sc_tx_th); 308 sc->sc_tx_th.wt_ihdr.it_present = ATH_TX_RADIOTAP_PRESENT; 309 310 sc->sc_rx_th.wr_ihdr.it_len = sizeof(sc->sc_rx_th); 311 sc->sc_rx_th.wr_ihdr.it_present = ATH_RX_RADIOTAP_PRESENT; 312 313 if_printf(ifp, "802.11 address: %s\n", ether_sprintf(ic->ic_myaddr)); 314 315 return 0; 316 bad: 317 if (ah) 318 ath_hal_detach(ah); 319 sc->sc_invalid = 1; 320 return error; 321 } 322 323 int 324 ath_detach(struct ath_softc *sc) 325 { 326 struct ifnet *ifp = &sc->sc_ic.ic_if; 327 328 DPRINTF(("ath_detach: if_flags %x\n", ifp->if_flags)); 329 330 mtx_lock(&sc->sc_mtx); 331 ath_stop(ifp); 332 bpfdetach(ifp); 333 ath_desc_free(sc); 334 ath_hal_detach(sc->sc_ah); 335 ieee80211_ifdetach(ifp); 336 mtx_unlock(&sc->sc_mtx); 337 return 0; 338 } 339 340 void 341 ath_suspend(struct ath_softc *sc) 342 { 343 struct ifnet *ifp = &sc->sc_ic.ic_if; 344 345 DPRINTF(("ath_suspend: if_flags %x\n", ifp->if_flags)); 346 347 ath_stop(ifp); 348 } 349 350 void 351 ath_resume(struct ath_softc *sc) 352 { 353 struct ifnet *ifp = &sc->sc_ic.ic_if; 354 355 DPRINTF(("ath_resume: if_flags %x\n", ifp->if_flags)); 356 357 if (ifp->if_flags & IFF_UP) { 358 ath_init(ifp); 359 if (ifp->if_flags & IFF_RUNNING) 360 ath_start(ifp); 361 } 362 } 363 364 void 365 ath_shutdown(struct ath_softc *sc) 366 { 367 struct ifnet *ifp = &sc->sc_ic.ic_if; 368 369 DPRINTF(("ath_shutdown: if_flags %x\n", ifp->if_flags)); 370 371 ath_stop(ifp); 372 } 373 374 void 375 ath_intr(void *arg) 376 { 377 struct ath_softc *sc = arg; 378 struct ieee80211com *ic = &sc->sc_ic; 379 struct ifnet *ifp = &ic->ic_if; 380 struct ath_hal *ah = sc->sc_ah; 381 HAL_INT status; 382 383 if (sc->sc_invalid) { 384 /* 385 * The hardware is not ready/present, don't touch anything. 386 * Note this can happen early on if the IRQ is shared. 387 */ 388 DPRINTF(("ath_intr: invalid; ignored\n")); 389 return; 390 } 391 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 392 DPRINTF(("ath_intr: if_flags 0x%x\n", ifp->if_flags)); 393 ath_hal_getisr(ah, &status); /* clear ISR */ 394 ath_hal_intrset(ah, 0); /* disable further intr's */ 395 return; 396 } 397 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 398 DPRINTF2(("ath_intr: status 0x%x\n", status)); 399 #ifdef AR_DEBUG 400 if (ath_debug && 401 (status & (HAL_INT_FATAL|HAL_INT_RXORN|HAL_INT_BMISS))) { 402 if_printf(ifp, "ath_intr: status 0x%x\n", status); 403 ath_hal_dumpstate(ah); 404 } 405 #endif /* AR_DEBUG */ 406 if (status & HAL_INT_FATAL) { 407 sc->sc_stats.ast_hardware++; 408 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 409 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask); 410 } else if (status & HAL_INT_RXORN) { 411 sc->sc_stats.ast_rxorn++; 412 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 413 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask); 414 } else { 415 if (status & HAL_INT_RXEOL) { 416 /* 417 * NB: the hardware should re-read the link when 418 * RXE bit is written, but it doesn't work at 419 * least on older hardware revs. 420 */ 421 sc->sc_stats.ast_rxeol++; 422 sc->sc_rxlink = NULL; 423 } 424 if (status & HAL_INT_TXURN) { 425 sc->sc_stats.ast_txurn++; 426 /* bump tx trigger level */ 427 ath_hal_updatetxtriglevel(ah, AH_TRUE); 428 } 429 if (status & HAL_INT_RX) 430 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask); 431 if (status & HAL_INT_TX) 432 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask); 433 if (status & HAL_INT_SWBA) 434 taskqueue_enqueue(taskqueue_swi, &sc->sc_swbatask); 435 if (status & HAL_INT_BMISS) { 436 sc->sc_stats.ast_bmiss++; 437 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask); 438 } 439 } 440 } 441 442 static void 443 ath_fatal_proc(void *arg, int pending) 444 { 445 struct ath_softc *sc = arg; 446 447 device_printf(sc->sc_dev, "hardware error; resetting\n"); 448 ath_reset(sc); 449 } 450 451 static void 452 ath_rxorn_proc(void *arg, int pending) 453 { 454 struct ath_softc *sc = arg; 455 456 device_printf(sc->sc_dev, "rx FIFO overrun; resetting\n"); 457 ath_reset(sc); 458 } 459 460 static void 461 ath_bmiss_proc(void *arg, int pending) 462 { 463 struct ath_softc *sc = arg; 464 struct ieee80211com *ic = &sc->sc_ic; 465 466 DPRINTF(("ath_bmiss_proc: pending %u\n", pending)); 467 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 468 ("unexpect operating mode %u", ic->ic_opmode)); 469 if (ic->ic_state == IEEE80211_S_RUN) 470 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 471 } 472 473 static u_int 474 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 475 { 476 static const u_int modeflags[] = { 477 0, /* IEEE80211_MODE_AUTO */ 478 CHANNEL_A, /* IEEE80211_MODE_11A */ 479 CHANNEL_B, /* IEEE80211_MODE_11B */ 480 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 481 CHANNEL_T /* IEEE80211_MODE_TURBO */ 482 }; 483 return modeflags[ieee80211_chan2mode(ic, chan)]; 484 } 485 486 static void 487 ath_init(void *arg) 488 { 489 struct ath_softc *sc = (struct ath_softc *) arg; 490 struct ieee80211com *ic = &sc->sc_ic; 491 struct ifnet *ifp = &ic->ic_if; 492 struct ieee80211_node *ni; 493 enum ieee80211_phymode mode; 494 struct ath_hal *ah = sc->sc_ah; 495 HAL_STATUS status; 496 HAL_CHANNEL hchan; 497 498 DPRINTF(("ath_init: if_flags 0x%x\n", ifp->if_flags)); 499 500 mtx_lock(&sc->sc_mtx); 501 /* 502 * Stop anything previously setup. This is safe 503 * whether this is the first time through or not. 504 */ 505 ath_stop(ifp); 506 507 /* 508 * The basic interface to setting the hardware in a good 509 * state is ``reset''. On return the hardware is known to 510 * be powered up and with interrupts disabled. This must 511 * be followed by initialization of the appropriate bits 512 * and then setup of the interrupt mask. 513 */ 514 hchan.channel = ic->ic_ibss_chan->ic_freq; 515 hchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 516 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_FALSE, &status)) { 517 if_printf(ifp, "unable to reset hardware; hal status %u\n", 518 status); 519 goto done; 520 } 521 522 /* 523 * Setup the hardware after reset: the key cache 524 * is filled as needed and the receive engine is 525 * set going. Frame transmit is handled entirely 526 * in the frame output path; there's nothing to do 527 * here except setup the interrupt mask. 528 */ 529 if (ic->ic_flags & IEEE80211_F_WEPON) 530 ath_initkeytable(sc); 531 if (ath_startrecv(sc) != 0) { 532 if_printf(ifp, "unable to start recv logic\n"); 533 goto done; 534 } 535 536 /* 537 * Enable interrupts. 538 */ 539 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 540 | HAL_INT_RXEOL | HAL_INT_RXORN 541 | HAL_INT_FATAL | HAL_INT_GLOBAL; 542 ath_hal_intrset(ah, sc->sc_imask); 543 544 ifp->if_flags |= IFF_RUNNING; 545 ic->ic_state = IEEE80211_S_INIT; 546 547 /* 548 * The hardware should be ready to go now so it's safe 549 * to kick the 802.11 state machine as it's likely to 550 * immediately call back to us to send mgmt frames. 551 */ 552 ni = ic->ic_bss; 553 ni->ni_chan = ic->ic_ibss_chan; 554 mode = ieee80211_chan2mode(ic, ni->ni_chan); 555 if (mode != sc->sc_curmode) 556 ath_setcurmode(sc, mode); 557 if (ic->ic_opmode != IEEE80211_M_MONITOR) 558 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 559 else 560 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 561 done: 562 mtx_unlock(&sc->sc_mtx); 563 } 564 565 static void 566 ath_stop(struct ifnet *ifp) 567 { 568 struct ieee80211com *ic = (struct ieee80211com *) ifp; 569 struct ath_softc *sc = ifp->if_softc; 570 struct ath_hal *ah = sc->sc_ah; 571 572 DPRINTF(("ath_stop: invalid %u if_flags 0x%x\n", 573 sc->sc_invalid, ifp->if_flags)); 574 575 mtx_lock(&sc->sc_mtx); 576 if (ifp->if_flags & IFF_RUNNING) { 577 /* 578 * Shutdown the hardware and driver: 579 * disable interrupts 580 * turn off timers 581 * clear transmit machinery 582 * clear receive machinery 583 * drain and release tx queues 584 * reclaim beacon resources 585 * reset 802.11 state machine 586 * power down hardware 587 * 588 * Note that some of this work is not possible if the 589 * hardware is gone (invalid). 590 */ 591 ifp->if_flags &= ~IFF_RUNNING; 592 ifp->if_timer = 0; 593 if (!sc->sc_invalid) 594 ath_hal_intrset(ah, 0); 595 ath_draintxq(sc); 596 if (!sc->sc_invalid) 597 ath_stoprecv(sc); 598 else 599 sc->sc_rxlink = NULL; 600 IF_DRAIN(&ifp->if_snd); 601 ath_beacon_free(sc); 602 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 603 if (!sc->sc_invalid) 604 ath_hal_setpower(ah, HAL_PM_FULL_SLEEP, 0); 605 } 606 mtx_unlock(&sc->sc_mtx); 607 } 608 609 /* 610 * Reset the hardware w/o losing operational state. This is 611 * basically a more efficient way of doing ath_stop, ath_init, 612 * followed by state transitions to the current 802.11 613 * operational state. Used to recover from errors rx overrun 614 * and to reset the hardware when rf gain settings must be reset. 615 */ 616 static void 617 ath_reset(struct ath_softc *sc) 618 { 619 struct ieee80211com *ic = &sc->sc_ic; 620 struct ifnet *ifp = &ic->ic_if; 621 struct ath_hal *ah = sc->sc_ah; 622 struct ieee80211_channel *c; 623 HAL_STATUS status; 624 HAL_CHANNEL hchan; 625 626 /* 627 * Convert to a HAL channel description with the flags 628 * constrained to reflect the current operating mode. 629 */ 630 c = ic->ic_ibss_chan; 631 hchan.channel = c->ic_freq; 632 hchan.channelFlags = ath_chan2flags(ic, c); 633 634 ath_hal_intrset(ah, 0); /* disable interrupts */ 635 ath_draintxq(sc); /* stop xmit side */ 636 ath_stoprecv(sc); /* stop recv side */ 637 /* NB: indicate channel change so we do a full reset */ 638 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) 639 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 640 __func__, status); 641 ath_hal_intrset(ah, sc->sc_imask); 642 if (ath_startrecv(sc) != 0) /* restart recv */ 643 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 644 ath_start(ifp); /* restart xmit */ 645 if (ic->ic_state == IEEE80211_S_RUN) 646 ath_beacon_config(sc); /* restart beacons */ 647 } 648 649 static void 650 ath_start(struct ifnet *ifp) 651 { 652 struct ath_softc *sc = ifp->if_softc; 653 struct ath_hal *ah = sc->sc_ah; 654 struct ieee80211com *ic = &sc->sc_ic; 655 struct ieee80211_node *ni; 656 struct ath_buf *bf; 657 struct mbuf *m; 658 struct ieee80211_frame *wh; 659 660 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 661 return; 662 for (;;) { 663 /* 664 * Grab a TX buffer and associated resources. 665 */ 666 mtx_lock(&sc->sc_txbuflock); 667 bf = TAILQ_FIRST(&sc->sc_txbuf); 668 if (bf != NULL) 669 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 670 mtx_unlock(&sc->sc_txbuflock); 671 if (bf == NULL) { 672 DPRINTF(("ath_start: out of xmit buffers\n")); 673 sc->sc_stats.ast_tx_qstop++; 674 ifp->if_flags |= IFF_OACTIVE; 675 break; 676 } 677 /* 678 * Poll the management queue for frames; they 679 * have priority over normal data frames. 680 */ 681 IF_DEQUEUE(&ic->ic_mgtq, m); 682 if (m == NULL) { 683 /* 684 * No data frames go out unless we're associated. 685 */ 686 if (ic->ic_state != IEEE80211_S_RUN) { 687 DPRINTF(("ath_start: ignore data packet, " 688 "state %u\n", ic->ic_state)); 689 sc->sc_stats.ast_tx_discard++; 690 mtx_lock(&sc->sc_txbuflock); 691 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 692 mtx_unlock(&sc->sc_txbuflock); 693 break; 694 } 695 IF_DEQUEUE(&ifp->if_snd, m); 696 if (m == NULL) { 697 mtx_lock(&sc->sc_txbuflock); 698 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 699 mtx_unlock(&sc->sc_txbuflock); 700 break; 701 } 702 ifp->if_opackets++; 703 BPF_MTAP(ifp, m); 704 /* 705 * Encapsulate the packet in prep for transmission. 706 */ 707 m = ieee80211_encap(ifp, m, &ni); 708 if (m == NULL) { 709 DPRINTF(("ath_start: encapsulation failure\n")); 710 sc->sc_stats.ast_tx_encap++; 711 goto bad; 712 } 713 wh = mtod(m, struct ieee80211_frame *); 714 if (ic->ic_flags & IEEE80211_F_WEPON) 715 wh->i_fc[1] |= IEEE80211_FC1_WEP; 716 } else { 717 /* 718 * Hack! The referenced node pointer is in the 719 * rcvif field of the packet header. This is 720 * placed there by ieee80211_mgmt_output because 721 * we need to hold the reference with the frame 722 * and there's no other way (other than packet 723 * tags which we consider too expensive to use) 724 * to pass it along. 725 */ 726 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 727 m->m_pkthdr.rcvif = NULL; 728 729 wh = mtod(m, struct ieee80211_frame *); 730 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 731 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 732 /* fill time stamp */ 733 u_int64_t tsf; 734 u_int32_t *tstamp; 735 736 tsf = ath_hal_gettsf64(ah); 737 /* XXX: adjust 100us delay to xmit */ 738 tsf += 100; 739 tstamp = (u_int32_t *)&wh[1]; 740 tstamp[0] = htole32(tsf & 0xffffffff); 741 tstamp[1] = htole32(tsf >> 32); 742 } 743 sc->sc_stats.ast_tx_mgmt++; 744 } 745 if (ic->ic_rawbpf) 746 bpf_mtap(ic->ic_rawbpf, m); 747 748 if (sc->sc_drvbpf) { 749 struct mbuf *mb; 750 751 MGETHDR(mb, M_DONTWAIT, m->m_type); 752 if (mb != NULL) { 753 sc->sc_tx_th.wt_rate = 754 ni->ni_rates.rs_rates[ni->ni_txrate]; 755 756 mb->m_next = m; 757 mb->m_data = (caddr_t)&sc->sc_tx_th; 758 mb->m_len = sizeof(sc->sc_tx_th); 759 mb->m_pkthdr.len += mb->m_len; 760 bpf_mtap(sc->sc_drvbpf, mb); 761 m_free(mb); 762 } 763 } 764 765 if (ath_tx_start(sc, ni, bf, m)) { 766 bad: 767 mtx_lock(&sc->sc_txbuflock); 768 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 769 mtx_unlock(&sc->sc_txbuflock); 770 ifp->if_oerrors++; 771 if (ni && ni != ic->ic_bss) 772 ieee80211_free_node(ic, ni); 773 continue; 774 } 775 776 sc->sc_tx_timer = 5; 777 ifp->if_timer = 1; 778 } 779 } 780 781 static int 782 ath_media_change(struct ifnet *ifp) 783 { 784 int error; 785 786 error = ieee80211_media_change(ifp); 787 if (error == ENETRESET) { 788 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 789 (IFF_RUNNING|IFF_UP)) 790 ath_init(ifp); /* XXX lose error */ 791 error = 0; 792 } 793 return error; 794 } 795 796 static void 797 ath_watchdog(struct ifnet *ifp) 798 { 799 struct ath_softc *sc = ifp->if_softc; 800 struct ieee80211com *ic = &sc->sc_ic; 801 802 ifp->if_timer = 0; 803 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 804 return; 805 if (sc->sc_tx_timer) { 806 if (--sc->sc_tx_timer == 0) { 807 if_printf(ifp, "device timeout\n"); 808 #ifdef AR_DEBUG 809 if (ath_debug) 810 ath_hal_dumpstate(sc->sc_ah); 811 #endif /* AR_DEBUG */ 812 ath_init(ifp); /* XXX ath_reset??? */ 813 ifp->if_oerrors++; 814 sc->sc_stats.ast_watchdog++; 815 return; 816 } 817 ifp->if_timer = 1; 818 } 819 if (ic->ic_fixed_rate == -1) { 820 /* 821 * Run the rate control algorithm if we're not 822 * locked at a fixed rate. 823 */ 824 if (ic->ic_opmode == IEEE80211_M_STA) 825 ath_rate_ctl(sc, ic->ic_bss); 826 else 827 ieee80211_iterate_nodes(ic, ath_rate_ctl, sc); 828 } 829 ieee80211_watchdog(ifp); 830 } 831 832 static int 833 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 834 { 835 struct ath_softc *sc = ifp->if_softc; 836 struct ifreq *ifr = (struct ifreq *)data; 837 int error = 0; 838 839 mtx_lock(&sc->sc_mtx); 840 switch (cmd) { 841 case SIOCSIFFLAGS: 842 if (ifp->if_flags & IFF_UP) { 843 if (ifp->if_flags & IFF_RUNNING) { 844 /* 845 * To avoid rescanning another access point, 846 * do not call ath_init() here. Instead, 847 * only reflect promisc mode settings. 848 */ 849 ath_mode_init(sc); 850 } else 851 ath_init(ifp); /* XXX lose error */ 852 } else 853 ath_stop(ifp); 854 break; 855 case SIOCADDMULTI: 856 case SIOCDELMULTI: 857 /* 858 * The upper layer has already installed/removed 859 * the multicast address(es), just recalculate the 860 * multicast filter for the card. 861 */ 862 if (ifp->if_flags & IFF_RUNNING) 863 ath_mode_init(sc); 864 break; 865 case SIOCGATHSTATS: 866 copyout(&sc->sc_stats, ifr->ifr_data, sizeof (sc->sc_stats)); 867 break; 868 default: 869 error = ieee80211_ioctl(ifp, cmd, data); 870 if (error == ENETRESET) { 871 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 872 (IFF_RUNNING|IFF_UP)) 873 ath_init(ifp); /* XXX lose error */ 874 error = 0; 875 } 876 break; 877 } 878 mtx_unlock(&sc->sc_mtx); 879 return error; 880 } 881 882 /* 883 * Fill the hardware key cache with key entries. 884 */ 885 static void 886 ath_initkeytable(struct ath_softc *sc) 887 { 888 struct ieee80211com *ic = &sc->sc_ic; 889 struct ath_hal *ah = sc->sc_ah; 890 int i; 891 892 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 893 struct ieee80211_wepkey *k = &ic->ic_nw_keys[i]; 894 if (k->wk_len == 0) 895 ath_hal_keyreset(ah, i); 896 else 897 /* XXX return value */ 898 /* NB: this uses HAL_KEYVAL == ieee80211_wepkey */ 899 ath_hal_keyset(ah, i, (const HAL_KEYVAL *) k); 900 } 901 } 902 903 static void 904 ath_mode_init(struct ath_softc *sc) 905 { 906 struct ieee80211com *ic = &sc->sc_ic; 907 struct ath_hal *ah = sc->sc_ah; 908 struct ifnet *ifp = &ic->ic_if; 909 u_int32_t rfilt, mfilt[2], val; 910 u_int8_t pos; 911 struct ifmultiaddr *ifma; 912 913 /* configure operational mode */ 914 ath_hal_setopmode(ah, ic->ic_opmode); 915 916 /* receive filter */ 917 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 918 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 919 if (ic->ic_opmode != IEEE80211_M_STA) 920 rfilt |= HAL_RX_FILTER_PROBEREQ; 921 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 922 (ifp->if_flags & IFF_PROMISC)) 923 rfilt |= HAL_RX_FILTER_PROM; 924 if (ic->ic_state == IEEE80211_S_SCAN) 925 rfilt |= HAL_RX_FILTER_BEACON; 926 ath_hal_setrxfilter(ah, rfilt); 927 928 /* calculate and install multicast filter */ 929 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 930 mfilt[0] = mfilt[1] = 0; 931 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 932 caddr_t dl; 933 934 /* calculate XOR of eight 6bit values */ 935 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 936 val = LE_READ_4(dl + 0); 937 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 938 val = LE_READ_4(dl + 3); 939 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 940 pos &= 0x3f; 941 mfilt[pos / 32] |= (1 << (pos % 32)); 942 } 943 } else { 944 mfilt[0] = mfilt[1] = ~0; 945 } 946 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 947 DPRINTF(("ath_mode_init: RX filter 0x%x, MC filter %08x:%08x\n", 948 rfilt, mfilt[0], mfilt[1])); 949 } 950 951 static void 952 ath_mbuf_load_cb(void *arg, bus_dma_segment_t *seg, int nseg, bus_size_t mapsize, int error) 953 { 954 struct ath_buf *bf = arg; 955 956 KASSERT(nseg <= ATH_MAX_SCATTER, 957 ("ath_mbuf_load_cb: too many DMA segments %u", nseg)); 958 bf->bf_mapsize = mapsize; 959 bf->bf_nseg = nseg; 960 bcopy(seg, bf->bf_segs, nseg * sizeof (seg[0])); 961 } 962 963 static int 964 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 965 { 966 struct ieee80211com *ic = &sc->sc_ic; 967 struct ifnet *ifp = &ic->ic_if; 968 struct ath_hal *ah = sc->sc_ah; 969 struct ieee80211_frame *wh; 970 struct ath_buf *bf; 971 struct ath_desc *ds; 972 struct mbuf *m; 973 int error, pktlen; 974 u_int8_t *frm, rate; 975 u_int16_t capinfo; 976 struct ieee80211_rateset *rs; 977 const HAL_RATE_TABLE *rt; 978 979 bf = sc->sc_bcbuf; 980 if (bf->bf_m != NULL) { 981 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 982 m_freem(bf->bf_m); 983 bf->bf_m = NULL; 984 bf->bf_node = NULL; 985 } 986 /* 987 * NB: the beacon data buffer must be 32-bit aligned; 988 * we assume the mbuf routines will return us something 989 * with this alignment (perhaps should assert). 990 */ 991 rs = &ni->ni_rates; 992 pktlen = sizeof (struct ieee80211_frame) 993 + 8 + 2 + 2 + 2+ni->ni_esslen + 2+rs->rs_nrates + 6; 994 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 995 pktlen += 2; 996 if (pktlen <= MHLEN) 997 MGETHDR(m, M_DONTWAIT, MT_DATA); 998 else 999 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1000 if (m == NULL) { 1001 DPRINTF(("ath_beacon_alloc: cannot get mbuf/cluster; size %u\n", 1002 pktlen)); 1003 sc->sc_stats.ast_be_nombuf++; 1004 return ENOMEM; 1005 } 1006 1007 wh = mtod(m, struct ieee80211_frame *); 1008 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1009 IEEE80211_FC0_SUBTYPE_BEACON; 1010 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1011 *(u_int16_t *)wh->i_dur = 0; 1012 memcpy(wh->i_addr1, ifp->if_broadcastaddr, IEEE80211_ADDR_LEN); 1013 memcpy(wh->i_addr2, ic->ic_myaddr, IEEE80211_ADDR_LEN); 1014 memcpy(wh->i_addr3, ni->ni_bssid, IEEE80211_ADDR_LEN); 1015 *(u_int16_t *)wh->i_seq = 0; 1016 1017 /* 1018 * beacon frame format 1019 * [8] time stamp 1020 * [2] beacon interval 1021 * [2] cabability information 1022 * [tlv] ssid 1023 * [tlv] supported rates 1024 * [tlv] parameter set (IBSS) 1025 * [tlv] extended supported rates 1026 */ 1027 frm = (u_int8_t *)&wh[1]; 1028 memset(frm, 0, 8); /* timestamp is set by hardware */ 1029 frm += 8; 1030 *(u_int16_t *)frm = htole16(ni->ni_intval); 1031 frm += 2; 1032 if (ic->ic_opmode == IEEE80211_M_IBSS) 1033 capinfo = IEEE80211_CAPINFO_IBSS; 1034 else 1035 capinfo = IEEE80211_CAPINFO_ESS; 1036 if (ic->ic_flags & IEEE80211_F_WEPON) 1037 capinfo |= IEEE80211_CAPINFO_PRIVACY; 1038 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1039 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 1040 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1041 capinfo |= IEEE80211_CAPINFO_SHORT_SLOTTIME; 1042 *(u_int16_t *)frm = htole16(capinfo); 1043 frm += 2; 1044 *frm++ = IEEE80211_ELEMID_SSID; 1045 *frm++ = ni->ni_esslen; 1046 memcpy(frm, ni->ni_essid, ni->ni_esslen); 1047 frm += ni->ni_esslen; 1048 frm = ieee80211_add_rates(frm, rs); 1049 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1050 *frm++ = IEEE80211_ELEMID_IBSSPARMS; 1051 *frm++ = 2; 1052 *frm++ = 0; *frm++ = 0; /* TODO: ATIM window */ 1053 } else { 1054 /* TODO: TIM */ 1055 *frm++ = IEEE80211_ELEMID_TIM; 1056 *frm++ = 4; /* length */ 1057 *frm++ = 0; /* DTIM count */ 1058 *frm++ = 1; /* DTIM period */ 1059 *frm++ = 0; /* bitmap control */ 1060 *frm++ = 0; /* Partial Virtual Bitmap (variable length) */ 1061 } 1062 frm = ieee80211_add_xrates(frm, rs); 1063 m->m_pkthdr.len = m->m_len = frm - mtod(m, u_int8_t *); 1064 KASSERT(m->m_pkthdr.len <= pktlen, 1065 ("beacon bigger than expected, len %u calculated %u", 1066 m->m_pkthdr.len, pktlen)); 1067 1068 DPRINTF2(("ath_beacon_alloc: m %p len %u\n", m, m->m_len)); 1069 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1070 ath_mbuf_load_cb, bf, 1071 BUS_DMA_NOWAIT); 1072 if (error != 0) { 1073 m_freem(m); 1074 return error; 1075 } 1076 KASSERT(bf->bf_nseg == 1, 1077 ("ath_beacon_alloc: multi-segment packet; nseg %u", 1078 bf->bf_nseg)); 1079 bf->bf_m = m; 1080 1081 /* setup descriptors */ 1082 ds = bf->bf_desc; 1083 1084 ds->ds_link = 0; 1085 ds->ds_data = bf->bf_segs[0].ds_addr; 1086 /* 1087 * Calculate rate code. 1088 * XXX everything at min xmit rate 1089 */ 1090 rt = sc->sc_currates; 1091 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1092 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1093 rate = rt->info[0].rateCode | rt->info[0].shortPreamble; 1094 else 1095 rate = rt->info[0].rateCode; 1096 ath_hal_setuptxdesc(ah, ds 1097 , m->m_pkthdr.len + IEEE80211_CRC_LEN /* packet length */ 1098 , sizeof(struct ieee80211_frame) /* header length */ 1099 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1100 , 0x20 /* txpower XXX */ 1101 , rate, 1 /* series 0 rate/tries */ 1102 , HAL_TXKEYIX_INVALID /* no encryption */ 1103 , 0 /* antenna mode */ 1104 , HAL_TXDESC_NOACK /* no ack for beacons */ 1105 , 0 /* rts/cts rate */ 1106 , 0 /* rts/cts duration */ 1107 ); 1108 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1109 /* XXX verify mbuf data area covers this roundup */ 1110 ath_hal_filltxdesc(ah, ds 1111 , roundup(bf->bf_segs[0].ds_len, 4) /* buffer length */ 1112 , AH_TRUE /* first segment */ 1113 , AH_TRUE /* last segment */ 1114 ); 1115 1116 return 0; 1117 } 1118 1119 static void 1120 ath_beacon_proc(void *arg, int pending) 1121 { 1122 struct ath_softc *sc = arg; 1123 struct ieee80211com *ic = &sc->sc_ic; 1124 struct ath_buf *bf = sc->sc_bcbuf; 1125 struct ath_hal *ah = sc->sc_ah; 1126 1127 DPRINTF2(("%s: pending %u\n", __func__, pending)); 1128 if (ic->ic_opmode == IEEE80211_M_STA || 1129 bf == NULL || bf->bf_m == NULL) { 1130 DPRINTF(("%s: ic_flags=%x bf=%p bf_m=%p\n", 1131 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL)); 1132 return; 1133 } 1134 /* TODO: update beacon to reflect PS poll state */ 1135 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1136 DPRINTF(("%s: beacon queue %u did not stop?", 1137 __func__, sc->sc_bhalq)); 1138 return; /* busy, XXX is this right? */ 1139 } 1140 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1141 1142 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 1143 ath_hal_txstart(ah, sc->sc_bhalq); 1144 DPRINTF2(("%s: TXDP%u = %p (%p)\n", __func__, 1145 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1146 } 1147 1148 static void 1149 ath_beacon_free(struct ath_softc *sc) 1150 { 1151 struct ath_buf *bf = sc->sc_bcbuf; 1152 1153 if (bf->bf_m != NULL) { 1154 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1155 m_freem(bf->bf_m); 1156 bf->bf_m = NULL; 1157 bf->bf_node = NULL; 1158 } 1159 } 1160 1161 /* 1162 * Configure the beacon and sleep timers. 1163 * 1164 * When operating as an AP this resets the TSF and sets 1165 * up the hardware to notify us when we need to issue beacons. 1166 * 1167 * When operating in station mode this sets up the beacon 1168 * timers according to the timestamp of the last received 1169 * beacon and the current TSF, configures PCF and DTIM 1170 * handling, programs the sleep registers so the hardware 1171 * will wakeup in time to receive beacons, and configures 1172 * the beacon miss handling so we'll receive a BMISS 1173 * interrupt when we stop seeing beacons from the AP 1174 * we've associated with. 1175 */ 1176 static void 1177 ath_beacon_config(struct ath_softc *sc) 1178 { 1179 struct ath_hal *ah = sc->sc_ah; 1180 struct ieee80211com *ic = &sc->sc_ic; 1181 struct ieee80211_node *ni = ic->ic_bss; 1182 u_int32_t nexttbtt; 1183 1184 nexttbtt = (LE_READ_4(ni->ni_tstamp + 4) << 22) | 1185 (LE_READ_4(ni->ni_tstamp) >> 10); 1186 DPRINTF(("%s: nexttbtt=%u\n", __func__, nexttbtt)); 1187 nexttbtt += ni->ni_intval; 1188 if (ic->ic_opmode == IEEE80211_M_STA) { 1189 HAL_BEACON_STATE bs; 1190 u_int32_t bmisstime; 1191 1192 /* NB: no PCF support right now */ 1193 memset(&bs, 0, sizeof(bs)); 1194 bs.bs_intval = ni->ni_intval; 1195 bs.bs_nexttbtt = nexttbtt; 1196 bs.bs_dtimperiod = bs.bs_intval; 1197 bs.bs_nextdtim = nexttbtt; 1198 /* 1199 * Calculate the number of consecutive beacons to miss 1200 * before taking a BMISS interrupt. The configuration 1201 * is specified in ms, so we need to convert that to 1202 * TU's and then calculate based on the beacon interval. 1203 * Note that we clamp the result to at most 10 beacons. 1204 */ 1205 bmisstime = (ic->ic_bmisstimeout * 1000) / 1024; 1206 bs.bs_bmissthreshold = howmany(bmisstime,ni->ni_intval); 1207 if (bs.bs_bmissthreshold > 10) 1208 bs.bs_bmissthreshold = 10; 1209 else if (bs.bs_bmissthreshold <= 0) 1210 bs.bs_bmissthreshold = 1; 1211 1212 /* 1213 * Calculate sleep duration. The configuration is 1214 * given in ms. We insure a multiple of the beacon 1215 * period is used. Also, if the sleep duration is 1216 * greater than the DTIM period then it makes senses 1217 * to make it a multiple of that. 1218 * 1219 * XXX fixed at 100ms 1220 */ 1221 bs.bs_sleepduration = 1222 roundup((100 * 1000) / 1024, bs.bs_intval); 1223 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1224 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1225 1226 DPRINTF(("%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u\n" 1227 , __func__ 1228 , bs.bs_intval 1229 , bs.bs_nexttbtt 1230 , bs.bs_dtimperiod 1231 , bs.bs_nextdtim 1232 , bs.bs_bmissthreshold 1233 , bs.bs_sleepduration 1234 )); 1235 ath_hal_intrset(ah, 0); 1236 /* 1237 * Reset our tsf so the hardware will update the 1238 * tsf register to reflect timestamps found in 1239 * received beacons. 1240 */ 1241 ath_hal_resettsf(ah); 1242 ath_hal_beacontimers(ah, &bs, 0/*XXX*/, 0, 0); 1243 sc->sc_imask |= HAL_INT_BMISS; 1244 ath_hal_intrset(ah, sc->sc_imask); 1245 } else { 1246 DPRINTF(("%s: intval %u nexttbtt %u\n", 1247 __func__, ni->ni_intval, nexttbtt)); 1248 ath_hal_intrset(ah, 0); 1249 ath_hal_beaconinit(ah, ic->ic_opmode, 1250 nexttbtt, ni->ni_intval); 1251 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1252 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1253 ath_hal_intrset(ah, sc->sc_imask); 1254 } 1255 } 1256 1257 static void 1258 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1259 { 1260 bus_addr_t *paddr = (bus_addr_t*) arg; 1261 *paddr = segs->ds_addr; 1262 } 1263 1264 static int 1265 ath_desc_alloc(struct ath_softc *sc) 1266 { 1267 int i, bsize, error; 1268 struct ath_desc *ds; 1269 struct ath_buf *bf; 1270 1271 /* allocate descriptors */ 1272 sc->sc_desc_len = sizeof(struct ath_desc) * 1273 (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + 1); 1274 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1275 if (error != 0) 1276 return error; 1277 1278 error = bus_dmamem_alloc(sc->sc_dmat, (void**) &sc->sc_desc, 1279 BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1280 if (error != 0) 1281 goto fail0; 1282 1283 error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, 1284 sc->sc_desc, sc->sc_desc_len, 1285 ath_load_cb, &sc->sc_desc_paddr, 1286 BUS_DMA_NOWAIT); 1287 if (error != 0) 1288 goto fail1; 1289 1290 ds = sc->sc_desc; 1291 DPRINTF(("ath_desc_alloc: DMA map: %p (%d) -> %p (%lu)\n", 1292 ds, sc->sc_desc_len, 1293 (caddr_t) sc->sc_desc_paddr, /*XXX*/ (u_long) sc->sc_desc_len)); 1294 1295 /* allocate buffers */ 1296 bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 1); 1297 bf = malloc(bsize, M_DEVBUF, M_NOWAIT | M_ZERO); 1298 if (bf == NULL) 1299 goto fail2; 1300 sc->sc_bufptr = bf; 1301 1302 TAILQ_INIT(&sc->sc_rxbuf); 1303 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 1304 bf->bf_desc = ds; 1305 bf->bf_daddr = sc->sc_desc_paddr + 1306 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1307 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1308 &bf->bf_dmamap); 1309 if (error != 0) 1310 break; 1311 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1312 } 1313 1314 TAILQ_INIT(&sc->sc_txbuf); 1315 for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { 1316 bf->bf_desc = ds; 1317 bf->bf_daddr = sc->sc_desc_paddr + 1318 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1319 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1320 &bf->bf_dmamap); 1321 if (error != 0) 1322 break; 1323 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1324 } 1325 TAILQ_INIT(&sc->sc_txq); 1326 1327 /* beacon buffer */ 1328 bf->bf_desc = ds; 1329 bf->bf_daddr = sc->sc_desc_paddr + ((caddr_t)ds - (caddr_t)sc->sc_desc); 1330 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &bf->bf_dmamap); 1331 if (error != 0) 1332 return error; 1333 sc->sc_bcbuf = bf; 1334 return 0; 1335 1336 fail2: 1337 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1338 fail1: 1339 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1340 fail0: 1341 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1342 sc->sc_ddmamap = NULL; 1343 return error; 1344 } 1345 1346 static void 1347 ath_desc_free(struct ath_softc *sc) 1348 { 1349 struct ath_buf *bf; 1350 1351 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1352 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1353 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1354 1355 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1356 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1357 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1358 m_freem(bf->bf_m); 1359 } 1360 TAILQ_FOREACH(bf, &sc->sc_txbuf, bf_list) 1361 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1362 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1363 if (bf->bf_m) { 1364 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1365 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1366 m_freem(bf->bf_m); 1367 bf->bf_m = NULL; 1368 } 1369 } 1370 if (sc->sc_bcbuf != NULL) { 1371 bus_dmamap_unload(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1372 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1373 sc->sc_bcbuf = NULL; 1374 } 1375 1376 TAILQ_INIT(&sc->sc_rxbuf); 1377 TAILQ_INIT(&sc->sc_txbuf); 1378 TAILQ_INIT(&sc->sc_txq); 1379 free(sc->sc_bufptr, M_DEVBUF); 1380 sc->sc_bufptr = NULL; 1381 } 1382 1383 static struct ieee80211_node * 1384 ath_node_alloc(struct ieee80211com *ic) 1385 { 1386 struct ath_node *an = 1387 malloc(sizeof(struct ath_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1388 return an ? &an->an_node : NULL; 1389 } 1390 1391 static void 1392 ath_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 1393 { 1394 struct ath_softc *sc = ic->ic_if.if_softc; 1395 struct ath_buf *bf; 1396 1397 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1398 if (bf->bf_node == ni) 1399 bf->bf_node = NULL; 1400 } 1401 free(ni, M_DEVBUF); 1402 } 1403 1404 static void 1405 ath_node_copy(struct ieee80211com *ic, 1406 struct ieee80211_node *dst, const struct ieee80211_node *src) 1407 { 1408 *(struct ath_node *)dst = *(const struct ath_node *)src; 1409 } 1410 1411 static int 1412 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 1413 { 1414 struct ath_hal *ah = sc->sc_ah; 1415 int error; 1416 struct mbuf *m; 1417 struct ath_desc *ds; 1418 1419 m = bf->bf_m; 1420 if (m == NULL) { 1421 /* 1422 * NB: by assigning a page to the rx dma buffer we 1423 * implicitly satisfy the Atheros requirement that 1424 * this buffer be cache-line-aligned and sized to be 1425 * multiple of the cache line size. Not doing this 1426 * causes weird stuff to happen (for the 5210 at least). 1427 */ 1428 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1429 if (m == NULL) { 1430 DPRINTF(("ath_rxbuf_init: no mbuf/cluster\n")); 1431 sc->sc_stats.ast_rx_nombuf++; 1432 return ENOMEM; 1433 } 1434 bf->bf_m = m; 1435 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1436 1437 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1438 ath_mbuf_load_cb, bf, 1439 BUS_DMA_NOWAIT); 1440 if (error != 0) { 1441 DPRINTF(("ath_rxbuf_init: bus_dmamap_load_mbuf failed;" 1442 " error %d\n", error)); 1443 sc->sc_stats.ast_rx_busdma++; 1444 return error; 1445 } 1446 KASSERT(bf->bf_nseg == 1, 1447 ("ath_rxbuf_init: multi-segment packet; nseg %u", 1448 bf->bf_nseg)); 1449 } 1450 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 1451 1452 /* setup descriptors */ 1453 ds = bf->bf_desc; 1454 ds->ds_link = 0; 1455 ds->ds_data = bf->bf_segs[0].ds_addr; 1456 ath_hal_setuprxdesc(ah, ds 1457 , m->m_len /* buffer size */ 1458 , 0 1459 ); 1460 1461 if (sc->sc_rxlink != NULL) 1462 *sc->sc_rxlink = bf->bf_daddr; 1463 sc->sc_rxlink = &ds->ds_link; 1464 return 0; 1465 } 1466 1467 static void 1468 ath_rx_proc(void *arg, int npending) 1469 { 1470 struct ath_softc *sc = arg; 1471 struct ath_buf *bf; 1472 struct ieee80211com *ic = &sc->sc_ic; 1473 struct ifnet *ifp = &ic->ic_if; 1474 struct ath_hal *ah = sc->sc_ah; 1475 struct ath_desc *ds; 1476 struct mbuf *m; 1477 struct ieee80211_frame *wh, whbuf; 1478 struct ieee80211_node *ni; 1479 int len; 1480 u_int phyerr; 1481 HAL_STATUS status; 1482 1483 DPRINTF2(("ath_rx_proc: pending %u\n", npending)); 1484 do { 1485 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1486 if (bf == NULL) { /* NB: shouldn't happen */ 1487 if_printf(ifp, "ath_rx_proc: no buffer!\n"); 1488 break; 1489 } 1490 m = bf->bf_m; 1491 if (m == NULL) { /* NB: shouldn't happen */ 1492 if_printf(ifp, "ath_rx_proc: no mbuf!\n"); 1493 continue; 1494 } 1495 ds = bf->bf_desc; 1496 status = ath_hal_rxprocdesc(ah, ds); 1497 #ifdef AR_DEBUG 1498 if (ath_debug > 1) 1499 ath_printrxbuf(bf, status == HAL_OK); 1500 #endif 1501 if (status == HAL_EINPROGRESS) 1502 break; 1503 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1504 if (ds->ds_rxstat.rs_status != 0) { 1505 ifp->if_ierrors++; 1506 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 1507 sc->sc_stats.ast_rx_crcerr++; 1508 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 1509 sc->sc_stats.ast_rx_fifoerr++; 1510 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) 1511 sc->sc_stats.ast_rx_badcrypt++; 1512 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 1513 sc->sc_stats.ast_rx_phyerr++; 1514 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 1515 sc->sc_stats.ast_rx_phy[phyerr]++; 1516 } 1517 goto rx_next; 1518 } 1519 1520 len = ds->ds_rxstat.rs_datalen; 1521 if (len < sizeof(struct ieee80211_frame)) { 1522 DPRINTF(("ath_rx_proc: short packet %d\n", len)); 1523 sc->sc_stats.ast_rx_tooshort++; 1524 goto rx_next; 1525 } 1526 1527 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 1528 BUS_DMASYNC_POSTREAD); 1529 1530 wh = mtod(m, struct ieee80211_frame *); 1531 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1532 IEEE80211_FC0_TYPE_CTL && 1533 ic->ic_opmode != IEEE80211_M_MONITOR) { 1534 /* 1535 * Discard control frame when not in monitor mode. 1536 */ 1537 DPRINTF(("ath_rx_proc: control frame\n")); 1538 sc->sc_stats.ast_rx_ctl++; 1539 goto rx_next; 1540 } 1541 1542 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1543 bf->bf_m = NULL; 1544 m->m_pkthdr.rcvif = ifp; 1545 m->m_pkthdr.len = m->m_len = len; 1546 1547 if (sc->sc_drvbpf) { 1548 struct mbuf *mb; 1549 1550 /* XXX pre-allocate space when setting up recv's */ 1551 MGETHDR(mb, M_DONTWAIT, m->m_type); 1552 if (mb != NULL) { 1553 sc->sc_rx_th.wr_rate = 1554 sc->sc_hwmap[ds->ds_rxstat.rs_rate]; 1555 sc->sc_rx_th.wr_antsignal = 1556 ds->ds_rxstat.rs_rssi; 1557 sc->sc_rx_th.wr_antenna = 1558 ds->ds_rxstat.rs_antenna; 1559 /* XXX TSF */ 1560 1561 (void) m_dup_pkthdr(mb, m, M_DONTWAIT); 1562 mb->m_next = m; 1563 mb->m_data = (caddr_t)&sc->sc_rx_th; 1564 mb->m_len = sizeof(sc->sc_rx_th); 1565 mb->m_pkthdr.len += mb->m_len; 1566 bpf_mtap(sc->sc_drvbpf, mb); 1567 m_free(mb); 1568 } 1569 } 1570 1571 m_adj(m, -IEEE80211_CRC_LEN); 1572 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1573 /* 1574 * WEP is decrypted by hardware. Clear WEP bit 1575 * and trim WEP header for ieee80211_input(). 1576 */ 1577 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 1578 memcpy(&whbuf, wh, sizeof(whbuf)); 1579 m_adj(m, IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN); 1580 memcpy(mtod(m, caddr_t), &whbuf, sizeof(whbuf)); 1581 /* 1582 * Also trim WEP ICV from the tail. 1583 */ 1584 m_adj(m, -IEEE80211_WEP_CRCLEN); 1585 } 1586 1587 /* 1588 * Locate the node for sender, track state, and 1589 * then pass this node (referenced) up to the 802.11 1590 * layer for its use. We are required to pass 1591 * something so we fall back to ic_bss when this frame 1592 * is from an unknown sender. 1593 */ 1594 if (ic->ic_opmode != IEEE80211_M_STA) { 1595 ni = ieee80211_find_node(ic, wh->i_addr2); 1596 if (ni == NULL) 1597 ni = ieee80211_ref_node(ic->ic_bss); 1598 } else 1599 ni = ieee80211_ref_node(ic->ic_bss); 1600 ATH_NODE(ni)->an_rx_antenna = ds->ds_rxstat.rs_antenna; 1601 /* 1602 * Send frame up for processing. 1603 */ 1604 ieee80211_input(ifp, m, ni, 1605 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 1606 /* 1607 * The frame may have caused the node to be marked for 1608 * reclamation (e.g. in response to a DEAUTH message) 1609 * so use free_node here instead of unref_node. 1610 */ 1611 if (ni == ic->ic_bss) 1612 ieee80211_unref_node(&ni); 1613 else 1614 ieee80211_free_node(ic, ni); 1615 rx_next: 1616 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1617 } while (ath_rxbuf_init(sc, bf) == 0); 1618 1619 ath_hal_rxmonitor(ah); /* rx signal state monitoring */ 1620 ath_hal_rxena(ah); /* in case of RXEOL */ 1621 } 1622 1623 /* 1624 * XXX Size of an ACK control frame in bytes. 1625 */ 1626 #define IEEE80211_ACK_SIZE (2+2+IEEE80211_ADDR_LEN+4) 1627 1628 static int 1629 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 1630 struct mbuf *m0) 1631 { 1632 struct ieee80211com *ic = &sc->sc_ic; 1633 struct ath_hal *ah = sc->sc_ah; 1634 struct ifnet *ifp = &sc->sc_ic.ic_if; 1635 int i, error, iswep, hdrlen, pktlen; 1636 u_int8_t rix, cix, txrate, ctsrate; 1637 struct ath_desc *ds; 1638 struct mbuf *m; 1639 struct ieee80211_frame *wh; 1640 u_int32_t iv; 1641 u_int8_t *ivp; 1642 u_int8_t hdrbuf[sizeof(struct ieee80211_frame) + 1643 IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN]; 1644 u_int subtype, flags, ctsduration, antenna; 1645 HAL_PKT_TYPE atype; 1646 const HAL_RATE_TABLE *rt; 1647 HAL_BOOL shortPreamble; 1648 struct ath_node *an; 1649 1650 wh = mtod(m0, struct ieee80211_frame *); 1651 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1652 hdrlen = sizeof(struct ieee80211_frame); 1653 pktlen = m0->m_pkthdr.len; 1654 1655 if (iswep) { 1656 memcpy(hdrbuf, mtod(m0, caddr_t), hdrlen); 1657 m_adj(m0, hdrlen); 1658 M_PREPEND(m0, sizeof(hdrbuf), M_DONTWAIT); 1659 if (m0 == NULL) { 1660 sc->sc_stats.ast_tx_nombuf++; 1661 return ENOMEM; 1662 } 1663 ivp = hdrbuf + hdrlen; 1664 /* 1665 * XXX 1666 * IV must not duplicate during the lifetime of the key. 1667 * But no mechanism to renew keys is defined in IEEE 802.11 1668 * WEP. And IV may be duplicated between other stations 1669 * because of the session key itself is shared. 1670 * So we use pseudo random IV for now, though it is not the 1671 * right way. 1672 */ 1673 iv = arc4random(); 1674 for (i = 0; i < IEEE80211_WEP_IVLEN; i++) { 1675 ivp[i] = iv; 1676 iv >>= 8; 1677 } 1678 ivp[i] = sc->sc_ic.ic_wep_txkey << 6; /* Key ID and pad */ 1679 memcpy(mtod(m0, caddr_t), hdrbuf, sizeof(hdrbuf)); 1680 /* 1681 * The ICV length must be included into hdrlen and pktlen. 1682 */ 1683 hdrlen = sizeof(hdrbuf) + IEEE80211_WEP_CRCLEN; 1684 pktlen = m0->m_pkthdr.len + IEEE80211_WEP_CRCLEN; 1685 } 1686 pktlen += IEEE80211_CRC_LEN; 1687 1688 /* 1689 * Load the DMA map so any coalescing is done. This 1690 * also calculates the number of descriptors we need. 1691 */ 1692 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1693 ath_mbuf_load_cb, bf, 1694 BUS_DMA_NOWAIT); 1695 if (error != 0) { 1696 sc->sc_stats.ast_tx_busdma++; 1697 m_freem(m0); 1698 return error; 1699 } 1700 /* 1701 * Discard null packets and check for packets that 1702 * require too many TX descriptors. We try to convert 1703 * the latter to a cluster. 1704 */ 1705 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 1706 sc->sc_stats.ast_tx_linear++; 1707 MGETHDR(m, M_DONTWAIT, MT_DATA); 1708 if (m == NULL) { 1709 sc->sc_stats.ast_tx_nombuf++; 1710 m_freem(m0); 1711 return ENOMEM; 1712 } 1713 M_MOVE_PKTHDR(m, m0); 1714 MCLGET(m, M_DONTWAIT); 1715 if ((m->m_flags & M_EXT) == 0) { 1716 sc->sc_stats.ast_tx_nomcl++; 1717 m_freem(m0); 1718 m_free(m); 1719 return ENOMEM; 1720 } 1721 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1722 m_freem(m0); 1723 m->m_len = m->m_pkthdr.len; 1724 m0 = m; 1725 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1726 ath_mbuf_load_cb, bf, 1727 BUS_DMA_NOWAIT); 1728 if (error != 0) { 1729 sc->sc_stats.ast_tx_busdma++; 1730 m_freem(m0); 1731 return error; 1732 } 1733 KASSERT(bf->bf_nseg == 1, 1734 ("ath_tx_start: packet not one segment; nseg %u", 1735 bf->bf_nseg)); 1736 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 1737 sc->sc_stats.ast_tx_nodata++; 1738 m_freem(m0); 1739 return EIO; 1740 } 1741 DPRINTF2(("ath_tx_start: m %p len %u\n", m0, pktlen)); 1742 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1743 bf->bf_m = m0; 1744 bf->bf_node = ni; /* NB: held reference */ 1745 1746 /* setup descriptors */ 1747 ds = bf->bf_desc; 1748 rt = sc->sc_currates; 1749 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1750 1751 /* 1752 * Calculate Atheros packet type from IEEE80211 packet header 1753 * and setup for rate calculations. 1754 */ 1755 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1756 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1757 case IEEE80211_FC0_TYPE_MGT: 1758 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1759 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1760 atype = HAL_PKT_TYPE_BEACON; 1761 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1762 atype = HAL_PKT_TYPE_PROBE_RESP; 1763 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1764 atype = HAL_PKT_TYPE_ATIM; 1765 rix = 0; /* XXX lowest rate */ 1766 break; 1767 case IEEE80211_FC0_TYPE_CTL: 1768 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1769 if (subtype == IEEE80211_FC0_SUBTYPE_PS_POLL) 1770 atype = HAL_PKT_TYPE_PSPOLL; 1771 rix = 0; /* XXX lowest rate */ 1772 break; 1773 default: 1774 rix = sc->sc_rixmap[ni->ni_rates.rs_rates[ni->ni_txrate] & 1775 IEEE80211_RATE_VAL]; 1776 if (rix == 0xff) { 1777 if_printf(ifp, "bogus xmit rate 0x%x\n", 1778 ni->ni_rates.rs_rates[ni->ni_txrate]); 1779 sc->sc_stats.ast_tx_badrate++; 1780 m_freem(m0); 1781 return EIO; 1782 } 1783 break; 1784 } 1785 /* 1786 * NB: the 802.11 layer marks whether or not we should 1787 * use short preamble based on the current mode and 1788 * negotiated parameters. 1789 */ 1790 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1791 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1792 txrate = rt->info[rix].rateCode | rt->info[rix].shortPreamble; 1793 shortPreamble = AH_TRUE; 1794 sc->sc_stats.ast_tx_shortpre++; 1795 } else { 1796 txrate = rt->info[rix].rateCode; 1797 shortPreamble = AH_FALSE; 1798 } 1799 1800 /* 1801 * Calculate miscellaneous flags. 1802 */ 1803 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for wep errors */ 1804 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1805 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1806 sc->sc_stats.ast_tx_noack++; 1807 } else if (pktlen > ic->ic_rtsthreshold) { 1808 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1809 sc->sc_stats.ast_tx_rts++; 1810 } 1811 1812 /* 1813 * Calculate duration. This logically belongs in the 802.11 1814 * layer but it lacks sufficient information to calculate it. 1815 */ 1816 if ((flags & HAL_TXDESC_NOACK) == 0 && 1817 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 1818 u_int16_t dur; 1819 /* 1820 * XXX not right with fragmentation. 1821 */ 1822 dur = ath_hal_computetxtime(ah, rt, IEEE80211_ACK_SIZE, 1823 rix, shortPreamble); 1824 *((u_int16_t*) wh->i_dur) = htole16(dur); 1825 } 1826 1827 /* 1828 * Calculate RTS/CTS rate and duration if needed. 1829 */ 1830 ctsduration = 0; 1831 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 1832 /* 1833 * CTS transmit rate is derived from the transmit rate 1834 * by looking in the h/w rate table. We must also factor 1835 * in whether or not a short preamble is to be used. 1836 */ 1837 cix = rt->info[rix].controlRate; 1838 ctsrate = rt->info[cix].rateCode; 1839 if (shortPreamble) 1840 ctsrate |= rt->info[cix].shortPreamble; 1841 /* 1842 * Compute the transmit duration based on the size 1843 * of an ACK frame. We call into the HAL to do the 1844 * computation since it depends on the characteristics 1845 * of the actual PHY being used. 1846 */ 1847 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 1848 ctsduration += ath_hal_computetxtime(ah, 1849 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 1850 } 1851 /* SIFS + data */ 1852 ctsduration += ath_hal_computetxtime(ah, 1853 rt, pktlen, rix, shortPreamble); 1854 if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 1855 ctsduration += ath_hal_computetxtime(ah, 1856 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 1857 } 1858 } else 1859 ctsrate = 0; 1860 1861 /* 1862 * For now use the antenna on which the last good 1863 * frame was received on. We assume this field is 1864 * initialized to 0 which gives us ``auto'' or the 1865 * ``default'' antenna. 1866 */ 1867 an = (struct ath_node *) ni; 1868 if (an->an_tx_antenna) 1869 antenna = an->an_tx_antenna; 1870 else 1871 antenna = an->an_rx_antenna; 1872 1873 /* 1874 * Formulate first tx descriptor with tx controls. 1875 */ 1876 /* XXX check return value? */ 1877 ath_hal_setuptxdesc(ah, ds 1878 , pktlen /* packet length */ 1879 , hdrlen /* header length */ 1880 , atype /* Atheros packet type */ 1881 , 60 /* txpower XXX */ 1882 , txrate, 1+10 /* series 0 rate/tries */ 1883 , iswep ? sc->sc_ic.ic_wep_txkey : HAL_TXKEYIX_INVALID 1884 , antenna /* antenna mode */ 1885 , flags /* flags */ 1886 , ctsrate /* rts/cts rate */ 1887 , ctsduration /* rts/cts duration */ 1888 ); 1889 #ifdef notyet 1890 ath_hal_setupxtxdesc(ah, ds 1891 , AH_FALSE /* short preamble */ 1892 , 0, 0 /* series 1 rate/tries */ 1893 , 0, 0 /* series 2 rate/tries */ 1894 , 0, 0 /* series 3 rate/tries */ 1895 ); 1896 #endif 1897 /* 1898 * Fillin the remainder of the descriptor info. 1899 */ 1900 for (i = 0; i < bf->bf_nseg; i++, ds++) { 1901 ds->ds_data = bf->bf_segs[i].ds_addr; 1902 if (i == bf->bf_nseg - 1) 1903 ds->ds_link = 0; 1904 else 1905 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 1906 ath_hal_filltxdesc(ah, ds 1907 , bf->bf_segs[i].ds_len /* segment length */ 1908 , i == 0 /* first segment */ 1909 , i == bf->bf_nseg - 1 /* last segment */ 1910 ); 1911 DPRINTF2(("ath_tx_start: %d: %08x %08x %08x %08x %08x %08x\n", 1912 i, ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, 1913 ds->ds_hw[0], ds->ds_hw[1])); 1914 } 1915 1916 /* 1917 * Insert the frame on the outbound list and 1918 * pass it on to the hardware. 1919 */ 1920 mtx_lock(&sc->sc_txqlock); 1921 TAILQ_INSERT_TAIL(&sc->sc_txq, bf, bf_list); 1922 if (sc->sc_txlink == NULL) { 1923 ath_hal_puttxbuf(ah, sc->sc_txhalq, bf->bf_daddr); 1924 DPRINTF2(("ath_tx_start: TXDP0 = %p (%p)\n", 1925 (caddr_t)bf->bf_daddr, bf->bf_desc)); 1926 } else { 1927 *sc->sc_txlink = bf->bf_daddr; 1928 DPRINTF2(("ath_tx_start: link(%p)=%p (%p)\n", 1929 sc->sc_txlink, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1930 } 1931 sc->sc_txlink = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 1932 mtx_unlock(&sc->sc_txqlock); 1933 1934 ath_hal_txstart(ah, sc->sc_txhalq); 1935 return 0; 1936 } 1937 1938 static void 1939 ath_tx_proc(void *arg, int npending) 1940 { 1941 struct ath_softc *sc = arg; 1942 struct ath_hal *ah = sc->sc_ah; 1943 struct ath_buf *bf; 1944 struct ieee80211com *ic = &sc->sc_ic; 1945 struct ifnet *ifp = &ic->ic_if; 1946 struct ath_desc *ds; 1947 struct ieee80211_node *ni; 1948 struct ath_node *an; 1949 int sr, lr; 1950 HAL_STATUS status; 1951 1952 DPRINTF2(("ath_tx_proc: pending %u tx queue %p, link %p\n", 1953 npending, (caddr_t) ath_hal_gettxbuf(sc->sc_ah, sc->sc_txhalq), 1954 sc->sc_txlink)); 1955 for (;;) { 1956 mtx_lock(&sc->sc_txqlock); 1957 bf = TAILQ_FIRST(&sc->sc_txq); 1958 if (bf == NULL) { 1959 sc->sc_txlink = NULL; 1960 mtx_unlock(&sc->sc_txqlock); 1961 break; 1962 } 1963 /* only the last descriptor is needed */ 1964 ds = &bf->bf_desc[bf->bf_nseg - 1]; 1965 status = ath_hal_txprocdesc(ah, ds); 1966 #ifdef AR_DEBUG 1967 if (ath_debug > 1) 1968 ath_printtxbuf(bf, status == HAL_OK); 1969 #endif 1970 if (status == HAL_EINPROGRESS) { 1971 mtx_unlock(&sc->sc_txqlock); 1972 break; 1973 } 1974 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 1975 mtx_unlock(&sc->sc_txqlock); 1976 1977 ni = bf->bf_node; 1978 if (ni != NULL) { 1979 an = (struct ath_node *) ni; 1980 if (ds->ds_txstat.ts_status == 0) { 1981 an->an_tx_ok++; 1982 an->an_tx_antenna = ds->ds_txstat.ts_antenna; 1983 } else { 1984 an->an_tx_err++; 1985 ifp->if_oerrors++; 1986 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 1987 sc->sc_stats.ast_tx_xretries++; 1988 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 1989 sc->sc_stats.ast_tx_fifoerr++; 1990 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 1991 sc->sc_stats.ast_tx_filtered++; 1992 an->an_tx_antenna = 0; /* invalidate */ 1993 } 1994 sr = ds->ds_txstat.ts_shortretry; 1995 lr = ds->ds_txstat.ts_longretry; 1996 sc->sc_stats.ast_tx_shortretry += sr; 1997 sc->sc_stats.ast_tx_longretry += lr; 1998 if (sr + lr) 1999 an->an_tx_retr++; 2000 /* 2001 * Reclaim reference to node. 2002 * 2003 * NB: the node may be reclaimed here if, for example 2004 * this is a DEAUTH message that was sent and the 2005 * node was timed out due to inactivity. 2006 */ 2007 if (ni != ic->ic_bss) 2008 ieee80211_free_node(ic, ni); 2009 } 2010 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2011 BUS_DMASYNC_POSTWRITE); 2012 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2013 m_freem(bf->bf_m); 2014 bf->bf_m = NULL; 2015 bf->bf_node = NULL; 2016 2017 mtx_lock(&sc->sc_txbuflock); 2018 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2019 mtx_unlock(&sc->sc_txbuflock); 2020 } 2021 ifp->if_flags &= ~IFF_OACTIVE; 2022 sc->sc_tx_timer = 0; 2023 2024 ath_start(ifp); 2025 } 2026 2027 /* 2028 * Drain the transmit queue and reclaim resources. 2029 */ 2030 static void 2031 ath_draintxq(struct ath_softc *sc) 2032 { 2033 struct ath_hal *ah = sc->sc_ah; 2034 struct ifnet *ifp = &sc->sc_ic.ic_if; 2035 struct ath_buf *bf; 2036 2037 /* XXX return value */ 2038 if (!sc->sc_invalid) { 2039 /* don't touch the hardware if marked invalid */ 2040 (void) ath_hal_stoptxdma(ah, sc->sc_txhalq); 2041 DPRINTF(("ath_draintxq: tx queue %p, link %p\n", 2042 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_txhalq), 2043 sc->sc_txlink)); 2044 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 2045 DPRINTF(("ath_draintxq: beacon queue %p\n", 2046 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq))); 2047 } 2048 for (;;) { 2049 mtx_lock(&sc->sc_txqlock); 2050 bf = TAILQ_FIRST(&sc->sc_txq); 2051 if (bf == NULL) { 2052 sc->sc_txlink = NULL; 2053 mtx_unlock(&sc->sc_txqlock); 2054 break; 2055 } 2056 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2057 mtx_unlock(&sc->sc_txqlock); 2058 #ifdef AR_DEBUG 2059 if (ath_debug) 2060 ath_printtxbuf(bf, 2061 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 2062 #endif /* AR_DEBUG */ 2063 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2064 m_freem(bf->bf_m); 2065 bf->bf_m = NULL; 2066 bf->bf_node = NULL; 2067 mtx_lock(&sc->sc_txbuflock); 2068 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2069 mtx_unlock(&sc->sc_txbuflock); 2070 } 2071 ifp->if_flags &= ~IFF_OACTIVE; 2072 sc->sc_tx_timer = 0; 2073 } 2074 2075 /* 2076 * Disable the receive h/w in preparation for a reset. 2077 */ 2078 static void 2079 ath_stoprecv(struct ath_softc *sc) 2080 { 2081 struct ath_hal *ah = sc->sc_ah; 2082 2083 ath_hal_stoppcurecv(ah); /* disable PCU */ 2084 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 2085 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 2086 DELAY(3000); /* long enough for 1 frame */ 2087 #ifdef AR_DEBUG 2088 if (ath_debug) { 2089 struct ath_buf *bf; 2090 2091 DPRINTF(("ath_stoprecv: rx queue %p, link %p\n", 2092 (caddr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink)); 2093 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2094 if (ath_hal_rxprocdesc(ah, bf->bf_desc) == HAL_OK) 2095 ath_printrxbuf(bf, 1); 2096 } 2097 } 2098 #endif 2099 sc->sc_rxlink = NULL; /* just in case */ 2100 } 2101 2102 /* 2103 * Enable the receive h/w following a reset. 2104 */ 2105 static int 2106 ath_startrecv(struct ath_softc *sc) 2107 { 2108 struct ath_hal *ah = sc->sc_ah; 2109 struct ath_buf *bf; 2110 2111 sc->sc_rxlink = NULL; 2112 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2113 int error = ath_rxbuf_init(sc, bf); 2114 if (error != 0) { 2115 DPRINTF(("ath_startrecv: ath_rxbuf_init failed %d\n", 2116 error)); 2117 return error; 2118 } 2119 } 2120 2121 bf = TAILQ_FIRST(&sc->sc_rxbuf); 2122 ath_hal_putrxbuf(ah, bf->bf_daddr); 2123 ath_hal_rxena(ah); /* enable recv descriptors */ 2124 ath_mode_init(sc); /* set filters, etc. */ 2125 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 2126 return 0; 2127 } 2128 2129 /* 2130 * Set/change channels. If the channel is really being changed, 2131 * it's done by resetting the chip. To accomplish this we must 2132 * first cleanup any pending DMA, then restart stuff after a la 2133 * ath_init. 2134 */ 2135 static int 2136 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 2137 { 2138 struct ath_hal *ah = sc->sc_ah; 2139 struct ieee80211com *ic = &sc->sc_ic; 2140 2141 DPRINTF(("ath_chan_set: %u (%u MHz) -> %u (%u MHz)\n", 2142 ieee80211_chan2ieee(ic, ic->ic_ibss_chan), 2143 ic->ic_ibss_chan->ic_freq, 2144 ieee80211_chan2ieee(ic, chan), chan->ic_freq)); 2145 if (chan != ic->ic_ibss_chan) { 2146 HAL_STATUS status; 2147 HAL_CHANNEL hchan; 2148 enum ieee80211_phymode mode; 2149 2150 /* 2151 * To switch channels clear any pending DMA operations; 2152 * wait long enough for the RX fifo to drain, reset the 2153 * hardware at the new frequency, and then re-enable 2154 * the relevant bits of the h/w. 2155 */ 2156 ath_hal_intrset(ah, 0); /* disable interrupts */ 2157 ath_draintxq(sc); /* clear pending tx frames */ 2158 ath_stoprecv(sc); /* turn off frame recv */ 2159 /* 2160 * Convert to a HAL channel description with 2161 * the flags constrained to reflect the current 2162 * operating mode. 2163 */ 2164 hchan.channel = chan->ic_freq; 2165 hchan.channelFlags = ath_chan2flags(ic, chan); 2166 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 2167 if_printf(&ic->ic_if, "ath_chan_set: unable to reset " 2168 "channel %u (%u Mhz)\n", 2169 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 2170 return EIO; 2171 } 2172 /* 2173 * Re-enable rx framework. 2174 */ 2175 if (ath_startrecv(sc) != 0) { 2176 if_printf(&ic->ic_if, 2177 "ath_chan_set: unable to restart recv logic\n"); 2178 return EIO; 2179 } 2180 2181 /* 2182 * Update BPF state. 2183 */ 2184 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 2185 htole16(chan->ic_freq); 2186 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 2187 htole16(chan->ic_flags); 2188 2189 /* 2190 * Change channels and update the h/w rate map 2191 * if we're switching; e.g. 11a to 11b/g. 2192 */ 2193 ic->ic_ibss_chan = chan; 2194 mode = ieee80211_chan2mode(ic, chan); 2195 if (mode != sc->sc_curmode) 2196 ath_setcurmode(sc, mode); 2197 2198 /* 2199 * Re-enable interrupts. 2200 */ 2201 ath_hal_intrset(ah, sc->sc_imask); 2202 } 2203 return 0; 2204 } 2205 2206 static void 2207 ath_next_scan(void *arg) 2208 { 2209 struct ath_softc *sc = arg; 2210 struct ieee80211com *ic = &sc->sc_ic; 2211 struct ifnet *ifp = &ic->ic_if; 2212 2213 if (ic->ic_state == IEEE80211_S_SCAN) 2214 ieee80211_next_scan(ifp); 2215 } 2216 2217 /* 2218 * Periodically recalibrate the PHY to account 2219 * for temperature/environment changes. 2220 */ 2221 static void 2222 ath_calibrate(void *arg) 2223 { 2224 struct ath_softc *sc = arg; 2225 struct ath_hal *ah = sc->sc_ah; 2226 struct ieee80211com *ic = &sc->sc_ic; 2227 struct ieee80211_channel *c; 2228 HAL_CHANNEL hchan; 2229 2230 sc->sc_stats.ast_per_cal++; 2231 2232 /* 2233 * Convert to a HAL channel description with the flags 2234 * constrained to reflect the current operating mode. 2235 */ 2236 c = ic->ic_ibss_chan; 2237 hchan.channel = c->ic_freq; 2238 hchan.channelFlags = ath_chan2flags(ic, c); 2239 2240 DPRINTF(("%s: channel %u/%x\n", __func__, c->ic_freq, c->ic_flags)); 2241 2242 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 2243 /* 2244 * Rfgain is out of bounds, reset the chip 2245 * to load new gain values. 2246 */ 2247 sc->sc_stats.ast_per_rfgain++; 2248 ath_reset(sc); 2249 } 2250 if (!ath_hal_calibrate(ah, &hchan)) { 2251 DPRINTF(("%s: calibration of channel %u failed\n", 2252 __func__, c->ic_freq)); 2253 sc->sc_stats.ast_per_calfail++; 2254 } 2255 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, ath_calibrate, sc); 2256 } 2257 2258 static int 2259 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2260 { 2261 struct ifnet *ifp = &ic->ic_if; 2262 struct ath_softc *sc = ifp->if_softc; 2263 struct ath_hal *ah = sc->sc_ah; 2264 struct ieee80211_node *ni; 2265 int i, error; 2266 u_int8_t *bssid; 2267 u_int32_t rfilt; 2268 static const HAL_LED_STATE leds[] = { 2269 HAL_LED_INIT, /* IEEE80211_S_INIT */ 2270 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 2271 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 2272 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 2273 HAL_LED_RUN, /* IEEE80211_S_RUN */ 2274 }; 2275 2276 DPRINTF(("%s: %s -> %s\n", __func__, 2277 ieee80211_state_name[ic->ic_state], 2278 ieee80211_state_name[nstate])); 2279 2280 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 2281 2282 if (nstate == IEEE80211_S_INIT) { 2283 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2284 ath_hal_intrset(ah, sc->sc_imask); 2285 callout_stop(&sc->sc_scan_ch); 2286 callout_stop(&sc->sc_cal_ch); 2287 return (*sc->sc_newstate)(ic, nstate, arg); 2288 } 2289 ni = ic->ic_bss; 2290 error = ath_chan_set(sc, ni->ni_chan); 2291 if (error != 0) 2292 goto bad; 2293 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 2294 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2295 if (ic->ic_opmode != IEEE80211_M_STA) 2296 rfilt |= HAL_RX_FILTER_PROBEREQ; 2297 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2298 (ifp->if_flags & IFF_PROMISC)) 2299 rfilt |= HAL_RX_FILTER_PROM; 2300 if (nstate == IEEE80211_S_SCAN) { 2301 callout_reset(&sc->sc_scan_ch, (hz * ath_dwelltime) / 1000, 2302 ath_next_scan, sc); 2303 bssid = ifp->if_broadcastaddr; 2304 rfilt |= HAL_RX_FILTER_BEACON; 2305 } else { 2306 callout_stop(&sc->sc_scan_ch); 2307 bssid = ni->ni_bssid; 2308 } 2309 ath_hal_setrxfilter(ah, rfilt); 2310 DPRINTF(("%s: RX filter 0x%x bssid %s\n", 2311 __func__, rfilt, ether_sprintf(bssid))); 2312 2313 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 2314 ath_hal_setassocid(ah, bssid, ni->ni_associd); 2315 else 2316 ath_hal_setassocid(ah, bssid, 0); 2317 if (ic->ic_flags & IEEE80211_F_WEPON) { 2318 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2319 if (ath_hal_keyisvalid(ah, i)) 2320 ath_hal_keysetmac(ah, i, bssid); 2321 } 2322 2323 if (nstate == IEEE80211_S_RUN) { 2324 DPRINTF(("%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 2325 "capinfo=0x%04x chan=%d\n" 2326 , __func__ 2327 , ic->ic_flags 2328 , ni->ni_intval 2329 , ether_sprintf(ni->ni_bssid) 2330 , ni->ni_capinfo 2331 , ieee80211_chan2ieee(ic, ni->ni_chan))); 2332 2333 /* 2334 * Allocate and setup the beacon frame for AP or adhoc mode. 2335 */ 2336 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2337 ic->ic_opmode == IEEE80211_M_IBSS) { 2338 error = ath_beacon_alloc(sc, ni); 2339 if (error != 0) 2340 goto bad; 2341 } 2342 2343 /* 2344 * Configure the beacon and sleep timers. 2345 */ 2346 ath_beacon_config(sc); 2347 2348 /* start periodic recalibration timer */ 2349 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, 2350 ath_calibrate, sc); 2351 } else { 2352 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2353 ath_hal_intrset(ah, sc->sc_imask); 2354 callout_stop(&sc->sc_cal_ch); /* no calibration */ 2355 } 2356 /* 2357 * Reset the rate control state. 2358 */ 2359 ath_rate_ctl_reset(sc, nstate); 2360 /* 2361 * Invoke the parent method to complete the work. 2362 */ 2363 return (*sc->sc_newstate)(ic, nstate, arg); 2364 bad: 2365 callout_stop(&sc->sc_scan_ch); 2366 callout_stop(&sc->sc_cal_ch); 2367 /* NB: do not invoke the parent */ 2368 return error; 2369 } 2370 2371 /* 2372 * Setup driver-specific state for a newly associated node. 2373 * Note that we're called also on a re-associate, the isnew 2374 * param tells us if this is the first time or not. 2375 */ 2376 static void 2377 ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2378 { 2379 if (isnew) { 2380 struct ath_node *an = (struct ath_node *) ni; 2381 2382 an->an_tx_ok = an->an_tx_err = 2383 an->an_tx_retr = an->an_tx_upper = 0; 2384 /* start with highest negotiated rate */ 2385 /* 2386 * XXX should do otherwise but only when 2387 * the rate control algorithm is better. 2388 */ 2389 KASSERT(ni->ni_rates.rs_nrates > 0, 2390 ("new association w/ no rates!")); 2391 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2392 } 2393 } 2394 2395 static int 2396 ath_getchannels(struct ath_softc *sc, u_int cc, HAL_BOOL outdoor) 2397 { 2398 struct ieee80211com *ic = &sc->sc_ic; 2399 struct ifnet *ifp = &ic->ic_if; 2400 struct ath_hal *ah = sc->sc_ah; 2401 HAL_CHANNEL *chans; 2402 int i, ix, nchan; 2403 2404 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 2405 M_TEMP, M_NOWAIT); 2406 if (chans == NULL) { 2407 if_printf(ifp, "unable to allocate channel table\n"); 2408 return ENOMEM; 2409 } 2410 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 2411 cc, HAL_MODE_ALL, outdoor)) { 2412 if_printf(ifp, "unable to collect channel list from hal\n"); 2413 free(chans, M_TEMP); 2414 return EINVAL; 2415 } 2416 2417 /* 2418 * Convert HAL channels to ieee80211 ones and insert 2419 * them in the table according to their channel number. 2420 */ 2421 for (i = 0; i < nchan; i++) { 2422 HAL_CHANNEL *c = &chans[i]; 2423 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 2424 if (ix > IEEE80211_CHAN_MAX) { 2425 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 2426 ix, c->channel, c->channelFlags); 2427 continue; 2428 } 2429 /* NB: flags are known to be compatible */ 2430 if (ic->ic_channels[ix].ic_freq == 0) { 2431 ic->ic_channels[ix].ic_freq = c->channel; 2432 ic->ic_channels[ix].ic_flags = c->channelFlags; 2433 } else { 2434 /* channels overlap; e.g. 11g and 11b */ 2435 ic->ic_channels[ix].ic_flags |= c->channelFlags; 2436 } 2437 } 2438 free(chans, M_TEMP); 2439 return 0; 2440 } 2441 2442 static int 2443 ath_rate_setup(struct ath_softc *sc, u_int mode) 2444 { 2445 struct ath_hal *ah = sc->sc_ah; 2446 struct ieee80211com *ic = &sc->sc_ic; 2447 const HAL_RATE_TABLE *rt; 2448 struct ieee80211_rateset *rs; 2449 int i, maxrates; 2450 2451 switch (mode) { 2452 case IEEE80211_MODE_11A: 2453 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 2454 break; 2455 case IEEE80211_MODE_11B: 2456 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 2457 break; 2458 case IEEE80211_MODE_11G: 2459 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 2460 break; 2461 case IEEE80211_MODE_TURBO: 2462 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 2463 break; 2464 default: 2465 DPRINTF(("%s: invalid mode %u\n", __func__, mode)); 2466 return 0; 2467 } 2468 rt = sc->sc_rates[mode]; 2469 if (rt == NULL) 2470 return 0; 2471 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 2472 DPRINTF(("%s: rate table too small (%u > %u)\n", 2473 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE)); 2474 maxrates = IEEE80211_RATE_MAXSIZE; 2475 } else 2476 maxrates = rt->rateCount; 2477 rs = &ic->ic_sup_rates[mode]; 2478 for (i = 0; i < maxrates; i++) 2479 rs->rs_rates[i] = rt->info[i].dot11Rate; 2480 rs->rs_nrates = maxrates; 2481 return 1; 2482 } 2483 2484 static void 2485 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 2486 { 2487 const HAL_RATE_TABLE *rt; 2488 int i; 2489 2490 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 2491 rt = sc->sc_rates[mode]; 2492 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 2493 for (i = 0; i < rt->rateCount; i++) 2494 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 2495 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 2496 for (i = 0; i < 32; i++) 2497 sc->sc_hwmap[i] = rt->info[rt->rateCodeToIndex[i]].dot11Rate; 2498 sc->sc_currates = rt; 2499 sc->sc_curmode = mode; 2500 } 2501 2502 /* 2503 * Reset the rate control state for each 802.11 state transition. 2504 */ 2505 static void 2506 ath_rate_ctl_reset(struct ath_softc *sc, enum ieee80211_state state) 2507 { 2508 struct ieee80211com *ic = &sc->sc_ic; 2509 struct ieee80211_node *ni; 2510 struct ath_node *an; 2511 2512 an = (struct ath_node *) ic->ic_bss; 2513 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = an->an_tx_upper = 0; 2514 if (ic->ic_opmode == IEEE80211_M_STA) { 2515 ni = ic->ic_bss; 2516 if (state == IEEE80211_S_RUN) { 2517 /* start with highest negotiated rate */ 2518 KASSERT(ni->ni_rates.rs_nrates > 0, 2519 ("transition to RUN state w/ no rates!")); 2520 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2521 } else { 2522 /* use lowest rate */ 2523 ni->ni_txrate = 0; 2524 } 2525 } else { 2526 TAILQ_FOREACH(ni, &ic->ic_node, ni_list) { 2527 ni->ni_txrate = 0; /* use lowest rate */ 2528 an = (struct ath_node *) ni; 2529 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 2530 an->an_tx_upper = 0; 2531 } 2532 } 2533 } 2534 2535 /* 2536 * Examine and potentially adjust the transmit rate. 2537 */ 2538 static void 2539 ath_rate_ctl(void *arg, struct ieee80211_node *ni) 2540 { 2541 struct ath_softc *sc = arg; 2542 struct ath_node *an = (struct ath_node *) ni; 2543 struct ieee80211_rateset *rs = &ni->ni_rates; 2544 int mod = 0, orate, enough; 2545 2546 /* 2547 * Rate control 2548 * XXX: very primitive version. 2549 */ 2550 sc->sc_stats.ast_rate_calls++; 2551 2552 enough = (an->an_tx_ok + an->an_tx_err >= 10); 2553 2554 /* no packet reached -> down */ 2555 if (an->an_tx_err > 0 && an->an_tx_ok == 0) 2556 mod = -1; 2557 2558 /* all packets needs retry in average -> down */ 2559 if (enough && an->an_tx_ok < an->an_tx_retr) 2560 mod = -1; 2561 2562 /* no error and less than 10% of packets needs retry -> up */ 2563 if (enough && an->an_tx_err == 0 && an->an_tx_ok > an->an_tx_retr * 10) 2564 mod = 1; 2565 2566 orate = ni->ni_txrate; 2567 switch (mod) { 2568 case 0: 2569 if (enough && an->an_tx_upper > 0) 2570 an->an_tx_upper--; 2571 break; 2572 case -1: 2573 if (ni->ni_txrate > 0) { 2574 ni->ni_txrate--; 2575 sc->sc_stats.ast_rate_drop++; 2576 } 2577 an->an_tx_upper = 0; 2578 break; 2579 case 1: 2580 if (++an->an_tx_upper < 2) 2581 break; 2582 an->an_tx_upper = 0; 2583 if (ni->ni_txrate + 1 < rs->rs_nrates) { 2584 ni->ni_txrate++; 2585 sc->sc_stats.ast_rate_raise++; 2586 } 2587 break; 2588 } 2589 2590 if (ni->ni_txrate != orate) { 2591 printf("%s: %dM -> %dM (%d ok, %d err, %d retr)\n", 2592 __func__, 2593 (rs->rs_rates[orate] & IEEE80211_RATE_VAL) / 2, 2594 (rs->rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL) / 2, 2595 an->an_tx_ok, an->an_tx_err, an->an_tx_retr); 2596 } 2597 if (ni->ni_txrate != orate || enough) 2598 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 0; 2599 } 2600 2601 #ifdef AR_DEBUG 2602 static int 2603 sysctl_hw_ath_dump(SYSCTL_HANDLER_ARGS) 2604 { 2605 char dmode[64]; 2606 int error; 2607 2608 strncpy(dmode, "", sizeof(dmode) - 1); 2609 dmode[sizeof(dmode) - 1] = '\0'; 2610 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2611 2612 if (error == 0 && req->newptr != NULL) { 2613 struct ifnet *ifp; 2614 struct ath_softc *sc; 2615 2616 ifp = ifunit("ath0"); /* XXX */ 2617 if (!ifp) 2618 return EINVAL; 2619 sc = ifp->if_softc; 2620 if (strcmp(dmode, "hal") == 0) 2621 ath_hal_dumpstate(sc->sc_ah); 2622 else if (strcmp(dmode, "eeprom") == 0) 2623 ath_hal_dumpeeprom(sc->sc_ah); 2624 else if (strcmp(dmode, "rfgain") == 0) 2625 ath_hal_dumprfgain(sc->sc_ah); 2626 else if (strcmp(dmode, "ani") == 0) 2627 ath_hal_dumpani(sc->sc_ah); 2628 else 2629 return EINVAL; 2630 } 2631 return error; 2632 } 2633 SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2634 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state"); 2635 2636 static void 2637 ath_printrxbuf(struct ath_buf *bf, int done) 2638 { 2639 struct ath_desc *ds; 2640 int i; 2641 2642 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2643 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 2644 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2645 ds->ds_link, ds->ds_data, 2646 ds->ds_ctl0, ds->ds_ctl1, 2647 ds->ds_hw[0], ds->ds_hw[1], 2648 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 2649 } 2650 } 2651 2652 static void 2653 ath_printtxbuf(struct ath_buf *bf, int done) 2654 { 2655 struct ath_desc *ds; 2656 int i; 2657 2658 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2659 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 2660 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2661 ds->ds_link, ds->ds_data, 2662 ds->ds_ctl0, ds->ds_ctl1, 2663 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 2664 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 2665 } 2666 } 2667 #endif /* AR_DEBUG */ 2668