1 /*- 2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 /* 41 * Driver for the Atheros Wireless LAN controller. 42 * 43 * This software is derived from work of Atsushi Onoe; his contribution 44 * is greatly appreciated. 45 */ 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/lock.h> 55 #include <sys/mutex.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/errno.h> 60 #include <sys/callout.h> 61 #include <sys/bus.h> 62 #include <sys/endian.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_arp.h> 70 #include <net/ethernet.h> 71 #include <net/if_llc.h> 72 73 #include <net80211/ieee80211_var.h> 74 75 #include <net/bpf.h> 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/if_ether.h> 80 #endif 81 82 #define AR_DEBUG 83 #include <dev/ath/if_athvar.h> 84 #include <contrib/dev/ath/ah_desc.h> 85 86 /* unalligned little endian access */ 87 #define LE_READ_2(p) \ 88 ((u_int16_t) \ 89 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 90 #define LE_READ_4(p) \ 91 ((u_int32_t) \ 92 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 93 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 94 95 static void ath_init(void *); 96 static void ath_stop(struct ifnet *); 97 static void ath_start(struct ifnet *); 98 static void ath_reset(struct ath_softc *); 99 static int ath_media_change(struct ifnet *); 100 static void ath_watchdog(struct ifnet *); 101 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 102 static void ath_fatal_proc(void *, int); 103 static void ath_rxorn_proc(void *, int); 104 static void ath_bmiss_proc(void *, int); 105 static void ath_initkeytable(struct ath_softc *); 106 static void ath_mode_init(struct ath_softc *); 107 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 108 static void ath_beacon_proc(void *, int); 109 static void ath_beacon_free(struct ath_softc *); 110 static void ath_beacon_config(struct ath_softc *); 111 static int ath_desc_alloc(struct ath_softc *); 112 static void ath_desc_free(struct ath_softc *); 113 static struct ieee80211_node *ath_node_alloc(struct ieee80211com *); 114 static void ath_node_free(struct ieee80211com *, struct ieee80211_node *); 115 static void ath_node_copy(struct ieee80211com *, 116 struct ieee80211_node *, const struct ieee80211_node *); 117 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 118 static void ath_rx_proc(void *, int); 119 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 120 struct ath_buf *, struct mbuf *); 121 static void ath_tx_proc(void *, int); 122 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 123 static void ath_draintxq(struct ath_softc *); 124 static void ath_stoprecv(struct ath_softc *); 125 static int ath_startrecv(struct ath_softc *); 126 static void ath_next_scan(void *); 127 static void ath_calibrate(void *); 128 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 129 static void ath_newassoc(struct ieee80211com *, 130 struct ieee80211_node *, int); 131 static int ath_getchannels(struct ath_softc *, u_int cc, HAL_BOOL outdoor); 132 133 static int ath_rate_setup(struct ath_softc *sc, u_int mode); 134 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 135 static void ath_rate_ctl_reset(struct ath_softc *, enum ieee80211_state); 136 static void ath_rate_ctl(void *, struct ieee80211_node *); 137 138 SYSCTL_DECL(_hw_ath); 139 140 /* XXX validate sysctl values */ 141 static int ath_dwelltime = 200; /* 5 channels/second */ 142 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 143 0, "channel dwell time (ms) for AP/station scanning"); 144 static int ath_calinterval = 30; /* calibrate every 30 secs */ 145 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 146 0, "chip calibration interval (secs)"); 147 static int ath_outdoor = AH_TRUE; /* outdoor operation */ 148 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 149 0, "enable/disable outdoor operation"); 150 static int ath_countrycode = CTRY_DEFAULT; /* country code */ 151 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 152 0, "country code"); 153 static int ath_regdomain = 0; /* regulatory domain */ 154 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 155 0, "regulatory domain"); 156 157 #ifdef AR_DEBUG 158 int ath_debug = 0; 159 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 160 0, "control debugging printfs"); 161 #define IFF_DUMPPKTS(_ifp) \ 162 (ath_debug || \ 163 ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 164 static void ath_printrxbuf(struct ath_buf *bf, int); 165 static void ath_printtxbuf(struct ath_buf *bf, int); 166 #define DPRINTF(X) if (ath_debug) printf X 167 #define DPRINTF2(X) if (ath_debug > 1) printf X 168 #else 169 #define IFF_DUMPPKTS(_ifp) \ 170 (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 171 #define DPRINTF(X) 172 #define DPRINTF2(X) 173 #endif 174 175 int 176 ath_attach(u_int16_t devid, struct ath_softc *sc) 177 { 178 struct ieee80211com *ic = &sc->sc_ic; 179 struct ifnet *ifp = &ic->ic_if; 180 struct ath_hal *ah; 181 HAL_STATUS status; 182 int error = 0; 183 184 DPRINTF(("ath_attach: devid 0x%x\n", devid)); 185 186 /* set these up early for if_printf use */ 187 ifp->if_unit = device_get_unit(sc->sc_dev); 188 ifp->if_name = "ath"; 189 190 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 191 if (ah == NULL) { 192 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 193 status); 194 error = ENXIO; 195 goto bad; 196 } 197 sc->sc_ah = ah; 198 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 199 200 /* 201 * Collect the channel list using the default country 202 * code and including outdoor channels. The 802.11 layer 203 * is resposible for filtering this list based on settings 204 * like the phy mode. 205 */ 206 error = ath_getchannels(sc, ath_countrycode, ath_outdoor); 207 if (error != 0) 208 goto bad; 209 /* 210 * Copy these back; they are set as a side effect 211 * of constructing the channel list. 212 */ 213 ath_regdomain = ath_hal_getregdomain(ah); 214 ath_countrycode = ath_hal_getcountrycode(ah); 215 216 /* 217 * Setup rate tables for all potential media types. 218 */ 219 ath_rate_setup(sc, IEEE80211_MODE_11A); 220 ath_rate_setup(sc, IEEE80211_MODE_11B); 221 ath_rate_setup(sc, IEEE80211_MODE_11G); 222 ath_rate_setup(sc, IEEE80211_MODE_TURBO); 223 224 error = ath_desc_alloc(sc); 225 if (error != 0) { 226 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 227 goto bad; 228 } 229 callout_init(&sc->sc_scan_ch, CALLOUT_MPSAFE); 230 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 231 232 mtx_init(&sc->sc_txbuflock, 233 device_get_nameunit(sc->sc_dev), "xmit buf q", MTX_DEF); 234 mtx_init(&sc->sc_txqlock, 235 device_get_nameunit(sc->sc_dev), "xmit q", MTX_DEF); 236 237 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 238 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 239 TASK_INIT(&sc->sc_swbatask, 0, ath_beacon_proc, sc); 240 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 241 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 242 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 243 244 /* 245 * For now just pre-allocate one data queue and one 246 * beacon queue. Note that the HAL handles resetting 247 * them at the needed time. Eventually we'll want to 248 * allocate more tx queues for splitting management 249 * frames and for QOS support. 250 */ 251 sc->sc_txhalq = ath_hal_setuptxqueue(ah, 252 HAL_TX_QUEUE_DATA, 253 AH_TRUE /* enable interrupts */ 254 ); 255 if (sc->sc_txhalq == (u_int) -1) { 256 if_printf(ifp, "unable to setup a data xmit queue!\n"); 257 goto bad; 258 } 259 sc->sc_bhalq = ath_hal_setuptxqueue(ah, 260 HAL_TX_QUEUE_BEACON, 261 AH_TRUE /* enable interrupts */ 262 ); 263 if (sc->sc_bhalq == (u_int) -1) { 264 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 265 goto bad; 266 } 267 268 ifp->if_softc = sc; 269 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 270 ifp->if_start = ath_start; 271 ifp->if_watchdog = ath_watchdog; 272 ifp->if_ioctl = ath_ioctl; 273 ifp->if_init = ath_init; 274 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 275 276 ic->ic_softc = sc; 277 ic->ic_newassoc = ath_newassoc; 278 /* XXX not right but it's not used anywhere important */ 279 ic->ic_phytype = IEEE80211_T_OFDM; 280 ic->ic_opmode = IEEE80211_M_STA; 281 ic->ic_caps = IEEE80211_C_WEP | IEEE80211_C_IBSS | IEEE80211_C_HOSTAP 282 | IEEE80211_C_MONITOR | IEEE80211_C_SHPREAMBLE; 283 284 /* get mac address from hardware */ 285 ath_hal_getmac(ah, ic->ic_myaddr); 286 287 /* call MI attach routine. */ 288 ieee80211_ifattach(ifp); 289 /* override default methods */ 290 ic->ic_node_alloc = ath_node_alloc; 291 ic->ic_node_free = ath_node_free; 292 ic->ic_node_copy = ath_node_copy; 293 sc->sc_newstate = ic->ic_newstate; 294 ic->ic_newstate = ath_newstate; 295 /* complete initialization */ 296 ieee80211_media_init(ifp, ath_media_change, ieee80211_media_status); 297 298 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 299 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 300 &sc->sc_drvbpf); 301 /* 302 * Initialize constant fields. 303 * 304 * NB: the channel is setup each time we transition to the 305 * RUN state to avoid filling it in for each frame. 306 */ 307 sc->sc_tx_th.wt_ihdr.it_len = sizeof(sc->sc_tx_th); 308 sc->sc_tx_th.wt_ihdr.it_present = ATH_TX_RADIOTAP_PRESENT; 309 310 sc->sc_rx_th.wr_ihdr.it_len = sizeof(sc->sc_rx_th); 311 sc->sc_rx_th.wr_ihdr.it_present = ATH_RX_RADIOTAP_PRESENT; 312 313 if_printf(ifp, "802.11 address: %s\n", ether_sprintf(ic->ic_myaddr)); 314 315 return 0; 316 bad: 317 if (ah) 318 ath_hal_detach(ah); 319 sc->sc_invalid = 1; 320 return error; 321 } 322 323 int 324 ath_detach(struct ath_softc *sc) 325 { 326 struct ifnet *ifp = &sc->sc_ic.ic_if; 327 328 DPRINTF(("ath_detach: if_flags %x\n", ifp->if_flags)); 329 330 mtx_lock(&sc->sc_mtx); 331 ath_stop(ifp); 332 bpfdetach(ifp); 333 ath_desc_free(sc); 334 ath_hal_detach(sc->sc_ah); 335 ieee80211_ifdetach(ifp); 336 mtx_unlock(&sc->sc_mtx); 337 return 0; 338 } 339 340 void 341 ath_suspend(struct ath_softc *sc) 342 { 343 struct ifnet *ifp = &sc->sc_ic.ic_if; 344 345 DPRINTF(("ath_suspend: if_flags %x\n", ifp->if_flags)); 346 347 ath_stop(ifp); 348 } 349 350 void 351 ath_resume(struct ath_softc *sc) 352 { 353 struct ifnet *ifp = &sc->sc_ic.ic_if; 354 355 DPRINTF(("ath_resume: if_flags %x\n", ifp->if_flags)); 356 357 if (ifp->if_flags & IFF_UP) { 358 ath_init(ifp); 359 if (ifp->if_flags & IFF_RUNNING) 360 ath_start(ifp); 361 } 362 } 363 364 void 365 ath_shutdown(struct ath_softc *sc) 366 { 367 struct ifnet *ifp = &sc->sc_ic.ic_if; 368 369 DPRINTF(("ath_shutdown: if_flags %x\n", ifp->if_flags)); 370 371 ath_stop(ifp); 372 } 373 374 void 375 ath_intr(void *arg) 376 { 377 struct ath_softc *sc = arg; 378 struct ieee80211com *ic = &sc->sc_ic; 379 struct ifnet *ifp = &ic->ic_if; 380 struct ath_hal *ah = sc->sc_ah; 381 HAL_INT status; 382 383 if (sc->sc_invalid) { 384 /* 385 * The hardware is not ready/present, don't touch anything. 386 * Note this can happen early on if the IRQ is shared. 387 */ 388 DPRINTF(("ath_intr: invalid; ignored\n")); 389 return; 390 } 391 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 392 DPRINTF(("ath_intr: if_flags 0x%x\n", ifp->if_flags)); 393 ath_hal_getisr(ah, &status); /* clear ISR */ 394 ath_hal_intrset(ah, 0); /* disable further intr's */ 395 return; 396 } 397 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 398 DPRINTF2(("ath_intr: status 0x%x\n", status)); 399 #ifdef AR_DEBUG 400 if (ath_debug && 401 (status & (HAL_INT_FATAL|HAL_INT_RXORN|HAL_INT_BMISS))) { 402 if_printf(ifp, "ath_intr: status 0x%x\n", status); 403 ath_hal_dumpstate(ah); 404 } 405 #endif /* AR_DEBUG */ 406 status &= sc->sc_imask; /* discard unasked for bits */ 407 if (status & HAL_INT_FATAL) { 408 sc->sc_stats.ast_hardware++; 409 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 410 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask); 411 } else if (status & HAL_INT_RXORN) { 412 sc->sc_stats.ast_rxorn++; 413 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 414 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask); 415 } else { 416 if (status & HAL_INT_RXEOL) { 417 /* 418 * NB: the hardware should re-read the link when 419 * RXE bit is written, but it doesn't work at 420 * least on older hardware revs. 421 */ 422 sc->sc_stats.ast_rxeol++; 423 sc->sc_rxlink = NULL; 424 } 425 if (status & HAL_INT_TXURN) { 426 sc->sc_stats.ast_txurn++; 427 /* bump tx trigger level */ 428 ath_hal_updatetxtriglevel(ah, AH_TRUE); 429 } 430 if (status & HAL_INT_RX) 431 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask); 432 if (status & HAL_INT_TX) 433 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask); 434 if (status & HAL_INT_SWBA) 435 taskqueue_enqueue(taskqueue_swi, &sc->sc_swbatask); 436 if (status & HAL_INT_BMISS) { 437 sc->sc_stats.ast_bmiss++; 438 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask); 439 } 440 } 441 } 442 443 static void 444 ath_fatal_proc(void *arg, int pending) 445 { 446 struct ath_softc *sc = arg; 447 448 device_printf(sc->sc_dev, "hardware error; resetting\n"); 449 ath_reset(sc); 450 } 451 452 static void 453 ath_rxorn_proc(void *arg, int pending) 454 { 455 struct ath_softc *sc = arg; 456 457 device_printf(sc->sc_dev, "rx FIFO overrun; resetting\n"); 458 ath_reset(sc); 459 } 460 461 static void 462 ath_bmiss_proc(void *arg, int pending) 463 { 464 struct ath_softc *sc = arg; 465 struct ieee80211com *ic = &sc->sc_ic; 466 467 DPRINTF(("ath_bmiss_proc: pending %u\n", pending)); 468 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 469 ("unexpect operating mode %u", ic->ic_opmode)); 470 if (ic->ic_state == IEEE80211_S_RUN) 471 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 472 } 473 474 static u_int 475 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 476 { 477 static const u_int modeflags[] = { 478 0, /* IEEE80211_MODE_AUTO */ 479 CHANNEL_A, /* IEEE80211_MODE_11A */ 480 CHANNEL_B, /* IEEE80211_MODE_11B */ 481 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 482 CHANNEL_T /* IEEE80211_MODE_TURBO */ 483 }; 484 return modeflags[ieee80211_chan2mode(ic, chan)]; 485 } 486 487 static void 488 ath_init(void *arg) 489 { 490 struct ath_softc *sc = (struct ath_softc *) arg; 491 struct ieee80211com *ic = &sc->sc_ic; 492 struct ifnet *ifp = &ic->ic_if; 493 struct ieee80211_node *ni; 494 enum ieee80211_phymode mode; 495 struct ath_hal *ah = sc->sc_ah; 496 HAL_STATUS status; 497 HAL_CHANNEL hchan; 498 499 DPRINTF(("ath_init: if_flags 0x%x\n", ifp->if_flags)); 500 501 mtx_lock(&sc->sc_mtx); 502 /* 503 * Stop anything previously setup. This is safe 504 * whether this is the first time through or not. 505 */ 506 ath_stop(ifp); 507 508 /* 509 * The basic interface to setting the hardware in a good 510 * state is ``reset''. On return the hardware is known to 511 * be powered up and with interrupts disabled. This must 512 * be followed by initialization of the appropriate bits 513 * and then setup of the interrupt mask. 514 */ 515 hchan.channel = ic->ic_ibss_chan->ic_freq; 516 hchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 517 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_FALSE, &status)) { 518 if_printf(ifp, "unable to reset hardware; hal status %u\n", 519 status); 520 goto done; 521 } 522 523 /* 524 * Setup the hardware after reset: the key cache 525 * is filled as needed and the receive engine is 526 * set going. Frame transmit is handled entirely 527 * in the frame output path; there's nothing to do 528 * here except setup the interrupt mask. 529 */ 530 if (ic->ic_flags & IEEE80211_F_WEPON) 531 ath_initkeytable(sc); 532 if (ath_startrecv(sc) != 0) { 533 if_printf(ifp, "unable to start recv logic\n"); 534 goto done; 535 } 536 537 /* 538 * Enable interrupts. 539 */ 540 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 541 | HAL_INT_RXEOL | HAL_INT_RXORN 542 | HAL_INT_FATAL | HAL_INT_GLOBAL; 543 ath_hal_intrset(ah, sc->sc_imask); 544 545 ifp->if_flags |= IFF_RUNNING; 546 ic->ic_state = IEEE80211_S_INIT; 547 548 /* 549 * The hardware should be ready to go now so it's safe 550 * to kick the 802.11 state machine as it's likely to 551 * immediately call back to us to send mgmt frames. 552 */ 553 ni = ic->ic_bss; 554 ni->ni_chan = ic->ic_ibss_chan; 555 mode = ieee80211_chan2mode(ic, ni->ni_chan); 556 if (mode != sc->sc_curmode) 557 ath_setcurmode(sc, mode); 558 if (ic->ic_opmode != IEEE80211_M_MONITOR) 559 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 560 else 561 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 562 done: 563 mtx_unlock(&sc->sc_mtx); 564 } 565 566 static void 567 ath_stop(struct ifnet *ifp) 568 { 569 struct ieee80211com *ic = (struct ieee80211com *) ifp; 570 struct ath_softc *sc = ifp->if_softc; 571 struct ath_hal *ah = sc->sc_ah; 572 573 DPRINTF(("ath_stop: invalid %u if_flags 0x%x\n", 574 sc->sc_invalid, ifp->if_flags)); 575 576 mtx_lock(&sc->sc_mtx); 577 if (ifp->if_flags & IFF_RUNNING) { 578 /* 579 * Shutdown the hardware and driver: 580 * disable interrupts 581 * turn off timers 582 * clear transmit machinery 583 * clear receive machinery 584 * drain and release tx queues 585 * reclaim beacon resources 586 * reset 802.11 state machine 587 * power down hardware 588 * 589 * Note that some of this work is not possible if the 590 * hardware is gone (invalid). 591 */ 592 ifp->if_flags &= ~IFF_RUNNING; 593 ifp->if_timer = 0; 594 if (!sc->sc_invalid) 595 ath_hal_intrset(ah, 0); 596 ath_draintxq(sc); 597 if (!sc->sc_invalid) 598 ath_stoprecv(sc); 599 else 600 sc->sc_rxlink = NULL; 601 IF_DRAIN(&ifp->if_snd); 602 ath_beacon_free(sc); 603 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 604 if (!sc->sc_invalid) 605 ath_hal_setpower(ah, HAL_PM_FULL_SLEEP, 0); 606 } 607 mtx_unlock(&sc->sc_mtx); 608 } 609 610 /* 611 * Reset the hardware w/o losing operational state. This is 612 * basically a more efficient way of doing ath_stop, ath_init, 613 * followed by state transitions to the current 802.11 614 * operational state. Used to recover from errors rx overrun 615 * and to reset the hardware when rf gain settings must be reset. 616 */ 617 static void 618 ath_reset(struct ath_softc *sc) 619 { 620 struct ieee80211com *ic = &sc->sc_ic; 621 struct ifnet *ifp = &ic->ic_if; 622 struct ath_hal *ah = sc->sc_ah; 623 struct ieee80211_channel *c; 624 HAL_STATUS status; 625 HAL_CHANNEL hchan; 626 627 /* 628 * Convert to a HAL channel description with the flags 629 * constrained to reflect the current operating mode. 630 */ 631 c = ic->ic_ibss_chan; 632 hchan.channel = c->ic_freq; 633 hchan.channelFlags = ath_chan2flags(ic, c); 634 635 ath_hal_intrset(ah, 0); /* disable interrupts */ 636 ath_draintxq(sc); /* stop xmit side */ 637 ath_stoprecv(sc); /* stop recv side */ 638 /* NB: indicate channel change so we do a full reset */ 639 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) 640 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 641 __func__, status); 642 ath_hal_intrset(ah, sc->sc_imask); 643 if (ath_startrecv(sc) != 0) /* restart recv */ 644 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 645 ath_start(ifp); /* restart xmit */ 646 if (ic->ic_state == IEEE80211_S_RUN) 647 ath_beacon_config(sc); /* restart beacons */ 648 } 649 650 static void 651 ath_start(struct ifnet *ifp) 652 { 653 struct ath_softc *sc = ifp->if_softc; 654 struct ath_hal *ah = sc->sc_ah; 655 struct ieee80211com *ic = &sc->sc_ic; 656 struct ieee80211_node *ni; 657 struct ath_buf *bf; 658 struct mbuf *m; 659 struct ieee80211_frame *wh; 660 661 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 662 return; 663 for (;;) { 664 /* 665 * Grab a TX buffer and associated resources. 666 */ 667 mtx_lock(&sc->sc_txbuflock); 668 bf = TAILQ_FIRST(&sc->sc_txbuf); 669 if (bf != NULL) 670 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 671 mtx_unlock(&sc->sc_txbuflock); 672 if (bf == NULL) { 673 DPRINTF(("ath_start: out of xmit buffers\n")); 674 sc->sc_stats.ast_tx_qstop++; 675 ifp->if_flags |= IFF_OACTIVE; 676 break; 677 } 678 /* 679 * Poll the management queue for frames; they 680 * have priority over normal data frames. 681 */ 682 IF_DEQUEUE(&ic->ic_mgtq, m); 683 if (m == NULL) { 684 /* 685 * No data frames go out unless we're associated. 686 */ 687 if (ic->ic_state != IEEE80211_S_RUN) { 688 DPRINTF(("ath_start: ignore data packet, " 689 "state %u\n", ic->ic_state)); 690 sc->sc_stats.ast_tx_discard++; 691 mtx_lock(&sc->sc_txbuflock); 692 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 693 mtx_unlock(&sc->sc_txbuflock); 694 break; 695 } 696 IF_DEQUEUE(&ifp->if_snd, m); 697 if (m == NULL) { 698 mtx_lock(&sc->sc_txbuflock); 699 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 700 mtx_unlock(&sc->sc_txbuflock); 701 break; 702 } 703 ifp->if_opackets++; 704 BPF_MTAP(ifp, m); 705 /* 706 * Encapsulate the packet in prep for transmission. 707 */ 708 m = ieee80211_encap(ifp, m, &ni); 709 if (m == NULL) { 710 DPRINTF(("ath_start: encapsulation failure\n")); 711 sc->sc_stats.ast_tx_encap++; 712 goto bad; 713 } 714 wh = mtod(m, struct ieee80211_frame *); 715 if (ic->ic_flags & IEEE80211_F_WEPON) 716 wh->i_fc[1] |= IEEE80211_FC1_WEP; 717 } else { 718 /* 719 * Hack! The referenced node pointer is in the 720 * rcvif field of the packet header. This is 721 * placed there by ieee80211_mgmt_output because 722 * we need to hold the reference with the frame 723 * and there's no other way (other than packet 724 * tags which we consider too expensive to use) 725 * to pass it along. 726 */ 727 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 728 m->m_pkthdr.rcvif = NULL; 729 730 wh = mtod(m, struct ieee80211_frame *); 731 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 732 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 733 /* fill time stamp */ 734 u_int64_t tsf; 735 u_int32_t *tstamp; 736 737 tsf = ath_hal_gettsf64(ah); 738 /* XXX: adjust 100us delay to xmit */ 739 tsf += 100; 740 tstamp = (u_int32_t *)&wh[1]; 741 tstamp[0] = htole32(tsf & 0xffffffff); 742 tstamp[1] = htole32(tsf >> 32); 743 } 744 sc->sc_stats.ast_tx_mgmt++; 745 } 746 if (ic->ic_rawbpf) 747 bpf_mtap(ic->ic_rawbpf, m); 748 749 if (sc->sc_drvbpf) { 750 struct mbuf *mb; 751 752 MGETHDR(mb, M_DONTWAIT, m->m_type); 753 if (mb != NULL) { 754 sc->sc_tx_th.wt_rate = 755 ni->ni_rates.rs_rates[ni->ni_txrate]; 756 757 mb->m_next = m; 758 mb->m_data = (caddr_t)&sc->sc_tx_th; 759 mb->m_len = sizeof(sc->sc_tx_th); 760 mb->m_pkthdr.len += mb->m_len; 761 bpf_mtap(sc->sc_drvbpf, mb); 762 m_free(mb); 763 } 764 } 765 766 if (ath_tx_start(sc, ni, bf, m)) { 767 bad: 768 mtx_lock(&sc->sc_txbuflock); 769 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 770 mtx_unlock(&sc->sc_txbuflock); 771 ifp->if_oerrors++; 772 if (ni && ni != ic->ic_bss) 773 ieee80211_free_node(ic, ni); 774 continue; 775 } 776 777 sc->sc_tx_timer = 5; 778 ifp->if_timer = 1; 779 } 780 } 781 782 static int 783 ath_media_change(struct ifnet *ifp) 784 { 785 int error; 786 787 error = ieee80211_media_change(ifp); 788 if (error == ENETRESET) { 789 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 790 (IFF_RUNNING|IFF_UP)) 791 ath_init(ifp); /* XXX lose error */ 792 error = 0; 793 } 794 return error; 795 } 796 797 static void 798 ath_watchdog(struct ifnet *ifp) 799 { 800 struct ath_softc *sc = ifp->if_softc; 801 struct ieee80211com *ic = &sc->sc_ic; 802 803 ifp->if_timer = 0; 804 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 805 return; 806 if (sc->sc_tx_timer) { 807 if (--sc->sc_tx_timer == 0) { 808 if_printf(ifp, "device timeout\n"); 809 #ifdef AR_DEBUG 810 if (ath_debug) 811 ath_hal_dumpstate(sc->sc_ah); 812 #endif /* AR_DEBUG */ 813 ath_init(ifp); /* XXX ath_reset??? */ 814 ifp->if_oerrors++; 815 sc->sc_stats.ast_watchdog++; 816 return; 817 } 818 ifp->if_timer = 1; 819 } 820 if (ic->ic_fixed_rate == -1) { 821 /* 822 * Run the rate control algorithm if we're not 823 * locked at a fixed rate. 824 */ 825 if (ic->ic_opmode == IEEE80211_M_STA) 826 ath_rate_ctl(sc, ic->ic_bss); 827 else 828 ieee80211_iterate_nodes(ic, ath_rate_ctl, sc); 829 } 830 ieee80211_watchdog(ifp); 831 } 832 833 static int 834 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 835 { 836 struct ath_softc *sc = ifp->if_softc; 837 struct ifreq *ifr = (struct ifreq *)data; 838 int error = 0; 839 840 mtx_lock(&sc->sc_mtx); 841 switch (cmd) { 842 case SIOCSIFFLAGS: 843 if (ifp->if_flags & IFF_UP) { 844 if (ifp->if_flags & IFF_RUNNING) { 845 /* 846 * To avoid rescanning another access point, 847 * do not call ath_init() here. Instead, 848 * only reflect promisc mode settings. 849 */ 850 ath_mode_init(sc); 851 } else 852 ath_init(ifp); /* XXX lose error */ 853 } else 854 ath_stop(ifp); 855 break; 856 case SIOCADDMULTI: 857 case SIOCDELMULTI: 858 /* 859 * The upper layer has already installed/removed 860 * the multicast address(es), just recalculate the 861 * multicast filter for the card. 862 */ 863 if (ifp->if_flags & IFF_RUNNING) 864 ath_mode_init(sc); 865 break; 866 case SIOCGATHSTATS: 867 copyout(&sc->sc_stats, ifr->ifr_data, sizeof (sc->sc_stats)); 868 break; 869 default: 870 error = ieee80211_ioctl(ifp, cmd, data); 871 if (error == ENETRESET) { 872 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 873 (IFF_RUNNING|IFF_UP)) 874 ath_init(ifp); /* XXX lose error */ 875 error = 0; 876 } 877 break; 878 } 879 mtx_unlock(&sc->sc_mtx); 880 return error; 881 } 882 883 /* 884 * Fill the hardware key cache with key entries. 885 */ 886 static void 887 ath_initkeytable(struct ath_softc *sc) 888 { 889 struct ieee80211com *ic = &sc->sc_ic; 890 struct ath_hal *ah = sc->sc_ah; 891 int i; 892 893 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 894 struct ieee80211_wepkey *k = &ic->ic_nw_keys[i]; 895 if (k->wk_len == 0) 896 ath_hal_keyreset(ah, i); 897 else 898 /* XXX return value */ 899 /* NB: this uses HAL_KEYVAL == ieee80211_wepkey */ 900 ath_hal_keyset(ah, i, (const HAL_KEYVAL *) k); 901 } 902 } 903 904 static void 905 ath_mode_init(struct ath_softc *sc) 906 { 907 struct ieee80211com *ic = &sc->sc_ic; 908 struct ath_hal *ah = sc->sc_ah; 909 struct ifnet *ifp = &ic->ic_if; 910 u_int32_t rfilt, mfilt[2], val; 911 u_int8_t pos; 912 struct ifmultiaddr *ifma; 913 914 /* configure operational mode */ 915 ath_hal_setopmode(ah, ic->ic_opmode); 916 917 /* receive filter */ 918 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 919 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 920 if (ic->ic_opmode != IEEE80211_M_STA) 921 rfilt |= HAL_RX_FILTER_PROBEREQ; 922 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 923 (ifp->if_flags & IFF_PROMISC)) 924 rfilt |= HAL_RX_FILTER_PROM; 925 if (ic->ic_state == IEEE80211_S_SCAN) 926 rfilt |= HAL_RX_FILTER_BEACON; 927 ath_hal_setrxfilter(ah, rfilt); 928 929 /* calculate and install multicast filter */ 930 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 931 mfilt[0] = mfilt[1] = 0; 932 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 933 caddr_t dl; 934 935 /* calculate XOR of eight 6bit values */ 936 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 937 val = LE_READ_4(dl + 0); 938 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 939 val = LE_READ_4(dl + 3); 940 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 941 pos &= 0x3f; 942 mfilt[pos / 32] |= (1 << (pos % 32)); 943 } 944 } else { 945 mfilt[0] = mfilt[1] = ~0; 946 } 947 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 948 DPRINTF(("ath_mode_init: RX filter 0x%x, MC filter %08x:%08x\n", 949 rfilt, mfilt[0], mfilt[1])); 950 } 951 952 static void 953 ath_mbuf_load_cb(void *arg, bus_dma_segment_t *seg, int nseg, bus_size_t mapsize, int error) 954 { 955 struct ath_buf *bf = arg; 956 957 KASSERT(nseg <= ATH_MAX_SCATTER, 958 ("ath_mbuf_load_cb: too many DMA segments %u", nseg)); 959 bf->bf_mapsize = mapsize; 960 bf->bf_nseg = nseg; 961 bcopy(seg, bf->bf_segs, nseg * sizeof (seg[0])); 962 } 963 964 static int 965 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 966 { 967 struct ieee80211com *ic = &sc->sc_ic; 968 struct ifnet *ifp = &ic->ic_if; 969 struct ath_hal *ah = sc->sc_ah; 970 struct ieee80211_frame *wh; 971 struct ath_buf *bf; 972 struct ath_desc *ds; 973 struct mbuf *m; 974 int error, pktlen; 975 u_int8_t *frm, rate; 976 u_int16_t capinfo; 977 struct ieee80211_rateset *rs; 978 const HAL_RATE_TABLE *rt; 979 980 bf = sc->sc_bcbuf; 981 if (bf->bf_m != NULL) { 982 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 983 m_freem(bf->bf_m); 984 bf->bf_m = NULL; 985 bf->bf_node = NULL; 986 } 987 /* 988 * NB: the beacon data buffer must be 32-bit aligned; 989 * we assume the mbuf routines will return us something 990 * with this alignment (perhaps should assert). 991 */ 992 rs = &ni->ni_rates; 993 pktlen = sizeof (struct ieee80211_frame) 994 + 8 + 2 + 2 + 2+ni->ni_esslen + 2+rs->rs_nrates + 6; 995 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 996 pktlen += 2; 997 if (pktlen <= MHLEN) 998 MGETHDR(m, M_DONTWAIT, MT_DATA); 999 else 1000 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1001 if (m == NULL) { 1002 DPRINTF(("ath_beacon_alloc: cannot get mbuf/cluster; size %u\n", 1003 pktlen)); 1004 sc->sc_stats.ast_be_nombuf++; 1005 return ENOMEM; 1006 } 1007 1008 wh = mtod(m, struct ieee80211_frame *); 1009 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1010 IEEE80211_FC0_SUBTYPE_BEACON; 1011 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1012 *(u_int16_t *)wh->i_dur = 0; 1013 memcpy(wh->i_addr1, ifp->if_broadcastaddr, IEEE80211_ADDR_LEN); 1014 memcpy(wh->i_addr2, ic->ic_myaddr, IEEE80211_ADDR_LEN); 1015 memcpy(wh->i_addr3, ni->ni_bssid, IEEE80211_ADDR_LEN); 1016 *(u_int16_t *)wh->i_seq = 0; 1017 1018 /* 1019 * beacon frame format 1020 * [8] time stamp 1021 * [2] beacon interval 1022 * [2] cabability information 1023 * [tlv] ssid 1024 * [tlv] supported rates 1025 * [tlv] parameter set (IBSS) 1026 * [tlv] extended supported rates 1027 */ 1028 frm = (u_int8_t *)&wh[1]; 1029 memset(frm, 0, 8); /* timestamp is set by hardware */ 1030 frm += 8; 1031 *(u_int16_t *)frm = htole16(ni->ni_intval); 1032 frm += 2; 1033 if (ic->ic_opmode == IEEE80211_M_IBSS) 1034 capinfo = IEEE80211_CAPINFO_IBSS; 1035 else 1036 capinfo = IEEE80211_CAPINFO_ESS; 1037 if (ic->ic_flags & IEEE80211_F_WEPON) 1038 capinfo |= IEEE80211_CAPINFO_PRIVACY; 1039 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1040 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 1041 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 1042 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1043 capinfo |= IEEE80211_CAPINFO_SHORT_SLOTTIME; 1044 *(u_int16_t *)frm = htole16(capinfo); 1045 frm += 2; 1046 *frm++ = IEEE80211_ELEMID_SSID; 1047 *frm++ = ni->ni_esslen; 1048 memcpy(frm, ni->ni_essid, ni->ni_esslen); 1049 frm += ni->ni_esslen; 1050 frm = ieee80211_add_rates(frm, rs); 1051 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1052 *frm++ = IEEE80211_ELEMID_IBSSPARMS; 1053 *frm++ = 2; 1054 *frm++ = 0; *frm++ = 0; /* TODO: ATIM window */ 1055 } else { 1056 /* TODO: TIM */ 1057 *frm++ = IEEE80211_ELEMID_TIM; 1058 *frm++ = 4; /* length */ 1059 *frm++ = 0; /* DTIM count */ 1060 *frm++ = 1; /* DTIM period */ 1061 *frm++ = 0; /* bitmap control */ 1062 *frm++ = 0; /* Partial Virtual Bitmap (variable length) */ 1063 } 1064 frm = ieee80211_add_xrates(frm, rs); 1065 m->m_pkthdr.len = m->m_len = frm - mtod(m, u_int8_t *); 1066 KASSERT(m->m_pkthdr.len <= pktlen, 1067 ("beacon bigger than expected, len %u calculated %u", 1068 m->m_pkthdr.len, pktlen)); 1069 1070 DPRINTF2(("ath_beacon_alloc: m %p len %u\n", m, m->m_len)); 1071 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1072 ath_mbuf_load_cb, bf, 1073 BUS_DMA_NOWAIT); 1074 if (error != 0) { 1075 m_freem(m); 1076 return error; 1077 } 1078 KASSERT(bf->bf_nseg == 1, 1079 ("ath_beacon_alloc: multi-segment packet; nseg %u", 1080 bf->bf_nseg)); 1081 bf->bf_m = m; 1082 1083 /* setup descriptors */ 1084 ds = bf->bf_desc; 1085 1086 ds->ds_link = 0; 1087 ds->ds_data = bf->bf_segs[0].ds_addr; 1088 /* 1089 * Calculate rate code. 1090 * XXX everything at min xmit rate 1091 */ 1092 rt = sc->sc_currates; 1093 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1094 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1095 rate = rt->info[0].rateCode | rt->info[0].shortPreamble; 1096 else 1097 rate = rt->info[0].rateCode; 1098 ath_hal_setuptxdesc(ah, ds 1099 , m->m_pkthdr.len + IEEE80211_CRC_LEN /* packet length */ 1100 , sizeof(struct ieee80211_frame) /* header length */ 1101 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1102 , 0x20 /* txpower XXX */ 1103 , rate, 1 /* series 0 rate/tries */ 1104 , HAL_TXKEYIX_INVALID /* no encryption */ 1105 , 0 /* antenna mode */ 1106 , HAL_TXDESC_NOACK /* no ack for beacons */ 1107 , 0 /* rts/cts rate */ 1108 , 0 /* rts/cts duration */ 1109 ); 1110 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1111 /* XXX verify mbuf data area covers this roundup */ 1112 ath_hal_filltxdesc(ah, ds 1113 , roundup(bf->bf_segs[0].ds_len, 4) /* buffer length */ 1114 , AH_TRUE /* first segment */ 1115 , AH_TRUE /* last segment */ 1116 ); 1117 1118 return 0; 1119 } 1120 1121 static void 1122 ath_beacon_proc(void *arg, int pending) 1123 { 1124 struct ath_softc *sc = arg; 1125 struct ieee80211com *ic = &sc->sc_ic; 1126 struct ath_buf *bf = sc->sc_bcbuf; 1127 struct ath_hal *ah = sc->sc_ah; 1128 1129 DPRINTF2(("%s: pending %u\n", __func__, pending)); 1130 if (ic->ic_opmode == IEEE80211_M_STA || 1131 bf == NULL || bf->bf_m == NULL) { 1132 DPRINTF(("%s: ic_flags=%x bf=%p bf_m=%p\n", 1133 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL)); 1134 return; 1135 } 1136 /* TODO: update beacon to reflect PS poll state */ 1137 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1138 DPRINTF(("%s: beacon queue %u did not stop?", 1139 __func__, sc->sc_bhalq)); 1140 return; /* busy, XXX is this right? */ 1141 } 1142 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1143 1144 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 1145 ath_hal_txstart(ah, sc->sc_bhalq); 1146 DPRINTF2(("%s: TXDP%u = %p (%p)\n", __func__, 1147 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1148 } 1149 1150 static void 1151 ath_beacon_free(struct ath_softc *sc) 1152 { 1153 struct ath_buf *bf = sc->sc_bcbuf; 1154 1155 if (bf->bf_m != NULL) { 1156 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1157 m_freem(bf->bf_m); 1158 bf->bf_m = NULL; 1159 bf->bf_node = NULL; 1160 } 1161 } 1162 1163 /* 1164 * Configure the beacon and sleep timers. 1165 * 1166 * When operating as an AP this resets the TSF and sets 1167 * up the hardware to notify us when we need to issue beacons. 1168 * 1169 * When operating in station mode this sets up the beacon 1170 * timers according to the timestamp of the last received 1171 * beacon and the current TSF, configures PCF and DTIM 1172 * handling, programs the sleep registers so the hardware 1173 * will wakeup in time to receive beacons, and configures 1174 * the beacon miss handling so we'll receive a BMISS 1175 * interrupt when we stop seeing beacons from the AP 1176 * we've associated with. 1177 */ 1178 static void 1179 ath_beacon_config(struct ath_softc *sc) 1180 { 1181 struct ath_hal *ah = sc->sc_ah; 1182 struct ieee80211com *ic = &sc->sc_ic; 1183 struct ieee80211_node *ni = ic->ic_bss; 1184 u_int32_t nexttbtt; 1185 1186 nexttbtt = (LE_READ_4(ni->ni_tstamp + 4) << 22) | 1187 (LE_READ_4(ni->ni_tstamp) >> 10); 1188 DPRINTF(("%s: nexttbtt=%u\n", __func__, nexttbtt)); 1189 nexttbtt += ni->ni_intval; 1190 if (ic->ic_opmode == IEEE80211_M_STA) { 1191 HAL_BEACON_STATE bs; 1192 u_int32_t bmisstime; 1193 1194 /* NB: no PCF support right now */ 1195 memset(&bs, 0, sizeof(bs)); 1196 bs.bs_intval = ni->ni_intval; 1197 bs.bs_nexttbtt = nexttbtt; 1198 bs.bs_dtimperiod = bs.bs_intval; 1199 bs.bs_nextdtim = nexttbtt; 1200 /* 1201 * Calculate the number of consecutive beacons to miss 1202 * before taking a BMISS interrupt. The configuration 1203 * is specified in ms, so we need to convert that to 1204 * TU's and then calculate based on the beacon interval. 1205 * Note that we clamp the result to at most 10 beacons. 1206 */ 1207 bmisstime = (ic->ic_bmisstimeout * 1000) / 1024; 1208 bs.bs_bmissthreshold = howmany(bmisstime,ni->ni_intval); 1209 if (bs.bs_bmissthreshold > 10) 1210 bs.bs_bmissthreshold = 10; 1211 else if (bs.bs_bmissthreshold <= 0) 1212 bs.bs_bmissthreshold = 1; 1213 1214 /* 1215 * Calculate sleep duration. The configuration is 1216 * given in ms. We insure a multiple of the beacon 1217 * period is used. Also, if the sleep duration is 1218 * greater than the DTIM period then it makes senses 1219 * to make it a multiple of that. 1220 * 1221 * XXX fixed at 100ms 1222 */ 1223 bs.bs_sleepduration = 1224 roundup((100 * 1000) / 1024, bs.bs_intval); 1225 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1226 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1227 1228 DPRINTF(("%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u\n" 1229 , __func__ 1230 , bs.bs_intval 1231 , bs.bs_nexttbtt 1232 , bs.bs_dtimperiod 1233 , bs.bs_nextdtim 1234 , bs.bs_bmissthreshold 1235 , bs.bs_sleepduration 1236 )); 1237 ath_hal_intrset(ah, 0); 1238 /* 1239 * Reset our tsf so the hardware will update the 1240 * tsf register to reflect timestamps found in 1241 * received beacons. 1242 */ 1243 ath_hal_resettsf(ah); 1244 ath_hal_beacontimers(ah, &bs, 0/*XXX*/, 0, 0); 1245 sc->sc_imask |= HAL_INT_BMISS; 1246 ath_hal_intrset(ah, sc->sc_imask); 1247 } else { 1248 DPRINTF(("%s: intval %u nexttbtt %u\n", 1249 __func__, ni->ni_intval, nexttbtt)); 1250 ath_hal_intrset(ah, 0); 1251 ath_hal_beaconinit(ah, ic->ic_opmode, 1252 nexttbtt, ni->ni_intval); 1253 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1254 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1255 ath_hal_intrset(ah, sc->sc_imask); 1256 } 1257 } 1258 1259 static void 1260 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1261 { 1262 bus_addr_t *paddr = (bus_addr_t*) arg; 1263 *paddr = segs->ds_addr; 1264 } 1265 1266 static int 1267 ath_desc_alloc(struct ath_softc *sc) 1268 { 1269 int i, bsize, error; 1270 struct ath_desc *ds; 1271 struct ath_buf *bf; 1272 1273 /* allocate descriptors */ 1274 sc->sc_desc_len = sizeof(struct ath_desc) * 1275 (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + 1); 1276 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1277 if (error != 0) 1278 return error; 1279 1280 error = bus_dmamem_alloc(sc->sc_dmat, (void**) &sc->sc_desc, 1281 BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1282 if (error != 0) 1283 goto fail0; 1284 1285 error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, 1286 sc->sc_desc, sc->sc_desc_len, 1287 ath_load_cb, &sc->sc_desc_paddr, 1288 BUS_DMA_NOWAIT); 1289 if (error != 0) 1290 goto fail1; 1291 1292 ds = sc->sc_desc; 1293 DPRINTF(("ath_desc_alloc: DMA map: %p (%d) -> %p (%lu)\n", 1294 ds, sc->sc_desc_len, 1295 (caddr_t) sc->sc_desc_paddr, /*XXX*/ (u_long) sc->sc_desc_len)); 1296 1297 /* allocate buffers */ 1298 bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 1); 1299 bf = malloc(bsize, M_DEVBUF, M_NOWAIT | M_ZERO); 1300 if (bf == NULL) 1301 goto fail2; 1302 sc->sc_bufptr = bf; 1303 1304 TAILQ_INIT(&sc->sc_rxbuf); 1305 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 1306 bf->bf_desc = ds; 1307 bf->bf_daddr = sc->sc_desc_paddr + 1308 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1309 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1310 &bf->bf_dmamap); 1311 if (error != 0) 1312 break; 1313 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1314 } 1315 1316 TAILQ_INIT(&sc->sc_txbuf); 1317 for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { 1318 bf->bf_desc = ds; 1319 bf->bf_daddr = sc->sc_desc_paddr + 1320 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1321 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1322 &bf->bf_dmamap); 1323 if (error != 0) 1324 break; 1325 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1326 } 1327 TAILQ_INIT(&sc->sc_txq); 1328 1329 /* beacon buffer */ 1330 bf->bf_desc = ds; 1331 bf->bf_daddr = sc->sc_desc_paddr + ((caddr_t)ds - (caddr_t)sc->sc_desc); 1332 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &bf->bf_dmamap); 1333 if (error != 0) 1334 return error; 1335 sc->sc_bcbuf = bf; 1336 return 0; 1337 1338 fail2: 1339 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1340 fail1: 1341 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1342 fail0: 1343 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1344 sc->sc_ddmamap = NULL; 1345 return error; 1346 } 1347 1348 static void 1349 ath_desc_free(struct ath_softc *sc) 1350 { 1351 struct ath_buf *bf; 1352 1353 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1354 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1355 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1356 1357 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1358 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1359 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1360 m_freem(bf->bf_m); 1361 } 1362 TAILQ_FOREACH(bf, &sc->sc_txbuf, bf_list) 1363 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1364 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1365 if (bf->bf_m) { 1366 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1367 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1368 m_freem(bf->bf_m); 1369 bf->bf_m = NULL; 1370 } 1371 } 1372 if (sc->sc_bcbuf != NULL) { 1373 bus_dmamap_unload(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1374 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1375 sc->sc_bcbuf = NULL; 1376 } 1377 1378 TAILQ_INIT(&sc->sc_rxbuf); 1379 TAILQ_INIT(&sc->sc_txbuf); 1380 TAILQ_INIT(&sc->sc_txq); 1381 free(sc->sc_bufptr, M_DEVBUF); 1382 sc->sc_bufptr = NULL; 1383 } 1384 1385 static struct ieee80211_node * 1386 ath_node_alloc(struct ieee80211com *ic) 1387 { 1388 struct ath_node *an = 1389 malloc(sizeof(struct ath_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1390 return an ? &an->an_node : NULL; 1391 } 1392 1393 static void 1394 ath_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 1395 { 1396 struct ath_softc *sc = ic->ic_if.if_softc; 1397 struct ath_buf *bf; 1398 1399 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1400 if (bf->bf_node == ni) 1401 bf->bf_node = NULL; 1402 } 1403 free(ni, M_DEVBUF); 1404 } 1405 1406 static void 1407 ath_node_copy(struct ieee80211com *ic, 1408 struct ieee80211_node *dst, const struct ieee80211_node *src) 1409 { 1410 *(struct ath_node *)dst = *(const struct ath_node *)src; 1411 } 1412 1413 static int 1414 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 1415 { 1416 struct ath_hal *ah = sc->sc_ah; 1417 int error; 1418 struct mbuf *m; 1419 struct ath_desc *ds; 1420 1421 m = bf->bf_m; 1422 if (m == NULL) { 1423 /* 1424 * NB: by assigning a page to the rx dma buffer we 1425 * implicitly satisfy the Atheros requirement that 1426 * this buffer be cache-line-aligned and sized to be 1427 * multiple of the cache line size. Not doing this 1428 * causes weird stuff to happen (for the 5210 at least). 1429 */ 1430 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1431 if (m == NULL) { 1432 DPRINTF(("ath_rxbuf_init: no mbuf/cluster\n")); 1433 sc->sc_stats.ast_rx_nombuf++; 1434 return ENOMEM; 1435 } 1436 bf->bf_m = m; 1437 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1438 1439 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1440 ath_mbuf_load_cb, bf, 1441 BUS_DMA_NOWAIT); 1442 if (error != 0) { 1443 DPRINTF(("ath_rxbuf_init: bus_dmamap_load_mbuf failed;" 1444 " error %d\n", error)); 1445 sc->sc_stats.ast_rx_busdma++; 1446 return error; 1447 } 1448 KASSERT(bf->bf_nseg == 1, 1449 ("ath_rxbuf_init: multi-segment packet; nseg %u", 1450 bf->bf_nseg)); 1451 } 1452 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 1453 1454 /* setup descriptors */ 1455 ds = bf->bf_desc; 1456 ds->ds_link = 0; 1457 ds->ds_data = bf->bf_segs[0].ds_addr; 1458 ath_hal_setuprxdesc(ah, ds 1459 , m->m_len /* buffer size */ 1460 , 0 1461 ); 1462 1463 if (sc->sc_rxlink != NULL) 1464 *sc->sc_rxlink = bf->bf_daddr; 1465 sc->sc_rxlink = &ds->ds_link; 1466 return 0; 1467 } 1468 1469 static void 1470 ath_rx_proc(void *arg, int npending) 1471 { 1472 struct ath_softc *sc = arg; 1473 struct ath_buf *bf; 1474 struct ieee80211com *ic = &sc->sc_ic; 1475 struct ifnet *ifp = &ic->ic_if; 1476 struct ath_hal *ah = sc->sc_ah; 1477 struct ath_desc *ds; 1478 struct mbuf *m; 1479 struct ieee80211_frame *wh, whbuf; 1480 struct ieee80211_node *ni; 1481 int len; 1482 u_int phyerr; 1483 HAL_STATUS status; 1484 1485 DPRINTF2(("ath_rx_proc: pending %u\n", npending)); 1486 do { 1487 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1488 if (bf == NULL) { /* NB: shouldn't happen */ 1489 if_printf(ifp, "ath_rx_proc: no buffer!\n"); 1490 break; 1491 } 1492 m = bf->bf_m; 1493 if (m == NULL) { /* NB: shouldn't happen */ 1494 if_printf(ifp, "ath_rx_proc: no mbuf!\n"); 1495 continue; 1496 } 1497 ds = bf->bf_desc; 1498 status = ath_hal_rxprocdesc(ah, ds); 1499 #ifdef AR_DEBUG 1500 if (ath_debug > 1) 1501 ath_printrxbuf(bf, status == HAL_OK); 1502 #endif 1503 if (status == HAL_EINPROGRESS) 1504 break; 1505 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1506 if (ds->ds_rxstat.rs_status != 0) { 1507 ifp->if_ierrors++; 1508 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 1509 sc->sc_stats.ast_rx_crcerr++; 1510 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 1511 sc->sc_stats.ast_rx_fifoerr++; 1512 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) 1513 sc->sc_stats.ast_rx_badcrypt++; 1514 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 1515 sc->sc_stats.ast_rx_phyerr++; 1516 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 1517 sc->sc_stats.ast_rx_phy[phyerr]++; 1518 } 1519 goto rx_next; 1520 } 1521 1522 len = ds->ds_rxstat.rs_datalen; 1523 if (len < IEEE80211_MIN_LEN) { 1524 DPRINTF(("ath_rx_proc: short packet %d\n", len)); 1525 sc->sc_stats.ast_rx_tooshort++; 1526 goto rx_next; 1527 } 1528 1529 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 1530 BUS_DMASYNC_POSTREAD); 1531 1532 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1533 bf->bf_m = NULL; 1534 m->m_pkthdr.rcvif = ifp; 1535 m->m_pkthdr.len = m->m_len = len; 1536 1537 if (sc->sc_drvbpf) { 1538 struct mbuf *mb; 1539 1540 /* XXX pre-allocate space when setting up recv's */ 1541 MGETHDR(mb, M_DONTWAIT, m->m_type); 1542 if (mb != NULL) { 1543 sc->sc_rx_th.wr_rate = 1544 sc->sc_hwmap[ds->ds_rxstat.rs_rate]; 1545 sc->sc_rx_th.wr_antsignal = 1546 ds->ds_rxstat.rs_rssi; 1547 sc->sc_rx_th.wr_antenna = 1548 ds->ds_rxstat.rs_antenna; 1549 /* XXX TSF */ 1550 1551 (void) m_dup_pkthdr(mb, m, M_DONTWAIT); 1552 mb->m_next = m; 1553 mb->m_data = (caddr_t)&sc->sc_rx_th; 1554 mb->m_len = sizeof(sc->sc_rx_th); 1555 mb->m_pkthdr.len += mb->m_len; 1556 bpf_mtap(sc->sc_drvbpf, mb); 1557 m_free(mb); 1558 } 1559 } 1560 1561 m_adj(m, -IEEE80211_CRC_LEN); 1562 wh = mtod(m, struct ieee80211_frame *); 1563 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1564 /* 1565 * WEP is decrypted by hardware. Clear WEP bit 1566 * and trim WEP header for ieee80211_input(). 1567 */ 1568 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 1569 memcpy(&whbuf, wh, sizeof(whbuf)); 1570 m_adj(m, IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN); 1571 memcpy(mtod(m, caddr_t), &whbuf, sizeof(whbuf)); 1572 /* 1573 * Also trim WEP ICV from the tail. 1574 */ 1575 m_adj(m, -IEEE80211_WEP_CRCLEN); 1576 } 1577 1578 /* 1579 * Locate the node for sender, track state, and 1580 * then pass this node (referenced) up to the 802.11 1581 * layer for its use. We are required to pass 1582 * something so we fall back to ic_bss when this frame 1583 * is from an unknown sender. 1584 */ 1585 if (ic->ic_opmode != IEEE80211_M_STA) { 1586 ni = ieee80211_find_node(ic, wh->i_addr2); 1587 if (ni == NULL) 1588 ni = ieee80211_ref_node(ic->ic_bss); 1589 } else 1590 ni = ieee80211_ref_node(ic->ic_bss); 1591 ATH_NODE(ni)->an_rx_antenna = ds->ds_rxstat.rs_antenna; 1592 /* 1593 * Send frame up for processing. 1594 */ 1595 ieee80211_input(ifp, m, ni, 1596 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 1597 /* 1598 * The frame may have caused the node to be marked for 1599 * reclamation (e.g. in response to a DEAUTH message) 1600 * so use free_node here instead of unref_node. 1601 */ 1602 if (ni == ic->ic_bss) 1603 ieee80211_unref_node(&ni); 1604 else 1605 ieee80211_free_node(ic, ni); 1606 rx_next: 1607 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1608 } while (ath_rxbuf_init(sc, bf) == 0); 1609 1610 ath_hal_rxmonitor(ah); /* rx signal state monitoring */ 1611 ath_hal_rxena(ah); /* in case of RXEOL */ 1612 } 1613 1614 /* 1615 * XXX Size of an ACK control frame in bytes. 1616 */ 1617 #define IEEE80211_ACK_SIZE (2+2+IEEE80211_ADDR_LEN+4) 1618 1619 static int 1620 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 1621 struct mbuf *m0) 1622 { 1623 struct ieee80211com *ic = &sc->sc_ic; 1624 struct ath_hal *ah = sc->sc_ah; 1625 struct ifnet *ifp = &sc->sc_ic.ic_if; 1626 int i, error, iswep, hdrlen, pktlen; 1627 u_int8_t rix, cix, txrate, ctsrate; 1628 struct ath_desc *ds; 1629 struct mbuf *m; 1630 struct ieee80211_frame *wh; 1631 u_int32_t iv; 1632 u_int8_t *ivp; 1633 u_int8_t hdrbuf[sizeof(struct ieee80211_frame) + 1634 IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN]; 1635 u_int subtype, flags, ctsduration, antenna; 1636 HAL_PKT_TYPE atype; 1637 const HAL_RATE_TABLE *rt; 1638 HAL_BOOL shortPreamble; 1639 struct ath_node *an; 1640 1641 wh = mtod(m0, struct ieee80211_frame *); 1642 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1643 hdrlen = sizeof(struct ieee80211_frame); 1644 pktlen = m0->m_pkthdr.len; 1645 1646 if (iswep) { 1647 memcpy(hdrbuf, mtod(m0, caddr_t), hdrlen); 1648 m_adj(m0, hdrlen); 1649 M_PREPEND(m0, sizeof(hdrbuf), M_DONTWAIT); 1650 if (m0 == NULL) { 1651 sc->sc_stats.ast_tx_nombuf++; 1652 return ENOMEM; 1653 } 1654 ivp = hdrbuf + hdrlen; 1655 /* 1656 * XXX 1657 * IV must not duplicate during the lifetime of the key. 1658 * But no mechanism to renew keys is defined in IEEE 802.11 1659 * WEP. And IV may be duplicated between other stations 1660 * because of the session key itself is shared. 1661 * So we use pseudo random IV for now, though it is not the 1662 * right way. 1663 */ 1664 iv = arc4random(); 1665 for (i = 0; i < IEEE80211_WEP_IVLEN; i++) { 1666 ivp[i] = iv; 1667 iv >>= 8; 1668 } 1669 ivp[i] = sc->sc_ic.ic_wep_txkey << 6; /* Key ID and pad */ 1670 memcpy(mtod(m0, caddr_t), hdrbuf, sizeof(hdrbuf)); 1671 /* 1672 * The ICV length must be included into hdrlen and pktlen. 1673 */ 1674 hdrlen = sizeof(hdrbuf) + IEEE80211_WEP_CRCLEN; 1675 pktlen = m0->m_pkthdr.len + IEEE80211_WEP_CRCLEN; 1676 } 1677 pktlen += IEEE80211_CRC_LEN; 1678 1679 /* 1680 * Load the DMA map so any coalescing is done. This 1681 * also calculates the number of descriptors we need. 1682 */ 1683 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1684 ath_mbuf_load_cb, bf, 1685 BUS_DMA_NOWAIT); 1686 if (error != 0) { 1687 sc->sc_stats.ast_tx_busdma++; 1688 m_freem(m0); 1689 return error; 1690 } 1691 /* 1692 * Discard null packets and check for packets that 1693 * require too many TX descriptors. We try to convert 1694 * the latter to a cluster. 1695 */ 1696 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 1697 sc->sc_stats.ast_tx_linear++; 1698 MGETHDR(m, M_DONTWAIT, MT_DATA); 1699 if (m == NULL) { 1700 sc->sc_stats.ast_tx_nombuf++; 1701 m_freem(m0); 1702 return ENOMEM; 1703 } 1704 M_MOVE_PKTHDR(m, m0); 1705 MCLGET(m, M_DONTWAIT); 1706 if ((m->m_flags & M_EXT) == 0) { 1707 sc->sc_stats.ast_tx_nomcl++; 1708 m_freem(m0); 1709 m_free(m); 1710 return ENOMEM; 1711 } 1712 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1713 m_freem(m0); 1714 m->m_len = m->m_pkthdr.len; 1715 m0 = m; 1716 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1717 ath_mbuf_load_cb, bf, 1718 BUS_DMA_NOWAIT); 1719 if (error != 0) { 1720 sc->sc_stats.ast_tx_busdma++; 1721 m_freem(m0); 1722 return error; 1723 } 1724 KASSERT(bf->bf_nseg == 1, 1725 ("ath_tx_start: packet not one segment; nseg %u", 1726 bf->bf_nseg)); 1727 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 1728 sc->sc_stats.ast_tx_nodata++; 1729 m_freem(m0); 1730 return EIO; 1731 } 1732 DPRINTF2(("ath_tx_start: m %p len %u\n", m0, pktlen)); 1733 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1734 bf->bf_m = m0; 1735 bf->bf_node = ni; /* NB: held reference */ 1736 1737 /* setup descriptors */ 1738 ds = bf->bf_desc; 1739 rt = sc->sc_currates; 1740 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1741 1742 /* 1743 * Calculate Atheros packet type from IEEE80211 packet header 1744 * and setup for rate calculations. 1745 */ 1746 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1747 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1748 case IEEE80211_FC0_TYPE_MGT: 1749 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1750 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1751 atype = HAL_PKT_TYPE_BEACON; 1752 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1753 atype = HAL_PKT_TYPE_PROBE_RESP; 1754 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1755 atype = HAL_PKT_TYPE_ATIM; 1756 rix = 0; /* XXX lowest rate */ 1757 break; 1758 case IEEE80211_FC0_TYPE_CTL: 1759 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1760 if (subtype == IEEE80211_FC0_SUBTYPE_PS_POLL) 1761 atype = HAL_PKT_TYPE_PSPOLL; 1762 rix = 0; /* XXX lowest rate */ 1763 break; 1764 default: 1765 rix = sc->sc_rixmap[ni->ni_rates.rs_rates[ni->ni_txrate] & 1766 IEEE80211_RATE_VAL]; 1767 if (rix == 0xff) { 1768 if_printf(ifp, "bogus xmit rate 0x%x\n", 1769 ni->ni_rates.rs_rates[ni->ni_txrate]); 1770 sc->sc_stats.ast_tx_badrate++; 1771 m_freem(m0); 1772 return EIO; 1773 } 1774 break; 1775 } 1776 /* 1777 * NB: the 802.11 layer marks whether or not we should 1778 * use short preamble based on the current mode and 1779 * negotiated parameters. 1780 */ 1781 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1782 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1783 txrate = rt->info[rix].rateCode | rt->info[rix].shortPreamble; 1784 shortPreamble = AH_TRUE; 1785 sc->sc_stats.ast_tx_shortpre++; 1786 } else { 1787 txrate = rt->info[rix].rateCode; 1788 shortPreamble = AH_FALSE; 1789 } 1790 1791 /* 1792 * Calculate miscellaneous flags. 1793 */ 1794 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for wep errors */ 1795 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1796 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1797 sc->sc_stats.ast_tx_noack++; 1798 } else if (pktlen > ic->ic_rtsthreshold) { 1799 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1800 sc->sc_stats.ast_tx_rts++; 1801 } 1802 1803 /* 1804 * Calculate duration. This logically belongs in the 802.11 1805 * layer but it lacks sufficient information to calculate it. 1806 */ 1807 if ((flags & HAL_TXDESC_NOACK) == 0 && 1808 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 1809 u_int16_t dur; 1810 /* 1811 * XXX not right with fragmentation. 1812 */ 1813 dur = ath_hal_computetxtime(ah, rt, IEEE80211_ACK_SIZE, 1814 rix, shortPreamble); 1815 *((u_int16_t*) wh->i_dur) = htole16(dur); 1816 } 1817 1818 /* 1819 * Calculate RTS/CTS rate and duration if needed. 1820 */ 1821 ctsduration = 0; 1822 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 1823 /* 1824 * CTS transmit rate is derived from the transmit rate 1825 * by looking in the h/w rate table. We must also factor 1826 * in whether or not a short preamble is to be used. 1827 */ 1828 cix = rt->info[rix].controlRate; 1829 ctsrate = rt->info[cix].rateCode; 1830 if (shortPreamble) 1831 ctsrate |= rt->info[cix].shortPreamble; 1832 /* 1833 * Compute the transmit duration based on the size 1834 * of an ACK frame. We call into the HAL to do the 1835 * computation since it depends on the characteristics 1836 * of the actual PHY being used. 1837 */ 1838 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 1839 ctsduration += ath_hal_computetxtime(ah, 1840 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 1841 } 1842 /* SIFS + data */ 1843 ctsduration += ath_hal_computetxtime(ah, 1844 rt, pktlen, rix, shortPreamble); 1845 if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 1846 ctsduration += ath_hal_computetxtime(ah, 1847 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 1848 } 1849 } else 1850 ctsrate = 0; 1851 1852 /* 1853 * For now use the antenna on which the last good 1854 * frame was received on. We assume this field is 1855 * initialized to 0 which gives us ``auto'' or the 1856 * ``default'' antenna. 1857 */ 1858 an = (struct ath_node *) ni; 1859 if (an->an_tx_antenna) 1860 antenna = an->an_tx_antenna; 1861 else 1862 antenna = an->an_rx_antenna; 1863 1864 /* 1865 * Formulate first tx descriptor with tx controls. 1866 */ 1867 /* XXX check return value? */ 1868 ath_hal_setuptxdesc(ah, ds 1869 , pktlen /* packet length */ 1870 , hdrlen /* header length */ 1871 , atype /* Atheros packet type */ 1872 , 60 /* txpower XXX */ 1873 , txrate, 1+10 /* series 0 rate/tries */ 1874 , iswep ? sc->sc_ic.ic_wep_txkey : HAL_TXKEYIX_INVALID 1875 , antenna /* antenna mode */ 1876 , flags /* flags */ 1877 , ctsrate /* rts/cts rate */ 1878 , ctsduration /* rts/cts duration */ 1879 ); 1880 #ifdef notyet 1881 ath_hal_setupxtxdesc(ah, ds 1882 , AH_FALSE /* short preamble */ 1883 , 0, 0 /* series 1 rate/tries */ 1884 , 0, 0 /* series 2 rate/tries */ 1885 , 0, 0 /* series 3 rate/tries */ 1886 ); 1887 #endif 1888 /* 1889 * Fillin the remainder of the descriptor info. 1890 */ 1891 for (i = 0; i < bf->bf_nseg; i++, ds++) { 1892 ds->ds_data = bf->bf_segs[i].ds_addr; 1893 if (i == bf->bf_nseg - 1) 1894 ds->ds_link = 0; 1895 else 1896 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 1897 ath_hal_filltxdesc(ah, ds 1898 , bf->bf_segs[i].ds_len /* segment length */ 1899 , i == 0 /* first segment */ 1900 , i == bf->bf_nseg - 1 /* last segment */ 1901 ); 1902 DPRINTF2(("ath_tx_start: %d: %08x %08x %08x %08x %08x %08x\n", 1903 i, ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, 1904 ds->ds_hw[0], ds->ds_hw[1])); 1905 } 1906 1907 /* 1908 * Insert the frame on the outbound list and 1909 * pass it on to the hardware. 1910 */ 1911 mtx_lock(&sc->sc_txqlock); 1912 TAILQ_INSERT_TAIL(&sc->sc_txq, bf, bf_list); 1913 if (sc->sc_txlink == NULL) { 1914 ath_hal_puttxbuf(ah, sc->sc_txhalq, bf->bf_daddr); 1915 DPRINTF2(("ath_tx_start: TXDP0 = %p (%p)\n", 1916 (caddr_t)bf->bf_daddr, bf->bf_desc)); 1917 } else { 1918 *sc->sc_txlink = bf->bf_daddr; 1919 DPRINTF2(("ath_tx_start: link(%p)=%p (%p)\n", 1920 sc->sc_txlink, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1921 } 1922 sc->sc_txlink = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 1923 mtx_unlock(&sc->sc_txqlock); 1924 1925 ath_hal_txstart(ah, sc->sc_txhalq); 1926 return 0; 1927 } 1928 1929 static void 1930 ath_tx_proc(void *arg, int npending) 1931 { 1932 struct ath_softc *sc = arg; 1933 struct ath_hal *ah = sc->sc_ah; 1934 struct ath_buf *bf; 1935 struct ieee80211com *ic = &sc->sc_ic; 1936 struct ifnet *ifp = &ic->ic_if; 1937 struct ath_desc *ds; 1938 struct ieee80211_node *ni; 1939 struct ath_node *an; 1940 int sr, lr; 1941 HAL_STATUS status; 1942 1943 DPRINTF2(("ath_tx_proc: pending %u tx queue %p, link %p\n", 1944 npending, (caddr_t) ath_hal_gettxbuf(sc->sc_ah, sc->sc_txhalq), 1945 sc->sc_txlink)); 1946 for (;;) { 1947 mtx_lock(&sc->sc_txqlock); 1948 bf = TAILQ_FIRST(&sc->sc_txq); 1949 if (bf == NULL) { 1950 sc->sc_txlink = NULL; 1951 mtx_unlock(&sc->sc_txqlock); 1952 break; 1953 } 1954 /* only the last descriptor is needed */ 1955 ds = &bf->bf_desc[bf->bf_nseg - 1]; 1956 status = ath_hal_txprocdesc(ah, ds); 1957 #ifdef AR_DEBUG 1958 if (ath_debug > 1) 1959 ath_printtxbuf(bf, status == HAL_OK); 1960 #endif 1961 if (status == HAL_EINPROGRESS) { 1962 mtx_unlock(&sc->sc_txqlock); 1963 break; 1964 } 1965 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 1966 mtx_unlock(&sc->sc_txqlock); 1967 1968 ni = bf->bf_node; 1969 if (ni != NULL) { 1970 an = (struct ath_node *) ni; 1971 if (ds->ds_txstat.ts_status == 0) { 1972 an->an_tx_ok++; 1973 an->an_tx_antenna = ds->ds_txstat.ts_antenna; 1974 } else { 1975 an->an_tx_err++; 1976 ifp->if_oerrors++; 1977 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 1978 sc->sc_stats.ast_tx_xretries++; 1979 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 1980 sc->sc_stats.ast_tx_fifoerr++; 1981 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 1982 sc->sc_stats.ast_tx_filtered++; 1983 an->an_tx_antenna = 0; /* invalidate */ 1984 } 1985 sr = ds->ds_txstat.ts_shortretry; 1986 lr = ds->ds_txstat.ts_longretry; 1987 sc->sc_stats.ast_tx_shortretry += sr; 1988 sc->sc_stats.ast_tx_longretry += lr; 1989 if (sr + lr) 1990 an->an_tx_retr++; 1991 /* 1992 * Reclaim reference to node. 1993 * 1994 * NB: the node may be reclaimed here if, for example 1995 * this is a DEAUTH message that was sent and the 1996 * node was timed out due to inactivity. 1997 */ 1998 if (ni != ic->ic_bss) 1999 ieee80211_free_node(ic, ni); 2000 } 2001 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2002 BUS_DMASYNC_POSTWRITE); 2003 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2004 m_freem(bf->bf_m); 2005 bf->bf_m = NULL; 2006 bf->bf_node = NULL; 2007 2008 mtx_lock(&sc->sc_txbuflock); 2009 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2010 mtx_unlock(&sc->sc_txbuflock); 2011 } 2012 ifp->if_flags &= ~IFF_OACTIVE; 2013 sc->sc_tx_timer = 0; 2014 2015 ath_start(ifp); 2016 } 2017 2018 /* 2019 * Drain the transmit queue and reclaim resources. 2020 */ 2021 static void 2022 ath_draintxq(struct ath_softc *sc) 2023 { 2024 struct ath_hal *ah = sc->sc_ah; 2025 struct ifnet *ifp = &sc->sc_ic.ic_if; 2026 struct ath_buf *bf; 2027 2028 /* XXX return value */ 2029 if (!sc->sc_invalid) { 2030 /* don't touch the hardware if marked invalid */ 2031 (void) ath_hal_stoptxdma(ah, sc->sc_txhalq); 2032 DPRINTF(("ath_draintxq: tx queue %p, link %p\n", 2033 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_txhalq), 2034 sc->sc_txlink)); 2035 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 2036 DPRINTF(("ath_draintxq: beacon queue %p\n", 2037 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq))); 2038 } 2039 for (;;) { 2040 mtx_lock(&sc->sc_txqlock); 2041 bf = TAILQ_FIRST(&sc->sc_txq); 2042 if (bf == NULL) { 2043 sc->sc_txlink = NULL; 2044 mtx_unlock(&sc->sc_txqlock); 2045 break; 2046 } 2047 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2048 mtx_unlock(&sc->sc_txqlock); 2049 #ifdef AR_DEBUG 2050 if (ath_debug) 2051 ath_printtxbuf(bf, 2052 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 2053 #endif /* AR_DEBUG */ 2054 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2055 m_freem(bf->bf_m); 2056 bf->bf_m = NULL; 2057 bf->bf_node = NULL; 2058 mtx_lock(&sc->sc_txbuflock); 2059 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2060 mtx_unlock(&sc->sc_txbuflock); 2061 } 2062 ifp->if_flags &= ~IFF_OACTIVE; 2063 sc->sc_tx_timer = 0; 2064 } 2065 2066 /* 2067 * Disable the receive h/w in preparation for a reset. 2068 */ 2069 static void 2070 ath_stoprecv(struct ath_softc *sc) 2071 { 2072 struct ath_hal *ah = sc->sc_ah; 2073 2074 ath_hal_stoppcurecv(ah); /* disable PCU */ 2075 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 2076 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 2077 DELAY(3000); /* long enough for 1 frame */ 2078 #ifdef AR_DEBUG 2079 if (ath_debug) { 2080 struct ath_buf *bf; 2081 2082 DPRINTF(("ath_stoprecv: rx queue %p, link %p\n", 2083 (caddr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink)); 2084 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2085 if (ath_hal_rxprocdesc(ah, bf->bf_desc) == HAL_OK) 2086 ath_printrxbuf(bf, 1); 2087 } 2088 } 2089 #endif 2090 sc->sc_rxlink = NULL; /* just in case */ 2091 } 2092 2093 /* 2094 * Enable the receive h/w following a reset. 2095 */ 2096 static int 2097 ath_startrecv(struct ath_softc *sc) 2098 { 2099 struct ath_hal *ah = sc->sc_ah; 2100 struct ath_buf *bf; 2101 2102 sc->sc_rxlink = NULL; 2103 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2104 int error = ath_rxbuf_init(sc, bf); 2105 if (error != 0) { 2106 DPRINTF(("ath_startrecv: ath_rxbuf_init failed %d\n", 2107 error)); 2108 return error; 2109 } 2110 } 2111 2112 bf = TAILQ_FIRST(&sc->sc_rxbuf); 2113 ath_hal_putrxbuf(ah, bf->bf_daddr); 2114 ath_hal_rxena(ah); /* enable recv descriptors */ 2115 ath_mode_init(sc); /* set filters, etc. */ 2116 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 2117 return 0; 2118 } 2119 2120 /* 2121 * Set/change channels. If the channel is really being changed, 2122 * it's done by resetting the chip. To accomplish this we must 2123 * first cleanup any pending DMA, then restart stuff after a la 2124 * ath_init. 2125 */ 2126 static int 2127 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 2128 { 2129 struct ath_hal *ah = sc->sc_ah; 2130 struct ieee80211com *ic = &sc->sc_ic; 2131 2132 DPRINTF(("ath_chan_set: %u (%u MHz) -> %u (%u MHz)\n", 2133 ieee80211_chan2ieee(ic, ic->ic_ibss_chan), 2134 ic->ic_ibss_chan->ic_freq, 2135 ieee80211_chan2ieee(ic, chan), chan->ic_freq)); 2136 if (chan != ic->ic_ibss_chan) { 2137 HAL_STATUS status; 2138 HAL_CHANNEL hchan; 2139 enum ieee80211_phymode mode; 2140 2141 /* 2142 * To switch channels clear any pending DMA operations; 2143 * wait long enough for the RX fifo to drain, reset the 2144 * hardware at the new frequency, and then re-enable 2145 * the relevant bits of the h/w. 2146 */ 2147 ath_hal_intrset(ah, 0); /* disable interrupts */ 2148 ath_draintxq(sc); /* clear pending tx frames */ 2149 ath_stoprecv(sc); /* turn off frame recv */ 2150 /* 2151 * Convert to a HAL channel description with 2152 * the flags constrained to reflect the current 2153 * operating mode. 2154 */ 2155 hchan.channel = chan->ic_freq; 2156 hchan.channelFlags = ath_chan2flags(ic, chan); 2157 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 2158 if_printf(&ic->ic_if, "ath_chan_set: unable to reset " 2159 "channel %u (%u Mhz)\n", 2160 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 2161 return EIO; 2162 } 2163 /* 2164 * Re-enable rx framework. 2165 */ 2166 if (ath_startrecv(sc) != 0) { 2167 if_printf(&ic->ic_if, 2168 "ath_chan_set: unable to restart recv logic\n"); 2169 return EIO; 2170 } 2171 2172 /* 2173 * Update BPF state. 2174 */ 2175 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 2176 htole16(chan->ic_freq); 2177 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 2178 htole16(chan->ic_flags); 2179 2180 /* 2181 * Change channels and update the h/w rate map 2182 * if we're switching; e.g. 11a to 11b/g. 2183 */ 2184 ic->ic_ibss_chan = chan; 2185 mode = ieee80211_chan2mode(ic, chan); 2186 if (mode != sc->sc_curmode) 2187 ath_setcurmode(sc, mode); 2188 2189 /* 2190 * Re-enable interrupts. 2191 */ 2192 ath_hal_intrset(ah, sc->sc_imask); 2193 } 2194 return 0; 2195 } 2196 2197 static void 2198 ath_next_scan(void *arg) 2199 { 2200 struct ath_softc *sc = arg; 2201 struct ieee80211com *ic = &sc->sc_ic; 2202 struct ifnet *ifp = &ic->ic_if; 2203 2204 if (ic->ic_state == IEEE80211_S_SCAN) 2205 ieee80211_next_scan(ifp); 2206 } 2207 2208 /* 2209 * Periodically recalibrate the PHY to account 2210 * for temperature/environment changes. 2211 */ 2212 static void 2213 ath_calibrate(void *arg) 2214 { 2215 struct ath_softc *sc = arg; 2216 struct ath_hal *ah = sc->sc_ah; 2217 struct ieee80211com *ic = &sc->sc_ic; 2218 struct ieee80211_channel *c; 2219 HAL_CHANNEL hchan; 2220 2221 sc->sc_stats.ast_per_cal++; 2222 2223 /* 2224 * Convert to a HAL channel description with the flags 2225 * constrained to reflect the current operating mode. 2226 */ 2227 c = ic->ic_ibss_chan; 2228 hchan.channel = c->ic_freq; 2229 hchan.channelFlags = ath_chan2flags(ic, c); 2230 2231 DPRINTF(("%s: channel %u/%x\n", __func__, c->ic_freq, c->ic_flags)); 2232 2233 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 2234 /* 2235 * Rfgain is out of bounds, reset the chip 2236 * to load new gain values. 2237 */ 2238 sc->sc_stats.ast_per_rfgain++; 2239 ath_reset(sc); 2240 } 2241 if (!ath_hal_calibrate(ah, &hchan)) { 2242 DPRINTF(("%s: calibration of channel %u failed\n", 2243 __func__, c->ic_freq)); 2244 sc->sc_stats.ast_per_calfail++; 2245 } 2246 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, ath_calibrate, sc); 2247 } 2248 2249 static int 2250 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2251 { 2252 struct ifnet *ifp = &ic->ic_if; 2253 struct ath_softc *sc = ifp->if_softc; 2254 struct ath_hal *ah = sc->sc_ah; 2255 struct ieee80211_node *ni; 2256 int i, error; 2257 u_int8_t *bssid; 2258 u_int32_t rfilt; 2259 static const HAL_LED_STATE leds[] = { 2260 HAL_LED_INIT, /* IEEE80211_S_INIT */ 2261 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 2262 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 2263 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 2264 HAL_LED_RUN, /* IEEE80211_S_RUN */ 2265 }; 2266 2267 DPRINTF(("%s: %s -> %s\n", __func__, 2268 ieee80211_state_name[ic->ic_state], 2269 ieee80211_state_name[nstate])); 2270 2271 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 2272 2273 if (nstate == IEEE80211_S_INIT) { 2274 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2275 ath_hal_intrset(ah, sc->sc_imask); 2276 callout_stop(&sc->sc_scan_ch); 2277 callout_stop(&sc->sc_cal_ch); 2278 return (*sc->sc_newstate)(ic, nstate, arg); 2279 } 2280 ni = ic->ic_bss; 2281 error = ath_chan_set(sc, ni->ni_chan); 2282 if (error != 0) 2283 goto bad; 2284 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 2285 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2286 if (ic->ic_opmode != IEEE80211_M_STA) 2287 rfilt |= HAL_RX_FILTER_PROBEREQ; 2288 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2289 (ifp->if_flags & IFF_PROMISC)) 2290 rfilt |= HAL_RX_FILTER_PROM; 2291 if (nstate == IEEE80211_S_SCAN) { 2292 callout_reset(&sc->sc_scan_ch, (hz * ath_dwelltime) / 1000, 2293 ath_next_scan, sc); 2294 bssid = ifp->if_broadcastaddr; 2295 rfilt |= HAL_RX_FILTER_BEACON; 2296 } else { 2297 callout_stop(&sc->sc_scan_ch); 2298 bssid = ni->ni_bssid; 2299 } 2300 ath_hal_setrxfilter(ah, rfilt); 2301 DPRINTF(("%s: RX filter 0x%x bssid %s\n", 2302 __func__, rfilt, ether_sprintf(bssid))); 2303 2304 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 2305 ath_hal_setassocid(ah, bssid, ni->ni_associd); 2306 else 2307 ath_hal_setassocid(ah, bssid, 0); 2308 if (ic->ic_flags & IEEE80211_F_WEPON) { 2309 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2310 if (ath_hal_keyisvalid(ah, i)) 2311 ath_hal_keysetmac(ah, i, bssid); 2312 } 2313 2314 if (nstate == IEEE80211_S_RUN) { 2315 DPRINTF(("%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 2316 "capinfo=0x%04x chan=%d\n" 2317 , __func__ 2318 , ic->ic_flags 2319 , ni->ni_intval 2320 , ether_sprintf(ni->ni_bssid) 2321 , ni->ni_capinfo 2322 , ieee80211_chan2ieee(ic, ni->ni_chan))); 2323 2324 /* 2325 * Allocate and setup the beacon frame for AP or adhoc mode. 2326 */ 2327 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2328 ic->ic_opmode == IEEE80211_M_IBSS) { 2329 error = ath_beacon_alloc(sc, ni); 2330 if (error != 0) 2331 goto bad; 2332 } 2333 2334 /* 2335 * Configure the beacon and sleep timers. 2336 */ 2337 ath_beacon_config(sc); 2338 2339 /* start periodic recalibration timer */ 2340 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, 2341 ath_calibrate, sc); 2342 } else { 2343 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2344 ath_hal_intrset(ah, sc->sc_imask); 2345 callout_stop(&sc->sc_cal_ch); /* no calibration */ 2346 } 2347 /* 2348 * Reset the rate control state. 2349 */ 2350 ath_rate_ctl_reset(sc, nstate); 2351 /* 2352 * Invoke the parent method to complete the work. 2353 */ 2354 return (*sc->sc_newstate)(ic, nstate, arg); 2355 bad: 2356 callout_stop(&sc->sc_scan_ch); 2357 callout_stop(&sc->sc_cal_ch); 2358 /* NB: do not invoke the parent */ 2359 return error; 2360 } 2361 2362 /* 2363 * Setup driver-specific state for a newly associated node. 2364 * Note that we're called also on a re-associate, the isnew 2365 * param tells us if this is the first time or not. 2366 */ 2367 static void 2368 ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2369 { 2370 if (isnew) { 2371 struct ath_node *an = (struct ath_node *) ni; 2372 2373 an->an_tx_ok = an->an_tx_err = 2374 an->an_tx_retr = an->an_tx_upper = 0; 2375 /* start with highest negotiated rate */ 2376 /* 2377 * XXX should do otherwise but only when 2378 * the rate control algorithm is better. 2379 */ 2380 KASSERT(ni->ni_rates.rs_nrates > 0, 2381 ("new association w/ no rates!")); 2382 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2383 } 2384 } 2385 2386 static int 2387 ath_getchannels(struct ath_softc *sc, u_int cc, HAL_BOOL outdoor) 2388 { 2389 struct ieee80211com *ic = &sc->sc_ic; 2390 struct ifnet *ifp = &ic->ic_if; 2391 struct ath_hal *ah = sc->sc_ah; 2392 HAL_CHANNEL *chans; 2393 int i, ix, nchan; 2394 2395 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 2396 M_TEMP, M_NOWAIT); 2397 if (chans == NULL) { 2398 if_printf(ifp, "unable to allocate channel table\n"); 2399 return ENOMEM; 2400 } 2401 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 2402 cc, HAL_MODE_ALL, outdoor)) { 2403 if_printf(ifp, "unable to collect channel list from hal\n"); 2404 free(chans, M_TEMP); 2405 return EINVAL; 2406 } 2407 2408 /* 2409 * Convert HAL channels to ieee80211 ones and insert 2410 * them in the table according to their channel number. 2411 */ 2412 for (i = 0; i < nchan; i++) { 2413 HAL_CHANNEL *c = &chans[i]; 2414 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 2415 if (ix > IEEE80211_CHAN_MAX) { 2416 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 2417 ix, c->channel, c->channelFlags); 2418 continue; 2419 } 2420 /* NB: flags are known to be compatible */ 2421 if (ic->ic_channels[ix].ic_freq == 0) { 2422 ic->ic_channels[ix].ic_freq = c->channel; 2423 ic->ic_channels[ix].ic_flags = c->channelFlags; 2424 } else { 2425 /* channels overlap; e.g. 11g and 11b */ 2426 ic->ic_channels[ix].ic_flags |= c->channelFlags; 2427 } 2428 } 2429 free(chans, M_TEMP); 2430 return 0; 2431 } 2432 2433 static int 2434 ath_rate_setup(struct ath_softc *sc, u_int mode) 2435 { 2436 struct ath_hal *ah = sc->sc_ah; 2437 struct ieee80211com *ic = &sc->sc_ic; 2438 const HAL_RATE_TABLE *rt; 2439 struct ieee80211_rateset *rs; 2440 int i, maxrates; 2441 2442 switch (mode) { 2443 case IEEE80211_MODE_11A: 2444 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 2445 break; 2446 case IEEE80211_MODE_11B: 2447 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 2448 break; 2449 case IEEE80211_MODE_11G: 2450 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 2451 break; 2452 case IEEE80211_MODE_TURBO: 2453 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 2454 break; 2455 default: 2456 DPRINTF(("%s: invalid mode %u\n", __func__, mode)); 2457 return 0; 2458 } 2459 rt = sc->sc_rates[mode]; 2460 if (rt == NULL) 2461 return 0; 2462 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 2463 DPRINTF(("%s: rate table too small (%u > %u)\n", 2464 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE)); 2465 maxrates = IEEE80211_RATE_MAXSIZE; 2466 } else 2467 maxrates = rt->rateCount; 2468 rs = &ic->ic_sup_rates[mode]; 2469 for (i = 0; i < maxrates; i++) 2470 rs->rs_rates[i] = rt->info[i].dot11Rate; 2471 rs->rs_nrates = maxrates; 2472 return 1; 2473 } 2474 2475 static void 2476 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 2477 { 2478 const HAL_RATE_TABLE *rt; 2479 int i; 2480 2481 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 2482 rt = sc->sc_rates[mode]; 2483 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 2484 for (i = 0; i < rt->rateCount; i++) 2485 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 2486 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 2487 for (i = 0; i < 32; i++) 2488 sc->sc_hwmap[i] = rt->info[rt->rateCodeToIndex[i]].dot11Rate; 2489 sc->sc_currates = rt; 2490 sc->sc_curmode = mode; 2491 } 2492 2493 /* 2494 * Reset the rate control state for each 802.11 state transition. 2495 */ 2496 static void 2497 ath_rate_ctl_reset(struct ath_softc *sc, enum ieee80211_state state) 2498 { 2499 struct ieee80211com *ic = &sc->sc_ic; 2500 struct ieee80211_node *ni; 2501 struct ath_node *an; 2502 2503 an = (struct ath_node *) ic->ic_bss; 2504 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = an->an_tx_upper = 0; 2505 if (ic->ic_opmode == IEEE80211_M_STA) { 2506 ni = ic->ic_bss; 2507 if (state == IEEE80211_S_RUN) { 2508 /* start with highest negotiated rate */ 2509 KASSERT(ni->ni_rates.rs_nrates > 0, 2510 ("transition to RUN state w/ no rates!")); 2511 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2512 } else { 2513 /* use lowest rate */ 2514 ni->ni_txrate = 0; 2515 } 2516 } else { 2517 TAILQ_FOREACH(ni, &ic->ic_node, ni_list) { 2518 ni->ni_txrate = 0; /* use lowest rate */ 2519 an = (struct ath_node *) ni; 2520 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 2521 an->an_tx_upper = 0; 2522 } 2523 } 2524 } 2525 2526 /* 2527 * Examine and potentially adjust the transmit rate. 2528 */ 2529 static void 2530 ath_rate_ctl(void *arg, struct ieee80211_node *ni) 2531 { 2532 struct ath_softc *sc = arg; 2533 struct ath_node *an = (struct ath_node *) ni; 2534 struct ieee80211_rateset *rs = &ni->ni_rates; 2535 int mod = 0, orate, enough; 2536 2537 /* 2538 * Rate control 2539 * XXX: very primitive version. 2540 */ 2541 sc->sc_stats.ast_rate_calls++; 2542 2543 enough = (an->an_tx_ok + an->an_tx_err >= 10); 2544 2545 /* no packet reached -> down */ 2546 if (an->an_tx_err > 0 && an->an_tx_ok == 0) 2547 mod = -1; 2548 2549 /* all packets needs retry in average -> down */ 2550 if (enough && an->an_tx_ok < an->an_tx_retr) 2551 mod = -1; 2552 2553 /* no error and less than 10% of packets needs retry -> up */ 2554 if (enough && an->an_tx_err == 0 && an->an_tx_ok > an->an_tx_retr * 10) 2555 mod = 1; 2556 2557 orate = ni->ni_txrate; 2558 switch (mod) { 2559 case 0: 2560 if (enough && an->an_tx_upper > 0) 2561 an->an_tx_upper--; 2562 break; 2563 case -1: 2564 if (ni->ni_txrate > 0) { 2565 ni->ni_txrate--; 2566 sc->sc_stats.ast_rate_drop++; 2567 } 2568 an->an_tx_upper = 0; 2569 break; 2570 case 1: 2571 if (++an->an_tx_upper < 2) 2572 break; 2573 an->an_tx_upper = 0; 2574 if (ni->ni_txrate + 1 < rs->rs_nrates) { 2575 ni->ni_txrate++; 2576 sc->sc_stats.ast_rate_raise++; 2577 } 2578 break; 2579 } 2580 2581 if (ni->ni_txrate != orate) { 2582 printf("%s: %dM -> %dM (%d ok, %d err, %d retr)\n", 2583 __func__, 2584 (rs->rs_rates[orate] & IEEE80211_RATE_VAL) / 2, 2585 (rs->rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL) / 2, 2586 an->an_tx_ok, an->an_tx_err, an->an_tx_retr); 2587 } 2588 if (ni->ni_txrate != orate || enough) 2589 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 0; 2590 } 2591 2592 #ifdef AR_DEBUG 2593 static int 2594 sysctl_hw_ath_dump(SYSCTL_HANDLER_ARGS) 2595 { 2596 char dmode[64]; 2597 int error; 2598 2599 strncpy(dmode, "", sizeof(dmode) - 1); 2600 dmode[sizeof(dmode) - 1] = '\0'; 2601 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2602 2603 if (error == 0 && req->newptr != NULL) { 2604 struct ifnet *ifp; 2605 struct ath_softc *sc; 2606 2607 ifp = ifunit("ath0"); /* XXX */ 2608 if (!ifp) 2609 return EINVAL; 2610 sc = ifp->if_softc; 2611 if (strcmp(dmode, "hal") == 0) 2612 ath_hal_dumpstate(sc->sc_ah); 2613 else if (strcmp(dmode, "eeprom") == 0) 2614 ath_hal_dumpeeprom(sc->sc_ah); 2615 else if (strcmp(dmode, "rfgain") == 0) 2616 ath_hal_dumprfgain(sc->sc_ah); 2617 else if (strcmp(dmode, "ani") == 0) 2618 ath_hal_dumpani(sc->sc_ah); 2619 else 2620 return EINVAL; 2621 } 2622 return error; 2623 } 2624 SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2625 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state"); 2626 2627 static void 2628 ath_printrxbuf(struct ath_buf *bf, int done) 2629 { 2630 struct ath_desc *ds; 2631 int i; 2632 2633 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2634 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 2635 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2636 ds->ds_link, ds->ds_data, 2637 ds->ds_ctl0, ds->ds_ctl1, 2638 ds->ds_hw[0], ds->ds_hw[1], 2639 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 2640 } 2641 } 2642 2643 static void 2644 ath_printtxbuf(struct ath_buf *bf, int done) 2645 { 2646 struct ath_desc *ds; 2647 int i; 2648 2649 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2650 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 2651 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2652 ds->ds_link, ds->ds_data, 2653 ds->ds_ctl0, ds->ds_ctl1, 2654 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 2655 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 2656 } 2657 } 2658 #endif /* AR_DEBUG */ 2659