1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42 #include "opt_inet.h" 43 #include "opt_ath.h" 44 /* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51 #include "opt_ah.h" 52 #include "opt_wlan.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysctl.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/kernel.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 #include <sys/errno.h> 65 #include <sys/callout.h> 66 #include <sys/bus.h> 67 #include <sys/endian.h> 68 #include <sys/kthread.h> 69 #include <sys/taskqueue.h> 70 #include <sys/priv.h> 71 #include <sys/module.h> 72 #include <sys/ktr.h> 73 #include <sys/smp.h> /* for mp_ncpus */ 74 75 #include <machine/bus.h> 76 77 #include <net/if.h> 78 #include <net/if_var.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_var.h> 87 #include <net80211/ieee80211_regdomain.h> 88 #ifdef IEEE80211_SUPPORT_SUPERG 89 #include <net80211/ieee80211_superg.h> 90 #endif 91 #ifdef IEEE80211_SUPPORT_TDMA 92 #include <net80211/ieee80211_tdma.h> 93 #endif 94 95 #include <net/bpf.h> 96 97 #ifdef INET 98 #include <netinet/in.h> 99 #include <netinet/if_ether.h> 100 #endif 101 102 #include <dev/ath/if_athvar.h> 103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 104 #include <dev/ath/ath_hal/ah_diagcodes.h> 105 106 #include <dev/ath/if_ath_debug.h> 107 #include <dev/ath/if_ath_misc.h> 108 #include <dev/ath/if_ath_tsf.h> 109 #include <dev/ath/if_ath_tx.h> 110 #include <dev/ath/if_ath_sysctl.h> 111 #include <dev/ath/if_ath_led.h> 112 #include <dev/ath/if_ath_keycache.h> 113 #include <dev/ath/if_ath_rx.h> 114 #include <dev/ath/if_ath_rx_edma.h> 115 #include <dev/ath/if_ath_tx_edma.h> 116 #include <dev/ath/if_ath_beacon.h> 117 #include <dev/ath/if_ath_btcoex.h> 118 #include <dev/ath/if_ath_btcoex_mci.h> 119 #include <dev/ath/if_ath_spectral.h> 120 #include <dev/ath/if_ath_lna_div.h> 121 #include <dev/ath/if_athdfs.h> 122 #include <dev/ath/if_ath_ioctl.h> 123 #include <dev/ath/if_ath_descdma.h> 124 125 #ifdef ATH_TX99_DIAG 126 #include <dev/ath/ath_tx99/ath_tx99.h> 127 #endif 128 129 #ifdef ATH_DEBUG_ALQ 130 #include <dev/ath/if_ath_alq.h> 131 #endif 132 133 /* 134 * Only enable this if you're working on PS-POLL support. 135 */ 136 #define ATH_SW_PSQ 137 138 /* 139 * ATH_BCBUF determines the number of vap's that can transmit 140 * beacons and also (currently) the number of vap's that can 141 * have unique mac addresses/bssid. When staggering beacons 142 * 4 is probably a good max as otherwise the beacons become 143 * very closely spaced and there is limited time for cab q traffic 144 * to go out. You can burst beacons instead but that is not good 145 * for stations in power save and at some point you really want 146 * another radio (and channel). 147 * 148 * The limit on the number of mac addresses is tied to our use of 149 * the U/L bit and tracking addresses in a byte; it would be 150 * worthwhile to allow more for applications like proxy sta. 151 */ 152 CTASSERT(ATH_BCBUF <= 8); 153 154 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 155 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 156 const uint8_t [IEEE80211_ADDR_LEN], 157 const uint8_t [IEEE80211_ADDR_LEN]); 158 static void ath_vap_delete(struct ieee80211vap *); 159 static int ath_init(struct ath_softc *); 160 static void ath_stop(struct ath_softc *); 161 static int ath_reset_vap(struct ieee80211vap *, u_long); 162 static int ath_transmit(struct ieee80211com *, struct mbuf *); 163 static int ath_media_change(struct ifnet *); 164 static void ath_watchdog(void *); 165 static void ath_parent(struct ieee80211com *); 166 static void ath_fatal_proc(void *, int); 167 static void ath_bmiss_vap(struct ieee80211vap *); 168 static void ath_bmiss_proc(void *, int); 169 static void ath_key_update_begin(struct ieee80211vap *); 170 static void ath_key_update_end(struct ieee80211vap *); 171 static void ath_update_mcast_hw(struct ath_softc *); 172 static void ath_update_mcast(struct ieee80211com *); 173 static void ath_update_promisc(struct ieee80211com *); 174 static void ath_updateslot(struct ieee80211com *); 175 static void ath_bstuck_proc(void *, int); 176 static void ath_reset_proc(void *, int); 177 static int ath_desc_alloc(struct ath_softc *); 178 static void ath_desc_free(struct ath_softc *); 179 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 180 const uint8_t [IEEE80211_ADDR_LEN]); 181 static void ath_node_cleanup(struct ieee80211_node *); 182 static void ath_node_free(struct ieee80211_node *); 183 static void ath_node_getsignal(const struct ieee80211_node *, 184 int8_t *, int8_t *); 185 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 186 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 187 static int ath_tx_setup(struct ath_softc *, int, int); 188 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 189 static void ath_tx_cleanup(struct ath_softc *); 190 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, 191 int dosched); 192 static void ath_tx_proc_q0(void *, int); 193 static void ath_tx_proc_q0123(void *, int); 194 static void ath_tx_proc(void *, int); 195 static void ath_txq_sched_tasklet(void *, int); 196 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 197 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 198 static void ath_scan_start(struct ieee80211com *); 199 static void ath_scan_end(struct ieee80211com *); 200 static void ath_set_channel(struct ieee80211com *); 201 #ifdef ATH_ENABLE_11N 202 static void ath_update_chw(struct ieee80211com *); 203 #endif /* ATH_ENABLE_11N */ 204 static int ath_set_quiet_ie(struct ieee80211_node *, uint8_t *); 205 static void ath_calibrate(void *); 206 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 207 static void ath_setup_stationkey(struct ieee80211_node *); 208 static void ath_newassoc(struct ieee80211_node *, int); 209 static int ath_setregdomain(struct ieee80211com *, 210 struct ieee80211_regdomain *, int, 211 struct ieee80211_channel []); 212 static void ath_getradiocaps(struct ieee80211com *, int, int *, 213 struct ieee80211_channel []); 214 static int ath_getchannels(struct ath_softc *); 215 216 static int ath_rate_setup(struct ath_softc *, u_int mode); 217 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 218 219 static void ath_announce(struct ath_softc *); 220 221 static void ath_dfs_tasklet(void *, int); 222 static void ath_node_powersave(struct ieee80211_node *, int); 223 static int ath_node_set_tim(struct ieee80211_node *, int); 224 static void ath_node_recv_pspoll(struct ieee80211_node *, struct mbuf *); 225 226 #ifdef IEEE80211_SUPPORT_TDMA 227 #include <dev/ath/if_ath_tdma.h> 228 #endif 229 230 SYSCTL_DECL(_hw_ath); 231 232 /* XXX validate sysctl values */ 233 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 234 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 235 0, "long chip calibration interval (secs)"); 236 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 237 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 238 0, "short chip calibration interval (msecs)"); 239 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 240 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 241 0, "reset chip calibration results (secs)"); 242 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */ 243 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval, 244 0, "ANI calibration (msecs)"); 245 246 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 247 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &ath_rxbuf, 248 0, "rx buffers allocated"); 249 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 250 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RWTUN, &ath_txbuf, 251 0, "tx buffers allocated"); 252 int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */ 253 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RWTUN, &ath_txbuf_mgmt, 254 0, "tx (mgmt) buffers allocated"); 255 256 int ath_bstuck_threshold = 4; /* max missed beacons */ 257 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 258 0, "max missed beacon xmits before chip reset"); 259 260 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 261 262 void 263 ath_legacy_attach_comp_func(struct ath_softc *sc) 264 { 265 266 /* 267 * Special case certain configurations. Note the 268 * CAB queue is handled by these specially so don't 269 * include them when checking the txq setup mask. 270 */ 271 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 272 case 0x01: 273 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 274 break; 275 case 0x0f: 276 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 277 break; 278 default: 279 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 280 break; 281 } 282 } 283 284 /* 285 * Set the target power mode. 286 * 287 * If this is called during a point in time where 288 * the hardware is being programmed elsewhere, it will 289 * simply store it away and update it when all current 290 * uses of the hardware are completed. 291 * 292 * If the chip is going into network sleep or power off, then 293 * we will wait until all uses of the chip are done before 294 * going into network sleep or power off. 295 * 296 * If the chip is being programmed full-awake, then immediately 297 * program it full-awake so we can actually stay awake rather than 298 * the chip potentially going to sleep underneath us. 299 */ 300 void 301 _ath_power_setpower(struct ath_softc *sc, int power_state, int selfgen, 302 const char *file, int line) 303 { 304 ATH_LOCK_ASSERT(sc); 305 306 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d, target=%d, cur=%d\n", 307 __func__, 308 file, 309 line, 310 power_state, 311 sc->sc_powersave_refcnt, 312 sc->sc_target_powerstate, 313 sc->sc_cur_powerstate); 314 315 sc->sc_target_powerstate = power_state; 316 317 /* 318 * Don't program the chip into network sleep if the chip 319 * is being programmed elsewhere. 320 * 321 * However, if the chip is being programmed /awake/, force 322 * the chip awake so we stay awake. 323 */ 324 if ((sc->sc_powersave_refcnt == 0 || power_state == HAL_PM_AWAKE) && 325 power_state != sc->sc_cur_powerstate) { 326 sc->sc_cur_powerstate = power_state; 327 ath_hal_setpower(sc->sc_ah, power_state); 328 329 /* 330 * If the NIC is force-awake, then set the 331 * self-gen frame state appropriately. 332 * 333 * If the nic is in network sleep or full-sleep, 334 * we let the above call leave the self-gen 335 * state as "sleep". 336 */ 337 if (selfgen && 338 sc->sc_cur_powerstate == HAL_PM_AWAKE && 339 sc->sc_target_selfgen_state != HAL_PM_AWAKE) { 340 ath_hal_setselfgenpower(sc->sc_ah, 341 sc->sc_target_selfgen_state); 342 } 343 } 344 } 345 346 /* 347 * Set the current self-generated frames state. 348 * 349 * This is separate from the target power mode. The chip may be 350 * awake but the desired state is "sleep", so frames sent to the 351 * destination has PWRMGT=1 in the 802.11 header. The NIC also 352 * needs to know to set PWRMGT=1 in self-generated frames. 353 */ 354 void 355 _ath_power_set_selfgen(struct ath_softc *sc, int power_state, const char *file, int line) 356 { 357 358 ATH_LOCK_ASSERT(sc); 359 360 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n", 361 __func__, 362 file, 363 line, 364 power_state, 365 sc->sc_target_selfgen_state); 366 367 sc->sc_target_selfgen_state = power_state; 368 369 /* 370 * If the NIC is force-awake, then set the power state. 371 * Network-state and full-sleep will already transition it to 372 * mark self-gen frames as sleeping - and we can't 373 * guarantee the NIC is awake to program the self-gen frame 374 * setting anyway. 375 */ 376 if (sc->sc_cur_powerstate == HAL_PM_AWAKE) { 377 ath_hal_setselfgenpower(sc->sc_ah, power_state); 378 } 379 } 380 381 /* 382 * Set the hardware power mode and take a reference. 383 * 384 * This doesn't update the target power mode in the driver; 385 * it just updates the hardware power state. 386 * 387 * XXX it should only ever force the hardware awake; it should 388 * never be called to set it asleep. 389 */ 390 void 391 _ath_power_set_power_state(struct ath_softc *sc, int power_state, const char *file, int line) 392 { 393 ATH_LOCK_ASSERT(sc); 394 395 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n", 396 __func__, 397 file, 398 line, 399 power_state, 400 sc->sc_powersave_refcnt); 401 402 sc->sc_powersave_refcnt++; 403 404 /* 405 * Only do the power state change if we're not programming 406 * it elsewhere. 407 */ 408 if (power_state != sc->sc_cur_powerstate) { 409 ath_hal_setpower(sc->sc_ah, power_state); 410 sc->sc_cur_powerstate = power_state; 411 /* 412 * Adjust the self-gen powerstate if appropriate. 413 */ 414 if (sc->sc_cur_powerstate == HAL_PM_AWAKE && 415 sc->sc_target_selfgen_state != HAL_PM_AWAKE) { 416 ath_hal_setselfgenpower(sc->sc_ah, 417 sc->sc_target_selfgen_state); 418 } 419 } 420 } 421 422 /* 423 * Restore the power save mode to what it once was. 424 * 425 * This will decrement the reference counter and once it hits 426 * zero, it'll restore the powersave state. 427 */ 428 void 429 _ath_power_restore_power_state(struct ath_softc *sc, const char *file, int line) 430 { 431 432 ATH_LOCK_ASSERT(sc); 433 434 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) refcnt=%d, target state=%d\n", 435 __func__, 436 file, 437 line, 438 sc->sc_powersave_refcnt, 439 sc->sc_target_powerstate); 440 441 if (sc->sc_powersave_refcnt == 0) 442 device_printf(sc->sc_dev, "%s: refcnt=0?\n", __func__); 443 else 444 sc->sc_powersave_refcnt--; 445 446 if (sc->sc_powersave_refcnt == 0 && 447 sc->sc_target_powerstate != sc->sc_cur_powerstate) { 448 sc->sc_cur_powerstate = sc->sc_target_powerstate; 449 ath_hal_setpower(sc->sc_ah, sc->sc_target_powerstate); 450 } 451 452 /* 453 * Adjust the self-gen powerstate if appropriate. 454 */ 455 if (sc->sc_cur_powerstate == HAL_PM_AWAKE && 456 sc->sc_target_selfgen_state != HAL_PM_AWAKE) { 457 ath_hal_setselfgenpower(sc->sc_ah, 458 sc->sc_target_selfgen_state); 459 } 460 461 } 462 463 /* 464 * Configure the initial HAL configuration values based on bus 465 * specific parameters. 466 * 467 * Some PCI IDs and other information may need tweaking. 468 * 469 * XXX TODO: ath9k and the Atheros HAL only program comm2g_switch_enable 470 * if BT antenna diversity isn't enabled. 471 * 472 * So, let's also figure out how to enable BT diversity for AR9485. 473 */ 474 static void 475 ath_setup_hal_config(struct ath_softc *sc, HAL_OPS_CONFIG *ah_config) 476 { 477 /* XXX TODO: only for PCI devices? */ 478 479 if (sc->sc_pci_devinfo & (ATH_PCI_CUS198 | ATH_PCI_CUS230)) { 480 ah_config->ath_hal_ext_lna_ctl_gpio = 0x200; /* bit 9 */ 481 ah_config->ath_hal_ext_atten_margin_cfg = AH_TRUE; 482 ah_config->ath_hal_min_gainidx = AH_TRUE; 483 ah_config->ath_hal_ant_ctrl_comm2g_switch_enable = 0x000bbb88; 484 /* XXX low_rssi_thresh */ 485 /* XXX fast_div_bias */ 486 device_printf(sc->sc_dev, "configuring for %s\n", 487 (sc->sc_pci_devinfo & ATH_PCI_CUS198) ? 488 "CUS198" : "CUS230"); 489 } 490 491 if (sc->sc_pci_devinfo & ATH_PCI_CUS217) 492 device_printf(sc->sc_dev, "CUS217 card detected\n"); 493 494 if (sc->sc_pci_devinfo & ATH_PCI_CUS252) 495 device_printf(sc->sc_dev, "CUS252 card detected\n"); 496 497 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_1ANT) 498 device_printf(sc->sc_dev, "WB335 1-ANT card detected\n"); 499 500 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_2ANT) 501 device_printf(sc->sc_dev, "WB335 2-ANT card detected\n"); 502 503 if (sc->sc_pci_devinfo & ATH_PCI_BT_ANT_DIV) 504 device_printf(sc->sc_dev, 505 "Bluetooth Antenna Diversity card detected\n"); 506 507 if (sc->sc_pci_devinfo & ATH_PCI_KILLER) 508 device_printf(sc->sc_dev, "Killer Wireless card detected\n"); 509 510 #if 0 511 /* 512 * Some WB335 cards do not support antenna diversity. Since 513 * we use a hardcoded value for AR9565 instead of using the 514 * EEPROM/OTP data, remove the combining feature from 515 * the HW capabilities bitmap. 516 */ 517 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 518 if (!(sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV)) 519 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 520 } 521 522 if (sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV) { 523 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 524 device_printf(sc->sc_dev, "Set BT/WLAN RX diversity capability\n"); 525 } 526 #endif 527 528 if (sc->sc_pci_devinfo & ATH_PCI_D3_L1_WAR) { 529 ah_config->ath_hal_pcie_waen = 0x0040473b; 530 device_printf(sc->sc_dev, "Enable WAR for ASPM D3/L1\n"); 531 } 532 533 #if 0 534 if (sc->sc_pci_devinfo & ATH9K_PCI_NO_PLL_PWRSAVE) { 535 ah->config.no_pll_pwrsave = true; 536 device_printf(sc->sc_dev, "Disable PLL PowerSave\n"); 537 } 538 #endif 539 540 } 541 542 /* 543 * Attempt to fetch the MAC address from the kernel environment. 544 * 545 * Returns 0, macaddr in macaddr if successful; -1 otherwise. 546 */ 547 static int 548 ath_fetch_mac_kenv(struct ath_softc *sc, uint8_t *macaddr) 549 { 550 char devid_str[32]; 551 int local_mac = 0; 552 char *local_macstr; 553 554 /* 555 * Fetch from the kenv rather than using hints. 556 * 557 * Hints would be nice but the transition to dynamic 558 * hints/kenv doesn't happen early enough for this 559 * to work reliably (eg on anything embedded.) 560 */ 561 snprintf(devid_str, 32, "hint.%s.%d.macaddr", 562 device_get_name(sc->sc_dev), 563 device_get_unit(sc->sc_dev)); 564 565 if ((local_macstr = kern_getenv(devid_str)) != NULL) { 566 uint32_t tmpmac[ETHER_ADDR_LEN]; 567 int count; 568 int i; 569 570 /* Have a MAC address; should use it */ 571 device_printf(sc->sc_dev, 572 "Overriding MAC address from environment: '%s'\n", 573 local_macstr); 574 575 /* Extract out the MAC address */ 576 count = sscanf(local_macstr, "%x%*c%x%*c%x%*c%x%*c%x%*c%x", 577 &tmpmac[0], &tmpmac[1], 578 &tmpmac[2], &tmpmac[3], 579 &tmpmac[4], &tmpmac[5]); 580 if (count == 6) { 581 /* Valid! */ 582 local_mac = 1; 583 for (i = 0; i < ETHER_ADDR_LEN; i++) 584 macaddr[i] = tmpmac[i]; 585 } 586 /* Done! */ 587 freeenv(local_macstr); 588 local_macstr = NULL; 589 } 590 591 if (local_mac) 592 return (0); 593 return (-1); 594 } 595 596 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20) 597 #define HAL_MODE_HT40 \ 598 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \ 599 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS) 600 int 601 ath_attach(u_int16_t devid, struct ath_softc *sc) 602 { 603 struct ieee80211com *ic = &sc->sc_ic; 604 struct ath_hal *ah = NULL; 605 HAL_STATUS status; 606 int error = 0, i; 607 u_int wmodes; 608 int rx_chainmask, tx_chainmask; 609 HAL_OPS_CONFIG ah_config; 610 611 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 612 613 ic->ic_softc = sc; 614 ic->ic_name = device_get_nameunit(sc->sc_dev); 615 616 /* 617 * Configure the initial configuration data. 618 * 619 * This is stuff that may be needed early during attach 620 * rather than done via configuration calls later. 621 */ 622 bzero(&ah_config, sizeof(ah_config)); 623 ath_setup_hal_config(sc, &ah_config); 624 625 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, 626 sc->sc_eepromdata, &ah_config, &status); 627 if (ah == NULL) { 628 device_printf(sc->sc_dev, 629 "unable to attach hardware; HAL status %u\n", status); 630 error = ENXIO; 631 goto bad; 632 } 633 sc->sc_ah = ah; 634 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 635 #ifdef ATH_DEBUG 636 sc->sc_debug = ath_debug; 637 #endif 638 639 /* 640 * Force the chip awake during setup, just to keep 641 * the HAL/driver power tracking happy. 642 * 643 * There are some methods (eg ath_hal_setmac()) 644 * that poke the hardware. 645 */ 646 ATH_LOCK(sc); 647 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 648 ATH_UNLOCK(sc); 649 650 /* 651 * Setup the DMA/EDMA functions based on the current 652 * hardware support. 653 * 654 * This is required before the descriptors are allocated. 655 */ 656 if (ath_hal_hasedma(sc->sc_ah)) { 657 sc->sc_isedma = 1; 658 ath_recv_setup_edma(sc); 659 ath_xmit_setup_edma(sc); 660 } else { 661 ath_recv_setup_legacy(sc); 662 ath_xmit_setup_legacy(sc); 663 } 664 665 if (ath_hal_hasmybeacon(sc->sc_ah)) { 666 sc->sc_do_mybeacon = 1; 667 } 668 669 /* 670 * Check if the MAC has multi-rate retry support. 671 * We do this by trying to setup a fake extended 672 * descriptor. MAC's that don't have support will 673 * return false w/o doing anything. MAC's that do 674 * support it will return true w/o doing anything. 675 */ 676 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 677 678 /* 679 * Check if the device has hardware counters for PHY 680 * errors. If so we need to enable the MIB interrupt 681 * so we can act on stat triggers. 682 */ 683 if (ath_hal_hwphycounters(ah)) 684 sc->sc_needmib = 1; 685 686 /* 687 * Get the hardware key cache size. 688 */ 689 sc->sc_keymax = ath_hal_keycachesize(ah); 690 if (sc->sc_keymax > ATH_KEYMAX) { 691 device_printf(sc->sc_dev, 692 "Warning, using only %u of %u key cache slots\n", 693 ATH_KEYMAX, sc->sc_keymax); 694 sc->sc_keymax = ATH_KEYMAX; 695 } 696 /* 697 * Reset the key cache since some parts do not 698 * reset the contents on initial power up. 699 */ 700 for (i = 0; i < sc->sc_keymax; i++) 701 ath_hal_keyreset(ah, i); 702 703 /* 704 * Collect the default channel list. 705 */ 706 error = ath_getchannels(sc); 707 if (error != 0) 708 goto bad; 709 710 /* 711 * Setup rate tables for all potential media types. 712 */ 713 ath_rate_setup(sc, IEEE80211_MODE_11A); 714 ath_rate_setup(sc, IEEE80211_MODE_11B); 715 ath_rate_setup(sc, IEEE80211_MODE_11G); 716 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 717 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 718 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 719 ath_rate_setup(sc, IEEE80211_MODE_11NA); 720 ath_rate_setup(sc, IEEE80211_MODE_11NG); 721 ath_rate_setup(sc, IEEE80211_MODE_HALF); 722 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 723 724 /* NB: setup here so ath_rate_update is happy */ 725 ath_setcurmode(sc, IEEE80211_MODE_11A); 726 727 /* 728 * Allocate TX descriptors and populate the lists. 729 */ 730 error = ath_desc_alloc(sc); 731 if (error != 0) { 732 device_printf(sc->sc_dev, 733 "failed to allocate TX descriptors: %d\n", error); 734 goto bad; 735 } 736 error = ath_txdma_setup(sc); 737 if (error != 0) { 738 device_printf(sc->sc_dev, 739 "failed to allocate TX descriptors: %d\n", error); 740 goto bad; 741 } 742 743 /* 744 * Allocate RX descriptors and populate the lists. 745 */ 746 error = ath_rxdma_setup(sc); 747 if (error != 0) { 748 device_printf(sc->sc_dev, 749 "failed to allocate RX descriptors: %d\n", error); 750 goto bad; 751 } 752 753 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 754 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 755 756 ATH_TXBUF_LOCK_INIT(sc); 757 758 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 759 taskqueue_thread_enqueue, &sc->sc_tq); 760 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 761 device_get_nameunit(sc->sc_dev)); 762 763 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc); 764 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 765 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 766 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc); 767 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc); 768 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 769 770 /* 771 * Allocate hardware transmit queues: one queue for 772 * beacon frames and one data queue for each QoS 773 * priority. Note that the hal handles resetting 774 * these queues at the needed time. 775 * 776 * XXX PS-Poll 777 */ 778 sc->sc_bhalq = ath_beaconq_setup(sc); 779 if (sc->sc_bhalq == (u_int) -1) { 780 device_printf(sc->sc_dev, 781 "unable to setup a beacon xmit queue!\n"); 782 error = EIO; 783 goto bad2; 784 } 785 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 786 if (sc->sc_cabq == NULL) { 787 device_printf(sc->sc_dev, "unable to setup CAB xmit queue!\n"); 788 error = EIO; 789 goto bad2; 790 } 791 /* NB: insure BK queue is the lowest priority h/w queue */ 792 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 793 device_printf(sc->sc_dev, 794 "unable to setup xmit queue for %s traffic!\n", 795 ieee80211_wme_acnames[WME_AC_BK]); 796 error = EIO; 797 goto bad2; 798 } 799 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 800 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 801 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 802 /* 803 * Not enough hardware tx queues to properly do WME; 804 * just punt and assign them all to the same h/w queue. 805 * We could do a better job of this if, for example, 806 * we allocate queues when we switch from station to 807 * AP mode. 808 */ 809 if (sc->sc_ac2q[WME_AC_VI] != NULL) 810 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 811 if (sc->sc_ac2q[WME_AC_BE] != NULL) 812 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 813 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 814 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 815 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 816 } 817 818 /* 819 * Attach the TX completion function. 820 * 821 * The non-EDMA chips may have some special case optimisations; 822 * this method gives everyone a chance to attach cleanly. 823 */ 824 sc->sc_tx.xmit_attach_comp_func(sc); 825 826 /* 827 * Setup rate control. Some rate control modules 828 * call back to change the anntena state so expose 829 * the necessary entry points. 830 * XXX maybe belongs in struct ath_ratectrl? 831 */ 832 sc->sc_setdefantenna = ath_setdefantenna; 833 sc->sc_rc = ath_rate_attach(sc); 834 if (sc->sc_rc == NULL) { 835 error = EIO; 836 goto bad2; 837 } 838 839 /* Attach DFS module */ 840 if (! ath_dfs_attach(sc)) { 841 device_printf(sc->sc_dev, 842 "%s: unable to attach DFS\n", __func__); 843 error = EIO; 844 goto bad2; 845 } 846 847 /* Attach spectral module */ 848 if (ath_spectral_attach(sc) < 0) { 849 device_printf(sc->sc_dev, 850 "%s: unable to attach spectral\n", __func__); 851 error = EIO; 852 goto bad2; 853 } 854 855 /* Attach bluetooth coexistence module */ 856 if (ath_btcoex_attach(sc) < 0) { 857 device_printf(sc->sc_dev, 858 "%s: unable to attach bluetooth coexistence\n", __func__); 859 error = EIO; 860 goto bad2; 861 } 862 863 /* Attach LNA diversity module */ 864 if (ath_lna_div_attach(sc) < 0) { 865 device_printf(sc->sc_dev, 866 "%s: unable to attach LNA diversity\n", __func__); 867 error = EIO; 868 goto bad2; 869 } 870 871 /* Start DFS processing tasklet */ 872 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc); 873 874 /* Configure LED state */ 875 sc->sc_blinking = 0; 876 sc->sc_ledstate = 1; 877 sc->sc_ledon = 0; /* low true */ 878 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 879 callout_init(&sc->sc_ledtimer, 1); 880 881 /* 882 * Don't setup hardware-based blinking. 883 * 884 * Although some NICs may have this configured in the 885 * default reset register values, the user may wish 886 * to alter which pins have which function. 887 * 888 * The reference driver attaches the MAC network LED to GPIO1 and 889 * the MAC power LED to GPIO2. However, the DWA-552 cardbus 890 * NIC has these reversed. 891 */ 892 sc->sc_hardled = (1 == 0); 893 sc->sc_led_net_pin = -1; 894 sc->sc_led_pwr_pin = -1; 895 /* 896 * Auto-enable soft led processing for IBM cards and for 897 * 5211 minipci cards. Users can also manually enable/disable 898 * support with a sysctl. 899 */ 900 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 901 ath_led_config(sc); 902 ath_hal_setledstate(ah, HAL_LED_INIT); 903 904 /* XXX not right but it's not used anywhere important */ 905 ic->ic_phytype = IEEE80211_T_OFDM; 906 ic->ic_opmode = IEEE80211_M_STA; 907 ic->ic_caps = 908 IEEE80211_C_STA /* station mode */ 909 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 910 | IEEE80211_C_HOSTAP /* hostap mode */ 911 | IEEE80211_C_MONITOR /* monitor mode */ 912 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 913 | IEEE80211_C_WDS /* 4-address traffic works */ 914 | IEEE80211_C_MBSS /* mesh point link mode */ 915 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 916 | IEEE80211_C_SHSLOT /* short slot time supported */ 917 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 918 #ifndef ATH_ENABLE_11N 919 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 920 #endif 921 | IEEE80211_C_TXFRAG /* handle tx frags */ 922 #ifdef ATH_ENABLE_DFS 923 | IEEE80211_C_DFS /* Enable radar detection */ 924 #endif 925 | IEEE80211_C_PMGT /* Station side power mgmt */ 926 | IEEE80211_C_SWSLEEP 927 ; 928 /* 929 * Query the hal to figure out h/w crypto support. 930 */ 931 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 932 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 933 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 934 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 935 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 936 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 937 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 938 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 939 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 940 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 941 /* 942 * Check if h/w does the MIC and/or whether the 943 * separate key cache entries are required to 944 * handle both tx+rx MIC keys. 945 */ 946 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 947 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 948 /* 949 * If the h/w supports storing tx+rx MIC keys 950 * in one cache slot automatically enable use. 951 */ 952 if (ath_hal_hastkipsplit(ah) || 953 !ath_hal_settkipsplit(ah, AH_FALSE)) 954 sc->sc_splitmic = 1; 955 /* 956 * If the h/w can do TKIP MIC together with WME then 957 * we use it; otherwise we force the MIC to be done 958 * in software by the net80211 layer. 959 */ 960 if (ath_hal_haswmetkipmic(ah)) 961 sc->sc_wmetkipmic = 1; 962 } 963 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 964 /* 965 * Check for multicast key search support. 966 */ 967 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 968 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 969 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 970 } 971 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 972 /* 973 * Mark key cache slots associated with global keys 974 * as in use. If we knew TKIP was not to be used we 975 * could leave the +32, +64, and +32+64 slots free. 976 */ 977 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 978 setbit(sc->sc_keymap, i); 979 setbit(sc->sc_keymap, i+64); 980 if (sc->sc_splitmic) { 981 setbit(sc->sc_keymap, i+32); 982 setbit(sc->sc_keymap, i+32+64); 983 } 984 } 985 /* 986 * TPC support can be done either with a global cap or 987 * per-packet support. The latter is not available on 988 * all parts. We're a bit pedantic here as all parts 989 * support a global cap. 990 */ 991 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 992 ic->ic_caps |= IEEE80211_C_TXPMGT; 993 994 /* 995 * Mark WME capability only if we have sufficient 996 * hardware queues to do proper priority scheduling. 997 */ 998 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 999 ic->ic_caps |= IEEE80211_C_WME; 1000 /* 1001 * Check for misc other capabilities. 1002 */ 1003 if (ath_hal_hasbursting(ah)) 1004 ic->ic_caps |= IEEE80211_C_BURST; 1005 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 1006 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 1007 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 1008 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah); 1009 1010 /* XXX TODO: just make this a "store tx/rx timestamp length" operation */ 1011 if (ath_hal_get_rx_tsf_prec(ah, &i)) { 1012 if (i == 32) { 1013 sc->sc_rxtsf32 = 1; 1014 } 1015 if (bootverbose) 1016 device_printf(sc->sc_dev, "RX timestamp: %d bits\n", i); 1017 } 1018 if (ath_hal_get_tx_tsf_prec(ah, &i)) { 1019 if (bootverbose) 1020 device_printf(sc->sc_dev, "TX timestamp: %d bits\n", i); 1021 } 1022 1023 sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah); 1024 sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah); 1025 sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah); 1026 1027 /* 1028 * Some WB335 cards do not support antenna diversity. Since 1029 * we use a hardcoded value for AR9565 instead of using the 1030 * EEPROM/OTP data, remove the combining feature from 1031 * the HW capabilities bitmap. 1032 */ 1033 /* 1034 * XXX TODO: check reference driver and ath9k for what to do 1035 * here for WB335. I think we have to actually disable the 1036 * LNA div processing in the HAL and instead use the hard 1037 * coded values; and then use BT diversity. 1038 * 1039 * .. but also need to setup MCI too for WB335.. 1040 */ 1041 #if 0 1042 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 1043 device_printf(sc->sc_dev, "%s: WB335: disabling LNA mixer diversity\n", 1044 __func__); 1045 sc->sc_dolnadiv = 0; 1046 } 1047 #endif 1048 1049 if (ath_hal_hasfastframes(ah)) 1050 ic->ic_caps |= IEEE80211_C_FF; 1051 wmodes = ath_hal_getwirelessmodes(ah); 1052 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 1053 ic->ic_caps |= IEEE80211_C_TURBOP; 1054 #ifdef IEEE80211_SUPPORT_TDMA 1055 if (ath_hal_macversion(ah) > 0x78) { 1056 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 1057 ic->ic_tdma_update = ath_tdma_update; 1058 } 1059 #endif 1060 1061 /* 1062 * TODO: enforce that at least this many frames are available 1063 * in the txbuf list before allowing data frames (raw or 1064 * otherwise) to be transmitted. 1065 */ 1066 sc->sc_txq_data_minfree = 10; 1067 1068 /* 1069 * Shorten this to 64 packets, or 1/4 ath_txbuf, whichever 1070 * is smaller. 1071 * 1072 * Anything bigger can potentially see the cabq consume 1073 * almost all buffers, starving everything else, only to 1074 * see most fail to transmit in the given beacon interval. 1075 */ 1076 sc->sc_txq_mcastq_maxdepth = MIN(64, ath_txbuf / 4); 1077 1078 /* 1079 * How deep can the node software TX queue get whilst it's asleep. 1080 */ 1081 sc->sc_txq_node_psq_maxdepth = 16; 1082 1083 /* 1084 * Default the maximum queue to 1/4'th the TX buffers, or 1085 * 64, whichever is smaller. 1086 */ 1087 sc->sc_txq_node_maxdepth = MIN(64, ath_txbuf / 4); 1088 1089 /* Enable CABQ by default */ 1090 sc->sc_cabq_enable = 1; 1091 1092 /* 1093 * Allow the TX and RX chainmasks to be overridden by 1094 * environment variables and/or device.hints. 1095 * 1096 * This must be done early - before the hardware is 1097 * calibrated or before the 802.11n stream calculation 1098 * is done. 1099 */ 1100 if (resource_int_value(device_get_name(sc->sc_dev), 1101 device_get_unit(sc->sc_dev), "rx_chainmask", 1102 &rx_chainmask) == 0) { 1103 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n", 1104 rx_chainmask); 1105 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask); 1106 } 1107 if (resource_int_value(device_get_name(sc->sc_dev), 1108 device_get_unit(sc->sc_dev), "tx_chainmask", 1109 &tx_chainmask) == 0) { 1110 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n", 1111 tx_chainmask); 1112 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask); 1113 } 1114 1115 /* 1116 * Query the TX/RX chainmask configuration. 1117 * 1118 * This is only relevant for 11n devices. 1119 */ 1120 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask); 1121 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask); 1122 1123 /* 1124 * Disable MRR with protected frames by default. 1125 * Only 802.11n series NICs can handle this. 1126 */ 1127 sc->sc_mrrprot = 0; /* XXX should be a capability */ 1128 1129 /* 1130 * Query the enterprise mode information the HAL. 1131 */ 1132 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0, 1133 &sc->sc_ent_cfg) == HAL_OK) 1134 sc->sc_use_ent = 1; 1135 1136 #ifdef ATH_ENABLE_11N 1137 /* 1138 * Query HT capabilities 1139 */ 1140 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK && 1141 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) { 1142 uint32_t rxs, txs; 1143 uint32_t ldpc; 1144 1145 device_printf(sc->sc_dev, "[HT] enabling HT modes\n"); 1146 1147 sc->sc_mrrprot = 1; /* XXX should be a capability */ 1148 1149 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */ 1150 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */ 1151 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */ 1152 | IEEE80211_HTCAP_MAXAMSDU_3839 1153 /* max A-MSDU length */ 1154 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */ 1155 1156 /* 1157 * Enable short-GI for HT20 only if the hardware 1158 * advertises support. 1159 * Notably, anything earlier than the AR9287 doesn't. 1160 */ 1161 if ((ath_hal_getcapability(ah, 1162 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) && 1163 (wmodes & HAL_MODE_HT20)) { 1164 device_printf(sc->sc_dev, 1165 "[HT] enabling short-GI in 20MHz mode\n"); 1166 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20; 1167 } 1168 1169 if (wmodes & HAL_MODE_HT40) 1170 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40 1171 | IEEE80211_HTCAP_SHORTGI40; 1172 1173 /* 1174 * TX/RX streams need to be taken into account when 1175 * negotiating which MCS rates it'll receive and 1176 * what MCS rates are available for TX. 1177 */ 1178 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs); 1179 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs); 1180 ic->ic_txstream = txs; 1181 ic->ic_rxstream = rxs; 1182 1183 /* 1184 * Setup TX and RX STBC based on what the HAL allows and 1185 * the currently configured chainmask set. 1186 * Ie - don't enable STBC TX if only one chain is enabled. 1187 * STBC RX is fine on a single RX chain; it just won't 1188 * provide any real benefit. 1189 */ 1190 if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0, 1191 NULL) == HAL_OK) { 1192 sc->sc_rx_stbc = 1; 1193 device_printf(sc->sc_dev, 1194 "[HT] 1 stream STBC receive enabled\n"); 1195 ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM; 1196 } 1197 if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0, 1198 NULL) == HAL_OK) { 1199 sc->sc_tx_stbc = 1; 1200 device_printf(sc->sc_dev, 1201 "[HT] 1 stream STBC transmit enabled\n"); 1202 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 1203 } 1204 1205 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1, 1206 &sc->sc_rts_aggr_limit); 1207 if (sc->sc_rts_aggr_limit != (64 * 1024)) 1208 device_printf(sc->sc_dev, 1209 "[HT] RTS aggregates limited to %d KiB\n", 1210 sc->sc_rts_aggr_limit / 1024); 1211 1212 /* 1213 * LDPC 1214 */ 1215 if ((ath_hal_getcapability(ah, HAL_CAP_LDPC, 0, &ldpc)) 1216 == HAL_OK && (ldpc == 1)) { 1217 sc->sc_has_ldpc = 1; 1218 device_printf(sc->sc_dev, 1219 "[HT] LDPC transmit/receive enabled\n"); 1220 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC | 1221 IEEE80211_HTC_TXLDPC; 1222 } 1223 1224 1225 device_printf(sc->sc_dev, 1226 "[HT] %d RX streams; %d TX streams\n", rxs, txs); 1227 } 1228 #endif 1229 1230 /* 1231 * Initial aggregation settings. 1232 */ 1233 sc->sc_hwq_limit_aggr = ATH_AGGR_MIN_QDEPTH; 1234 sc->sc_hwq_limit_nonaggr = ATH_NONAGGR_MIN_QDEPTH; 1235 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW; 1236 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH; 1237 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE; 1238 sc->sc_delim_min_pad = 0; 1239 1240 /* 1241 * Check if the hardware requires PCI register serialisation. 1242 * Some of the Owl based MACs require this. 1243 */ 1244 if (mp_ncpus > 1 && 1245 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR, 1246 0, NULL) == HAL_OK) { 1247 sc->sc_ah->ah_config.ah_serialise_reg_war = 1; 1248 device_printf(sc->sc_dev, 1249 "Enabling register serialisation\n"); 1250 } 1251 1252 /* 1253 * Initialise the deferred completed RX buffer list. 1254 */ 1255 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]); 1256 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]); 1257 1258 /* 1259 * Indicate we need the 802.11 header padded to a 1260 * 32-bit boundary for 4-address and QoS frames. 1261 */ 1262 ic->ic_flags |= IEEE80211_F_DATAPAD; 1263 1264 /* 1265 * Query the hal about antenna support. 1266 */ 1267 sc->sc_defant = ath_hal_getdefantenna(ah); 1268 1269 /* 1270 * Not all chips have the VEOL support we want to 1271 * use with IBSS beacons; check here for it. 1272 */ 1273 sc->sc_hasveol = ath_hal_hasveol(ah); 1274 1275 /* get mac address from kenv first, then hardware */ 1276 if (ath_fetch_mac_kenv(sc, ic->ic_macaddr) == 0) { 1277 /* Tell the HAL now about the new MAC */ 1278 ath_hal_setmac(ah, ic->ic_macaddr); 1279 } else { 1280 ath_hal_getmac(ah, ic->ic_macaddr); 1281 } 1282 1283 if (sc->sc_hasbmask) 1284 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 1285 1286 /* NB: used to size node table key mapping array */ 1287 ic->ic_max_keyix = sc->sc_keymax; 1288 /* call MI attach routine. */ 1289 ieee80211_ifattach(ic); 1290 ic->ic_setregdomain = ath_setregdomain; 1291 ic->ic_getradiocaps = ath_getradiocaps; 1292 sc->sc_opmode = HAL_M_STA; 1293 1294 /* override default methods */ 1295 ic->ic_ioctl = ath_ioctl; 1296 ic->ic_parent = ath_parent; 1297 ic->ic_transmit = ath_transmit; 1298 ic->ic_newassoc = ath_newassoc; 1299 ic->ic_updateslot = ath_updateslot; 1300 ic->ic_wme.wme_update = ath_wme_update; 1301 ic->ic_vap_create = ath_vap_create; 1302 ic->ic_vap_delete = ath_vap_delete; 1303 ic->ic_raw_xmit = ath_raw_xmit; 1304 ic->ic_update_mcast = ath_update_mcast; 1305 ic->ic_update_promisc = ath_update_promisc; 1306 ic->ic_node_alloc = ath_node_alloc; 1307 sc->sc_node_free = ic->ic_node_free; 1308 ic->ic_node_free = ath_node_free; 1309 sc->sc_node_cleanup = ic->ic_node_cleanup; 1310 ic->ic_node_cleanup = ath_node_cleanup; 1311 ic->ic_node_getsignal = ath_node_getsignal; 1312 ic->ic_scan_start = ath_scan_start; 1313 ic->ic_scan_end = ath_scan_end; 1314 ic->ic_set_channel = ath_set_channel; 1315 #ifdef ATH_ENABLE_11N 1316 /* 802.11n specific - but just override anyway */ 1317 sc->sc_addba_request = ic->ic_addba_request; 1318 sc->sc_addba_response = ic->ic_addba_response; 1319 sc->sc_addba_stop = ic->ic_addba_stop; 1320 sc->sc_bar_response = ic->ic_bar_response; 1321 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout; 1322 1323 ic->ic_addba_request = ath_addba_request; 1324 ic->ic_addba_response = ath_addba_response; 1325 ic->ic_addba_response_timeout = ath_addba_response_timeout; 1326 ic->ic_addba_stop = ath_addba_stop; 1327 ic->ic_bar_response = ath_bar_response; 1328 1329 ic->ic_update_chw = ath_update_chw; 1330 #endif /* ATH_ENABLE_11N */ 1331 ic->ic_set_quiet = ath_set_quiet_ie; 1332 1333 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 1334 /* 1335 * There's one vendor bitmap entry in the RX radiotap 1336 * header; make sure that's taken into account. 1337 */ 1338 ieee80211_radiotap_attachv(ic, 1339 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0, 1340 ATH_TX_RADIOTAP_PRESENT, 1341 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1, 1342 ATH_RX_RADIOTAP_PRESENT); 1343 #else 1344 /* 1345 * No vendor bitmap/extensions are present. 1346 */ 1347 ieee80211_radiotap_attach(ic, 1348 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 1349 ATH_TX_RADIOTAP_PRESENT, 1350 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1351 ATH_RX_RADIOTAP_PRESENT); 1352 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 1353 1354 /* 1355 * Setup the ALQ logging if required 1356 */ 1357 #ifdef ATH_DEBUG_ALQ 1358 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev)); 1359 if_ath_alq_setcfg(&sc->sc_alq, 1360 sc->sc_ah->ah_macVersion, 1361 sc->sc_ah->ah_macRev, 1362 sc->sc_ah->ah_phyRev, 1363 sc->sc_ah->ah_magic); 1364 #endif 1365 1366 /* 1367 * Setup dynamic sysctl's now that country code and 1368 * regdomain are available from the hal. 1369 */ 1370 ath_sysctlattach(sc); 1371 ath_sysctl_stats_attach(sc); 1372 ath_sysctl_hal_attach(sc); 1373 1374 if (bootverbose) 1375 ieee80211_announce(ic); 1376 ath_announce(sc); 1377 1378 /* 1379 * Put it to sleep for now. 1380 */ 1381 ATH_LOCK(sc); 1382 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1); 1383 ATH_UNLOCK(sc); 1384 1385 return 0; 1386 bad2: 1387 ath_tx_cleanup(sc); 1388 ath_desc_free(sc); 1389 ath_txdma_teardown(sc); 1390 ath_rxdma_teardown(sc); 1391 1392 bad: 1393 if (ah) 1394 ath_hal_detach(ah); 1395 sc->sc_invalid = 1; 1396 return error; 1397 } 1398 1399 int 1400 ath_detach(struct ath_softc *sc) 1401 { 1402 1403 /* 1404 * NB: the order of these is important: 1405 * o stop the chip so no more interrupts will fire 1406 * o call the 802.11 layer before detaching the hal to 1407 * insure callbacks into the driver to delete global 1408 * key cache entries can be handled 1409 * o free the taskqueue which drains any pending tasks 1410 * o reclaim the tx queue data structures after calling 1411 * the 802.11 layer as we'll get called back to reclaim 1412 * node state and potentially want to use them 1413 * o to cleanup the tx queues the hal is called, so detach 1414 * it last 1415 * Other than that, it's straightforward... 1416 */ 1417 1418 /* 1419 * XXX Wake the hardware up first. ath_stop() will still 1420 * wake it up first, but I'd rather do it here just to 1421 * ensure it's awake. 1422 */ 1423 ATH_LOCK(sc); 1424 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1425 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 1426 1427 /* 1428 * Stop things cleanly. 1429 */ 1430 ath_stop(sc); 1431 ATH_UNLOCK(sc); 1432 1433 ieee80211_ifdetach(&sc->sc_ic); 1434 taskqueue_free(sc->sc_tq); 1435 #ifdef ATH_TX99_DIAG 1436 if (sc->sc_tx99 != NULL) 1437 sc->sc_tx99->detach(sc->sc_tx99); 1438 #endif 1439 ath_rate_detach(sc->sc_rc); 1440 #ifdef ATH_DEBUG_ALQ 1441 if_ath_alq_tidyup(&sc->sc_alq); 1442 #endif 1443 ath_lna_div_detach(sc); 1444 ath_btcoex_detach(sc); 1445 ath_spectral_detach(sc); 1446 ath_dfs_detach(sc); 1447 ath_desc_free(sc); 1448 ath_txdma_teardown(sc); 1449 ath_rxdma_teardown(sc); 1450 ath_tx_cleanup(sc); 1451 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 1452 1453 return 0; 1454 } 1455 1456 /* 1457 * MAC address handling for multiple BSS on the same radio. 1458 * The first vap uses the MAC address from the EEPROM. For 1459 * subsequent vap's we set the U/L bit (bit 1) in the MAC 1460 * address and use the next six bits as an index. 1461 */ 1462 static void 1463 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 1464 { 1465 int i; 1466 1467 if (clone && sc->sc_hasbmask) { 1468 /* NB: we only do this if h/w supports multiple bssid */ 1469 for (i = 0; i < 8; i++) 1470 if ((sc->sc_bssidmask & (1<<i)) == 0) 1471 break; 1472 if (i != 0) 1473 mac[0] |= (i << 2)|0x2; 1474 } else 1475 i = 0; 1476 sc->sc_bssidmask |= 1<<i; 1477 sc->sc_hwbssidmask[0] &= ~mac[0]; 1478 if (i == 0) 1479 sc->sc_nbssid0++; 1480 } 1481 1482 static void 1483 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 1484 { 1485 int i = mac[0] >> 2; 1486 uint8_t mask; 1487 1488 if (i != 0 || --sc->sc_nbssid0 == 0) { 1489 sc->sc_bssidmask &= ~(1<<i); 1490 /* recalculate bssid mask from remaining addresses */ 1491 mask = 0xff; 1492 for (i = 1; i < 8; i++) 1493 if (sc->sc_bssidmask & (1<<i)) 1494 mask &= ~((i<<2)|0x2); 1495 sc->sc_hwbssidmask[0] |= mask; 1496 } 1497 } 1498 1499 /* 1500 * Assign a beacon xmit slot. We try to space out 1501 * assignments so when beacons are staggered the 1502 * traffic coming out of the cab q has maximal time 1503 * to go out before the next beacon is scheduled. 1504 */ 1505 static int 1506 assign_bslot(struct ath_softc *sc) 1507 { 1508 u_int slot, free; 1509 1510 free = 0; 1511 for (slot = 0; slot < ATH_BCBUF; slot++) 1512 if (sc->sc_bslot[slot] == NULL) { 1513 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 1514 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 1515 return slot; 1516 free = slot; 1517 /* NB: keep looking for a double slot */ 1518 } 1519 return free; 1520 } 1521 1522 static struct ieee80211vap * 1523 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1524 enum ieee80211_opmode opmode, int flags, 1525 const uint8_t bssid[IEEE80211_ADDR_LEN], 1526 const uint8_t mac0[IEEE80211_ADDR_LEN]) 1527 { 1528 struct ath_softc *sc = ic->ic_softc; 1529 struct ath_vap *avp; 1530 struct ieee80211vap *vap; 1531 uint8_t mac[IEEE80211_ADDR_LEN]; 1532 int needbeacon, error; 1533 enum ieee80211_opmode ic_opmode; 1534 1535 avp = malloc(sizeof(struct ath_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1536 needbeacon = 0; 1537 IEEE80211_ADDR_COPY(mac, mac0); 1538 1539 ATH_LOCK(sc); 1540 ic_opmode = opmode; /* default to opmode of new vap */ 1541 switch (opmode) { 1542 case IEEE80211_M_STA: 1543 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 1544 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 1545 goto bad; 1546 } 1547 if (sc->sc_nvaps) { 1548 /* 1549 * With multiple vaps we must fall back 1550 * to s/w beacon miss handling. 1551 */ 1552 flags |= IEEE80211_CLONE_NOBEACONS; 1553 } 1554 if (flags & IEEE80211_CLONE_NOBEACONS) { 1555 /* 1556 * Station mode w/o beacons are implemented w/ AP mode. 1557 */ 1558 ic_opmode = IEEE80211_M_HOSTAP; 1559 } 1560 break; 1561 case IEEE80211_M_IBSS: 1562 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 1563 device_printf(sc->sc_dev, 1564 "only 1 ibss vap supported\n"); 1565 goto bad; 1566 } 1567 needbeacon = 1; 1568 break; 1569 case IEEE80211_M_AHDEMO: 1570 #ifdef IEEE80211_SUPPORT_TDMA 1571 if (flags & IEEE80211_CLONE_TDMA) { 1572 if (sc->sc_nvaps != 0) { 1573 device_printf(sc->sc_dev, 1574 "only 1 tdma vap supported\n"); 1575 goto bad; 1576 } 1577 needbeacon = 1; 1578 flags |= IEEE80211_CLONE_NOBEACONS; 1579 } 1580 /* fall thru... */ 1581 #endif 1582 case IEEE80211_M_MONITOR: 1583 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 1584 /* 1585 * Adopt existing mode. Adding a monitor or ahdemo 1586 * vap to an existing configuration is of dubious 1587 * value but should be ok. 1588 */ 1589 /* XXX not right for monitor mode */ 1590 ic_opmode = ic->ic_opmode; 1591 } 1592 break; 1593 case IEEE80211_M_HOSTAP: 1594 case IEEE80211_M_MBSS: 1595 needbeacon = 1; 1596 break; 1597 case IEEE80211_M_WDS: 1598 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 1599 device_printf(sc->sc_dev, 1600 "wds not supported in sta mode\n"); 1601 goto bad; 1602 } 1603 /* 1604 * Silently remove any request for a unique 1605 * bssid; WDS vap's always share the local 1606 * mac address. 1607 */ 1608 flags &= ~IEEE80211_CLONE_BSSID; 1609 if (sc->sc_nvaps == 0) 1610 ic_opmode = IEEE80211_M_HOSTAP; 1611 else 1612 ic_opmode = ic->ic_opmode; 1613 break; 1614 default: 1615 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 1616 goto bad; 1617 } 1618 /* 1619 * Check that a beacon buffer is available; the code below assumes it. 1620 */ 1621 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) { 1622 device_printf(sc->sc_dev, "no beacon buffer available\n"); 1623 goto bad; 1624 } 1625 1626 /* STA, AHDEMO? */ 1627 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS || opmode == IEEE80211_M_STA) { 1628 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 1629 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1630 } 1631 1632 vap = &avp->av_vap; 1633 /* XXX can't hold mutex across if_alloc */ 1634 ATH_UNLOCK(sc); 1635 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1636 ATH_LOCK(sc); 1637 if (error != 0) { 1638 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 1639 __func__, error); 1640 goto bad2; 1641 } 1642 1643 /* h/w crypto support */ 1644 vap->iv_key_alloc = ath_key_alloc; 1645 vap->iv_key_delete = ath_key_delete; 1646 vap->iv_key_set = ath_key_set; 1647 vap->iv_key_update_begin = ath_key_update_begin; 1648 vap->iv_key_update_end = ath_key_update_end; 1649 1650 /* override various methods */ 1651 avp->av_recv_mgmt = vap->iv_recv_mgmt; 1652 vap->iv_recv_mgmt = ath_recv_mgmt; 1653 vap->iv_reset = ath_reset_vap; 1654 vap->iv_update_beacon = ath_beacon_update; 1655 avp->av_newstate = vap->iv_newstate; 1656 vap->iv_newstate = ath_newstate; 1657 avp->av_bmiss = vap->iv_bmiss; 1658 vap->iv_bmiss = ath_bmiss_vap; 1659 1660 avp->av_node_ps = vap->iv_node_ps; 1661 vap->iv_node_ps = ath_node_powersave; 1662 1663 avp->av_set_tim = vap->iv_set_tim; 1664 vap->iv_set_tim = ath_node_set_tim; 1665 1666 avp->av_recv_pspoll = vap->iv_recv_pspoll; 1667 vap->iv_recv_pspoll = ath_node_recv_pspoll; 1668 1669 /* Set default parameters */ 1670 1671 /* 1672 * Anything earlier than some AR9300 series MACs don't 1673 * support a smaller MPDU density. 1674 */ 1675 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8; 1676 /* 1677 * All NICs can handle the maximum size, however 1678 * AR5416 based MACs can only TX aggregates w/ RTS 1679 * protection when the total aggregate size is <= 8k. 1680 * However, for now that's enforced by the TX path. 1681 */ 1682 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1683 vap->iv_ampdu_limit = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1684 1685 avp->av_bslot = -1; 1686 if (needbeacon) { 1687 /* 1688 * Allocate beacon state and setup the q for buffered 1689 * multicast frames. We know a beacon buffer is 1690 * available because we checked above. 1691 */ 1692 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf); 1693 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list); 1694 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1695 /* 1696 * Assign the vap to a beacon xmit slot. As above 1697 * this cannot fail to find a free one. 1698 */ 1699 avp->av_bslot = assign_bslot(sc); 1700 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1701 ("beacon slot %u not empty", avp->av_bslot)); 1702 sc->sc_bslot[avp->av_bslot] = vap; 1703 sc->sc_nbcnvaps++; 1704 } 1705 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1706 /* 1707 * Multple vaps are to transmit beacons and we 1708 * have h/w support for TSF adjusting; enable 1709 * use of staggered beacons. 1710 */ 1711 sc->sc_stagbeacons = 1; 1712 } 1713 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1714 } 1715 1716 ic->ic_opmode = ic_opmode; 1717 if (opmode != IEEE80211_M_WDS) { 1718 sc->sc_nvaps++; 1719 if (opmode == IEEE80211_M_STA) 1720 sc->sc_nstavaps++; 1721 if (opmode == IEEE80211_M_MBSS) 1722 sc->sc_nmeshvaps++; 1723 } 1724 switch (ic_opmode) { 1725 case IEEE80211_M_IBSS: 1726 sc->sc_opmode = HAL_M_IBSS; 1727 break; 1728 case IEEE80211_M_STA: 1729 sc->sc_opmode = HAL_M_STA; 1730 break; 1731 case IEEE80211_M_AHDEMO: 1732 #ifdef IEEE80211_SUPPORT_TDMA 1733 if (vap->iv_caps & IEEE80211_C_TDMA) { 1734 sc->sc_tdma = 1; 1735 /* NB: disable tsf adjust */ 1736 sc->sc_stagbeacons = 0; 1737 } 1738 /* 1739 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1740 * just ap mode. 1741 */ 1742 /* fall thru... */ 1743 #endif 1744 case IEEE80211_M_HOSTAP: 1745 case IEEE80211_M_MBSS: 1746 sc->sc_opmode = HAL_M_HOSTAP; 1747 break; 1748 case IEEE80211_M_MONITOR: 1749 sc->sc_opmode = HAL_M_MONITOR; 1750 break; 1751 default: 1752 /* XXX should not happen */ 1753 break; 1754 } 1755 if (sc->sc_hastsfadd) { 1756 /* 1757 * Configure whether or not TSF adjust should be done. 1758 */ 1759 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1760 } 1761 if (flags & IEEE80211_CLONE_NOBEACONS) { 1762 /* 1763 * Enable s/w beacon miss handling. 1764 */ 1765 sc->sc_swbmiss = 1; 1766 } 1767 ATH_UNLOCK(sc); 1768 1769 /* complete setup */ 1770 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status, 1771 mac); 1772 return vap; 1773 bad2: 1774 reclaim_address(sc, mac); 1775 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1776 bad: 1777 free(avp, M_80211_VAP); 1778 ATH_UNLOCK(sc); 1779 return NULL; 1780 } 1781 1782 static void 1783 ath_vap_delete(struct ieee80211vap *vap) 1784 { 1785 struct ieee80211com *ic = vap->iv_ic; 1786 struct ath_softc *sc = ic->ic_softc; 1787 struct ath_hal *ah = sc->sc_ah; 1788 struct ath_vap *avp = ATH_VAP(vap); 1789 1790 ATH_LOCK(sc); 1791 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1792 ATH_UNLOCK(sc); 1793 1794 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 1795 if (sc->sc_running) { 1796 /* 1797 * Quiesce the hardware while we remove the vap. In 1798 * particular we need to reclaim all references to 1799 * the vap state by any frames pending on the tx queues. 1800 */ 1801 ath_hal_intrset(ah, 0); /* disable interrupts */ 1802 /* XXX Do all frames from all vaps/nodes need draining here? */ 1803 ath_stoprecv(sc, 1); /* stop recv side */ 1804 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */ 1805 } 1806 1807 /* .. leave the hardware awake for now. */ 1808 1809 ieee80211_vap_detach(vap); 1810 1811 /* 1812 * XXX Danger Will Robinson! Danger! 1813 * 1814 * Because ieee80211_vap_detach() can queue a frame (the station 1815 * diassociate message?) after we've drained the TXQ and 1816 * flushed the software TXQ, we will end up with a frame queued 1817 * to a node whose vap is about to be freed. 1818 * 1819 * To work around this, flush the hardware/software again. 1820 * This may be racy - the ath task may be running and the packet 1821 * may be being scheduled between sw->hw txq. Tsk. 1822 * 1823 * TODO: figure out why a new node gets allocated somewhere around 1824 * here (after the ath_tx_swq() call; and after an ath_stop() 1825 * call!) 1826 */ 1827 1828 ath_draintxq(sc, ATH_RESET_DEFAULT); 1829 1830 ATH_LOCK(sc); 1831 /* 1832 * Reclaim beacon state. Note this must be done before 1833 * the vap instance is reclaimed as we may have a reference 1834 * to it in the buffer for the beacon frame. 1835 */ 1836 if (avp->av_bcbuf != NULL) { 1837 if (avp->av_bslot != -1) { 1838 sc->sc_bslot[avp->av_bslot] = NULL; 1839 sc->sc_nbcnvaps--; 1840 } 1841 ath_beacon_return(sc, avp->av_bcbuf); 1842 avp->av_bcbuf = NULL; 1843 if (sc->sc_nbcnvaps == 0) { 1844 sc->sc_stagbeacons = 0; 1845 if (sc->sc_hastsfadd) 1846 ath_hal_settsfadjust(sc->sc_ah, 0); 1847 } 1848 /* 1849 * Reclaim any pending mcast frames for the vap. 1850 */ 1851 ath_tx_draintxq(sc, &avp->av_mcastq); 1852 } 1853 /* 1854 * Update bookkeeping. 1855 */ 1856 if (vap->iv_opmode == IEEE80211_M_STA) { 1857 sc->sc_nstavaps--; 1858 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1859 sc->sc_swbmiss = 0; 1860 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1861 vap->iv_opmode == IEEE80211_M_STA || 1862 vap->iv_opmode == IEEE80211_M_MBSS) { 1863 reclaim_address(sc, vap->iv_myaddr); 1864 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1865 if (vap->iv_opmode == IEEE80211_M_MBSS) 1866 sc->sc_nmeshvaps--; 1867 } 1868 if (vap->iv_opmode != IEEE80211_M_WDS) 1869 sc->sc_nvaps--; 1870 #ifdef IEEE80211_SUPPORT_TDMA 1871 /* TDMA operation ceases when the last vap is destroyed */ 1872 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1873 sc->sc_tdma = 0; 1874 sc->sc_swbmiss = 0; 1875 } 1876 #endif 1877 free(avp, M_80211_VAP); 1878 1879 if (sc->sc_running) { 1880 /* 1881 * Restart rx+tx machines if still running (RUNNING will 1882 * be reset if we just destroyed the last vap). 1883 */ 1884 if (ath_startrecv(sc) != 0) 1885 device_printf(sc->sc_dev, 1886 "%s: unable to restart recv logic\n", __func__); 1887 if (sc->sc_beacons) { /* restart beacons */ 1888 #ifdef IEEE80211_SUPPORT_TDMA 1889 if (sc->sc_tdma) 1890 ath_tdma_config(sc, NULL); 1891 else 1892 #endif 1893 ath_beacon_config(sc, NULL); 1894 } 1895 ath_hal_intrset(ah, sc->sc_imask); 1896 } 1897 1898 /* Ok, let the hardware asleep. */ 1899 ath_power_restore_power_state(sc); 1900 ATH_UNLOCK(sc); 1901 } 1902 1903 void 1904 ath_suspend(struct ath_softc *sc) 1905 { 1906 struct ieee80211com *ic = &sc->sc_ic; 1907 1908 sc->sc_resume_up = ic->ic_nrunning != 0; 1909 1910 ieee80211_suspend_all(ic); 1911 /* 1912 * NB: don't worry about putting the chip in low power 1913 * mode; pci will power off our socket on suspend and 1914 * CardBus detaches the device. 1915 * 1916 * XXX TODO: well, that's great, except for non-cardbus 1917 * devices! 1918 */ 1919 1920 /* 1921 * XXX This doesn't wait until all pending taskqueue 1922 * items and parallel transmit/receive/other threads 1923 * are running! 1924 */ 1925 ath_hal_intrset(sc->sc_ah, 0); 1926 taskqueue_block(sc->sc_tq); 1927 1928 ATH_LOCK(sc); 1929 callout_stop(&sc->sc_cal_ch); 1930 ATH_UNLOCK(sc); 1931 1932 /* 1933 * XXX ensure sc_invalid is 1 1934 */ 1935 1936 /* Disable the PCIe PHY, complete with workarounds */ 1937 ath_hal_enablepcie(sc->sc_ah, 1, 1); 1938 } 1939 1940 /* 1941 * Reset the key cache since some parts do not reset the 1942 * contents on resume. First we clear all entries, then 1943 * re-load keys that the 802.11 layer assumes are setup 1944 * in h/w. 1945 */ 1946 static void 1947 ath_reset_keycache(struct ath_softc *sc) 1948 { 1949 struct ieee80211com *ic = &sc->sc_ic; 1950 struct ath_hal *ah = sc->sc_ah; 1951 int i; 1952 1953 ATH_LOCK(sc); 1954 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1955 for (i = 0; i < sc->sc_keymax; i++) 1956 ath_hal_keyreset(ah, i); 1957 ath_power_restore_power_state(sc); 1958 ATH_UNLOCK(sc); 1959 ieee80211_crypto_reload_keys(ic); 1960 } 1961 1962 /* 1963 * Fetch the current chainmask configuration based on the current 1964 * operating channel and options. 1965 */ 1966 static void 1967 ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan) 1968 { 1969 1970 /* 1971 * Set TX chainmask to the currently configured chainmask; 1972 * the TX chainmask depends upon the current operating mode. 1973 */ 1974 sc->sc_cur_rxchainmask = sc->sc_rxchainmask; 1975 if (IEEE80211_IS_CHAN_HT(chan)) { 1976 sc->sc_cur_txchainmask = sc->sc_txchainmask; 1977 } else { 1978 sc->sc_cur_txchainmask = 1; 1979 } 1980 1981 DPRINTF(sc, ATH_DEBUG_RESET, 1982 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n", 1983 __func__, 1984 sc->sc_cur_txchainmask, 1985 sc->sc_cur_rxchainmask); 1986 } 1987 1988 void 1989 ath_resume(struct ath_softc *sc) 1990 { 1991 struct ieee80211com *ic = &sc->sc_ic; 1992 struct ath_hal *ah = sc->sc_ah; 1993 HAL_STATUS status; 1994 1995 ath_hal_enablepcie(ah, 0, 0); 1996 1997 /* 1998 * Must reset the chip before we reload the 1999 * keycache as we were powered down on suspend. 2000 */ 2001 ath_update_chainmasks(sc, 2002 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan); 2003 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2004 sc->sc_cur_rxchainmask); 2005 2006 /* Ensure we set the current power state to on */ 2007 ATH_LOCK(sc); 2008 ath_power_setselfgen(sc, HAL_PM_AWAKE); 2009 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2010 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 2011 ATH_UNLOCK(sc); 2012 2013 ath_hal_reset(ah, sc->sc_opmode, 2014 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 2015 AH_FALSE, HAL_RESET_NORMAL, &status); 2016 ath_reset_keycache(sc); 2017 2018 ATH_RX_LOCK(sc); 2019 sc->sc_rx_stopped = 1; 2020 sc->sc_rx_resetted = 1; 2021 ATH_RX_UNLOCK(sc); 2022 2023 /* Let DFS at it in case it's a DFS channel */ 2024 ath_dfs_radar_enable(sc, ic->ic_curchan); 2025 2026 /* Let spectral at in case spectral is enabled */ 2027 ath_spectral_enable(sc, ic->ic_curchan); 2028 2029 /* 2030 * Let bluetooth coexistence at in case it's needed for this channel 2031 */ 2032 ath_btcoex_enable(sc, ic->ic_curchan); 2033 2034 /* 2035 * If we're doing TDMA, enforce the TXOP limitation for chips that 2036 * support it. 2037 */ 2038 if (sc->sc_hasenforcetxop && sc->sc_tdma) 2039 ath_hal_setenforcetxop(sc->sc_ah, 1); 2040 else 2041 ath_hal_setenforcetxop(sc->sc_ah, 0); 2042 2043 /* Restore the LED configuration */ 2044 ath_led_config(sc); 2045 ath_hal_setledstate(ah, HAL_LED_INIT); 2046 2047 if (sc->sc_resume_up) 2048 ieee80211_resume_all(ic); 2049 2050 ATH_LOCK(sc); 2051 ath_power_restore_power_state(sc); 2052 ATH_UNLOCK(sc); 2053 2054 /* XXX beacons ? */ 2055 } 2056 2057 void 2058 ath_shutdown(struct ath_softc *sc) 2059 { 2060 2061 ATH_LOCK(sc); 2062 ath_stop(sc); 2063 ATH_UNLOCK(sc); 2064 /* NB: no point powering down chip as we're about to reboot */ 2065 } 2066 2067 /* 2068 * Interrupt handler. Most of the actual processing is deferred. 2069 */ 2070 void 2071 ath_intr(void *arg) 2072 { 2073 struct ath_softc *sc = arg; 2074 struct ath_hal *ah = sc->sc_ah; 2075 HAL_INT status = 0; 2076 uint32_t txqs; 2077 2078 /* 2079 * If we're inside a reset path, just print a warning and 2080 * clear the ISR. The reset routine will finish it for us. 2081 */ 2082 ATH_PCU_LOCK(sc); 2083 if (sc->sc_inreset_cnt) { 2084 HAL_INT status; 2085 ath_hal_getisr(ah, &status); /* clear ISR */ 2086 ath_hal_intrset(ah, 0); /* disable further intr's */ 2087 DPRINTF(sc, ATH_DEBUG_ANY, 2088 "%s: in reset, ignoring: status=0x%x\n", 2089 __func__, status); 2090 ATH_PCU_UNLOCK(sc); 2091 return; 2092 } 2093 2094 if (sc->sc_invalid) { 2095 /* 2096 * The hardware is not ready/present, don't touch anything. 2097 * Note this can happen early on if the IRQ is shared. 2098 */ 2099 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 2100 ATH_PCU_UNLOCK(sc); 2101 return; 2102 } 2103 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */ 2104 ATH_PCU_UNLOCK(sc); 2105 return; 2106 } 2107 2108 ATH_LOCK(sc); 2109 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2110 ATH_UNLOCK(sc); 2111 2112 if (sc->sc_ic.ic_nrunning == 0 && sc->sc_running == 0) { 2113 HAL_INT status; 2114 2115 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_nrunning %d sc_running %d\n", 2116 __func__, sc->sc_ic.ic_nrunning, sc->sc_running); 2117 ath_hal_getisr(ah, &status); /* clear ISR */ 2118 ath_hal_intrset(ah, 0); /* disable further intr's */ 2119 ATH_PCU_UNLOCK(sc); 2120 2121 ATH_LOCK(sc); 2122 ath_power_restore_power_state(sc); 2123 ATH_UNLOCK(sc); 2124 return; 2125 } 2126 2127 /* 2128 * Figure out the reason(s) for the interrupt. Note 2129 * that the hal returns a pseudo-ISR that may include 2130 * bits we haven't explicitly enabled so we mask the 2131 * value to insure we only process bits we requested. 2132 */ 2133 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 2134 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 2135 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status); 2136 #ifdef ATH_DEBUG_ALQ 2137 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate, 2138 ah->ah_syncstate); 2139 #endif /* ATH_DEBUG_ALQ */ 2140 #ifdef ATH_KTR_INTR_DEBUG 2141 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5, 2142 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x", 2143 ah->ah_intrstate[0], 2144 ah->ah_intrstate[1], 2145 ah->ah_intrstate[2], 2146 ah->ah_intrstate[3], 2147 ah->ah_intrstate[6]); 2148 #endif 2149 2150 /* Squirrel away SYNC interrupt debugging */ 2151 if (ah->ah_syncstate != 0) { 2152 int i; 2153 for (i = 0; i < 32; i++) 2154 if (ah->ah_syncstate & (i << i)) 2155 sc->sc_intr_stats.sync_intr[i]++; 2156 } 2157 2158 status &= sc->sc_imask; /* discard unasked for bits */ 2159 2160 /* Short-circuit un-handled interrupts */ 2161 if (status == 0x0) { 2162 ATH_PCU_UNLOCK(sc); 2163 2164 ATH_LOCK(sc); 2165 ath_power_restore_power_state(sc); 2166 ATH_UNLOCK(sc); 2167 2168 return; 2169 } 2170 2171 /* 2172 * Take a note that we're inside the interrupt handler, so 2173 * the reset routines know to wait. 2174 */ 2175 sc->sc_intr_cnt++; 2176 ATH_PCU_UNLOCK(sc); 2177 2178 /* 2179 * Handle the interrupt. We won't run concurrent with the reset 2180 * or channel change routines as they'll wait for sc_intr_cnt 2181 * to be 0 before continuing. 2182 */ 2183 if (status & HAL_INT_FATAL) { 2184 sc->sc_stats.ast_hardware++; 2185 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 2186 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask); 2187 } else { 2188 if (status & HAL_INT_SWBA) { 2189 /* 2190 * Software beacon alert--time to send a beacon. 2191 * Handle beacon transmission directly; deferring 2192 * this is too slow to meet timing constraints 2193 * under load. 2194 */ 2195 #ifdef IEEE80211_SUPPORT_TDMA 2196 if (sc->sc_tdma) { 2197 if (sc->sc_tdmaswba == 0) { 2198 struct ieee80211com *ic = &sc->sc_ic; 2199 struct ieee80211vap *vap = 2200 TAILQ_FIRST(&ic->ic_vaps); 2201 ath_tdma_beacon_send(sc, vap); 2202 sc->sc_tdmaswba = 2203 vap->iv_tdma->tdma_bintval; 2204 } else 2205 sc->sc_tdmaswba--; 2206 } else 2207 #endif 2208 { 2209 ath_beacon_proc(sc, 0); 2210 #ifdef IEEE80211_SUPPORT_SUPERG 2211 /* 2212 * Schedule the rx taskq in case there's no 2213 * traffic so any frames held on the staging 2214 * queue are aged and potentially flushed. 2215 */ 2216 sc->sc_rx.recv_sched(sc, 1); 2217 #endif 2218 } 2219 } 2220 if (status & HAL_INT_RXEOL) { 2221 int imask; 2222 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL"); 2223 if (! sc->sc_isedma) { 2224 ATH_PCU_LOCK(sc); 2225 /* 2226 * NB: the hardware should re-read the link when 2227 * RXE bit is written, but it doesn't work at 2228 * least on older hardware revs. 2229 */ 2230 sc->sc_stats.ast_rxeol++; 2231 /* 2232 * Disable RXEOL/RXORN - prevent an interrupt 2233 * storm until the PCU logic can be reset. 2234 * In case the interface is reset some other 2235 * way before "sc_kickpcu" is called, don't 2236 * modify sc_imask - that way if it is reset 2237 * by a call to ath_reset() somehow, the 2238 * interrupt mask will be correctly reprogrammed. 2239 */ 2240 imask = sc->sc_imask; 2241 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN); 2242 ath_hal_intrset(ah, imask); 2243 /* 2244 * Only blank sc_rxlink if we've not yet kicked 2245 * the PCU. 2246 * 2247 * This isn't entirely correct - the correct solution 2248 * would be to have a PCU lock and engage that for 2249 * the duration of the PCU fiddling; which would include 2250 * running the RX process. Otherwise we could end up 2251 * messing up the RX descriptor chain and making the 2252 * RX desc list much shorter. 2253 */ 2254 if (! sc->sc_kickpcu) 2255 sc->sc_rxlink = NULL; 2256 sc->sc_kickpcu = 1; 2257 ATH_PCU_UNLOCK(sc); 2258 } 2259 /* 2260 * Enqueue an RX proc to handle whatever 2261 * is in the RX queue. 2262 * This will then kick the PCU if required. 2263 */ 2264 sc->sc_rx.recv_sched(sc, 1); 2265 } 2266 if (status & HAL_INT_TXURN) { 2267 sc->sc_stats.ast_txurn++; 2268 /* bump tx trigger level */ 2269 ath_hal_updatetxtriglevel(ah, AH_TRUE); 2270 } 2271 /* 2272 * Handle both the legacy and RX EDMA interrupt bits. 2273 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC. 2274 */ 2275 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) { 2276 sc->sc_stats.ast_rx_intr++; 2277 sc->sc_rx.recv_sched(sc, 1); 2278 } 2279 if (status & HAL_INT_TX) { 2280 sc->sc_stats.ast_tx_intr++; 2281 /* 2282 * Grab all the currently set bits in the HAL txq bitmap 2283 * and blank them. This is the only place we should be 2284 * doing this. 2285 */ 2286 if (! sc->sc_isedma) { 2287 ATH_PCU_LOCK(sc); 2288 txqs = 0xffffffff; 2289 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs); 2290 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3, 2291 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x", 2292 txqs, 2293 sc->sc_txq_active, 2294 sc->sc_txq_active | txqs); 2295 sc->sc_txq_active |= txqs; 2296 ATH_PCU_UNLOCK(sc); 2297 } 2298 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 2299 } 2300 if (status & HAL_INT_BMISS) { 2301 sc->sc_stats.ast_bmiss++; 2302 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 2303 } 2304 if (status & HAL_INT_GTT) 2305 sc->sc_stats.ast_tx_timeout++; 2306 if (status & HAL_INT_CST) 2307 sc->sc_stats.ast_tx_cst++; 2308 if (status & HAL_INT_MIB) { 2309 sc->sc_stats.ast_mib++; 2310 ATH_PCU_LOCK(sc); 2311 /* 2312 * Disable interrupts until we service the MIB 2313 * interrupt; otherwise it will continue to fire. 2314 */ 2315 ath_hal_intrset(ah, 0); 2316 /* 2317 * Let the hal handle the event. We assume it will 2318 * clear whatever condition caused the interrupt. 2319 */ 2320 ath_hal_mibevent(ah, &sc->sc_halstats); 2321 /* 2322 * Don't reset the interrupt if we've just 2323 * kicked the PCU, or we may get a nested 2324 * RXEOL before the rxproc has had a chance 2325 * to run. 2326 */ 2327 if (sc->sc_kickpcu == 0) 2328 ath_hal_intrset(ah, sc->sc_imask); 2329 ATH_PCU_UNLOCK(sc); 2330 } 2331 if (status & HAL_INT_RXORN) { 2332 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 2333 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN"); 2334 sc->sc_stats.ast_rxorn++; 2335 } 2336 if (status & HAL_INT_TSFOOR) { 2337 /* out of range beacon - wake the chip up, 2338 * but don't modify self-gen frame config */ 2339 device_printf(sc->sc_dev, "%s: TSFOOR\n", __func__); 2340 sc->sc_syncbeacon = 1; 2341 ATH_LOCK(sc); 2342 ath_power_setpower(sc, HAL_PM_AWAKE, 0); 2343 ATH_UNLOCK(sc); 2344 } 2345 if (status & HAL_INT_MCI) { 2346 ath_btcoex_mci_intr(sc); 2347 } 2348 } 2349 ATH_PCU_LOCK(sc); 2350 sc->sc_intr_cnt--; 2351 ATH_PCU_UNLOCK(sc); 2352 2353 ATH_LOCK(sc); 2354 ath_power_restore_power_state(sc); 2355 ATH_UNLOCK(sc); 2356 } 2357 2358 static void 2359 ath_fatal_proc(void *arg, int pending) 2360 { 2361 struct ath_softc *sc = arg; 2362 u_int32_t *state; 2363 u_int32_t len; 2364 void *sp; 2365 2366 if (sc->sc_invalid) 2367 return; 2368 2369 device_printf(sc->sc_dev, "hardware error; resetting\n"); 2370 /* 2371 * Fatal errors are unrecoverable. Typically these 2372 * are caused by DMA errors. Collect h/w state from 2373 * the hal so we can diagnose what's going on. 2374 */ 2375 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 2376 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 2377 state = sp; 2378 device_printf(sc->sc_dev, 2379 "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", state[0], 2380 state[1] , state[2], state[3], state[4], state[5]); 2381 } 2382 ath_reset(sc, ATH_RESET_NOLOSS); 2383 } 2384 2385 static void 2386 ath_bmiss_vap(struct ieee80211vap *vap) 2387 { 2388 struct ath_softc *sc = vap->iv_ic->ic_softc; 2389 2390 /* 2391 * Workaround phantom bmiss interrupts by sanity-checking 2392 * the time of our last rx'd frame. If it is within the 2393 * beacon miss interval then ignore the interrupt. If it's 2394 * truly a bmiss we'll get another interrupt soon and that'll 2395 * be dispatched up for processing. Note this applies only 2396 * for h/w beacon miss events. 2397 */ 2398 2399 /* 2400 * XXX TODO: Just read the TSF during the interrupt path; 2401 * that way we don't have to wake up again just to read it 2402 * again. 2403 */ 2404 ATH_LOCK(sc); 2405 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2406 ATH_UNLOCK(sc); 2407 2408 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 2409 u_int64_t lastrx = sc->sc_lastrx; 2410 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 2411 /* XXX should take a locked ref to iv_bss */ 2412 u_int bmisstimeout = 2413 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 2414 2415 DPRINTF(sc, ATH_DEBUG_BEACON, 2416 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 2417 __func__, (unsigned long long) tsf, 2418 (unsigned long long)(tsf - lastrx), 2419 (unsigned long long) lastrx, bmisstimeout); 2420 2421 if (tsf - lastrx <= bmisstimeout) { 2422 sc->sc_stats.ast_bmiss_phantom++; 2423 2424 ATH_LOCK(sc); 2425 ath_power_restore_power_state(sc); 2426 ATH_UNLOCK(sc); 2427 2428 return; 2429 } 2430 } 2431 2432 /* 2433 * Keep the hardware awake if it's asleep (and leave self-gen 2434 * frame config alone) until the next beacon, so we can resync 2435 * against the next beacon. 2436 * 2437 * This handles three common beacon miss cases in STA powersave mode - 2438 * (a) the beacon TBTT isnt a multiple of bintval; 2439 * (b) the beacon was missed; and 2440 * (c) the beacons are being delayed because the AP is busy and 2441 * isn't reliably able to meet its TBTT. 2442 */ 2443 ATH_LOCK(sc); 2444 ath_power_setpower(sc, HAL_PM_AWAKE, 0); 2445 ath_power_restore_power_state(sc); 2446 ATH_UNLOCK(sc); 2447 DPRINTF(sc, ATH_DEBUG_BEACON, 2448 "%s: forced awake; force syncbeacon=1\n", __func__); 2449 2450 /* 2451 * Attempt to force a beacon resync. 2452 */ 2453 sc->sc_syncbeacon = 1; 2454 2455 ATH_VAP(vap)->av_bmiss(vap); 2456 } 2457 2458 /* XXX this needs a force wakeup! */ 2459 int 2460 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 2461 { 2462 uint32_t rsize; 2463 void *sp; 2464 2465 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize)) 2466 return 0; 2467 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 2468 *hangs = *(uint32_t *)sp; 2469 return 1; 2470 } 2471 2472 static void 2473 ath_bmiss_proc(void *arg, int pending) 2474 { 2475 struct ath_softc *sc = arg; 2476 uint32_t hangs; 2477 2478 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 2479 2480 ATH_LOCK(sc); 2481 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2482 ATH_UNLOCK(sc); 2483 2484 ath_beacon_miss(sc); 2485 2486 /* 2487 * Do a reset upon any becaon miss event. 2488 * 2489 * It may be a non-recognised RX clear hang which needs a reset 2490 * to clear. 2491 */ 2492 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 2493 ath_reset(sc, ATH_RESET_NOLOSS); 2494 device_printf(sc->sc_dev, 2495 "bb hang detected (0x%x), resetting\n", hangs); 2496 } else { 2497 ath_reset(sc, ATH_RESET_NOLOSS); 2498 ieee80211_beacon_miss(&sc->sc_ic); 2499 } 2500 2501 /* Force a beacon resync, in case they've drifted */ 2502 sc->sc_syncbeacon = 1; 2503 2504 ATH_LOCK(sc); 2505 ath_power_restore_power_state(sc); 2506 ATH_UNLOCK(sc); 2507 } 2508 2509 /* 2510 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 2511 * calcs together with WME. If necessary disable the crypto 2512 * hardware and mark the 802.11 state so keys will be setup 2513 * with the MIC work done in software. 2514 */ 2515 static void 2516 ath_settkipmic(struct ath_softc *sc) 2517 { 2518 struct ieee80211com *ic = &sc->sc_ic; 2519 2520 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 2521 if (ic->ic_flags & IEEE80211_F_WME) { 2522 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 2523 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 2524 } else { 2525 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 2526 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 2527 } 2528 } 2529 } 2530 2531 static void 2532 ath_vap_clear_quiet_ie(struct ath_softc *sc) 2533 { 2534 struct ieee80211com *ic = &sc->sc_ic; 2535 struct ieee80211vap *vap; 2536 struct ath_vap *avp; 2537 2538 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 2539 avp = ATH_VAP(vap); 2540 /* Quiet time handling - ensure we resync */ 2541 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 2542 } 2543 } 2544 2545 static int 2546 ath_init(struct ath_softc *sc) 2547 { 2548 struct ieee80211com *ic = &sc->sc_ic; 2549 struct ath_hal *ah = sc->sc_ah; 2550 HAL_STATUS status; 2551 2552 ATH_LOCK_ASSERT(sc); 2553 2554 /* 2555 * Force the sleep state awake. 2556 */ 2557 ath_power_setselfgen(sc, HAL_PM_AWAKE); 2558 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2559 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 2560 2561 /* 2562 * Stop anything previously setup. This is safe 2563 * whether this is the first time through or not. 2564 */ 2565 ath_stop(sc); 2566 2567 /* 2568 * The basic interface to setting the hardware in a good 2569 * state is ``reset''. On return the hardware is known to 2570 * be powered up and with interrupts disabled. This must 2571 * be followed by initialization of the appropriate bits 2572 * and then setup of the interrupt mask. 2573 */ 2574 ath_settkipmic(sc); 2575 ath_update_chainmasks(sc, ic->ic_curchan); 2576 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2577 sc->sc_cur_rxchainmask); 2578 2579 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, 2580 HAL_RESET_NORMAL, &status)) { 2581 device_printf(sc->sc_dev, 2582 "unable to reset hardware; hal status %u\n", status); 2583 return (ENODEV); 2584 } 2585 2586 ATH_RX_LOCK(sc); 2587 sc->sc_rx_stopped = 1; 2588 sc->sc_rx_resetted = 1; 2589 ATH_RX_UNLOCK(sc); 2590 2591 /* Clear quiet IE state for each VAP */ 2592 ath_vap_clear_quiet_ie(sc); 2593 2594 ath_chan_change(sc, ic->ic_curchan); 2595 2596 /* Let DFS at it in case it's a DFS channel */ 2597 ath_dfs_radar_enable(sc, ic->ic_curchan); 2598 2599 /* Let spectral at in case spectral is enabled */ 2600 ath_spectral_enable(sc, ic->ic_curchan); 2601 2602 /* 2603 * Let bluetooth coexistence at in case it's needed for this channel 2604 */ 2605 ath_btcoex_enable(sc, ic->ic_curchan); 2606 2607 /* 2608 * If we're doing TDMA, enforce the TXOP limitation for chips that 2609 * support it. 2610 */ 2611 if (sc->sc_hasenforcetxop && sc->sc_tdma) 2612 ath_hal_setenforcetxop(sc->sc_ah, 1); 2613 else 2614 ath_hal_setenforcetxop(sc->sc_ah, 0); 2615 2616 /* 2617 * Likewise this is set during reset so update 2618 * state cached in the driver. 2619 */ 2620 sc->sc_diversity = ath_hal_getdiversity(ah); 2621 sc->sc_lastlongcal = ticks; 2622 sc->sc_resetcal = 1; 2623 sc->sc_lastcalreset = 0; 2624 sc->sc_lastani = ticks; 2625 sc->sc_lastshortcal = ticks; 2626 sc->sc_doresetcal = AH_FALSE; 2627 /* 2628 * Beacon timers were cleared here; give ath_newstate() 2629 * a hint that the beacon timers should be poked when 2630 * things transition to the RUN state. 2631 */ 2632 sc->sc_beacons = 0; 2633 2634 /* 2635 * Setup the hardware after reset: the key cache 2636 * is filled as needed and the receive engine is 2637 * set going. Frame transmit is handled entirely 2638 * in the frame output path; there's nothing to do 2639 * here except setup the interrupt mask. 2640 */ 2641 if (ath_startrecv(sc) != 0) { 2642 device_printf(sc->sc_dev, "unable to start recv logic\n"); 2643 ath_power_restore_power_state(sc); 2644 return (ENODEV); 2645 } 2646 2647 /* 2648 * Enable interrupts. 2649 */ 2650 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 2651 | HAL_INT_RXORN | HAL_INT_TXURN 2652 | HAL_INT_FATAL | HAL_INT_GLOBAL; 2653 2654 /* 2655 * Enable RX EDMA bits. Note these overlap with 2656 * HAL_INT_RX and HAL_INT_RXDESC respectively. 2657 */ 2658 if (sc->sc_isedma) 2659 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP); 2660 2661 /* 2662 * If we're an EDMA NIC, we don't care about RXEOL. 2663 * Writing a new descriptor in will simply restart 2664 * RX DMA. 2665 */ 2666 if (! sc->sc_isedma) 2667 sc->sc_imask |= HAL_INT_RXEOL; 2668 2669 /* 2670 * Enable MCI interrupt for MCI devices. 2671 */ 2672 if (sc->sc_btcoex_mci) 2673 sc->sc_imask |= HAL_INT_MCI; 2674 2675 /* 2676 * Enable MIB interrupts when there are hardware phy counters. 2677 * Note we only do this (at the moment) for station mode. 2678 */ 2679 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 2680 sc->sc_imask |= HAL_INT_MIB; 2681 2682 /* 2683 * XXX add capability for this. 2684 * 2685 * If we're in STA mode (and maybe IBSS?) then register for 2686 * TSFOOR interrupts. 2687 */ 2688 if (ic->ic_opmode == IEEE80211_M_STA) 2689 sc->sc_imask |= HAL_INT_TSFOOR; 2690 2691 /* Enable global TX timeout and carrier sense timeout if available */ 2692 if (ath_hal_gtxto_supported(ah)) 2693 sc->sc_imask |= HAL_INT_GTT; 2694 2695 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n", 2696 __func__, sc->sc_imask); 2697 2698 sc->sc_running = 1; 2699 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 2700 ath_hal_intrset(ah, sc->sc_imask); 2701 2702 ath_power_restore_power_state(sc); 2703 2704 return (0); 2705 } 2706 2707 static void 2708 ath_stop(struct ath_softc *sc) 2709 { 2710 struct ath_hal *ah = sc->sc_ah; 2711 2712 ATH_LOCK_ASSERT(sc); 2713 2714 /* 2715 * Wake the hardware up before fiddling with it. 2716 */ 2717 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2718 2719 if (sc->sc_running) { 2720 /* 2721 * Shutdown the hardware and driver: 2722 * reset 802.11 state machine 2723 * turn off timers 2724 * disable interrupts 2725 * turn off the radio 2726 * clear transmit machinery 2727 * clear receive machinery 2728 * drain and release tx queues 2729 * reclaim beacon resources 2730 * power down hardware 2731 * 2732 * Note that some of this work is not possible if the 2733 * hardware is gone (invalid). 2734 */ 2735 #ifdef ATH_TX99_DIAG 2736 if (sc->sc_tx99 != NULL) 2737 sc->sc_tx99->stop(sc->sc_tx99); 2738 #endif 2739 callout_stop(&sc->sc_wd_ch); 2740 sc->sc_wd_timer = 0; 2741 sc->sc_running = 0; 2742 if (!sc->sc_invalid) { 2743 if (sc->sc_softled) { 2744 callout_stop(&sc->sc_ledtimer); 2745 ath_hal_gpioset(ah, sc->sc_ledpin, 2746 !sc->sc_ledon); 2747 sc->sc_blinking = 0; 2748 } 2749 ath_hal_intrset(ah, 0); 2750 } 2751 /* XXX we should stop RX regardless of whether it's valid */ 2752 if (!sc->sc_invalid) { 2753 ath_stoprecv(sc, 1); 2754 ath_hal_phydisable(ah); 2755 } else 2756 sc->sc_rxlink = NULL; 2757 ath_draintxq(sc, ATH_RESET_DEFAULT); 2758 ath_beacon_free(sc); /* XXX not needed */ 2759 } 2760 2761 /* And now, restore the current power state */ 2762 ath_power_restore_power_state(sc); 2763 } 2764 2765 /* 2766 * Wait until all pending TX/RX has completed. 2767 * 2768 * This waits until all existing transmit, receive and interrupts 2769 * have completed. It's assumed that the caller has first 2770 * grabbed the reset lock so it doesn't try to do overlapping 2771 * chip resets. 2772 */ 2773 #define MAX_TXRX_ITERATIONS 100 2774 static void 2775 ath_txrx_stop_locked(struct ath_softc *sc) 2776 { 2777 int i = MAX_TXRX_ITERATIONS; 2778 2779 ATH_UNLOCK_ASSERT(sc); 2780 ATH_PCU_LOCK_ASSERT(sc); 2781 2782 /* 2783 * Sleep until all the pending operations have completed. 2784 * 2785 * The caller must ensure that reset has been incremented 2786 * or the pending operations may continue being queued. 2787 */ 2788 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt || 2789 sc->sc_txstart_cnt || sc->sc_intr_cnt) { 2790 if (i <= 0) 2791 break; 2792 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 2793 msecs_to_ticks(10)); 2794 i--; 2795 } 2796 2797 if (i <= 0) 2798 device_printf(sc->sc_dev, 2799 "%s: didn't finish after %d iterations\n", 2800 __func__, MAX_TXRX_ITERATIONS); 2801 } 2802 #undef MAX_TXRX_ITERATIONS 2803 2804 #if 0 2805 static void 2806 ath_txrx_stop(struct ath_softc *sc) 2807 { 2808 ATH_UNLOCK_ASSERT(sc); 2809 ATH_PCU_UNLOCK_ASSERT(sc); 2810 2811 ATH_PCU_LOCK(sc); 2812 ath_txrx_stop_locked(sc); 2813 ATH_PCU_UNLOCK(sc); 2814 } 2815 #endif 2816 2817 static void 2818 ath_txrx_start(struct ath_softc *sc) 2819 { 2820 2821 taskqueue_unblock(sc->sc_tq); 2822 } 2823 2824 /* 2825 * Grab the reset lock, and wait around until no one else 2826 * is trying to do anything with it. 2827 * 2828 * This is totally horrible but we can't hold this lock for 2829 * long enough to do TX/RX or we end up with net80211/ip stack 2830 * LORs and eventual deadlock. 2831 * 2832 * "dowait" signals whether to spin, waiting for the reset 2833 * lock count to reach 0. This should (for now) only be used 2834 * during the reset path, as the rest of the code may not 2835 * be locking-reentrant enough to behave correctly. 2836 * 2837 * Another, cleaner way should be found to serialise all of 2838 * these operations. 2839 */ 2840 #define MAX_RESET_ITERATIONS 25 2841 static int 2842 ath_reset_grablock(struct ath_softc *sc, int dowait) 2843 { 2844 int w = 0; 2845 int i = MAX_RESET_ITERATIONS; 2846 2847 ATH_PCU_LOCK_ASSERT(sc); 2848 do { 2849 if (sc->sc_inreset_cnt == 0) { 2850 w = 1; 2851 break; 2852 } 2853 if (dowait == 0) { 2854 w = 0; 2855 break; 2856 } 2857 ATH_PCU_UNLOCK(sc); 2858 /* 2859 * 1 tick is likely not enough time for long calibrations 2860 * to complete. So we should wait quite a while. 2861 */ 2862 pause("ath_reset_grablock", msecs_to_ticks(100)); 2863 i--; 2864 ATH_PCU_LOCK(sc); 2865 } while (i > 0); 2866 2867 /* 2868 * We always increment the refcounter, regardless 2869 * of whether we succeeded to get it in an exclusive 2870 * way. 2871 */ 2872 sc->sc_inreset_cnt++; 2873 2874 if (i <= 0) 2875 device_printf(sc->sc_dev, 2876 "%s: didn't finish after %d iterations\n", 2877 __func__, MAX_RESET_ITERATIONS); 2878 2879 if (w == 0) 2880 device_printf(sc->sc_dev, 2881 "%s: warning, recursive reset path!\n", 2882 __func__); 2883 2884 return w; 2885 } 2886 #undef MAX_RESET_ITERATIONS 2887 2888 /* 2889 * Reset the hardware w/o losing operational state. This is 2890 * basically a more efficient way of doing ath_stop, ath_init, 2891 * followed by state transitions to the current 802.11 2892 * operational state. Used to recover from various errors and 2893 * to reset or reload hardware state. 2894 */ 2895 int 2896 ath_reset(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 2897 { 2898 struct ieee80211com *ic = &sc->sc_ic; 2899 struct ath_hal *ah = sc->sc_ah; 2900 HAL_STATUS status; 2901 int i; 2902 2903 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 2904 2905 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */ 2906 ATH_PCU_UNLOCK_ASSERT(sc); 2907 ATH_UNLOCK_ASSERT(sc); 2908 2909 /* Try to (stop any further TX/RX from occurring */ 2910 taskqueue_block(sc->sc_tq); 2911 2912 /* 2913 * Wake the hardware up. 2914 */ 2915 ATH_LOCK(sc); 2916 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2917 ATH_UNLOCK(sc); 2918 2919 ATH_PCU_LOCK(sc); 2920 2921 /* 2922 * Grab the reset lock before TX/RX is stopped. 2923 * 2924 * This is needed to ensure that when the TX/RX actually does finish, 2925 * no further TX/RX/reset runs in parallel with this. 2926 */ 2927 if (ath_reset_grablock(sc, 1) == 0) { 2928 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 2929 __func__); 2930 } 2931 2932 /* disable interrupts */ 2933 ath_hal_intrset(ah, 0); 2934 2935 /* 2936 * Now, ensure that any in progress TX/RX completes before we 2937 * continue. 2938 */ 2939 ath_txrx_stop_locked(sc); 2940 2941 ATH_PCU_UNLOCK(sc); 2942 2943 /* 2944 * Regardless of whether we're doing a no-loss flush or 2945 * not, stop the PCU and handle what's in the RX queue. 2946 * That way frames aren't dropped which shouldn't be. 2947 */ 2948 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS)); 2949 ath_rx_flush(sc); 2950 2951 /* 2952 * Should now wait for pending TX/RX to complete 2953 * and block future ones from occurring. This needs to be 2954 * done before the TX queue is drained. 2955 */ 2956 ath_draintxq(sc, reset_type); /* stop xmit side */ 2957 2958 ath_settkipmic(sc); /* configure TKIP MIC handling */ 2959 /* NB: indicate channel change so we do a full reset */ 2960 ath_update_chainmasks(sc, ic->ic_curchan); 2961 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2962 sc->sc_cur_rxchainmask); 2963 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, 2964 HAL_RESET_NORMAL, &status)) 2965 device_printf(sc->sc_dev, 2966 "%s: unable to reset hardware; hal status %u\n", 2967 __func__, status); 2968 sc->sc_diversity = ath_hal_getdiversity(ah); 2969 2970 ATH_RX_LOCK(sc); 2971 sc->sc_rx_stopped = 1; 2972 sc->sc_rx_resetted = 1; 2973 ATH_RX_UNLOCK(sc); 2974 2975 /* Quiet time handling - ensure we resync */ 2976 ath_vap_clear_quiet_ie(sc); 2977 2978 /* Let DFS at it in case it's a DFS channel */ 2979 ath_dfs_radar_enable(sc, ic->ic_curchan); 2980 2981 /* Let spectral at in case spectral is enabled */ 2982 ath_spectral_enable(sc, ic->ic_curchan); 2983 2984 /* 2985 * Let bluetooth coexistence at in case it's needed for this channel 2986 */ 2987 ath_btcoex_enable(sc, ic->ic_curchan); 2988 2989 /* 2990 * If we're doing TDMA, enforce the TXOP limitation for chips that 2991 * support it. 2992 */ 2993 if (sc->sc_hasenforcetxop && sc->sc_tdma) 2994 ath_hal_setenforcetxop(sc->sc_ah, 1); 2995 else 2996 ath_hal_setenforcetxop(sc->sc_ah, 0); 2997 2998 if (ath_startrecv(sc) != 0) /* restart recv */ 2999 device_printf(sc->sc_dev, 3000 "%s: unable to start recv logic\n", __func__); 3001 /* 3002 * We may be doing a reset in response to an ioctl 3003 * that changes the channel so update any state that 3004 * might change as a result. 3005 */ 3006 ath_chan_change(sc, ic->ic_curchan); 3007 if (sc->sc_beacons) { /* restart beacons */ 3008 #ifdef IEEE80211_SUPPORT_TDMA 3009 if (sc->sc_tdma) 3010 ath_tdma_config(sc, NULL); 3011 else 3012 #endif 3013 ath_beacon_config(sc, NULL); 3014 } 3015 3016 /* 3017 * Release the reset lock and re-enable interrupts here. 3018 * If an interrupt was being processed in ath_intr(), 3019 * it would disable interrupts at this point. So we have 3020 * to atomically enable interrupts and decrement the 3021 * reset counter - this way ath_intr() doesn't end up 3022 * disabling interrupts without a corresponding enable 3023 * in the rest or channel change path. 3024 * 3025 * Grab the TX reference in case we need to transmit. 3026 * That way a parallel transmit doesn't. 3027 */ 3028 ATH_PCU_LOCK(sc); 3029 sc->sc_inreset_cnt--; 3030 sc->sc_txstart_cnt++; 3031 /* XXX only do this if sc_inreset_cnt == 0? */ 3032 ath_hal_intrset(ah, sc->sc_imask); 3033 ATH_PCU_UNLOCK(sc); 3034 3035 /* 3036 * TX and RX can be started here. If it were started with 3037 * sc_inreset_cnt > 0, the TX and RX path would abort. 3038 * Thus if this is a nested call through the reset or 3039 * channel change code, TX completion will occur but 3040 * RX completion and ath_start / ath_tx_start will not 3041 * run. 3042 */ 3043 3044 /* Restart TX/RX as needed */ 3045 ath_txrx_start(sc); 3046 3047 /* XXX TODO: we need to hold the tx refcount here! */ 3048 3049 /* Restart TX completion and pending TX */ 3050 if (reset_type == ATH_RESET_NOLOSS) { 3051 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 3052 if (ATH_TXQ_SETUP(sc, i)) { 3053 ATH_TXQ_LOCK(&sc->sc_txq[i]); 3054 ath_txq_restart_dma(sc, &sc->sc_txq[i]); 3055 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 3056 3057 ATH_TX_LOCK(sc); 3058 ath_txq_sched(sc, &sc->sc_txq[i]); 3059 ATH_TX_UNLOCK(sc); 3060 } 3061 } 3062 } 3063 3064 ATH_LOCK(sc); 3065 ath_power_restore_power_state(sc); 3066 ATH_UNLOCK(sc); 3067 3068 ATH_PCU_LOCK(sc); 3069 sc->sc_txstart_cnt--; 3070 ATH_PCU_UNLOCK(sc); 3071 3072 /* Handle any frames in the TX queue */ 3073 /* 3074 * XXX should this be done by the caller, rather than 3075 * ath_reset() ? 3076 */ 3077 ath_tx_kick(sc); /* restart xmit */ 3078 return 0; 3079 } 3080 3081 static int 3082 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 3083 { 3084 struct ieee80211com *ic = vap->iv_ic; 3085 struct ath_softc *sc = ic->ic_softc; 3086 struct ath_hal *ah = sc->sc_ah; 3087 3088 switch (cmd) { 3089 case IEEE80211_IOC_TXPOWER: 3090 /* 3091 * If per-packet TPC is enabled, then we have nothing 3092 * to do; otherwise we need to force the global limit. 3093 * All this can happen directly; no need to reset. 3094 */ 3095 if (!ath_hal_gettpc(ah)) 3096 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 3097 return 0; 3098 } 3099 /* XXX? Full or NOLOSS? */ 3100 return ath_reset(sc, ATH_RESET_FULL); 3101 } 3102 3103 struct ath_buf * 3104 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype) 3105 { 3106 struct ath_buf *bf; 3107 3108 ATH_TXBUF_LOCK_ASSERT(sc); 3109 3110 if (btype == ATH_BUFTYPE_MGMT) 3111 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt); 3112 else 3113 bf = TAILQ_FIRST(&sc->sc_txbuf); 3114 3115 if (bf == NULL) { 3116 sc->sc_stats.ast_tx_getnobuf++; 3117 } else { 3118 if (bf->bf_flags & ATH_BUF_BUSY) { 3119 sc->sc_stats.ast_tx_getbusybuf++; 3120 bf = NULL; 3121 } 3122 } 3123 3124 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) { 3125 if (btype == ATH_BUFTYPE_MGMT) 3126 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list); 3127 else { 3128 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 3129 sc->sc_txbuf_cnt--; 3130 3131 /* 3132 * This shuldn't happen; however just to be 3133 * safe print a warning and fudge the txbuf 3134 * count. 3135 */ 3136 if (sc->sc_txbuf_cnt < 0) { 3137 device_printf(sc->sc_dev, 3138 "%s: sc_txbuf_cnt < 0?\n", 3139 __func__); 3140 sc->sc_txbuf_cnt = 0; 3141 } 3142 } 3143 } else 3144 bf = NULL; 3145 3146 if (bf == NULL) { 3147 /* XXX should check which list, mgmt or otherwise */ 3148 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 3149 TAILQ_FIRST(&sc->sc_txbuf) == NULL ? 3150 "out of xmit buffers" : "xmit buffer busy"); 3151 return NULL; 3152 } 3153 3154 /* XXX TODO: should do this at buffer list initialisation */ 3155 /* XXX (then, ensure the buffer has the right flag set) */ 3156 bf->bf_flags = 0; 3157 if (btype == ATH_BUFTYPE_MGMT) 3158 bf->bf_flags |= ATH_BUF_MGMT; 3159 else 3160 bf->bf_flags &= (~ATH_BUF_MGMT); 3161 3162 /* Valid bf here; clear some basic fields */ 3163 bf->bf_next = NULL; /* XXX just to be sure */ 3164 bf->bf_last = NULL; /* XXX again, just to be sure */ 3165 bf->bf_comp = NULL; /* XXX again, just to be sure */ 3166 bzero(&bf->bf_state, sizeof(bf->bf_state)); 3167 3168 /* 3169 * Track the descriptor ID only if doing EDMA 3170 */ 3171 if (sc->sc_isedma) { 3172 bf->bf_descid = sc->sc_txbuf_descid; 3173 sc->sc_txbuf_descid++; 3174 } 3175 3176 return bf; 3177 } 3178 3179 /* 3180 * When retrying a software frame, buffers marked ATH_BUF_BUSY 3181 * can't be thrown back on the queue as they could still be 3182 * in use by the hardware. 3183 * 3184 * This duplicates the buffer, or returns NULL. 3185 * 3186 * The descriptor is also copied but the link pointers and 3187 * the DMA segments aren't copied; this frame should thus 3188 * be again passed through the descriptor setup/chain routines 3189 * so the link is correct. 3190 * 3191 * The caller must free the buffer using ath_freebuf(). 3192 */ 3193 struct ath_buf * 3194 ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf) 3195 { 3196 struct ath_buf *tbf; 3197 3198 tbf = ath_getbuf(sc, 3199 (bf->bf_flags & ATH_BUF_MGMT) ? 3200 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL); 3201 if (tbf == NULL) 3202 return NULL; /* XXX failure? Why? */ 3203 3204 /* Copy basics */ 3205 tbf->bf_next = NULL; 3206 tbf->bf_nseg = bf->bf_nseg; 3207 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE; 3208 tbf->bf_status = bf->bf_status; 3209 tbf->bf_m = bf->bf_m; 3210 tbf->bf_node = bf->bf_node; 3211 KASSERT((bf->bf_node != NULL), ("%s: bf_node=NULL!", __func__)); 3212 /* will be setup by the chain/setup function */ 3213 tbf->bf_lastds = NULL; 3214 /* for now, last == self */ 3215 tbf->bf_last = tbf; 3216 tbf->bf_comp = bf->bf_comp; 3217 3218 /* NOTE: DMA segments will be setup by the setup/chain functions */ 3219 3220 /* The caller has to re-init the descriptor + links */ 3221 3222 /* 3223 * Free the DMA mapping here, before we NULL the mbuf. 3224 * We must only call bus_dmamap_unload() once per mbuf chain 3225 * or behaviour is undefined. 3226 */ 3227 if (bf->bf_m != NULL) { 3228 /* 3229 * XXX is this POSTWRITE call required? 3230 */ 3231 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3232 BUS_DMASYNC_POSTWRITE); 3233 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3234 } 3235 3236 bf->bf_m = NULL; 3237 bf->bf_node = NULL; 3238 3239 /* Copy state */ 3240 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state)); 3241 3242 return tbf; 3243 } 3244 3245 struct ath_buf * 3246 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype) 3247 { 3248 struct ath_buf *bf; 3249 3250 ATH_TXBUF_LOCK(sc); 3251 bf = _ath_getbuf_locked(sc, btype); 3252 /* 3253 * If a mgmt buffer was requested but we're out of those, 3254 * try requesting a normal one. 3255 */ 3256 if (bf == NULL && btype == ATH_BUFTYPE_MGMT) 3257 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 3258 ATH_TXBUF_UNLOCK(sc); 3259 if (bf == NULL) { 3260 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 3261 sc->sc_stats.ast_tx_qstop++; 3262 } 3263 return bf; 3264 } 3265 3266 /* 3267 * Transmit a single frame. 3268 * 3269 * net80211 will free the node reference if the transmit 3270 * fails, so don't free the node reference here. 3271 */ 3272 static int 3273 ath_transmit(struct ieee80211com *ic, struct mbuf *m) 3274 { 3275 struct ath_softc *sc = ic->ic_softc; 3276 struct ieee80211_node *ni; 3277 struct mbuf *next; 3278 struct ath_buf *bf; 3279 ath_bufhead frags; 3280 int retval = 0; 3281 3282 /* 3283 * Tell the reset path that we're currently transmitting. 3284 */ 3285 ATH_PCU_LOCK(sc); 3286 if (sc->sc_inreset_cnt > 0) { 3287 DPRINTF(sc, ATH_DEBUG_XMIT, 3288 "%s: sc_inreset_cnt > 0; bailing\n", __func__); 3289 ATH_PCU_UNLOCK(sc); 3290 sc->sc_stats.ast_tx_qstop++; 3291 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish"); 3292 return (ENOBUFS); /* XXX should be EINVAL or? */ 3293 } 3294 sc->sc_txstart_cnt++; 3295 ATH_PCU_UNLOCK(sc); 3296 3297 /* Wake the hardware up already */ 3298 ATH_LOCK(sc); 3299 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3300 ATH_UNLOCK(sc); 3301 3302 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: start"); 3303 /* 3304 * Grab the TX lock - it's ok to do this here; we haven't 3305 * yet started transmitting. 3306 */ 3307 ATH_TX_LOCK(sc); 3308 3309 /* 3310 * Node reference, if there's one. 3311 */ 3312 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 3313 3314 /* 3315 * Enforce how deep a node queue can get. 3316 * 3317 * XXX it would be nicer if we kept an mbuf queue per 3318 * node and only whacked them into ath_bufs when we 3319 * are ready to schedule some traffic from them. 3320 * .. that may come later. 3321 * 3322 * XXX we should also track the per-node hardware queue 3323 * depth so it is easy to limit the _SUM_ of the swq and 3324 * hwq frames. Since we only schedule two HWQ frames 3325 * at a time, this should be OK for now. 3326 */ 3327 if ((!(m->m_flags & M_EAPOL)) && 3328 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) { 3329 sc->sc_stats.ast_tx_nodeq_overflow++; 3330 retval = ENOBUFS; 3331 goto finish; 3332 } 3333 3334 /* 3335 * Check how many TX buffers are available. 3336 * 3337 * If this is for non-EAPOL traffic, just leave some 3338 * space free in order for buffer cloning and raw 3339 * frame transmission to occur. 3340 * 3341 * If it's for EAPOL traffic, ignore this for now. 3342 * Management traffic will be sent via the raw transmit 3343 * method which bypasses this check. 3344 * 3345 * This is needed to ensure that EAPOL frames during 3346 * (re) keying have a chance to go out. 3347 * 3348 * See kern/138379 for more information. 3349 */ 3350 if ((!(m->m_flags & M_EAPOL)) && 3351 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) { 3352 sc->sc_stats.ast_tx_nobuf++; 3353 retval = ENOBUFS; 3354 goto finish; 3355 } 3356 3357 /* 3358 * Grab a TX buffer and associated resources. 3359 * 3360 * If it's an EAPOL frame, allocate a MGMT ath_buf. 3361 * That way even with temporary buffer exhaustion due to 3362 * the data path doesn't leave us without the ability 3363 * to transmit management frames. 3364 * 3365 * Otherwise allocate a normal buffer. 3366 */ 3367 if (m->m_flags & M_EAPOL) 3368 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT); 3369 else 3370 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL); 3371 3372 if (bf == NULL) { 3373 /* 3374 * If we failed to allocate a buffer, fail. 3375 * 3376 * We shouldn't fail normally, due to the check 3377 * above. 3378 */ 3379 sc->sc_stats.ast_tx_nobuf++; 3380 retval = ENOBUFS; 3381 goto finish; 3382 } 3383 3384 /* 3385 * At this point we have a buffer; so we need to free it 3386 * if we hit any error conditions. 3387 */ 3388 3389 /* 3390 * Check for fragmentation. If this frame 3391 * has been broken up verify we have enough 3392 * buffers to send all the fragments so all 3393 * go out or none... 3394 */ 3395 TAILQ_INIT(&frags); 3396 if ((m->m_flags & M_FRAG) && 3397 !ath_txfrag_setup(sc, &frags, m, ni)) { 3398 DPRINTF(sc, ATH_DEBUG_XMIT, 3399 "%s: out of txfrag buffers\n", __func__); 3400 sc->sc_stats.ast_tx_nofrag++; 3401 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 3402 /* 3403 * XXXGL: is mbuf valid after ath_txfrag_setup? If yes, 3404 * we shouldn't free it but return back. 3405 */ 3406 ieee80211_free_mbuf(m); 3407 m = NULL; 3408 goto bad; 3409 } 3410 3411 /* 3412 * At this point if we have any TX fragments, then we will 3413 * have bumped the node reference once for each of those. 3414 */ 3415 3416 /* 3417 * XXX Is there anything actually _enforcing_ that the 3418 * fragments are being transmitted in one hit, rather than 3419 * being interleaved with other transmissions on that 3420 * hardware queue? 3421 * 3422 * The ATH TX output lock is the only thing serialising this 3423 * right now. 3424 */ 3425 3426 /* 3427 * Calculate the "next fragment" length field in ath_buf 3428 * in order to let the transmit path know enough about 3429 * what to next write to the hardware. 3430 */ 3431 if (m->m_flags & M_FRAG) { 3432 struct ath_buf *fbf = bf; 3433 struct ath_buf *n_fbf = NULL; 3434 struct mbuf *fm = m->m_nextpkt; 3435 3436 /* 3437 * We need to walk the list of fragments and set 3438 * the next size to the following buffer. 3439 * However, the first buffer isn't in the frag 3440 * list, so we have to do some gymnastics here. 3441 */ 3442 TAILQ_FOREACH(n_fbf, &frags, bf_list) { 3443 fbf->bf_nextfraglen = fm->m_pkthdr.len; 3444 fbf = n_fbf; 3445 fm = fm->m_nextpkt; 3446 } 3447 } 3448 3449 nextfrag: 3450 /* 3451 * Pass the frame to the h/w for transmission. 3452 * Fragmented frames have each frag chained together 3453 * with m_nextpkt. We know there are sufficient ath_buf's 3454 * to send all the frags because of work done by 3455 * ath_txfrag_setup. We leave m_nextpkt set while 3456 * calling ath_tx_start so it can use it to extend the 3457 * the tx duration to cover the subsequent frag and 3458 * so it can reclaim all the mbufs in case of an error; 3459 * ath_tx_start clears m_nextpkt once it commits to 3460 * handing the frame to the hardware. 3461 * 3462 * Note: if this fails, then the mbufs are freed but 3463 * not the node reference. 3464 * 3465 * So, we now have to free the node reference ourselves here 3466 * and return OK up to the stack. 3467 */ 3468 next = m->m_nextpkt; 3469 if (ath_tx_start(sc, ni, bf, m)) { 3470 bad: 3471 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 3472 reclaim: 3473 bf->bf_m = NULL; 3474 bf->bf_node = NULL; 3475 ATH_TXBUF_LOCK(sc); 3476 ath_returnbuf_head(sc, bf); 3477 /* 3478 * Free the rest of the node references and 3479 * buffers for the fragment list. 3480 */ 3481 ath_txfrag_cleanup(sc, &frags, ni); 3482 ATH_TXBUF_UNLOCK(sc); 3483 3484 /* 3485 * XXX: And free the node/return OK; ath_tx_start() may have 3486 * modified the buffer. We currently have no way to 3487 * signify that the mbuf was freed but there was an error. 3488 */ 3489 ieee80211_free_node(ni); 3490 retval = 0; 3491 goto finish; 3492 } 3493 3494 /* 3495 * Check here if the node is in power save state. 3496 */ 3497 ath_tx_update_tim(sc, ni, 1); 3498 3499 if (next != NULL) { 3500 /* 3501 * Beware of state changing between frags. 3502 * XXX check sta power-save state? 3503 */ 3504 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 3505 DPRINTF(sc, ATH_DEBUG_XMIT, 3506 "%s: flush fragmented packet, state %s\n", 3507 __func__, 3508 ieee80211_state_name[ni->ni_vap->iv_state]); 3509 /* XXX dmamap */ 3510 ieee80211_free_mbuf(next); 3511 goto reclaim; 3512 } 3513 m = next; 3514 bf = TAILQ_FIRST(&frags); 3515 KASSERT(bf != NULL, ("no buf for txfrag")); 3516 TAILQ_REMOVE(&frags, bf, bf_list); 3517 goto nextfrag; 3518 } 3519 3520 /* 3521 * Bump watchdog timer. 3522 */ 3523 sc->sc_wd_timer = 5; 3524 3525 finish: 3526 ATH_TX_UNLOCK(sc); 3527 3528 /* 3529 * Finished transmitting! 3530 */ 3531 ATH_PCU_LOCK(sc); 3532 sc->sc_txstart_cnt--; 3533 ATH_PCU_UNLOCK(sc); 3534 3535 /* Sleep the hardware if required */ 3536 ATH_LOCK(sc); 3537 ath_power_restore_power_state(sc); 3538 ATH_UNLOCK(sc); 3539 3540 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: finished"); 3541 3542 return (retval); 3543 } 3544 3545 static int 3546 ath_media_change(struct ifnet *ifp) 3547 { 3548 int error = ieee80211_media_change(ifp); 3549 /* NB: only the fixed rate can change and that doesn't need a reset */ 3550 return (error == ENETRESET ? 0 : error); 3551 } 3552 3553 /* 3554 * Block/unblock tx+rx processing while a key change is done. 3555 * We assume the caller serializes key management operations 3556 * so we only need to worry about synchronization with other 3557 * uses that originate in the driver. 3558 */ 3559 static void 3560 ath_key_update_begin(struct ieee80211vap *vap) 3561 { 3562 struct ath_softc *sc = vap->iv_ic->ic_softc; 3563 3564 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 3565 taskqueue_block(sc->sc_tq); 3566 } 3567 3568 static void 3569 ath_key_update_end(struct ieee80211vap *vap) 3570 { 3571 struct ath_softc *sc = vap->iv_ic->ic_softc; 3572 3573 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 3574 taskqueue_unblock(sc->sc_tq); 3575 } 3576 3577 static void 3578 ath_update_promisc(struct ieee80211com *ic) 3579 { 3580 struct ath_softc *sc = ic->ic_softc; 3581 u_int32_t rfilt; 3582 3583 /* configure rx filter */ 3584 ATH_LOCK(sc); 3585 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3586 rfilt = ath_calcrxfilter(sc); 3587 ath_hal_setrxfilter(sc->sc_ah, rfilt); 3588 ath_power_restore_power_state(sc); 3589 ATH_UNLOCK(sc); 3590 3591 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 3592 } 3593 3594 /* 3595 * Driver-internal mcast update call. 3596 * 3597 * Assumes the hardware is already awake. 3598 */ 3599 static void 3600 ath_update_mcast_hw(struct ath_softc *sc) 3601 { 3602 struct ieee80211com *ic = &sc->sc_ic; 3603 u_int32_t mfilt[2]; 3604 3605 /* calculate and install multicast filter */ 3606 if (ic->ic_allmulti == 0) { 3607 struct ieee80211vap *vap; 3608 struct ifnet *ifp; 3609 struct ifmultiaddr *ifma; 3610 3611 /* 3612 * Merge multicast addresses to form the hardware filter. 3613 */ 3614 mfilt[0] = mfilt[1] = 0; 3615 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 3616 ifp = vap->iv_ifp; 3617 if_maddr_rlock(ifp); 3618 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 3619 caddr_t dl; 3620 uint32_t val; 3621 uint8_t pos; 3622 3623 /* calculate XOR of eight 6bit values */ 3624 dl = LLADDR((struct sockaddr_dl *) 3625 ifma->ifma_addr); 3626 val = le32dec(dl + 0); 3627 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ 3628 val; 3629 val = le32dec(dl + 3); 3630 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ 3631 val; 3632 pos &= 0x3f; 3633 mfilt[pos / 32] |= (1 << (pos % 32)); 3634 } 3635 if_maddr_runlock(ifp); 3636 } 3637 } else 3638 mfilt[0] = mfilt[1] = ~0; 3639 3640 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 3641 3642 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 3643 __func__, mfilt[0], mfilt[1]); 3644 } 3645 3646 /* 3647 * Called from the net80211 layer - force the hardware 3648 * awake before operating. 3649 */ 3650 static void 3651 ath_update_mcast(struct ieee80211com *ic) 3652 { 3653 struct ath_softc *sc = ic->ic_softc; 3654 3655 ATH_LOCK(sc); 3656 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3657 ATH_UNLOCK(sc); 3658 3659 ath_update_mcast_hw(sc); 3660 3661 ATH_LOCK(sc); 3662 ath_power_restore_power_state(sc); 3663 ATH_UNLOCK(sc); 3664 } 3665 3666 void 3667 ath_mode_init(struct ath_softc *sc) 3668 { 3669 struct ieee80211com *ic = &sc->sc_ic; 3670 struct ath_hal *ah = sc->sc_ah; 3671 u_int32_t rfilt; 3672 3673 /* XXX power state? */ 3674 3675 /* configure rx filter */ 3676 rfilt = ath_calcrxfilter(sc); 3677 ath_hal_setrxfilter(ah, rfilt); 3678 3679 /* configure operational mode */ 3680 ath_hal_setopmode(ah); 3681 3682 /* handle any link-level address change */ 3683 ath_hal_setmac(ah, ic->ic_macaddr); 3684 3685 /* calculate and install multicast filter */ 3686 ath_update_mcast_hw(sc); 3687 } 3688 3689 /* 3690 * Set the slot time based on the current setting. 3691 */ 3692 void 3693 ath_setslottime(struct ath_softc *sc) 3694 { 3695 struct ieee80211com *ic = &sc->sc_ic; 3696 struct ath_hal *ah = sc->sc_ah; 3697 u_int usec; 3698 3699 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 3700 usec = 13; 3701 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 3702 usec = 21; 3703 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 3704 /* honor short/long slot time only in 11g */ 3705 /* XXX shouldn't honor on pure g or turbo g channel */ 3706 if (ic->ic_flags & IEEE80211_F_SHSLOT) 3707 usec = HAL_SLOT_TIME_9; 3708 else 3709 usec = HAL_SLOT_TIME_20; 3710 } else 3711 usec = HAL_SLOT_TIME_9; 3712 3713 DPRINTF(sc, ATH_DEBUG_RESET, 3714 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 3715 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 3716 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 3717 3718 /* Wake up the hardware first before updating the slot time */ 3719 ATH_LOCK(sc); 3720 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3721 ath_hal_setslottime(ah, usec); 3722 ath_power_restore_power_state(sc); 3723 sc->sc_updateslot = OK; 3724 ATH_UNLOCK(sc); 3725 } 3726 3727 /* 3728 * Callback from the 802.11 layer to update the 3729 * slot time based on the current setting. 3730 */ 3731 static void 3732 ath_updateslot(struct ieee80211com *ic) 3733 { 3734 struct ath_softc *sc = ic->ic_softc; 3735 3736 /* 3737 * When not coordinating the BSS, change the hardware 3738 * immediately. For other operation we defer the change 3739 * until beacon updates have propagated to the stations. 3740 * 3741 * XXX sc_updateslot isn't changed behind a lock? 3742 */ 3743 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3744 ic->ic_opmode == IEEE80211_M_MBSS) 3745 sc->sc_updateslot = UPDATE; 3746 else 3747 ath_setslottime(sc); 3748 } 3749 3750 /* 3751 * Append the contents of src to dst; both queues 3752 * are assumed to be locked. 3753 */ 3754 void 3755 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 3756 { 3757 3758 ATH_TXQ_LOCK_ASSERT(src); 3759 ATH_TXQ_LOCK_ASSERT(dst); 3760 3761 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list); 3762 dst->axq_link = src->axq_link; 3763 src->axq_link = NULL; 3764 dst->axq_depth += src->axq_depth; 3765 dst->axq_aggr_depth += src->axq_aggr_depth; 3766 src->axq_depth = 0; 3767 src->axq_aggr_depth = 0; 3768 } 3769 3770 /* 3771 * Reset the hardware, with no loss. 3772 * 3773 * This can't be used for a general case reset. 3774 */ 3775 static void 3776 ath_reset_proc(void *arg, int pending) 3777 { 3778 struct ath_softc *sc = arg; 3779 3780 #if 0 3781 device_printf(sc->sc_dev, "%s: resetting\n", __func__); 3782 #endif 3783 ath_reset(sc, ATH_RESET_NOLOSS); 3784 } 3785 3786 /* 3787 * Reset the hardware after detecting beacons have stopped. 3788 */ 3789 static void 3790 ath_bstuck_proc(void *arg, int pending) 3791 { 3792 struct ath_softc *sc = arg; 3793 uint32_t hangs = 0; 3794 3795 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) 3796 device_printf(sc->sc_dev, "bb hang detected (0x%x)\n", hangs); 3797 3798 #ifdef ATH_DEBUG_ALQ 3799 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON)) 3800 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL); 3801 #endif 3802 3803 device_printf(sc->sc_dev, "stuck beacon; resetting (bmiss count %u)\n", 3804 sc->sc_bmisscount); 3805 sc->sc_stats.ast_bstuck++; 3806 /* 3807 * This assumes that there's no simultaneous channel mode change 3808 * occurring. 3809 */ 3810 ath_reset(sc, ATH_RESET_NOLOSS); 3811 } 3812 3813 static int 3814 ath_desc_alloc(struct ath_softc *sc) 3815 { 3816 int error; 3817 3818 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3819 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER); 3820 if (error != 0) { 3821 return error; 3822 } 3823 sc->sc_txbuf_cnt = ath_txbuf; 3824 3825 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt, 3826 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt, 3827 ATH_TXDESC); 3828 if (error != 0) { 3829 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3830 return error; 3831 } 3832 3833 /* 3834 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the 3835 * flag doesn't have to be set in ath_getbuf_locked(). 3836 */ 3837 3838 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3839 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1); 3840 if (error != 0) { 3841 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3842 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3843 &sc->sc_txbuf_mgmt); 3844 return error; 3845 } 3846 return 0; 3847 } 3848 3849 static void 3850 ath_desc_free(struct ath_softc *sc) 3851 { 3852 3853 if (sc->sc_bdma.dd_desc_len != 0) 3854 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3855 if (sc->sc_txdma.dd_desc_len != 0) 3856 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3857 if (sc->sc_txdma_mgmt.dd_desc_len != 0) 3858 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3859 &sc->sc_txbuf_mgmt); 3860 } 3861 3862 static struct ieee80211_node * 3863 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3864 { 3865 struct ieee80211com *ic = vap->iv_ic; 3866 struct ath_softc *sc = ic->ic_softc; 3867 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3868 struct ath_node *an; 3869 3870 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3871 if (an == NULL) { 3872 /* XXX stat+msg */ 3873 return NULL; 3874 } 3875 ath_rate_node_init(sc, an); 3876 3877 /* Setup the mutex - there's no associd yet so set the name to NULL */ 3878 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p", 3879 device_get_nameunit(sc->sc_dev), an); 3880 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF); 3881 3882 /* XXX setup ath_tid */ 3883 ath_tx_tid_init(sc, an); 3884 3885 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an); 3886 return &an->an_node; 3887 } 3888 3889 static void 3890 ath_node_cleanup(struct ieee80211_node *ni) 3891 { 3892 struct ieee80211com *ic = ni->ni_ic; 3893 struct ath_softc *sc = ic->ic_softc; 3894 3895 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, 3896 ni->ni_macaddr, ":", ATH_NODE(ni)); 3897 3898 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */ 3899 ath_tx_node_flush(sc, ATH_NODE(ni)); 3900 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3901 sc->sc_node_cleanup(ni); 3902 } 3903 3904 static void 3905 ath_node_free(struct ieee80211_node *ni) 3906 { 3907 struct ieee80211com *ic = ni->ni_ic; 3908 struct ath_softc *sc = ic->ic_softc; 3909 3910 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, 3911 ni->ni_macaddr, ":", ATH_NODE(ni)); 3912 mtx_destroy(&ATH_NODE(ni)->an_mtx); 3913 sc->sc_node_free(ni); 3914 } 3915 3916 static void 3917 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3918 { 3919 struct ieee80211com *ic = ni->ni_ic; 3920 struct ath_softc *sc = ic->ic_softc; 3921 struct ath_hal *ah = sc->sc_ah; 3922 3923 *rssi = ic->ic_node_getrssi(ni); 3924 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3925 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3926 else 3927 *noise = -95; /* nominally correct */ 3928 } 3929 3930 /* 3931 * Set the default antenna. 3932 */ 3933 void 3934 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3935 { 3936 struct ath_hal *ah = sc->sc_ah; 3937 3938 /* XXX block beacon interrupts */ 3939 ath_hal_setdefantenna(ah, antenna); 3940 if (sc->sc_defant != antenna) 3941 sc->sc_stats.ast_ant_defswitch++; 3942 sc->sc_defant = antenna; 3943 sc->sc_rxotherant = 0; 3944 } 3945 3946 static void 3947 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 3948 { 3949 txq->axq_qnum = qnum; 3950 txq->axq_ac = 0; 3951 txq->axq_depth = 0; 3952 txq->axq_aggr_depth = 0; 3953 txq->axq_intrcnt = 0; 3954 txq->axq_link = NULL; 3955 txq->axq_softc = sc; 3956 TAILQ_INIT(&txq->axq_q); 3957 TAILQ_INIT(&txq->axq_tidq); 3958 TAILQ_INIT(&txq->fifo.axq_q); 3959 ATH_TXQ_LOCK_INIT(sc, txq); 3960 } 3961 3962 /* 3963 * Setup a h/w transmit queue. 3964 */ 3965 static struct ath_txq * 3966 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3967 { 3968 struct ath_hal *ah = sc->sc_ah; 3969 HAL_TXQ_INFO qi; 3970 int qnum; 3971 3972 memset(&qi, 0, sizeof(qi)); 3973 qi.tqi_subtype = subtype; 3974 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3975 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3976 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3977 /* 3978 * Enable interrupts only for EOL and DESC conditions. 3979 * We mark tx descriptors to receive a DESC interrupt 3980 * when a tx queue gets deep; otherwise waiting for the 3981 * EOL to reap descriptors. Note that this is done to 3982 * reduce interrupt load and this only defers reaping 3983 * descriptors, never transmitting frames. Aside from 3984 * reducing interrupts this also permits more concurrency. 3985 * The only potential downside is if the tx queue backs 3986 * up in which case the top half of the kernel may backup 3987 * due to a lack of tx descriptors. 3988 */ 3989 if (sc->sc_isedma) 3990 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | 3991 HAL_TXQ_TXOKINT_ENABLE; 3992 else 3993 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | 3994 HAL_TXQ_TXDESCINT_ENABLE; 3995 3996 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3997 if (qnum == -1) { 3998 /* 3999 * NB: don't print a message, this happens 4000 * normally on parts with too few tx queues 4001 */ 4002 return NULL; 4003 } 4004 if (qnum >= nitems(sc->sc_txq)) { 4005 device_printf(sc->sc_dev, 4006 "hal qnum %u out of range, max %zu!\n", 4007 qnum, nitems(sc->sc_txq)); 4008 ath_hal_releasetxqueue(ah, qnum); 4009 return NULL; 4010 } 4011 if (!ATH_TXQ_SETUP(sc, qnum)) { 4012 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4013 sc->sc_txqsetup |= 1<<qnum; 4014 } 4015 return &sc->sc_txq[qnum]; 4016 } 4017 4018 /* 4019 * Setup a hardware data transmit queue for the specified 4020 * access control. The hal may not support all requested 4021 * queues in which case it will return a reference to a 4022 * previously setup queue. We record the mapping from ac's 4023 * to h/w queues for use by ath_tx_start and also track 4024 * the set of h/w queues being used to optimize work in the 4025 * transmit interrupt handler and related routines. 4026 */ 4027 static int 4028 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4029 { 4030 struct ath_txq *txq; 4031 4032 if (ac >= nitems(sc->sc_ac2q)) { 4033 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4034 ac, nitems(sc->sc_ac2q)); 4035 return 0; 4036 } 4037 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4038 if (txq != NULL) { 4039 txq->axq_ac = ac; 4040 sc->sc_ac2q[ac] = txq; 4041 return 1; 4042 } else 4043 return 0; 4044 } 4045 4046 /* 4047 * Update WME parameters for a transmit queue. 4048 */ 4049 static int 4050 ath_txq_update(struct ath_softc *sc, int ac) 4051 { 4052 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4053 struct ieee80211com *ic = &sc->sc_ic; 4054 struct ath_txq *txq = sc->sc_ac2q[ac]; 4055 struct chanAccParams chp; 4056 struct wmeParams *wmep; 4057 struct ath_hal *ah = sc->sc_ah; 4058 HAL_TXQ_INFO qi; 4059 4060 ieee80211_wme_ic_getparams(ic, &chp); 4061 wmep = &chp.cap_wmeParams[ac]; 4062 4063 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4064 #ifdef IEEE80211_SUPPORT_TDMA 4065 if (sc->sc_tdma) { 4066 /* 4067 * AIFS is zero so there's no pre-transmit wait. The 4068 * burst time defines the slot duration and is configured 4069 * through net80211. The QCU is setup to not do post-xmit 4070 * back off, lockout all lower-priority QCU's, and fire 4071 * off the DMA beacon alert timer which is setup based 4072 * on the slot configuration. 4073 */ 4074 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4075 | HAL_TXQ_TXERRINT_ENABLE 4076 | HAL_TXQ_TXURNINT_ENABLE 4077 | HAL_TXQ_TXEOLINT_ENABLE 4078 | HAL_TXQ_DBA_GATED 4079 | HAL_TXQ_BACKOFF_DISABLE 4080 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4081 ; 4082 qi.tqi_aifs = 0; 4083 /* XXX +dbaprep? */ 4084 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4085 qi.tqi_burstTime = qi.tqi_readyTime; 4086 } else { 4087 #endif 4088 /* 4089 * XXX shouldn't this just use the default flags 4090 * used in the previous queue setup? 4091 */ 4092 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4093 | HAL_TXQ_TXERRINT_ENABLE 4094 | HAL_TXQ_TXDESCINT_ENABLE 4095 | HAL_TXQ_TXURNINT_ENABLE 4096 | HAL_TXQ_TXEOLINT_ENABLE 4097 ; 4098 qi.tqi_aifs = wmep->wmep_aifsn; 4099 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4100 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4101 qi.tqi_readyTime = 0; 4102 qi.tqi_burstTime = IEEE80211_TXOP_TO_US(wmep->wmep_txopLimit); 4103 #ifdef IEEE80211_SUPPORT_TDMA 4104 } 4105 #endif 4106 4107 DPRINTF(sc, ATH_DEBUG_RESET, 4108 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4109 __func__, txq->axq_qnum, qi.tqi_qflags, 4110 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4111 4112 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4113 device_printf(sc->sc_dev, "unable to update hardware queue " 4114 "parameters for %s traffic!\n", ieee80211_wme_acnames[ac]); 4115 return 0; 4116 } else { 4117 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4118 return 1; 4119 } 4120 #undef ATH_EXPONENT_TO_VALUE 4121 } 4122 4123 /* 4124 * Callback from the 802.11 layer to update WME parameters. 4125 */ 4126 int 4127 ath_wme_update(struct ieee80211com *ic) 4128 { 4129 struct ath_softc *sc = ic->ic_softc; 4130 4131 return !ath_txq_update(sc, WME_AC_BE) || 4132 !ath_txq_update(sc, WME_AC_BK) || 4133 !ath_txq_update(sc, WME_AC_VI) || 4134 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4135 } 4136 4137 /* 4138 * Reclaim resources for a setup queue. 4139 */ 4140 static void 4141 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4142 { 4143 4144 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4145 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4146 ATH_TXQ_LOCK_DESTROY(txq); 4147 } 4148 4149 /* 4150 * Reclaim all tx queue resources. 4151 */ 4152 static void 4153 ath_tx_cleanup(struct ath_softc *sc) 4154 { 4155 int i; 4156 4157 ATH_TXBUF_LOCK_DESTROY(sc); 4158 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4159 if (ATH_TXQ_SETUP(sc, i)) 4160 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4161 } 4162 4163 /* 4164 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 4165 * using the current rates in sc_rixmap. 4166 */ 4167 int 4168 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 4169 { 4170 int rix = sc->sc_rixmap[rate]; 4171 /* NB: return lowest rix for invalid rate */ 4172 return (rix == 0xff ? 0 : rix); 4173 } 4174 4175 static void 4176 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts, 4177 struct ath_buf *bf) 4178 { 4179 struct ieee80211_node *ni = bf->bf_node; 4180 struct ieee80211com *ic = &sc->sc_ic; 4181 int sr, lr, pri; 4182 4183 if (ts->ts_status == 0) { 4184 u_int8_t txant = ts->ts_antenna; 4185 sc->sc_stats.ast_ant_tx[txant]++; 4186 sc->sc_ant_tx[txant]++; 4187 if (ts->ts_finaltsi != 0) 4188 sc->sc_stats.ast_tx_altrate++; 4189 4190 /* XXX TODO: should do per-pri conuters */ 4191 pri = M_WME_GETAC(bf->bf_m); 4192 if (pri >= WME_AC_VO) 4193 ic->ic_wme.wme_hipri_traffic++; 4194 4195 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) 4196 ni->ni_inact = ni->ni_inact_reload; 4197 } else { 4198 if (ts->ts_status & HAL_TXERR_XRETRY) 4199 sc->sc_stats.ast_tx_xretries++; 4200 if (ts->ts_status & HAL_TXERR_FIFO) 4201 sc->sc_stats.ast_tx_fifoerr++; 4202 if (ts->ts_status & HAL_TXERR_FILT) 4203 sc->sc_stats.ast_tx_filtered++; 4204 if (ts->ts_status & HAL_TXERR_XTXOP) 4205 sc->sc_stats.ast_tx_xtxop++; 4206 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED) 4207 sc->sc_stats.ast_tx_timerexpired++; 4208 4209 if (bf->bf_m->m_flags & M_FF) 4210 sc->sc_stats.ast_ff_txerr++; 4211 } 4212 /* XXX when is this valid? */ 4213 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR) 4214 sc->sc_stats.ast_tx_desccfgerr++; 4215 /* 4216 * This can be valid for successful frame transmission! 4217 * If there's a TX FIFO underrun during aggregate transmission, 4218 * the MAC will pad the rest of the aggregate with delimiters. 4219 * If a BA is returned, the frame is marked as "OK" and it's up 4220 * to the TX completion code to notice which frames weren't 4221 * successfully transmitted. 4222 */ 4223 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN) 4224 sc->sc_stats.ast_tx_data_underrun++; 4225 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN) 4226 sc->sc_stats.ast_tx_delim_underrun++; 4227 4228 sr = ts->ts_shortretry; 4229 lr = ts->ts_longretry; 4230 sc->sc_stats.ast_tx_shortretry += sr; 4231 sc->sc_stats.ast_tx_longretry += lr; 4232 4233 } 4234 4235 /* 4236 * The default completion. If fail is 1, this means 4237 * "please don't retry the frame, and just return -1 status 4238 * to the net80211 stack. 4239 */ 4240 void 4241 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 4242 { 4243 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 4244 int st; 4245 4246 if (fail == 1) 4247 st = -1; 4248 else 4249 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ? 4250 ts->ts_status : HAL_TXERR_XRETRY; 4251 4252 #if 0 4253 if (bf->bf_state.bfs_dobaw) 4254 device_printf(sc->sc_dev, 4255 "%s: bf %p: seqno %d: dobaw should've been cleared!\n", 4256 __func__, 4257 bf, 4258 SEQNO(bf->bf_state.bfs_seqno)); 4259 #endif 4260 if (bf->bf_next != NULL) 4261 device_printf(sc->sc_dev, 4262 "%s: bf %p: seqno %d: bf_next not NULL!\n", 4263 __func__, 4264 bf, 4265 SEQNO(bf->bf_state.bfs_seqno)); 4266 4267 /* 4268 * Check if the node software queue is empty; if so 4269 * then clear the TIM. 4270 * 4271 * This needs to be done before the buffer is freed as 4272 * otherwise the node reference will have been released 4273 * and the node may not actually exist any longer. 4274 * 4275 * XXX I don't like this belonging here, but it's cleaner 4276 * to do it here right now then all the other places 4277 * where ath_tx_default_comp() is called. 4278 * 4279 * XXX TODO: during drain, ensure that the callback is 4280 * being called so we get a chance to update the TIM. 4281 */ 4282 if (bf->bf_node) { 4283 ATH_TX_LOCK(sc); 4284 ath_tx_update_tim(sc, bf->bf_node, 0); 4285 ATH_TX_UNLOCK(sc); 4286 } 4287 4288 /* 4289 * Do any tx complete callback. Note this must 4290 * be done before releasing the node reference. 4291 * This will free the mbuf, release the net80211 4292 * node and recycle the ath_buf. 4293 */ 4294 ath_tx_freebuf(sc, bf, st); 4295 } 4296 4297 /* 4298 * Update rate control with the given completion status. 4299 */ 4300 void 4301 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 4302 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen, 4303 int nframes, int nbad) 4304 { 4305 struct ath_node *an; 4306 4307 /* Only for unicast frames */ 4308 if (ni == NULL) 4309 return; 4310 4311 an = ATH_NODE(ni); 4312 ATH_NODE_UNLOCK_ASSERT(an); 4313 4314 if ((ts->ts_status & HAL_TXERR_FILT) == 0) { 4315 ATH_NODE_LOCK(an); 4316 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad); 4317 ATH_NODE_UNLOCK(an); 4318 } 4319 } 4320 4321 /* 4322 * Process the completion of the given buffer. 4323 * 4324 * This calls the rate control update and then the buffer completion. 4325 * This will either free the buffer or requeue it. In any case, the 4326 * bf pointer should be treated as invalid after this function is called. 4327 */ 4328 void 4329 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq, 4330 struct ath_tx_status *ts, struct ath_buf *bf) 4331 { 4332 struct ieee80211_node *ni = bf->bf_node; 4333 4334 ATH_TX_UNLOCK_ASSERT(sc); 4335 ATH_TXQ_UNLOCK_ASSERT(txq); 4336 4337 /* If unicast frame, update general statistics */ 4338 if (ni != NULL) { 4339 /* update statistics */ 4340 ath_tx_update_stats(sc, ts, bf); 4341 } 4342 4343 /* 4344 * Call the completion handler. 4345 * The completion handler is responsible for 4346 * calling the rate control code. 4347 * 4348 * Frames with no completion handler get the 4349 * rate control code called here. 4350 */ 4351 if (bf->bf_comp == NULL) { 4352 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4353 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) { 4354 /* 4355 * XXX assume this isn't an aggregate 4356 * frame. 4357 */ 4358 ath_tx_update_ratectrl(sc, ni, 4359 bf->bf_state.bfs_rc, ts, 4360 bf->bf_state.bfs_pktlen, 1, 4361 (ts->ts_status == 0 ? 0 : 1)); 4362 } 4363 ath_tx_default_comp(sc, bf, 0); 4364 } else 4365 bf->bf_comp(sc, bf, 0); 4366 } 4367 4368 4369 4370 /* 4371 * Process completed xmit descriptors from the specified queue. 4372 * Kick the packet scheduler if needed. This can occur from this 4373 * particular task. 4374 */ 4375 static int 4376 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched) 4377 { 4378 struct ath_hal *ah = sc->sc_ah; 4379 struct ath_buf *bf; 4380 struct ath_desc *ds; 4381 struct ath_tx_status *ts; 4382 struct ieee80211_node *ni; 4383 #ifdef IEEE80211_SUPPORT_SUPERG 4384 struct ieee80211com *ic = &sc->sc_ic; 4385 #endif /* IEEE80211_SUPPORT_SUPERG */ 4386 int nacked; 4387 HAL_STATUS status; 4388 4389 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4390 __func__, txq->axq_qnum, 4391 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4392 txq->axq_link); 4393 4394 ATH_KTR(sc, ATH_KTR_TXCOMP, 4, 4395 "ath_tx_processq: txq=%u head %p link %p depth %p", 4396 txq->axq_qnum, 4397 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4398 txq->axq_link, 4399 txq->axq_depth); 4400 4401 nacked = 0; 4402 for (;;) { 4403 ATH_TXQ_LOCK(txq); 4404 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4405 bf = TAILQ_FIRST(&txq->axq_q); 4406 if (bf == NULL) { 4407 ATH_TXQ_UNLOCK(txq); 4408 break; 4409 } 4410 ds = bf->bf_lastds; /* XXX must be setup correctly! */ 4411 ts = &bf->bf_status.ds_txstat; 4412 4413 status = ath_hal_txprocdesc(ah, ds, ts); 4414 #ifdef ATH_DEBUG 4415 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4416 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4417 status == HAL_OK); 4418 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0)) 4419 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4420 status == HAL_OK); 4421 #endif 4422 #ifdef ATH_DEBUG_ALQ 4423 if (if_ath_alq_checkdebug(&sc->sc_alq, 4424 ATH_ALQ_EDMA_TXSTATUS)) { 4425 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS, 4426 sc->sc_tx_statuslen, 4427 (char *) ds); 4428 } 4429 #endif 4430 4431 if (status == HAL_EINPROGRESS) { 4432 ATH_KTR(sc, ATH_KTR_TXCOMP, 3, 4433 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS", 4434 txq->axq_qnum, bf, ds); 4435 ATH_TXQ_UNLOCK(txq); 4436 break; 4437 } 4438 ATH_TXQ_REMOVE(txq, bf, bf_list); 4439 4440 /* 4441 * Sanity check. 4442 */ 4443 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) { 4444 device_printf(sc->sc_dev, 4445 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n", 4446 __func__, 4447 txq->axq_qnum, 4448 bf, 4449 bf->bf_state.bfs_tx_queue); 4450 } 4451 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) { 4452 device_printf(sc->sc_dev, 4453 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n", 4454 __func__, 4455 txq->axq_qnum, 4456 bf->bf_last, 4457 bf->bf_last->bf_state.bfs_tx_queue); 4458 } 4459 4460 #if 0 4461 if (txq->axq_depth > 0) { 4462 /* 4463 * More frames follow. Mark the buffer busy 4464 * so it's not re-used while the hardware may 4465 * still re-read the link field in the descriptor. 4466 * 4467 * Use the last buffer in an aggregate as that 4468 * is where the hardware may be - intermediate 4469 * descriptors won't be "busy". 4470 */ 4471 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 4472 } else 4473 txq->axq_link = NULL; 4474 #else 4475 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 4476 #endif 4477 if (bf->bf_state.bfs_aggr) 4478 txq->axq_aggr_depth--; 4479 4480 ni = bf->bf_node; 4481 4482 ATH_KTR(sc, ATH_KTR_TXCOMP, 5, 4483 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x", 4484 txq->axq_qnum, bf, ds, ni, ts->ts_status); 4485 /* 4486 * If unicast frame was ack'd update RSSI, 4487 * including the last rx time used to 4488 * workaround phantom bmiss interrupts. 4489 */ 4490 if (ni != NULL && ts->ts_status == 0 && 4491 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 4492 nacked++; 4493 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4494 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4495 ts->ts_rssi); 4496 } 4497 ATH_TXQ_UNLOCK(txq); 4498 4499 /* 4500 * Update statistics and call completion 4501 */ 4502 ath_tx_process_buf_completion(sc, txq, ts, bf); 4503 4504 /* XXX at this point, bf and ni may be totally invalid */ 4505 } 4506 #ifdef IEEE80211_SUPPORT_SUPERG 4507 /* 4508 * Flush fast-frame staging queue when traffic slows. 4509 */ 4510 if (txq->axq_depth <= 1) 4511 ieee80211_ff_flush(ic, txq->axq_ac); 4512 #endif 4513 4514 /* Kick the software TXQ scheduler */ 4515 if (dosched) { 4516 ATH_TX_LOCK(sc); 4517 ath_txq_sched(sc, txq); 4518 ATH_TX_UNLOCK(sc); 4519 } 4520 4521 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4522 "ath_tx_processq: txq=%u: done", 4523 txq->axq_qnum); 4524 4525 return nacked; 4526 } 4527 4528 #define TXQACTIVE(t, q) ( (t) & (1 << (q))) 4529 4530 /* 4531 * Deferred processing of transmit interrupt; special-cased 4532 * for a single hardware transmit queue (e.g. 5210 and 5211). 4533 */ 4534 static void 4535 ath_tx_proc_q0(void *arg, int npending) 4536 { 4537 struct ath_softc *sc = arg; 4538 uint32_t txqs; 4539 4540 ATH_PCU_LOCK(sc); 4541 sc->sc_txproc_cnt++; 4542 txqs = sc->sc_txq_active; 4543 sc->sc_txq_active &= ~txqs; 4544 ATH_PCU_UNLOCK(sc); 4545 4546 ATH_LOCK(sc); 4547 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4548 ATH_UNLOCK(sc); 4549 4550 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4551 "ath_tx_proc_q0: txqs=0x%08x", txqs); 4552 4553 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1)) 4554 /* XXX why is lastrx updated in tx code? */ 4555 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4556 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4557 ath_tx_processq(sc, sc->sc_cabq, 1); 4558 sc->sc_wd_timer = 0; 4559 4560 if (sc->sc_softled) 4561 ath_led_event(sc, sc->sc_txrix); 4562 4563 ATH_PCU_LOCK(sc); 4564 sc->sc_txproc_cnt--; 4565 ATH_PCU_UNLOCK(sc); 4566 4567 ATH_LOCK(sc); 4568 ath_power_restore_power_state(sc); 4569 ATH_UNLOCK(sc); 4570 4571 ath_tx_kick(sc); 4572 } 4573 4574 /* 4575 * Deferred processing of transmit interrupt; special-cased 4576 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4577 */ 4578 static void 4579 ath_tx_proc_q0123(void *arg, int npending) 4580 { 4581 struct ath_softc *sc = arg; 4582 int nacked; 4583 uint32_t txqs; 4584 4585 ATH_PCU_LOCK(sc); 4586 sc->sc_txproc_cnt++; 4587 txqs = sc->sc_txq_active; 4588 sc->sc_txq_active &= ~txqs; 4589 ATH_PCU_UNLOCK(sc); 4590 4591 ATH_LOCK(sc); 4592 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4593 ATH_UNLOCK(sc); 4594 4595 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4596 "ath_tx_proc_q0123: txqs=0x%08x", txqs); 4597 4598 /* 4599 * Process each active queue. 4600 */ 4601 nacked = 0; 4602 if (TXQACTIVE(txqs, 0)) 4603 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1); 4604 if (TXQACTIVE(txqs, 1)) 4605 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1); 4606 if (TXQACTIVE(txqs, 2)) 4607 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1); 4608 if (TXQACTIVE(txqs, 3)) 4609 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1); 4610 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4611 ath_tx_processq(sc, sc->sc_cabq, 1); 4612 if (nacked) 4613 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4614 4615 sc->sc_wd_timer = 0; 4616 4617 if (sc->sc_softled) 4618 ath_led_event(sc, sc->sc_txrix); 4619 4620 ATH_PCU_LOCK(sc); 4621 sc->sc_txproc_cnt--; 4622 ATH_PCU_UNLOCK(sc); 4623 4624 ATH_LOCK(sc); 4625 ath_power_restore_power_state(sc); 4626 ATH_UNLOCK(sc); 4627 4628 ath_tx_kick(sc); 4629 } 4630 4631 /* 4632 * Deferred processing of transmit interrupt. 4633 */ 4634 static void 4635 ath_tx_proc(void *arg, int npending) 4636 { 4637 struct ath_softc *sc = arg; 4638 int i, nacked; 4639 uint32_t txqs; 4640 4641 ATH_PCU_LOCK(sc); 4642 sc->sc_txproc_cnt++; 4643 txqs = sc->sc_txq_active; 4644 sc->sc_txq_active &= ~txqs; 4645 ATH_PCU_UNLOCK(sc); 4646 4647 ATH_LOCK(sc); 4648 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4649 ATH_UNLOCK(sc); 4650 4651 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs); 4652 4653 /* 4654 * Process each active queue. 4655 */ 4656 nacked = 0; 4657 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4658 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i)) 4659 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1); 4660 if (nacked) 4661 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4662 4663 sc->sc_wd_timer = 0; 4664 4665 if (sc->sc_softled) 4666 ath_led_event(sc, sc->sc_txrix); 4667 4668 ATH_PCU_LOCK(sc); 4669 sc->sc_txproc_cnt--; 4670 ATH_PCU_UNLOCK(sc); 4671 4672 ATH_LOCK(sc); 4673 ath_power_restore_power_state(sc); 4674 ATH_UNLOCK(sc); 4675 4676 ath_tx_kick(sc); 4677 } 4678 #undef TXQACTIVE 4679 4680 /* 4681 * Deferred processing of TXQ rescheduling. 4682 */ 4683 static void 4684 ath_txq_sched_tasklet(void *arg, int npending) 4685 { 4686 struct ath_softc *sc = arg; 4687 int i; 4688 4689 /* XXX is skipping ok? */ 4690 ATH_PCU_LOCK(sc); 4691 #if 0 4692 if (sc->sc_inreset_cnt > 0) { 4693 device_printf(sc->sc_dev, 4694 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 4695 ATH_PCU_UNLOCK(sc); 4696 return; 4697 } 4698 #endif 4699 sc->sc_txproc_cnt++; 4700 ATH_PCU_UNLOCK(sc); 4701 4702 ATH_LOCK(sc); 4703 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4704 ATH_UNLOCK(sc); 4705 4706 ATH_TX_LOCK(sc); 4707 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 4708 if (ATH_TXQ_SETUP(sc, i)) { 4709 ath_txq_sched(sc, &sc->sc_txq[i]); 4710 } 4711 } 4712 ATH_TX_UNLOCK(sc); 4713 4714 ATH_LOCK(sc); 4715 ath_power_restore_power_state(sc); 4716 ATH_UNLOCK(sc); 4717 4718 ATH_PCU_LOCK(sc); 4719 sc->sc_txproc_cnt--; 4720 ATH_PCU_UNLOCK(sc); 4721 } 4722 4723 void 4724 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf) 4725 { 4726 4727 ATH_TXBUF_LOCK_ASSERT(sc); 4728 4729 if (bf->bf_flags & ATH_BUF_MGMT) 4730 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list); 4731 else { 4732 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4733 sc->sc_txbuf_cnt++; 4734 if (sc->sc_txbuf_cnt > ath_txbuf) { 4735 device_printf(sc->sc_dev, 4736 "%s: sc_txbuf_cnt > %d?\n", 4737 __func__, 4738 ath_txbuf); 4739 sc->sc_txbuf_cnt = ath_txbuf; 4740 } 4741 } 4742 } 4743 4744 void 4745 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf) 4746 { 4747 4748 ATH_TXBUF_LOCK_ASSERT(sc); 4749 4750 if (bf->bf_flags & ATH_BUF_MGMT) 4751 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list); 4752 else { 4753 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 4754 sc->sc_txbuf_cnt++; 4755 if (sc->sc_txbuf_cnt > ATH_TXBUF) { 4756 device_printf(sc->sc_dev, 4757 "%s: sc_txbuf_cnt > %d?\n", 4758 __func__, 4759 ATH_TXBUF); 4760 sc->sc_txbuf_cnt = ATH_TXBUF; 4761 } 4762 } 4763 } 4764 4765 /* 4766 * Free the holding buffer if it exists 4767 */ 4768 void 4769 ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq) 4770 { 4771 ATH_TXBUF_UNLOCK_ASSERT(sc); 4772 ATH_TXQ_LOCK_ASSERT(txq); 4773 4774 if (txq->axq_holdingbf == NULL) 4775 return; 4776 4777 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY; 4778 4779 ATH_TXBUF_LOCK(sc); 4780 ath_returnbuf_tail(sc, txq->axq_holdingbf); 4781 ATH_TXBUF_UNLOCK(sc); 4782 4783 txq->axq_holdingbf = NULL; 4784 } 4785 4786 /* 4787 * Add this buffer to the holding queue, freeing the previous 4788 * one if it exists. 4789 */ 4790 static void 4791 ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf) 4792 { 4793 struct ath_txq *txq; 4794 4795 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue]; 4796 4797 ATH_TXBUF_UNLOCK_ASSERT(sc); 4798 ATH_TXQ_LOCK_ASSERT(txq); 4799 4800 /* XXX assert ATH_BUF_BUSY is set */ 4801 4802 /* XXX assert the tx queue is under the max number */ 4803 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) { 4804 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n", 4805 __func__, 4806 bf, 4807 bf->bf_state.bfs_tx_queue); 4808 bf->bf_flags &= ~ATH_BUF_BUSY; 4809 ath_returnbuf_tail(sc, bf); 4810 return; 4811 } 4812 ath_txq_freeholdingbuf(sc, txq); 4813 txq->axq_holdingbf = bf; 4814 } 4815 4816 /* 4817 * Return a buffer to the pool and update the 'busy' flag on the 4818 * previous 'tail' entry. 4819 * 4820 * This _must_ only be called when the buffer is involved in a completed 4821 * TX. The logic is that if it was part of an active TX, the previous 4822 * buffer on the list is now not involved in a halted TX DMA queue, waiting 4823 * for restart (eg for TDMA.) 4824 * 4825 * The caller must free the mbuf and recycle the node reference. 4826 * 4827 * XXX This method of handling busy / holding buffers is insanely stupid. 4828 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would 4829 * be much nicer if buffers in the processq() methods would instead be 4830 * always completed there (pushed onto a txq or ath_bufhead) so we knew 4831 * exactly what hardware queue they came from in the first place. 4832 */ 4833 void 4834 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf) 4835 { 4836 struct ath_txq *txq; 4837 4838 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue]; 4839 4840 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__)); 4841 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__)); 4842 4843 /* 4844 * If this buffer is busy, push it onto the holding queue. 4845 */ 4846 if (bf->bf_flags & ATH_BUF_BUSY) { 4847 ATH_TXQ_LOCK(txq); 4848 ath_txq_addholdingbuf(sc, bf); 4849 ATH_TXQ_UNLOCK(txq); 4850 return; 4851 } 4852 4853 /* 4854 * Not a busy buffer, so free normally 4855 */ 4856 ATH_TXBUF_LOCK(sc); 4857 ath_returnbuf_tail(sc, bf); 4858 ATH_TXBUF_UNLOCK(sc); 4859 } 4860 4861 /* 4862 * This is currently used by ath_tx_draintxq() and 4863 * ath_tx_tid_free_pkts(). 4864 * 4865 * It recycles a single ath_buf. 4866 */ 4867 void 4868 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status) 4869 { 4870 struct ieee80211_node *ni = bf->bf_node; 4871 struct mbuf *m0 = bf->bf_m; 4872 4873 /* 4874 * Make sure that we only sync/unload if there's an mbuf. 4875 * If not (eg we cloned a buffer), the unload will have already 4876 * occurred. 4877 */ 4878 if (bf->bf_m != NULL) { 4879 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4880 BUS_DMASYNC_POSTWRITE); 4881 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4882 } 4883 4884 bf->bf_node = NULL; 4885 bf->bf_m = NULL; 4886 4887 /* Free the buffer, it's not needed any longer */ 4888 ath_freebuf(sc, bf); 4889 4890 /* Pass the buffer back to net80211 - completing it */ 4891 ieee80211_tx_complete(ni, m0, status); 4892 } 4893 4894 static struct ath_buf * 4895 ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq) 4896 { 4897 struct ath_buf *bf; 4898 4899 ATH_TXQ_LOCK_ASSERT(txq); 4900 4901 /* 4902 * Drain the FIFO queue first, then if it's 4903 * empty, move to the normal frame queue. 4904 */ 4905 bf = TAILQ_FIRST(&txq->fifo.axq_q); 4906 if (bf != NULL) { 4907 /* 4908 * Is it the last buffer in this set? 4909 * Decrement the FIFO counter. 4910 */ 4911 if (bf->bf_flags & ATH_BUF_FIFOEND) { 4912 if (txq->axq_fifo_depth == 0) { 4913 device_printf(sc->sc_dev, 4914 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n", 4915 __func__, 4916 txq->axq_qnum, 4917 txq->fifo.axq_depth); 4918 } else 4919 txq->axq_fifo_depth--; 4920 } 4921 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list); 4922 return (bf); 4923 } 4924 4925 /* 4926 * Debugging! 4927 */ 4928 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) { 4929 device_printf(sc->sc_dev, 4930 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n", 4931 __func__, 4932 txq->axq_qnum, 4933 txq->axq_fifo_depth, 4934 txq->fifo.axq_depth); 4935 } 4936 4937 /* 4938 * Now drain the pending queue. 4939 */ 4940 bf = TAILQ_FIRST(&txq->axq_q); 4941 if (bf == NULL) { 4942 txq->axq_link = NULL; 4943 return (NULL); 4944 } 4945 ATH_TXQ_REMOVE(txq, bf, bf_list); 4946 return (bf); 4947 } 4948 4949 void 4950 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4951 { 4952 #ifdef ATH_DEBUG 4953 struct ath_hal *ah = sc->sc_ah; 4954 #endif 4955 struct ath_buf *bf; 4956 u_int ix; 4957 4958 /* 4959 * NB: this assumes output has been stopped and 4960 * we do not need to block ath_tx_proc 4961 */ 4962 for (ix = 0;; ix++) { 4963 ATH_TXQ_LOCK(txq); 4964 bf = ath_tx_draintxq_get_one(sc, txq); 4965 if (bf == NULL) { 4966 ATH_TXQ_UNLOCK(txq); 4967 break; 4968 } 4969 if (bf->bf_state.bfs_aggr) 4970 txq->axq_aggr_depth--; 4971 #ifdef ATH_DEBUG 4972 if (sc->sc_debug & ATH_DEBUG_RESET) { 4973 struct ieee80211com *ic = &sc->sc_ic; 4974 int status = 0; 4975 4976 /* 4977 * EDMA operation has a TX completion FIFO 4978 * separate from the TX descriptor, so this 4979 * method of checking the "completion" status 4980 * is wrong. 4981 */ 4982 if (! sc->sc_isedma) { 4983 status = (ath_hal_txprocdesc(ah, 4984 bf->bf_lastds, 4985 &bf->bf_status.ds_txstat) == HAL_OK); 4986 } 4987 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status); 4988 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 4989 bf->bf_m->m_len, 0, -1); 4990 } 4991 #endif /* ATH_DEBUG */ 4992 /* 4993 * Since we're now doing magic in the completion 4994 * functions, we -must- call it for aggregation 4995 * destinations or BAW tracking will get upset. 4996 */ 4997 /* 4998 * Clear ATH_BUF_BUSY; the completion handler 4999 * will free the buffer. 5000 */ 5001 ATH_TXQ_UNLOCK(txq); 5002 bf->bf_flags &= ~ATH_BUF_BUSY; 5003 if (bf->bf_comp) 5004 bf->bf_comp(sc, bf, 1); 5005 else 5006 ath_tx_default_comp(sc, bf, 1); 5007 } 5008 5009 /* 5010 * Free the holding buffer if it exists 5011 */ 5012 ATH_TXQ_LOCK(txq); 5013 ath_txq_freeholdingbuf(sc, txq); 5014 ATH_TXQ_UNLOCK(txq); 5015 5016 /* 5017 * Drain software queued frames which are on 5018 * active TIDs. 5019 */ 5020 ath_tx_txq_drain(sc, txq); 5021 } 5022 5023 static void 5024 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5025 { 5026 struct ath_hal *ah = sc->sc_ah; 5027 5028 ATH_TXQ_LOCK_ASSERT(txq); 5029 5030 DPRINTF(sc, ATH_DEBUG_RESET, 5031 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, " 5032 "link %p, holdingbf=%p\n", 5033 __func__, 5034 txq->axq_qnum, 5035 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5036 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)), 5037 (int) ath_hal_numtxpending(ah, txq->axq_qnum), 5038 txq->axq_flags, 5039 txq->axq_link, 5040 txq->axq_holdingbf); 5041 5042 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5043 /* We've stopped TX DMA, so mark this as stopped. */ 5044 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING; 5045 5046 #ifdef ATH_DEBUG 5047 if ((sc->sc_debug & ATH_DEBUG_RESET) 5048 && (txq->axq_holdingbf != NULL)) { 5049 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0); 5050 } 5051 #endif 5052 } 5053 5054 int 5055 ath_stoptxdma(struct ath_softc *sc) 5056 { 5057 struct ath_hal *ah = sc->sc_ah; 5058 int i; 5059 5060 /* XXX return value */ 5061 if (sc->sc_invalid) 5062 return 0; 5063 5064 if (!sc->sc_invalid) { 5065 /* don't touch the hardware if marked invalid */ 5066 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5067 __func__, sc->sc_bhalq, 5068 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5069 NULL); 5070 5071 /* stop the beacon queue */ 5072 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5073 5074 /* Stop the data queues */ 5075 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5076 if (ATH_TXQ_SETUP(sc, i)) { 5077 ATH_TXQ_LOCK(&sc->sc_txq[i]); 5078 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5079 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 5080 } 5081 } 5082 } 5083 5084 return 1; 5085 } 5086 5087 #ifdef ATH_DEBUG 5088 void 5089 ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq) 5090 { 5091 struct ath_hal *ah = sc->sc_ah; 5092 struct ath_buf *bf; 5093 int i = 0; 5094 5095 if (! (sc->sc_debug & ATH_DEBUG_RESET)) 5096 return; 5097 5098 device_printf(sc->sc_dev, "%s: Q%d: begin\n", 5099 __func__, txq->axq_qnum); 5100 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) { 5101 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 5102 ath_hal_txprocdesc(ah, bf->bf_lastds, 5103 &bf->bf_status.ds_txstat) == HAL_OK); 5104 i++; 5105 } 5106 device_printf(sc->sc_dev, "%s: Q%d: end\n", 5107 __func__, txq->axq_qnum); 5108 } 5109 #endif /* ATH_DEBUG */ 5110 5111 /* 5112 * Drain the transmit queues and reclaim resources. 5113 */ 5114 void 5115 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 5116 { 5117 struct ath_hal *ah = sc->sc_ah; 5118 struct ath_buf *bf_last; 5119 int i; 5120 5121 (void) ath_stoptxdma(sc); 5122 5123 /* 5124 * Dump the queue contents 5125 */ 5126 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5127 /* 5128 * XXX TODO: should we just handle the completed TX frames 5129 * here, whether or not the reset is a full one or not? 5130 */ 5131 if (ATH_TXQ_SETUP(sc, i)) { 5132 #ifdef ATH_DEBUG 5133 if (sc->sc_debug & ATH_DEBUG_RESET) 5134 ath_tx_dump(sc, &sc->sc_txq[i]); 5135 #endif /* ATH_DEBUG */ 5136 if (reset_type == ATH_RESET_NOLOSS) { 5137 ath_tx_processq(sc, &sc->sc_txq[i], 0); 5138 ATH_TXQ_LOCK(&sc->sc_txq[i]); 5139 /* 5140 * Free the holding buffer; DMA is now 5141 * stopped. 5142 */ 5143 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]); 5144 /* 5145 * Setup the link pointer to be the 5146 * _last_ buffer/descriptor in the list. 5147 * If there's nothing in the list, set it 5148 * to NULL. 5149 */ 5150 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i], 5151 axq_q_s); 5152 if (bf_last != NULL) { 5153 ath_hal_gettxdesclinkptr(ah, 5154 bf_last->bf_lastds, 5155 &sc->sc_txq[i].axq_link); 5156 } else { 5157 sc->sc_txq[i].axq_link = NULL; 5158 } 5159 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 5160 } else 5161 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5162 } 5163 } 5164 #ifdef ATH_DEBUG 5165 if (sc->sc_debug & ATH_DEBUG_RESET) { 5166 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf); 5167 if (bf != NULL && bf->bf_m != NULL) { 5168 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5169 ath_hal_txprocdesc(ah, bf->bf_lastds, 5170 &bf->bf_status.ds_txstat) == HAL_OK); 5171 ieee80211_dump_pkt(&sc->sc_ic, 5172 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 5173 0, -1); 5174 } 5175 } 5176 #endif /* ATH_DEBUG */ 5177 sc->sc_wd_timer = 0; 5178 } 5179 5180 /* 5181 * Update internal state after a channel change. 5182 */ 5183 static void 5184 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5185 { 5186 enum ieee80211_phymode mode; 5187 5188 /* 5189 * Change channels and update the h/w rate map 5190 * if we're switching; e.g. 11a to 11b/g. 5191 */ 5192 mode = ieee80211_chan2mode(chan); 5193 if (mode != sc->sc_curmode) 5194 ath_setcurmode(sc, mode); 5195 sc->sc_curchan = chan; 5196 } 5197 5198 /* 5199 * Set/change channels. If the channel is really being changed, 5200 * it's done by resetting the chip. To accomplish this we must 5201 * first cleanup any pending DMA, then restart stuff after a la 5202 * ath_init. 5203 */ 5204 static int 5205 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5206 { 5207 struct ieee80211com *ic = &sc->sc_ic; 5208 struct ath_hal *ah = sc->sc_ah; 5209 int ret = 0; 5210 5211 /* Treat this as an interface reset */ 5212 ATH_PCU_UNLOCK_ASSERT(sc); 5213 ATH_UNLOCK_ASSERT(sc); 5214 5215 /* (Try to) stop TX/RX from occurring */ 5216 taskqueue_block(sc->sc_tq); 5217 5218 ATH_PCU_LOCK(sc); 5219 5220 /* Disable interrupts */ 5221 ath_hal_intrset(ah, 0); 5222 5223 /* Stop new RX/TX/interrupt completion */ 5224 if (ath_reset_grablock(sc, 1) == 0) { 5225 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 5226 __func__); 5227 } 5228 5229 /* Stop pending RX/TX completion */ 5230 ath_txrx_stop_locked(sc); 5231 5232 ATH_PCU_UNLOCK(sc); 5233 5234 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 5235 __func__, ieee80211_chan2ieee(ic, chan), 5236 chan->ic_freq, chan->ic_flags); 5237 if (chan != sc->sc_curchan) { 5238 HAL_STATUS status; 5239 /* 5240 * To switch channels clear any pending DMA operations; 5241 * wait long enough for the RX fifo to drain, reset the 5242 * hardware at the new frequency, and then re-enable 5243 * the relevant bits of the h/w. 5244 */ 5245 #if 0 5246 ath_hal_intrset(ah, 0); /* disable interrupts */ 5247 #endif 5248 ath_stoprecv(sc, 1); /* turn off frame recv */ 5249 /* 5250 * First, handle completed TX/RX frames. 5251 */ 5252 ath_rx_flush(sc); 5253 ath_draintxq(sc, ATH_RESET_NOLOSS); 5254 /* 5255 * Next, flush the non-scheduled frames. 5256 */ 5257 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */ 5258 5259 ath_update_chainmasks(sc, chan); 5260 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 5261 sc->sc_cur_rxchainmask); 5262 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, 5263 HAL_RESET_NORMAL, &status)) { 5264 device_printf(sc->sc_dev, "%s: unable to reset " 5265 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 5266 __func__, ieee80211_chan2ieee(ic, chan), 5267 chan->ic_freq, chan->ic_flags, status); 5268 ret = EIO; 5269 goto finish; 5270 } 5271 sc->sc_diversity = ath_hal_getdiversity(ah); 5272 5273 ATH_RX_LOCK(sc); 5274 sc->sc_rx_stopped = 1; 5275 sc->sc_rx_resetted = 1; 5276 ATH_RX_UNLOCK(sc); 5277 5278 /* Quiet time handling - ensure we resync */ 5279 ath_vap_clear_quiet_ie(sc); 5280 5281 /* Let DFS at it in case it's a DFS channel */ 5282 ath_dfs_radar_enable(sc, chan); 5283 5284 /* Let spectral at in case spectral is enabled */ 5285 ath_spectral_enable(sc, chan); 5286 5287 /* 5288 * Let bluetooth coexistence at in case it's needed for this 5289 * channel 5290 */ 5291 ath_btcoex_enable(sc, ic->ic_curchan); 5292 5293 /* 5294 * If we're doing TDMA, enforce the TXOP limitation for chips 5295 * that support it. 5296 */ 5297 if (sc->sc_hasenforcetxop && sc->sc_tdma) 5298 ath_hal_setenforcetxop(sc->sc_ah, 1); 5299 else 5300 ath_hal_setenforcetxop(sc->sc_ah, 0); 5301 5302 /* 5303 * Re-enable rx framework. 5304 */ 5305 if (ath_startrecv(sc) != 0) { 5306 device_printf(sc->sc_dev, 5307 "%s: unable to restart recv logic\n", __func__); 5308 ret = EIO; 5309 goto finish; 5310 } 5311 5312 /* 5313 * Change channels and update the h/w rate map 5314 * if we're switching; e.g. 11a to 11b/g. 5315 */ 5316 ath_chan_change(sc, chan); 5317 5318 /* 5319 * Reset clears the beacon timers; reset them 5320 * here if needed. 5321 */ 5322 if (sc->sc_beacons) { /* restart beacons */ 5323 #ifdef IEEE80211_SUPPORT_TDMA 5324 if (sc->sc_tdma) 5325 ath_tdma_config(sc, NULL); 5326 else 5327 #endif 5328 ath_beacon_config(sc, NULL); 5329 } 5330 5331 /* 5332 * Re-enable interrupts. 5333 */ 5334 #if 0 5335 ath_hal_intrset(ah, sc->sc_imask); 5336 #endif 5337 } 5338 5339 finish: 5340 ATH_PCU_LOCK(sc); 5341 sc->sc_inreset_cnt--; 5342 /* XXX only do this if sc_inreset_cnt == 0? */ 5343 ath_hal_intrset(ah, sc->sc_imask); 5344 ATH_PCU_UNLOCK(sc); 5345 5346 ath_txrx_start(sc); 5347 /* XXX ath_start? */ 5348 5349 return ret; 5350 } 5351 5352 /* 5353 * Periodically recalibrate the PHY to account 5354 * for temperature/environment changes. 5355 */ 5356 static void 5357 ath_calibrate(void *arg) 5358 { 5359 struct ath_softc *sc = arg; 5360 struct ath_hal *ah = sc->sc_ah; 5361 struct ieee80211com *ic = &sc->sc_ic; 5362 HAL_BOOL longCal, isCalDone = AH_TRUE; 5363 HAL_BOOL aniCal, shortCal = AH_FALSE; 5364 int nextcal; 5365 5366 ATH_LOCK_ASSERT(sc); 5367 5368 /* 5369 * Force the hardware awake for ANI work. 5370 */ 5371 ath_power_set_power_state(sc, HAL_PM_AWAKE); 5372 5373 /* Skip trying to do this if we're in reset */ 5374 if (sc->sc_inreset_cnt) 5375 goto restart; 5376 5377 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 5378 goto restart; 5379 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5380 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000); 5381 if (sc->sc_doresetcal) 5382 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000); 5383 5384 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal); 5385 if (aniCal) { 5386 sc->sc_stats.ast_ani_cal++; 5387 sc->sc_lastani = ticks; 5388 ath_hal_ani_poll(ah, sc->sc_curchan); 5389 } 5390 5391 if (longCal) { 5392 sc->sc_stats.ast_per_cal++; 5393 sc->sc_lastlongcal = ticks; 5394 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5395 /* 5396 * Rfgain is out of bounds, reset the chip 5397 * to load new gain values. 5398 */ 5399 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5400 "%s: rfgain change\n", __func__); 5401 sc->sc_stats.ast_per_rfgain++; 5402 sc->sc_resetcal = 0; 5403 sc->sc_doresetcal = AH_TRUE; 5404 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 5405 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 5406 ath_power_restore_power_state(sc); 5407 return; 5408 } 5409 /* 5410 * If this long cal is after an idle period, then 5411 * reset the data collection state so we start fresh. 5412 */ 5413 if (sc->sc_resetcal) { 5414 (void) ath_hal_calreset(ah, sc->sc_curchan); 5415 sc->sc_lastcalreset = ticks; 5416 sc->sc_lastshortcal = ticks; 5417 sc->sc_resetcal = 0; 5418 sc->sc_doresetcal = AH_TRUE; 5419 } 5420 } 5421 5422 /* Only call if we're doing a short/long cal, not for ANI calibration */ 5423 if (shortCal || longCal) { 5424 isCalDone = AH_FALSE; 5425 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 5426 if (longCal) { 5427 /* 5428 * Calibrate noise floor data again in case of change. 5429 */ 5430 ath_hal_process_noisefloor(ah); 5431 } 5432 } else { 5433 DPRINTF(sc, ATH_DEBUG_ANY, 5434 "%s: calibration of channel %u failed\n", 5435 __func__, sc->sc_curchan->ic_freq); 5436 sc->sc_stats.ast_per_calfail++; 5437 } 5438 if (shortCal) 5439 sc->sc_lastshortcal = ticks; 5440 } 5441 if (!isCalDone) { 5442 restart: 5443 /* 5444 * Use a shorter interval to potentially collect multiple 5445 * data samples required to complete calibration. Once 5446 * we're told the work is done we drop back to a longer 5447 * interval between requests. We're more aggressive doing 5448 * work when operating as an AP to improve operation right 5449 * after startup. 5450 */ 5451 sc->sc_lastshortcal = ticks; 5452 nextcal = ath_shortcalinterval*hz/1000; 5453 if (sc->sc_opmode != HAL_M_HOSTAP) 5454 nextcal *= 10; 5455 sc->sc_doresetcal = AH_TRUE; 5456 } else { 5457 /* nextcal should be the shortest time for next event */ 5458 nextcal = ath_longcalinterval*hz; 5459 if (sc->sc_lastcalreset == 0) 5460 sc->sc_lastcalreset = sc->sc_lastlongcal; 5461 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 5462 sc->sc_resetcal = 1; /* setup reset next trip */ 5463 sc->sc_doresetcal = AH_FALSE; 5464 } 5465 /* ANI calibration may occur more often than short/long/resetcal */ 5466 if (ath_anicalinterval > 0) 5467 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000); 5468 5469 if (nextcal != 0) { 5470 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 5471 __func__, nextcal, isCalDone ? "" : "!"); 5472 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 5473 } else { 5474 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 5475 __func__); 5476 /* NB: don't rearm timer */ 5477 } 5478 /* 5479 * Restore power state now that we're done. 5480 */ 5481 ath_power_restore_power_state(sc); 5482 } 5483 5484 static void 5485 ath_scan_start(struct ieee80211com *ic) 5486 { 5487 struct ath_softc *sc = ic->ic_softc; 5488 struct ath_hal *ah = sc->sc_ah; 5489 u_int32_t rfilt; 5490 5491 /* XXX calibration timer? */ 5492 /* XXXGL: is constant ieee80211broadcastaddr a correct choice? */ 5493 5494 ATH_LOCK(sc); 5495 sc->sc_scanning = 1; 5496 sc->sc_syncbeacon = 0; 5497 rfilt = ath_calcrxfilter(sc); 5498 ATH_UNLOCK(sc); 5499 5500 ATH_PCU_LOCK(sc); 5501 ath_hal_setrxfilter(ah, rfilt); 5502 ath_hal_setassocid(ah, ieee80211broadcastaddr, 0); 5503 ATH_PCU_UNLOCK(sc); 5504 5505 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5506 __func__, rfilt, ether_sprintf(ieee80211broadcastaddr)); 5507 } 5508 5509 static void 5510 ath_scan_end(struct ieee80211com *ic) 5511 { 5512 struct ath_softc *sc = ic->ic_softc; 5513 struct ath_hal *ah = sc->sc_ah; 5514 u_int32_t rfilt; 5515 5516 ATH_LOCK(sc); 5517 sc->sc_scanning = 0; 5518 rfilt = ath_calcrxfilter(sc); 5519 ATH_UNLOCK(sc); 5520 5521 ATH_PCU_LOCK(sc); 5522 ath_hal_setrxfilter(ah, rfilt); 5523 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5524 5525 ath_hal_process_noisefloor(ah); 5526 ATH_PCU_UNLOCK(sc); 5527 5528 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5529 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5530 sc->sc_curaid); 5531 } 5532 5533 #ifdef ATH_ENABLE_11N 5534 /* 5535 * For now, just do a channel change. 5536 * 5537 * Later, we'll go through the hard slog of suspending tx/rx, changing rate 5538 * control state and resetting the hardware without dropping frames out 5539 * of the queue. 5540 * 5541 * The unfortunate trouble here is making absolutely sure that the 5542 * channel width change has propagated enough so the hardware 5543 * absolutely isn't handed bogus frames for it's current operating 5544 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and 5545 * does occur in parallel, we need to make certain we've blocked 5546 * any further ongoing TX (and RX, that can cause raw TX) 5547 * before we do this. 5548 */ 5549 static void 5550 ath_update_chw(struct ieee80211com *ic) 5551 { 5552 struct ath_softc *sc = ic->ic_softc; 5553 5554 //DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__); 5555 device_printf(sc->sc_dev, "%s: called\n", __func__); 5556 5557 /* 5558 * XXX TODO: schedule a tasklet that stops things without freeing, 5559 * walks the now stopped TX queue(s) looking for frames to retry 5560 * as if we TX filtered them (whch may mean dropping non-ampdu frames!) 5561 * but okay) then place them back on the software queue so they 5562 * can have the rate control lookup done again. 5563 */ 5564 ath_set_channel(ic); 5565 } 5566 #endif /* ATH_ENABLE_11N */ 5567 5568 /* 5569 * This is called by the beacon parsing routine in the receive 5570 * path to update the current quiet time information provided by 5571 * an AP. 5572 * 5573 * This is STA specific, it doesn't take the AP TBTT/beacon slot 5574 * offset into account. 5575 * 5576 * The quiet IE doesn't control the /now/ beacon interval - it 5577 * controls the upcoming beacon interval. So, when tbtt=1, 5578 * the quiet element programming shall be for the next beacon 5579 * interval. There's no tbtt=0 behaviour defined, so don't. 5580 * 5581 * Since we're programming the next quiet interval, we have 5582 * to keep in mind what we will see when the next beacon 5583 * is received with potentially a quiet IE. For example, if 5584 * quiet_period is 1, then we are always getting a quiet interval 5585 * each TBTT - so if we just program it in upon each beacon received, 5586 * it will constantly reflect the "next" TBTT and we will never 5587 * let the counter stay programmed correctly. 5588 * 5589 * So: 5590 * + the first time we see the quiet IE, program it and store 5591 * the details somewhere; 5592 * + if the quiet parameters don't change (ie, period/duration/offset) 5593 * then just leave the programming enabled; 5594 * + (we can "skip" beacons, so don't try to enforce tbttcount unless 5595 * you're willing to also do the skipped beacon math); 5596 * + if the quiet IE is removed, then halt quiet time. 5597 */ 5598 static int 5599 ath_set_quiet_ie(struct ieee80211_node *ni, uint8_t *ie) 5600 { 5601 struct ieee80211_quiet_ie *q; 5602 struct ieee80211vap *vap = ni->ni_vap; 5603 struct ath_vap *avp = ATH_VAP(vap); 5604 struct ieee80211com *ic = vap->iv_ic; 5605 struct ath_softc *sc = ic->ic_softc; 5606 5607 if (vap->iv_opmode != IEEE80211_M_STA) 5608 return (0); 5609 5610 /* Verify we have a quiet time IE */ 5611 if (ie == NULL) { 5612 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5613 "%s: called; NULL IE, disabling\n", __func__); 5614 5615 ath_hal_set_quiet(sc->sc_ah, 0, 0, 0, HAL_QUIET_DISABLE); 5616 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 5617 return (0); 5618 } 5619 5620 /* If we do, verify it's actually legit */ 5621 if (ie[0] != IEEE80211_ELEMID_QUIET) 5622 return 0; 5623 if (ie[1] != 6) 5624 return 0; 5625 5626 /* Note: this belongs in net80211, parsed out and everything */ 5627 q = (void *) ie; 5628 5629 /* 5630 * Compare what we have stored to what we last saw. 5631 * If they're the same then don't program in anything. 5632 */ 5633 if ((q->period == avp->quiet_ie.period) && 5634 (le16dec(&q->duration) == le16dec(&avp->quiet_ie.duration)) && 5635 (le16dec(&q->offset) == le16dec(&avp->quiet_ie.offset))) 5636 return (0); 5637 5638 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5639 "%s: called; tbttcount=%d, period=%d, duration=%d, offset=%d\n", 5640 __func__, 5641 (int) q->tbttcount, 5642 (int) q->period, 5643 (int) le16dec(&q->duration), 5644 (int) le16dec(&q->offset)); 5645 5646 /* 5647 * Don't program in garbage values. 5648 */ 5649 if ((le16dec(&q->duration) == 0) || 5650 (le16dec(&q->duration) >= ni->ni_intval)) { 5651 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5652 "%s: invalid duration (%d)\n", __func__, 5653 le16dec(&q->duration)); 5654 return (0); 5655 } 5656 /* 5657 * Can have a 0 offset, but not a duration - so just check 5658 * they don't exceed the intval. 5659 */ 5660 if (le16dec(&q->duration) + le16dec(&q->offset) >= ni->ni_intval) { 5661 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5662 "%s: invalid duration + offset (%d+%d)\n", __func__, 5663 le16dec(&q->duration), 5664 le16dec(&q->offset)); 5665 return (0); 5666 } 5667 if (q->tbttcount == 0) { 5668 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5669 "%s: invalid tbttcount (0)\n", __func__); 5670 return (0); 5671 } 5672 if (q->period == 0) { 5673 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5674 "%s: invalid period (0)\n", __func__); 5675 return (0); 5676 } 5677 5678 /* 5679 * This is a new quiet time IE config, so wait until tbttcount 5680 * is equal to 1, and program it in. 5681 */ 5682 if (q->tbttcount == 1) { 5683 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5684 "%s: programming\n", __func__); 5685 ath_hal_set_quiet(sc->sc_ah, 5686 q->period * ni->ni_intval, /* convert to TU */ 5687 le16dec(&q->duration), /* already in TU */ 5688 le16dec(&q->offset) + ni->ni_intval, 5689 HAL_QUIET_ENABLE | HAL_QUIET_ADD_CURRENT_TSF); 5690 /* 5691 * Note: no HAL_QUIET_ADD_SWBA_RESP_TIME; as this is for 5692 * STA mode 5693 */ 5694 5695 /* Update local state */ 5696 memcpy(&avp->quiet_ie, ie, sizeof(struct ieee80211_quiet_ie)); 5697 } 5698 5699 return (0); 5700 } 5701 5702 static void 5703 ath_set_channel(struct ieee80211com *ic) 5704 { 5705 struct ath_softc *sc = ic->ic_softc; 5706 5707 ATH_LOCK(sc); 5708 ath_power_set_power_state(sc, HAL_PM_AWAKE); 5709 ATH_UNLOCK(sc); 5710 5711 (void) ath_chan_set(sc, ic->ic_curchan); 5712 /* 5713 * If we are returning to our bss channel then mark state 5714 * so the next recv'd beacon's tsf will be used to sync the 5715 * beacon timers. Note that since we only hear beacons in 5716 * sta/ibss mode this has no effect in other operating modes. 5717 */ 5718 ATH_LOCK(sc); 5719 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5720 sc->sc_syncbeacon = 1; 5721 ath_power_restore_power_state(sc); 5722 ATH_UNLOCK(sc); 5723 } 5724 5725 /* 5726 * Walk the vap list and check if there any vap's in RUN state. 5727 */ 5728 static int 5729 ath_isanyrunningvaps(struct ieee80211vap *this) 5730 { 5731 struct ieee80211com *ic = this->iv_ic; 5732 struct ieee80211vap *vap; 5733 5734 IEEE80211_LOCK_ASSERT(ic); 5735 5736 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5737 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 5738 return 1; 5739 } 5740 return 0; 5741 } 5742 5743 static int 5744 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5745 { 5746 struct ieee80211com *ic = vap->iv_ic; 5747 struct ath_softc *sc = ic->ic_softc; 5748 struct ath_vap *avp = ATH_VAP(vap); 5749 struct ath_hal *ah = sc->sc_ah; 5750 struct ieee80211_node *ni = NULL; 5751 int i, error, stamode; 5752 u_int32_t rfilt; 5753 int csa_run_transition = 0; 5754 enum ieee80211_state ostate = vap->iv_state; 5755 5756 static const HAL_LED_STATE leds[] = { 5757 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5758 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5759 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5760 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5761 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5762 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5763 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5764 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5765 }; 5766 5767 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5768 ieee80211_state_name[ostate], 5769 ieee80211_state_name[nstate]); 5770 5771 /* 5772 * net80211 _should_ have the comlock asserted at this point. 5773 * There are some comments around the calls to vap->iv_newstate 5774 * which indicate that it (newstate) may end up dropping the 5775 * lock. This and the subsequent lock assert check after newstate 5776 * are an attempt to catch these and figure out how/why. 5777 */ 5778 IEEE80211_LOCK_ASSERT(ic); 5779 5780 /* Before we touch the hardware - wake it up */ 5781 ATH_LOCK(sc); 5782 /* 5783 * If the NIC is in anything other than SLEEP state, 5784 * we need to ensure that self-generated frames are 5785 * set for PWRMGT=0. Otherwise we may end up with 5786 * strange situations. 5787 * 5788 * XXX TODO: is this actually the case? :-) 5789 */ 5790 if (nstate != IEEE80211_S_SLEEP) 5791 ath_power_setselfgen(sc, HAL_PM_AWAKE); 5792 5793 /* 5794 * Now, wake the thing up. 5795 */ 5796 ath_power_set_power_state(sc, HAL_PM_AWAKE); 5797 5798 /* 5799 * And stop the calibration callout whilst we have 5800 * ATH_LOCK held. 5801 */ 5802 callout_stop(&sc->sc_cal_ch); 5803 ATH_UNLOCK(sc); 5804 5805 if (ostate == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN) 5806 csa_run_transition = 1; 5807 5808 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5809 5810 if (nstate == IEEE80211_S_SCAN) { 5811 /* 5812 * Scanning: turn off beacon miss and don't beacon. 5813 * Mark beacon state so when we reach RUN state we'll 5814 * [re]setup beacons. Unblock the task q thread so 5815 * deferred interrupt processing is done. 5816 */ 5817 5818 /* Ensure we stay awake during scan */ 5819 ATH_LOCK(sc); 5820 ath_power_setselfgen(sc, HAL_PM_AWAKE); 5821 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 5822 ATH_UNLOCK(sc); 5823 5824 ath_hal_intrset(ah, 5825 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5826 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5827 sc->sc_beacons = 0; 5828 taskqueue_unblock(sc->sc_tq); 5829 } 5830 5831 ni = ieee80211_ref_node(vap->iv_bss); 5832 rfilt = ath_calcrxfilter(sc); 5833 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5834 vap->iv_opmode == IEEE80211_M_AHDEMO || 5835 vap->iv_opmode == IEEE80211_M_IBSS); 5836 5837 /* 5838 * XXX Dont need to do this (and others) if we've transitioned 5839 * from SLEEP->RUN. 5840 */ 5841 if (stamode && nstate == IEEE80211_S_RUN) { 5842 sc->sc_curaid = ni->ni_associd; 5843 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5844 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5845 } 5846 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5847 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5848 ath_hal_setrxfilter(ah, rfilt); 5849 5850 /* XXX is this to restore keycache on resume? */ 5851 if (vap->iv_opmode != IEEE80211_M_STA && 5852 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5853 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5854 if (ath_hal_keyisvalid(ah, i)) 5855 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5856 } 5857 5858 /* 5859 * Invoke the parent method to do net80211 work. 5860 */ 5861 error = avp->av_newstate(vap, nstate, arg); 5862 if (error != 0) 5863 goto bad; 5864 5865 /* 5866 * See above: ensure av_newstate() doesn't drop the lock 5867 * on us. 5868 */ 5869 IEEE80211_LOCK_ASSERT(ic); 5870 5871 /* 5872 * XXX TODO: if nstate is _S_CAC, then we should disable 5873 * ACK processing until CAC is completed. 5874 */ 5875 5876 /* 5877 * XXX TODO: if we're on a passive channel, then we should 5878 * not allow any ACKs or self-generated frames until we hear 5879 * a beacon. Unfortunately there isn't a notification from 5880 * net80211 so perhaps we could slot that particular check 5881 * into the mgmt receive path and just ensure that we clear 5882 * it on RX of beacons in passive mode (and only clear it 5883 * once, obviously.) 5884 */ 5885 5886 /* 5887 * XXX TODO: net80211 should be tracking whether channels 5888 * have heard beacons and are thus considered "OK" for 5889 * transmitting - and then inform the driver about this 5890 * state change. That way if we hear an AP go quiet 5891 * (and nothing else is beaconing on a channel) the 5892 * channel can go back to being passive until another 5893 * beacon is heard. 5894 */ 5895 5896 /* 5897 * XXX TODO: if nstate is _S_CAC, then we should disable 5898 * ACK processing until CAC is completed. 5899 */ 5900 5901 /* 5902 * XXX TODO: if we're on a passive channel, then we should 5903 * not allow any ACKs or self-generated frames until we hear 5904 * a beacon. Unfortunately there isn't a notification from 5905 * net80211 so perhaps we could slot that particular check 5906 * into the mgmt receive path and just ensure that we clear 5907 * it on RX of beacons in passive mode (and only clear it 5908 * once, obviously.) 5909 */ 5910 5911 /* 5912 * XXX TODO: net80211 should be tracking whether channels 5913 * have heard beacons and are thus considered "OK" for 5914 * transmitting - and then inform the driver about this 5915 * state change. That way if we hear an AP go quiet 5916 * (and nothing else is beaconing on a channel) the 5917 * channel can go back to being passive until another 5918 * beacon is heard. 5919 */ 5920 5921 if (nstate == IEEE80211_S_RUN) { 5922 /* NB: collect bss node again, it may have changed */ 5923 ieee80211_free_node(ni); 5924 ni = ieee80211_ref_node(vap->iv_bss); 5925 5926 DPRINTF(sc, ATH_DEBUG_STATE, 5927 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5928 "capinfo 0x%04x chan %d\n", __func__, 5929 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5930 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5931 5932 switch (vap->iv_opmode) { 5933 #ifdef IEEE80211_SUPPORT_TDMA 5934 case IEEE80211_M_AHDEMO: 5935 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5936 break; 5937 /* fall thru... */ 5938 #endif 5939 case IEEE80211_M_HOSTAP: 5940 case IEEE80211_M_IBSS: 5941 case IEEE80211_M_MBSS: 5942 5943 /* 5944 * TODO: Enable ACK processing (ie, clear AR_DIAG_ACK_DIS.) 5945 * For channels that are in CAC, we may have disabled 5946 * this during CAC to ensure we don't ACK frames 5947 * sent to us. 5948 */ 5949 5950 /* 5951 * Allocate and setup the beacon frame. 5952 * 5953 * Stop any previous beacon DMA. This may be 5954 * necessary, for example, when an ibss merge 5955 * causes reconfiguration; there will be a state 5956 * transition from RUN->RUN that means we may 5957 * be called with beacon transmission active. 5958 */ 5959 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5960 5961 error = ath_beacon_alloc(sc, ni); 5962 if (error != 0) 5963 goto bad; 5964 /* 5965 * If joining an adhoc network defer beacon timer 5966 * configuration to the next beacon frame so we 5967 * have a current TSF to use. Otherwise we're 5968 * starting an ibss/bss so there's no need to delay; 5969 * if this is the first vap moving to RUN state, then 5970 * beacon state needs to be [re]configured. 5971 */ 5972 if (vap->iv_opmode == IEEE80211_M_IBSS && 5973 ni->ni_tstamp.tsf != 0) { 5974 sc->sc_syncbeacon = 1; 5975 } else if (!sc->sc_beacons) { 5976 #ifdef IEEE80211_SUPPORT_TDMA 5977 if (vap->iv_caps & IEEE80211_C_TDMA) 5978 ath_tdma_config(sc, vap); 5979 else 5980 #endif 5981 ath_beacon_config(sc, vap); 5982 sc->sc_beacons = 1; 5983 } 5984 break; 5985 case IEEE80211_M_STA: 5986 /* 5987 * Defer beacon timer configuration to the next 5988 * beacon frame so we have a current TSF to use 5989 * (any TSF collected when scanning is likely old). 5990 * However if it's due to a CSA -> RUN transition, 5991 * force a beacon update so we pick up a lack of 5992 * beacons from an AP in CAC and thus force a 5993 * scan. 5994 * 5995 * And, there's also corner cases here where 5996 * after a scan, the AP may have disappeared. 5997 * In that case, we may not receive an actual 5998 * beacon to update the beacon timer and thus we 5999 * won't get notified of the missing beacons. 6000 */ 6001 if (ostate != IEEE80211_S_RUN && 6002 ostate != IEEE80211_S_SLEEP) { 6003 DPRINTF(sc, ATH_DEBUG_BEACON, 6004 "%s: STA; syncbeacon=1\n", __func__); 6005 sc->sc_syncbeacon = 1; 6006 6007 /* Quiet time handling - ensure we resync */ 6008 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 6009 6010 if (csa_run_transition) 6011 ath_beacon_config(sc, vap); 6012 6013 /* 6014 * PR: kern/175227 6015 * 6016 * Reconfigure beacons during reset; as otherwise 6017 * we won't get the beacon timers reprogrammed 6018 * after a reset and thus we won't pick up a 6019 * beacon miss interrupt. 6020 * 6021 * Hopefully we'll see a beacon before the BMISS 6022 * timer fires (too often), leading to a STA 6023 * disassociation. 6024 */ 6025 sc->sc_beacons = 1; 6026 } 6027 break; 6028 case IEEE80211_M_MONITOR: 6029 /* 6030 * Monitor mode vaps have only INIT->RUN and RUN->RUN 6031 * transitions so we must re-enable interrupts here to 6032 * handle the case of a single monitor mode vap. 6033 */ 6034 ath_hal_intrset(ah, sc->sc_imask); 6035 break; 6036 case IEEE80211_M_WDS: 6037 break; 6038 default: 6039 break; 6040 } 6041 /* 6042 * Let the hal process statistics collected during a 6043 * scan so it can provide calibrated noise floor data. 6044 */ 6045 ath_hal_process_noisefloor(ah); 6046 /* 6047 * Reset rssi stats; maybe not the best place... 6048 */ 6049 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 6050 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 6051 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 6052 6053 /* 6054 * Force awake for RUN mode. 6055 */ 6056 ATH_LOCK(sc); 6057 ath_power_setselfgen(sc, HAL_PM_AWAKE); 6058 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 6059 6060 /* 6061 * Finally, start any timers and the task q thread 6062 * (in case we didn't go through SCAN state). 6063 */ 6064 if (ath_longcalinterval != 0) { 6065 /* start periodic recalibration timer */ 6066 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 6067 } else { 6068 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 6069 "%s: calibration disabled\n", __func__); 6070 } 6071 ATH_UNLOCK(sc); 6072 6073 taskqueue_unblock(sc->sc_tq); 6074 } else if (nstate == IEEE80211_S_INIT) { 6075 6076 /* Quiet time handling - ensure we resync */ 6077 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 6078 6079 /* 6080 * If there are no vaps left in RUN state then 6081 * shutdown host/driver operation: 6082 * o disable interrupts 6083 * o disable the task queue thread 6084 * o mark beacon processing as stopped 6085 */ 6086 if (!ath_isanyrunningvaps(vap)) { 6087 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 6088 /* disable interrupts */ 6089 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 6090 taskqueue_block(sc->sc_tq); 6091 sc->sc_beacons = 0; 6092 } 6093 #ifdef IEEE80211_SUPPORT_TDMA 6094 ath_hal_setcca(ah, AH_TRUE); 6095 #endif 6096 } else if (nstate == IEEE80211_S_SLEEP) { 6097 /* We're going to sleep, so transition appropriately */ 6098 /* For now, only do this if we're a single STA vap */ 6099 if (sc->sc_nvaps == 1 && 6100 vap->iv_opmode == IEEE80211_M_STA) { 6101 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: syncbeacon=%d\n", __func__, sc->sc_syncbeacon); 6102 ATH_LOCK(sc); 6103 /* 6104 * Always at least set the self-generated 6105 * frame config to set PWRMGT=1. 6106 */ 6107 ath_power_setselfgen(sc, HAL_PM_NETWORK_SLEEP); 6108 6109 /* 6110 * If we're not syncing beacons, transition 6111 * to NETWORK_SLEEP. 6112 * 6113 * We stay awake if syncbeacon > 0 in case 6114 * we need to listen for some beacons otherwise 6115 * our beacon timer config may be wrong. 6116 */ 6117 if (sc->sc_syncbeacon == 0) { 6118 ath_power_setpower(sc, HAL_PM_NETWORK_SLEEP, 1); 6119 } 6120 ATH_UNLOCK(sc); 6121 } 6122 } else if (nstate == IEEE80211_S_SCAN) { 6123 /* Quiet time handling - ensure we resync */ 6124 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 6125 } 6126 bad: 6127 ieee80211_free_node(ni); 6128 6129 /* 6130 * Restore the power state - either to what it was, or 6131 * to network_sleep if it's alright. 6132 */ 6133 ATH_LOCK(sc); 6134 ath_power_restore_power_state(sc); 6135 ATH_UNLOCK(sc); 6136 return error; 6137 } 6138 6139 /* 6140 * Allocate a key cache slot to the station so we can 6141 * setup a mapping from key index to node. The key cache 6142 * slot is needed for managing antenna state and for 6143 * compression when stations do not use crypto. We do 6144 * it uniliaterally here; if crypto is employed this slot 6145 * will be reassigned. 6146 */ 6147 static void 6148 ath_setup_stationkey(struct ieee80211_node *ni) 6149 { 6150 struct ieee80211vap *vap = ni->ni_vap; 6151 struct ath_softc *sc = vap->iv_ic->ic_softc; 6152 ieee80211_keyix keyix, rxkeyix; 6153 6154 /* XXX should take a locked ref to vap->iv_bss */ 6155 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 6156 /* 6157 * Key cache is full; we'll fall back to doing 6158 * the more expensive lookup in software. Note 6159 * this also means no h/w compression. 6160 */ 6161 /* XXX msg+statistic */ 6162 } else { 6163 /* XXX locking? */ 6164 ni->ni_ucastkey.wk_keyix = keyix; 6165 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 6166 /* NB: must mark device key to get called back on delete */ 6167 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 6168 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 6169 /* NB: this will create a pass-thru key entry */ 6170 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss); 6171 } 6172 } 6173 6174 /* 6175 * Setup driver-specific state for a newly associated node. 6176 * Note that we're called also on a re-associate, the isnew 6177 * param tells us if this is the first time or not. 6178 */ 6179 static void 6180 ath_newassoc(struct ieee80211_node *ni, int isnew) 6181 { 6182 struct ath_node *an = ATH_NODE(ni); 6183 struct ieee80211vap *vap = ni->ni_vap; 6184 struct ath_softc *sc = vap->iv_ic->ic_softc; 6185 const struct ieee80211_txparam *tp = ni->ni_txparms; 6186 6187 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 6188 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 6189 6190 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: reassoc; isnew=%d, is_powersave=%d\n", 6191 __func__, 6192 ni->ni_macaddr, 6193 ":", 6194 isnew, 6195 an->an_is_powersave); 6196 6197 ATH_NODE_LOCK(an); 6198 ath_rate_newassoc(sc, an, isnew); 6199 ATH_NODE_UNLOCK(an); 6200 6201 if (isnew && 6202 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 6203 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 6204 ath_setup_stationkey(ni); 6205 6206 /* 6207 * If we're reassociating, make sure that any paused queues 6208 * get unpaused. 6209 * 6210 * Now, we may have frames in the hardware queue for this node. 6211 * So if we are reassociating and there are frames in the queue, 6212 * we need to go through the cleanup path to ensure that they're 6213 * marked as non-aggregate. 6214 */ 6215 if (! isnew) { 6216 DPRINTF(sc, ATH_DEBUG_NODE, 6217 "%s: %6D: reassoc; is_powersave=%d\n", 6218 __func__, 6219 ni->ni_macaddr, 6220 ":", 6221 an->an_is_powersave); 6222 6223 /* XXX for now, we can't hold the lock across assoc */ 6224 ath_tx_node_reassoc(sc, an); 6225 6226 /* XXX for now, we can't hold the lock across wakeup */ 6227 if (an->an_is_powersave) 6228 ath_tx_node_wakeup(sc, an); 6229 } 6230 } 6231 6232 static int 6233 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 6234 int nchans, struct ieee80211_channel chans[]) 6235 { 6236 struct ath_softc *sc = ic->ic_softc; 6237 struct ath_hal *ah = sc->sc_ah; 6238 HAL_STATUS status; 6239 6240 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 6241 "%s: rd %u cc %u location %c%s\n", 6242 __func__, reg->regdomain, reg->country, reg->location, 6243 reg->ecm ? " ecm" : ""); 6244 6245 status = ath_hal_set_channels(ah, chans, nchans, 6246 reg->country, reg->regdomain); 6247 if (status != HAL_OK) { 6248 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 6249 __func__, status); 6250 return EINVAL; /* XXX */ 6251 } 6252 6253 return 0; 6254 } 6255 6256 static void 6257 ath_getradiocaps(struct ieee80211com *ic, 6258 int maxchans, int *nchans, struct ieee80211_channel chans[]) 6259 { 6260 struct ath_softc *sc = ic->ic_softc; 6261 struct ath_hal *ah = sc->sc_ah; 6262 6263 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 6264 __func__, SKU_DEBUG, CTRY_DEFAULT); 6265 6266 /* XXX check return */ 6267 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 6268 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 6269 6270 } 6271 6272 static int 6273 ath_getchannels(struct ath_softc *sc) 6274 { 6275 struct ieee80211com *ic = &sc->sc_ic; 6276 struct ath_hal *ah = sc->sc_ah; 6277 HAL_STATUS status; 6278 6279 /* 6280 * Collect channel set based on EEPROM contents. 6281 */ 6282 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 6283 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 6284 if (status != HAL_OK) { 6285 device_printf(sc->sc_dev, 6286 "%s: unable to collect channel list from hal, status %d\n", 6287 __func__, status); 6288 return EINVAL; 6289 } 6290 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 6291 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 6292 /* XXX map Atheros sku's to net80211 SKU's */ 6293 /* XXX net80211 types too small */ 6294 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 6295 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 6296 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 6297 ic->ic_regdomain.isocc[1] = ' '; 6298 6299 ic->ic_regdomain.ecm = 1; 6300 ic->ic_regdomain.location = 'I'; 6301 6302 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 6303 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 6304 __func__, sc->sc_eerd, sc->sc_eecc, 6305 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 6306 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 6307 return 0; 6308 } 6309 6310 static int 6311 ath_rate_setup(struct ath_softc *sc, u_int mode) 6312 { 6313 struct ath_hal *ah = sc->sc_ah; 6314 const HAL_RATE_TABLE *rt; 6315 6316 switch (mode) { 6317 case IEEE80211_MODE_11A: 6318 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 6319 break; 6320 case IEEE80211_MODE_HALF: 6321 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 6322 break; 6323 case IEEE80211_MODE_QUARTER: 6324 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 6325 break; 6326 case IEEE80211_MODE_11B: 6327 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 6328 break; 6329 case IEEE80211_MODE_11G: 6330 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 6331 break; 6332 case IEEE80211_MODE_TURBO_A: 6333 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 6334 break; 6335 case IEEE80211_MODE_TURBO_G: 6336 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 6337 break; 6338 case IEEE80211_MODE_STURBO_A: 6339 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 6340 break; 6341 case IEEE80211_MODE_11NA: 6342 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 6343 break; 6344 case IEEE80211_MODE_11NG: 6345 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 6346 break; 6347 default: 6348 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 6349 __func__, mode); 6350 return 0; 6351 } 6352 sc->sc_rates[mode] = rt; 6353 return (rt != NULL); 6354 } 6355 6356 static void 6357 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 6358 { 6359 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 6360 static const struct { 6361 u_int rate; /* tx/rx 802.11 rate */ 6362 u_int16_t timeOn; /* LED on time (ms) */ 6363 u_int16_t timeOff; /* LED off time (ms) */ 6364 } blinkrates[] = { 6365 { 108, 40, 10 }, 6366 { 96, 44, 11 }, 6367 { 72, 50, 13 }, 6368 { 48, 57, 14 }, 6369 { 36, 67, 16 }, 6370 { 24, 80, 20 }, 6371 { 22, 100, 25 }, 6372 { 18, 133, 34 }, 6373 { 12, 160, 40 }, 6374 { 10, 200, 50 }, 6375 { 6, 240, 58 }, 6376 { 4, 267, 66 }, 6377 { 2, 400, 100 }, 6378 { 0, 500, 130 }, 6379 /* XXX half/quarter rates */ 6380 }; 6381 const HAL_RATE_TABLE *rt; 6382 int i, j; 6383 6384 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 6385 rt = sc->sc_rates[mode]; 6386 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 6387 for (i = 0; i < rt->rateCount; i++) { 6388 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6389 if (rt->info[i].phy != IEEE80211_T_HT) 6390 sc->sc_rixmap[ieeerate] = i; 6391 else 6392 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 6393 } 6394 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6395 for (i = 0; i < nitems(sc->sc_hwmap); i++) { 6396 if (i >= rt->rateCount) { 6397 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6398 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6399 continue; 6400 } 6401 sc->sc_hwmap[i].ieeerate = 6402 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6403 if (rt->info[i].phy == IEEE80211_T_HT) 6404 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 6405 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6406 if (rt->info[i].shortPreamble || 6407 rt->info[i].phy == IEEE80211_T_OFDM) 6408 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6409 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 6410 for (j = 0; j < nitems(blinkrates)-1; j++) 6411 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6412 break; 6413 /* NB: this uses the last entry if the rate isn't found */ 6414 /* XXX beware of overlow */ 6415 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6416 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6417 } 6418 sc->sc_currates = rt; 6419 sc->sc_curmode = mode; 6420 /* 6421 * All protection frames are transmitted at 2Mb/s for 6422 * 11g, otherwise at 1Mb/s. 6423 */ 6424 if (mode == IEEE80211_MODE_11G) 6425 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 6426 else 6427 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 6428 /* NB: caller is responsible for resetting rate control state */ 6429 } 6430 6431 static void 6432 ath_watchdog(void *arg) 6433 { 6434 struct ath_softc *sc = arg; 6435 struct ieee80211com *ic = &sc->sc_ic; 6436 int do_reset = 0; 6437 6438 ATH_LOCK_ASSERT(sc); 6439 6440 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 6441 uint32_t hangs; 6442 6443 ath_power_set_power_state(sc, HAL_PM_AWAKE); 6444 6445 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 6446 hangs != 0) { 6447 device_printf(sc->sc_dev, "%s hang detected (0x%x)\n", 6448 hangs & 0xff ? "bb" : "mac", hangs); 6449 } else 6450 device_printf(sc->sc_dev, "device timeout\n"); 6451 do_reset = 1; 6452 counter_u64_add(ic->ic_oerrors, 1); 6453 sc->sc_stats.ast_watchdog++; 6454 6455 ath_power_restore_power_state(sc); 6456 } 6457 6458 /* 6459 * We can't hold the lock across the ath_reset() call. 6460 * 6461 * And since this routine can't hold a lock and sleep, 6462 * do the reset deferred. 6463 */ 6464 if (do_reset) { 6465 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 6466 } 6467 6468 callout_schedule(&sc->sc_wd_ch, hz); 6469 } 6470 6471 static void 6472 ath_parent(struct ieee80211com *ic) 6473 { 6474 struct ath_softc *sc = ic->ic_softc; 6475 int error = EDOOFUS; 6476 6477 ATH_LOCK(sc); 6478 if (ic->ic_nrunning > 0) { 6479 /* 6480 * To avoid rescanning another access point, 6481 * do not call ath_init() here. Instead, 6482 * only reflect promisc mode settings. 6483 */ 6484 if (sc->sc_running) { 6485 ath_power_set_power_state(sc, HAL_PM_AWAKE); 6486 ath_mode_init(sc); 6487 ath_power_restore_power_state(sc); 6488 } else if (!sc->sc_invalid) { 6489 /* 6490 * Beware of being called during attach/detach 6491 * to reset promiscuous mode. In that case we 6492 * will still be marked UP but not RUNNING. 6493 * However trying to re-init the interface 6494 * is the wrong thing to do as we've already 6495 * torn down much of our state. There's 6496 * probably a better way to deal with this. 6497 */ 6498 error = ath_init(sc); 6499 } 6500 } else { 6501 ath_stop(sc); 6502 if (!sc->sc_invalid) 6503 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1); 6504 } 6505 ATH_UNLOCK(sc); 6506 6507 if (error == 0) { 6508 #ifdef ATH_TX99_DIAG 6509 if (sc->sc_tx99 != NULL) 6510 sc->sc_tx99->start(sc->sc_tx99); 6511 else 6512 #endif 6513 ieee80211_start_all(ic); 6514 } 6515 } 6516 6517 /* 6518 * Announce various information on device/driver attach. 6519 */ 6520 static void 6521 ath_announce(struct ath_softc *sc) 6522 { 6523 struct ath_hal *ah = sc->sc_ah; 6524 6525 device_printf(sc->sc_dev, "%s mac %d.%d RF%s phy %d.%d\n", 6526 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 6527 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 6528 device_printf(sc->sc_dev, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n", 6529 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev); 6530 if (bootverbose) { 6531 int i; 6532 for (i = 0; i <= WME_AC_VO; i++) { 6533 struct ath_txq *txq = sc->sc_ac2q[i]; 6534 device_printf(sc->sc_dev, 6535 "Use hw queue %u for %s traffic\n", 6536 txq->axq_qnum, ieee80211_wme_acnames[i]); 6537 } 6538 device_printf(sc->sc_dev, "Use hw queue %u for CAB traffic\n", 6539 sc->sc_cabq->axq_qnum); 6540 device_printf(sc->sc_dev, "Use hw queue %u for beacons\n", 6541 sc->sc_bhalq); 6542 } 6543 if (ath_rxbuf != ATH_RXBUF) 6544 device_printf(sc->sc_dev, "using %u rx buffers\n", ath_rxbuf); 6545 if (ath_txbuf != ATH_TXBUF) 6546 device_printf(sc->sc_dev, "using %u tx buffers\n", ath_txbuf); 6547 if (sc->sc_mcastkey && bootverbose) 6548 device_printf(sc->sc_dev, "using multicast key search\n"); 6549 } 6550 6551 static void 6552 ath_dfs_tasklet(void *p, int npending) 6553 { 6554 struct ath_softc *sc = (struct ath_softc *) p; 6555 struct ieee80211com *ic = &sc->sc_ic; 6556 6557 /* 6558 * If previous processing has found a radar event, 6559 * signal this to the net80211 layer to begin DFS 6560 * processing. 6561 */ 6562 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) { 6563 /* DFS event found, initiate channel change */ 6564 6565 /* 6566 * XXX TODO: immediately disable ACK processing 6567 * on the current channel. This would be done 6568 * by setting AR_DIAG_ACK_DIS (AR5212; may be 6569 * different for others) until we are out of 6570 * CAC. 6571 */ 6572 6573 /* 6574 * XXX doesn't currently tell us whether the event 6575 * XXX was found in the primary or extension 6576 * XXX channel! 6577 */ 6578 IEEE80211_LOCK(ic); 6579 ieee80211_dfs_notify_radar(ic, sc->sc_curchan); 6580 IEEE80211_UNLOCK(ic); 6581 } 6582 } 6583 6584 /* 6585 * Enable/disable power save. This must be called with 6586 * no TX driver locks currently held, so it should only 6587 * be called from the RX path (which doesn't hold any 6588 * TX driver locks.) 6589 */ 6590 static void 6591 ath_node_powersave(struct ieee80211_node *ni, int enable) 6592 { 6593 #ifdef ATH_SW_PSQ 6594 struct ath_node *an = ATH_NODE(ni); 6595 struct ieee80211com *ic = ni->ni_ic; 6596 struct ath_softc *sc = ic->ic_softc; 6597 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6598 6599 /* XXX and no TXQ locks should be held here */ 6600 6601 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n", 6602 __func__, 6603 ni->ni_macaddr, 6604 ":", 6605 !! enable); 6606 6607 /* Suspend or resume software queue handling */ 6608 if (enable) 6609 ath_tx_node_sleep(sc, an); 6610 else 6611 ath_tx_node_wakeup(sc, an); 6612 6613 /* Update net80211 state */ 6614 avp->av_node_ps(ni, enable); 6615 #else 6616 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6617 6618 /* Update net80211 state */ 6619 avp->av_node_ps(ni, enable); 6620 #endif/* ATH_SW_PSQ */ 6621 } 6622 6623 /* 6624 * Notification from net80211 that the powersave queue state has 6625 * changed. 6626 * 6627 * Since the software queue also may have some frames: 6628 * 6629 * + if the node software queue has frames and the TID state 6630 * is 0, we set the TIM; 6631 * + if the node and the stack are both empty, we clear the TIM bit. 6632 * + If the stack tries to set the bit, always set it. 6633 * + If the stack tries to clear the bit, only clear it if the 6634 * software queue in question is also cleared. 6635 * 6636 * TODO: this is called during node teardown; so let's ensure this 6637 * is all correctly handled and that the TIM bit is cleared. 6638 * It may be that the node flush is called _AFTER_ the net80211 6639 * stack clears the TIM. 6640 * 6641 * Here is the racy part. Since it's possible >1 concurrent, 6642 * overlapping TXes will appear complete with a TX completion in 6643 * another thread, it's possible that the concurrent TIM calls will 6644 * clash. We can't hold the node lock here because setting the 6645 * TIM grabs the net80211 comlock and this may cause a LOR. 6646 * The solution is either to totally serialise _everything_ at 6647 * this point (ie, all TX, completion and any reset/flush go into 6648 * one taskqueue) or a new "ath TIM lock" needs to be created that 6649 * just wraps the driver state change and this call to avp->av_set_tim(). 6650 * 6651 * The same race exists in the net80211 power save queue handling 6652 * as well. Since multiple transmitting threads may queue frames 6653 * into the driver, as well as ps-poll and the driver transmitting 6654 * frames (and thus clearing the psq), it's quite possible that 6655 * a packet entering the PSQ and a ps-poll being handled will 6656 * race, causing the TIM to be cleared and not re-set. 6657 */ 6658 static int 6659 ath_node_set_tim(struct ieee80211_node *ni, int enable) 6660 { 6661 #ifdef ATH_SW_PSQ 6662 struct ieee80211com *ic = ni->ni_ic; 6663 struct ath_softc *sc = ic->ic_softc; 6664 struct ath_node *an = ATH_NODE(ni); 6665 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6666 int changed = 0; 6667 6668 ATH_TX_LOCK(sc); 6669 an->an_stack_psq = enable; 6670 6671 /* 6672 * This will get called for all operating modes, 6673 * even if avp->av_set_tim is unset. 6674 * It's currently set for hostap/ibss modes; but 6675 * the same infrastructure is used for both STA 6676 * and AP/IBSS node power save. 6677 */ 6678 if (avp->av_set_tim == NULL) { 6679 ATH_TX_UNLOCK(sc); 6680 return (0); 6681 } 6682 6683 /* 6684 * If setting the bit, always set it here. 6685 * If clearing the bit, only clear it if the 6686 * software queue is also empty. 6687 * 6688 * If the node has left power save, just clear the TIM 6689 * bit regardless of the state of the power save queue. 6690 * 6691 * XXX TODO: although atomics are used, it's quite possible 6692 * that a race will occur between this and setting/clearing 6693 * in another thread. TX completion will occur always in 6694 * one thread, however setting/clearing the TIM bit can come 6695 * from a variety of different process contexts! 6696 */ 6697 if (enable && an->an_tim_set == 1) { 6698 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6699 "%s: %6D: enable=%d, tim_set=1, ignoring\n", 6700 __func__, 6701 ni->ni_macaddr, 6702 ":", 6703 enable); 6704 ATH_TX_UNLOCK(sc); 6705 } else if (enable) { 6706 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6707 "%s: %6D: enable=%d, enabling TIM\n", 6708 __func__, 6709 ni->ni_macaddr, 6710 ":", 6711 enable); 6712 an->an_tim_set = 1; 6713 ATH_TX_UNLOCK(sc); 6714 changed = avp->av_set_tim(ni, enable); 6715 } else if (an->an_swq_depth == 0) { 6716 /* disable */ 6717 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6718 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n", 6719 __func__, 6720 ni->ni_macaddr, 6721 ":", 6722 enable); 6723 an->an_tim_set = 0; 6724 ATH_TX_UNLOCK(sc); 6725 changed = avp->av_set_tim(ni, enable); 6726 } else if (! an->an_is_powersave) { 6727 /* 6728 * disable regardless; the node isn't in powersave now 6729 */ 6730 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6731 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n", 6732 __func__, 6733 ni->ni_macaddr, 6734 ":", 6735 enable); 6736 an->an_tim_set = 0; 6737 ATH_TX_UNLOCK(sc); 6738 changed = avp->av_set_tim(ni, enable); 6739 } else { 6740 /* 6741 * psq disable, node is currently in powersave, node 6742 * software queue isn't empty, so don't clear the TIM bit 6743 * for now. 6744 */ 6745 ATH_TX_UNLOCK(sc); 6746 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6747 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n", 6748 __func__, 6749 ni->ni_macaddr, 6750 ":", 6751 enable); 6752 changed = 0; 6753 } 6754 6755 return (changed); 6756 #else 6757 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6758 6759 /* 6760 * Some operating modes don't set av_set_tim(), so don't 6761 * update it here. 6762 */ 6763 if (avp->av_set_tim == NULL) 6764 return (0); 6765 6766 return (avp->av_set_tim(ni, enable)); 6767 #endif /* ATH_SW_PSQ */ 6768 } 6769 6770 /* 6771 * Set or update the TIM from the software queue. 6772 * 6773 * Check the software queue depth before attempting to do lock 6774 * anything; that avoids trying to obtain the lock. Then, 6775 * re-check afterwards to ensure nothing has changed in the 6776 * meantime. 6777 * 6778 * set: This is designed to be called from the TX path, after 6779 * a frame has been queued; to see if the swq > 0. 6780 * 6781 * clear: This is designed to be called from the buffer completion point 6782 * (right now it's ath_tx_default_comp()) where the state of 6783 * a software queue has changed. 6784 * 6785 * It makes sense to place it at buffer free / completion rather 6786 * than after each software queue operation, as there's no real 6787 * point in churning the TIM bit as the last frames in the software 6788 * queue are transmitted. If they fail and we retry them, we'd 6789 * just be setting the TIM bit again anyway. 6790 */ 6791 void 6792 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni, 6793 int enable) 6794 { 6795 #ifdef ATH_SW_PSQ 6796 struct ath_node *an; 6797 struct ath_vap *avp; 6798 6799 /* Don't do this for broadcast/etc frames */ 6800 if (ni == NULL) 6801 return; 6802 6803 an = ATH_NODE(ni); 6804 avp = ATH_VAP(ni->ni_vap); 6805 6806 /* 6807 * And for operating modes without the TIM handler set, let's 6808 * just skip those. 6809 */ 6810 if (avp->av_set_tim == NULL) 6811 return; 6812 6813 ATH_TX_LOCK_ASSERT(sc); 6814 6815 if (enable) { 6816 if (an->an_is_powersave && 6817 an->an_tim_set == 0 && 6818 an->an_swq_depth != 0) { 6819 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6820 "%s: %6D: swq_depth>0, tim_set=0, set!\n", 6821 __func__, 6822 ni->ni_macaddr, 6823 ":"); 6824 an->an_tim_set = 1; 6825 (void) avp->av_set_tim(ni, 1); 6826 } 6827 } else { 6828 /* 6829 * Don't bother grabbing the lock unless the queue is empty. 6830 */ 6831 if (an->an_swq_depth != 0) 6832 return; 6833 6834 if (an->an_is_powersave && 6835 an->an_stack_psq == 0 && 6836 an->an_tim_set == 1 && 6837 an->an_swq_depth == 0) { 6838 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6839 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0," 6840 " clear!\n", 6841 __func__, 6842 ni->ni_macaddr, 6843 ":"); 6844 an->an_tim_set = 0; 6845 (void) avp->av_set_tim(ni, 0); 6846 } 6847 } 6848 #else 6849 return; 6850 #endif /* ATH_SW_PSQ */ 6851 } 6852 6853 /* 6854 * Received a ps-poll frame from net80211. 6855 * 6856 * Here we get a chance to serve out a software-queued frame ourselves 6857 * before we punt it to net80211 to transmit us one itself - either 6858 * because there's traffic in the net80211 psq, or a NULL frame to 6859 * indicate there's nothing else. 6860 */ 6861 static void 6862 ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m) 6863 { 6864 #ifdef ATH_SW_PSQ 6865 struct ath_node *an; 6866 struct ath_vap *avp; 6867 struct ieee80211com *ic = ni->ni_ic; 6868 struct ath_softc *sc = ic->ic_softc; 6869 int tid; 6870 6871 /* Just paranoia */ 6872 if (ni == NULL) 6873 return; 6874 6875 /* 6876 * Unassociated (temporary node) station. 6877 */ 6878 if (ni->ni_associd == 0) 6879 return; 6880 6881 /* 6882 * We do have an active node, so let's begin looking into it. 6883 */ 6884 an = ATH_NODE(ni); 6885 avp = ATH_VAP(ni->ni_vap); 6886 6887 /* 6888 * For now, we just call the original ps-poll method. 6889 * Once we're ready to flip this on: 6890 * 6891 * + Set leak to 1, as no matter what we're going to have 6892 * to send a frame; 6893 * + Check the software queue and if there's something in it, 6894 * schedule the highest TID thas has traffic from this node. 6895 * Then make sure we schedule the software scheduler to 6896 * run so it picks up said frame. 6897 * 6898 * That way whatever happens, we'll at least send _a_ frame 6899 * to the given node. 6900 * 6901 * Again, yes, it's crappy QoS if the node has multiple 6902 * TIDs worth of traffic - but let's get it working first 6903 * before we optimise it. 6904 * 6905 * Also yes, there's definitely latency here - we're not 6906 * direct dispatching to the hardware in this path (and 6907 * we're likely being called from the packet receive path, 6908 * so going back into TX may be a little hairy!) but again 6909 * I'd like to get this working first before optimising 6910 * turn-around time. 6911 */ 6912 6913 ATH_TX_LOCK(sc); 6914 6915 /* 6916 * Legacy - we're called and the node isn't asleep. 6917 * Immediately punt. 6918 */ 6919 if (! an->an_is_powersave) { 6920 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6921 "%s: %6D: not in powersave?\n", 6922 __func__, 6923 ni->ni_macaddr, 6924 ":"); 6925 ATH_TX_UNLOCK(sc); 6926 avp->av_recv_pspoll(ni, m); 6927 return; 6928 } 6929 6930 /* 6931 * We're in powersave. 6932 * 6933 * Leak a frame. 6934 */ 6935 an->an_leak_count = 1; 6936 6937 /* 6938 * Now, if there's no frames in the node, just punt to 6939 * recv_pspoll. 6940 * 6941 * Don't bother checking if the TIM bit is set, we really 6942 * only care if there are any frames here! 6943 */ 6944 if (an->an_swq_depth == 0) { 6945 ATH_TX_UNLOCK(sc); 6946 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6947 "%s: %6D: SWQ empty; punting to net80211\n", 6948 __func__, 6949 ni->ni_macaddr, 6950 ":"); 6951 avp->av_recv_pspoll(ni, m); 6952 return; 6953 } 6954 6955 /* 6956 * Ok, let's schedule the highest TID that has traffic 6957 * and then schedule something. 6958 */ 6959 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) { 6960 struct ath_tid *atid = &an->an_tid[tid]; 6961 /* 6962 * No frames? Skip. 6963 */ 6964 if (atid->axq_depth == 0) 6965 continue; 6966 ath_tx_tid_sched(sc, atid); 6967 /* 6968 * XXX we could do a direct call to the TXQ 6969 * scheduler code here to optimise latency 6970 * at the expense of a REALLY deep callstack. 6971 */ 6972 ATH_TX_UNLOCK(sc); 6973 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 6974 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6975 "%s: %6D: leaking frame to TID %d\n", 6976 __func__, 6977 ni->ni_macaddr, 6978 ":", 6979 tid); 6980 return; 6981 } 6982 6983 ATH_TX_UNLOCK(sc); 6984 6985 /* 6986 * XXX nothing in the TIDs at this point? Eek. 6987 */ 6988 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6989 "%s: %6D: TIDs empty, but ath_node showed traffic?!\n", 6990 __func__, 6991 ni->ni_macaddr, 6992 ":"); 6993 avp->av_recv_pspoll(ni, m); 6994 #else 6995 avp->av_recv_pspoll(ni, m); 6996 #endif /* ATH_SW_PSQ */ 6997 } 6998 6999 MODULE_VERSION(ath_main, 1); 7000 MODULE_DEPEND(ath_main, wlan, 1, 1, 1); /* 802.11 media layer */ 7001 MODULE_DEPEND(ath_main, ath_rate, 1, 1, 1); 7002 MODULE_DEPEND(ath_main, ath_dfs, 1, 1, 1); 7003 MODULE_DEPEND(ath_main, ath_hal, 1, 1, 1); 7004 #if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) || defined(ATH_DEBUG_ALQ) 7005 MODULE_DEPEND(ath_main, alq, 1, 1, 1); 7006 #endif 7007