1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 #include "opt_wlan.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/sysctl.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/lock.h> 50 #include <sys/mutex.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/errno.h> 55 #include <sys/callout.h> 56 #include <sys/bus.h> 57 #include <sys/endian.h> 58 #include <sys/kthread.h> 59 #include <sys/taskqueue.h> 60 #include <sys/priv.h> 61 62 #include <machine/bus.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 #include <net/if_arp.h> 69 #include <net/ethernet.h> 70 #include <net/if_llc.h> 71 72 #include <net80211/ieee80211_var.h> 73 #include <net80211/ieee80211_regdomain.h> 74 #ifdef IEEE80211_SUPPORT_SUPERG 75 #include <net80211/ieee80211_superg.h> 76 #endif 77 #ifdef IEEE80211_SUPPORT_TDMA 78 #include <net80211/ieee80211_tdma.h> 79 #endif 80 81 #include <net/bpf.h> 82 83 #ifdef INET 84 #include <netinet/in.h> 85 #include <netinet/if_ether.h> 86 #endif 87 88 #include <dev/ath/if_athvar.h> 89 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 90 91 #ifdef ATH_TX99_DIAG 92 #include <dev/ath/ath_tx99/ath_tx99.h> 93 #endif 94 95 /* 96 * ATH_BCBUF determines the number of vap's that can transmit 97 * beacons and also (currently) the number of vap's that can 98 * have unique mac addresses/bssid. When staggering beacons 99 * 4 is probably a good max as otherwise the beacons become 100 * very closely spaced and there is limited time for cab q traffic 101 * to go out. You can burst beacons instead but that is not good 102 * for stations in power save and at some point you really want 103 * another radio (and channel). 104 * 105 * The limit on the number of mac addresses is tied to our use of 106 * the U/L bit and tracking addresses in a byte; it would be 107 * worthwhile to allow more for applications like proxy sta. 108 */ 109 CTASSERT(ATH_BCBUF <= 8); 110 111 /* unaligned little endian access */ 112 #define LE_READ_2(p) \ 113 ((u_int16_t) \ 114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 115 #define LE_READ_4(p) \ 116 ((u_int32_t) \ 117 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 118 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 119 120 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 121 const char name[IFNAMSIZ], int unit, int opmode, 122 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 123 const uint8_t mac[IEEE80211_ADDR_LEN]); 124 static void ath_vap_delete(struct ieee80211vap *); 125 static void ath_init(void *); 126 static void ath_stop_locked(struct ifnet *); 127 static void ath_stop(struct ifnet *); 128 static void ath_start(struct ifnet *); 129 static int ath_reset(struct ifnet *); 130 static int ath_reset_vap(struct ieee80211vap *, u_long); 131 static int ath_media_change(struct ifnet *); 132 static void ath_watchdog(void *); 133 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 134 static void ath_fatal_proc(void *, int); 135 static void ath_bmiss_vap(struct ieee80211vap *); 136 static void ath_bmiss_proc(void *, int); 137 static int ath_keyset(struct ath_softc *, const struct ieee80211_key *, 138 struct ieee80211_node *); 139 static int ath_key_alloc(struct ieee80211vap *, 140 struct ieee80211_key *, 141 ieee80211_keyix *, ieee80211_keyix *); 142 static int ath_key_delete(struct ieee80211vap *, 143 const struct ieee80211_key *); 144 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *, 145 const u_int8_t mac[IEEE80211_ADDR_LEN]); 146 static void ath_key_update_begin(struct ieee80211vap *); 147 static void ath_key_update_end(struct ieee80211vap *); 148 static void ath_update_mcast(struct ifnet *); 149 static void ath_update_promisc(struct ifnet *); 150 static void ath_mode_init(struct ath_softc *); 151 static void ath_setslottime(struct ath_softc *); 152 static void ath_updateslot(struct ifnet *); 153 static int ath_beaconq_setup(struct ath_hal *); 154 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 155 static void ath_beacon_update(struct ieee80211vap *, int item); 156 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 157 static void ath_beacon_proc(void *, int); 158 static struct ath_buf *ath_beacon_generate(struct ath_softc *, 159 struct ieee80211vap *); 160 static void ath_bstuck_proc(void *, int); 161 static void ath_beacon_return(struct ath_softc *, struct ath_buf *); 162 static void ath_beacon_free(struct ath_softc *); 163 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *); 164 static void ath_descdma_cleanup(struct ath_softc *sc, 165 struct ath_descdma *, ath_bufhead *); 166 static int ath_desc_alloc(struct ath_softc *); 167 static void ath_desc_free(struct ath_softc *); 168 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 169 const uint8_t [IEEE80211_ADDR_LEN]); 170 static void ath_node_free(struct ieee80211_node *); 171 static void ath_node_getsignal(const struct ieee80211_node *, 172 int8_t *, int8_t *); 173 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 174 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 175 int subtype, int rssi, int nf); 176 static void ath_setdefantenna(struct ath_softc *, u_int); 177 static void ath_rx_proc(void *, int); 178 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 179 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 180 static int ath_tx_setup(struct ath_softc *, int, int); 181 static int ath_wme_update(struct ieee80211com *); 182 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 183 static void ath_tx_cleanup(struct ath_softc *); 184 static void ath_freetx(struct mbuf *); 185 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 186 struct ath_buf *, struct mbuf *); 187 static void ath_tx_proc_q0(void *, int); 188 static void ath_tx_proc_q0123(void *, int); 189 static void ath_tx_proc(void *, int); 190 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *); 191 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 192 static void ath_draintxq(struct ath_softc *); 193 static void ath_stoprecv(struct ath_softc *); 194 static int ath_startrecv(struct ath_softc *); 195 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 196 static void ath_scan_start(struct ieee80211com *); 197 static void ath_scan_end(struct ieee80211com *); 198 static void ath_set_channel(struct ieee80211com *); 199 static void ath_calibrate(void *); 200 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 201 static void ath_setup_stationkey(struct ieee80211_node *); 202 static void ath_newassoc(struct ieee80211_node *, int); 203 static int ath_setregdomain(struct ieee80211com *, 204 struct ieee80211_regdomain *, int, 205 struct ieee80211_channel []); 206 static void ath_getradiocaps(struct ieee80211com *, int, int *, 207 struct ieee80211_channel []); 208 static int ath_getchannels(struct ath_softc *); 209 static void ath_led_event(struct ath_softc *, int); 210 211 static int ath_rate_setup(struct ath_softc *, u_int mode); 212 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 213 214 static void ath_sysctlattach(struct ath_softc *); 215 static int ath_raw_xmit(struct ieee80211_node *, 216 struct mbuf *, const struct ieee80211_bpf_params *); 217 static void ath_announce(struct ath_softc *); 218 219 #ifdef IEEE80211_SUPPORT_TDMA 220 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, 221 u_int32_t bintval); 222 static void ath_tdma_bintvalsetup(struct ath_softc *sc, 223 const struct ieee80211_tdma_state *tdma); 224 static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap); 225 static void ath_tdma_update(struct ieee80211_node *ni, 226 const struct ieee80211_tdma_param *tdma, int); 227 static void ath_tdma_beacon_send(struct ath_softc *sc, 228 struct ieee80211vap *vap); 229 230 static __inline void 231 ath_hal_setcca(struct ath_hal *ah, int ena) 232 { 233 /* 234 * NB: fill me in; this is not provided by default because disabling 235 * CCA in most locales violates regulatory. 236 */ 237 } 238 239 static __inline int 240 ath_hal_getcca(struct ath_hal *ah) 241 { 242 u_int32_t diag; 243 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK) 244 return 1; 245 return ((diag & 0x500000) == 0); 246 } 247 248 #define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */ 249 #define TDMA_LPF_LEN 6 250 #define TDMA_DUMMY_MARKER 0x127 251 #define TDMA_EP_MUL(x, mul) ((x) * (mul)) 252 #define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER)) 253 #define TDMA_LPF(x, y, len) \ 254 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y)) 255 #define TDMA_SAMPLE(x, y) do { \ 256 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \ 257 } while (0) 258 #define TDMA_EP_RND(x,mul) \ 259 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 260 #define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER) 261 #endif /* IEEE80211_SUPPORT_TDMA */ 262 263 SYSCTL_DECL(_hw_ath); 264 265 /* XXX validate sysctl values */ 266 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 267 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 268 0, "long chip calibration interval (secs)"); 269 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 270 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 271 0, "short chip calibration interval (msecs)"); 272 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 273 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 274 0, "reset chip calibration results (secs)"); 275 276 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 277 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 278 0, "rx buffers allocated"); 279 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 280 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 281 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 282 0, "tx buffers allocated"); 283 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 284 285 static int ath_bstuck_threshold = 4; /* max missed beacons */ 286 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 287 0, "max missed beacon xmits before chip reset"); 288 289 #ifdef ATH_DEBUG 290 enum { 291 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 292 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 293 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 294 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 295 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 296 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 297 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 298 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 299 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 300 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 301 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 302 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 303 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 304 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 305 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 306 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 307 ATH_DEBUG_NODE = 0x00080000, /* node management */ 308 ATH_DEBUG_LED = 0x00100000, /* led management */ 309 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 310 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 311 ATH_DEBUG_TDMA = 0x00800000, /* TDMA processing */ 312 ATH_DEBUG_TDMA_TIMER = 0x01000000, /* TDMA timer processing */ 313 ATH_DEBUG_REGDOMAIN = 0x02000000, /* regulatory processing */ 314 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 315 ATH_DEBUG_ANY = 0xffffffff 316 }; 317 static int ath_debug = 0; 318 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 319 0, "control debugging printfs"); 320 TUNABLE_INT("hw.ath.debug", &ath_debug); 321 322 #define IFF_DUMPPKTS(sc, m) \ 323 ((sc->sc_debug & (m)) || \ 324 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 325 #define DPRINTF(sc, m, fmt, ...) do { \ 326 if (sc->sc_debug & (m)) \ 327 printf(fmt, __VA_ARGS__); \ 328 } while (0) 329 #define KEYPRINTF(sc, ix, hk, mac) do { \ 330 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 331 ath_keyprint(sc, __func__, ix, hk, mac); \ 332 } while (0) 333 static void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf, 334 u_int ix, int); 335 static void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf, 336 u_int qnum, u_int ix, int done); 337 #else 338 #define IFF_DUMPPKTS(sc, m) \ 339 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 340 #define DPRINTF(sc, m, fmt, ...) do { \ 341 (void) sc; \ 342 } while (0) 343 #define KEYPRINTF(sc, k, ix, mac) do { \ 344 (void) sc; \ 345 } while (0) 346 #endif 347 348 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 349 350 int 351 ath_attach(u_int16_t devid, struct ath_softc *sc) 352 { 353 struct ifnet *ifp; 354 struct ieee80211com *ic; 355 struct ath_hal *ah = NULL; 356 HAL_STATUS status; 357 int error = 0, i; 358 u_int wmodes; 359 uint8_t macaddr[IEEE80211_ADDR_LEN]; 360 361 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 362 363 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 364 if (ifp == NULL) { 365 device_printf(sc->sc_dev, "can not if_alloc()\n"); 366 error = ENOSPC; 367 goto bad; 368 } 369 ic = ifp->if_l2com; 370 371 /* set these up early for if_printf use */ 372 if_initname(ifp, device_get_name(sc->sc_dev), 373 device_get_unit(sc->sc_dev)); 374 375 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 376 if (ah == NULL) { 377 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 378 status); 379 error = ENXIO; 380 goto bad; 381 } 382 sc->sc_ah = ah; 383 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 384 #ifdef ATH_DEBUG 385 sc->sc_debug = ath_debug; 386 #endif 387 388 /* 389 * Check if the MAC has multi-rate retry support. 390 * We do this by trying to setup a fake extended 391 * descriptor. MAC's that don't have support will 392 * return false w/o doing anything. MAC's that do 393 * support it will return true w/o doing anything. 394 */ 395 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 396 397 /* 398 * Check if the device has hardware counters for PHY 399 * errors. If so we need to enable the MIB interrupt 400 * so we can act on stat triggers. 401 */ 402 if (ath_hal_hwphycounters(ah)) 403 sc->sc_needmib = 1; 404 405 /* 406 * Get the hardware key cache size. 407 */ 408 sc->sc_keymax = ath_hal_keycachesize(ah); 409 if (sc->sc_keymax > ATH_KEYMAX) { 410 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 411 ATH_KEYMAX, sc->sc_keymax); 412 sc->sc_keymax = ATH_KEYMAX; 413 } 414 /* 415 * Reset the key cache since some parts do not 416 * reset the contents on initial power up. 417 */ 418 for (i = 0; i < sc->sc_keymax; i++) 419 ath_hal_keyreset(ah, i); 420 421 /* 422 * Collect the default channel list. 423 */ 424 error = ath_getchannels(sc); 425 if (error != 0) 426 goto bad; 427 428 /* 429 * Setup rate tables for all potential media types. 430 */ 431 ath_rate_setup(sc, IEEE80211_MODE_11A); 432 ath_rate_setup(sc, IEEE80211_MODE_11B); 433 ath_rate_setup(sc, IEEE80211_MODE_11G); 434 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 435 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 436 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 437 ath_rate_setup(sc, IEEE80211_MODE_11NA); 438 ath_rate_setup(sc, IEEE80211_MODE_11NG); 439 ath_rate_setup(sc, IEEE80211_MODE_HALF); 440 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 441 442 /* NB: setup here so ath_rate_update is happy */ 443 ath_setcurmode(sc, IEEE80211_MODE_11A); 444 445 /* 446 * Allocate tx+rx descriptors and populate the lists. 447 */ 448 error = ath_desc_alloc(sc); 449 if (error != 0) { 450 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 451 goto bad; 452 } 453 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 454 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 455 456 ATH_TXBUF_LOCK_INIT(sc); 457 458 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 459 taskqueue_thread_enqueue, &sc->sc_tq); 460 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 461 "%s taskq", ifp->if_xname); 462 463 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 464 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 465 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 466 467 /* 468 * Allocate hardware transmit queues: one queue for 469 * beacon frames and one data queue for each QoS 470 * priority. Note that the hal handles reseting 471 * these queues at the needed time. 472 * 473 * XXX PS-Poll 474 */ 475 sc->sc_bhalq = ath_beaconq_setup(ah); 476 if (sc->sc_bhalq == (u_int) -1) { 477 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 478 error = EIO; 479 goto bad2; 480 } 481 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 482 if (sc->sc_cabq == NULL) { 483 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 484 error = EIO; 485 goto bad2; 486 } 487 /* NB: insure BK queue is the lowest priority h/w queue */ 488 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 489 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 490 ieee80211_wme_acnames[WME_AC_BK]); 491 error = EIO; 492 goto bad2; 493 } 494 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 495 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 496 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 497 /* 498 * Not enough hardware tx queues to properly do WME; 499 * just punt and assign them all to the same h/w queue. 500 * We could do a better job of this if, for example, 501 * we allocate queues when we switch from station to 502 * AP mode. 503 */ 504 if (sc->sc_ac2q[WME_AC_VI] != NULL) 505 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 506 if (sc->sc_ac2q[WME_AC_BE] != NULL) 507 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 508 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 509 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 510 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 511 } 512 513 /* 514 * Special case certain configurations. Note the 515 * CAB queue is handled by these specially so don't 516 * include them when checking the txq setup mask. 517 */ 518 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 519 case 0x01: 520 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 521 break; 522 case 0x0f: 523 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 524 break; 525 default: 526 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 527 break; 528 } 529 530 /* 531 * Setup rate control. Some rate control modules 532 * call back to change the anntena state so expose 533 * the necessary entry points. 534 * XXX maybe belongs in struct ath_ratectrl? 535 */ 536 sc->sc_setdefantenna = ath_setdefantenna; 537 sc->sc_rc = ath_rate_attach(sc); 538 if (sc->sc_rc == NULL) { 539 error = EIO; 540 goto bad2; 541 } 542 543 sc->sc_blinking = 0; 544 sc->sc_ledstate = 1; 545 sc->sc_ledon = 0; /* low true */ 546 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 547 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 548 /* 549 * Auto-enable soft led processing for IBM cards and for 550 * 5211 minipci cards. Users can also manually enable/disable 551 * support with a sysctl. 552 */ 553 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 554 if (sc->sc_softled) { 555 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 556 HAL_GPIO_MUX_MAC_NETWORK_LED); 557 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 558 } 559 560 ifp->if_softc = sc; 561 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 562 ifp->if_start = ath_start; 563 ifp->if_watchdog = NULL; 564 ifp->if_ioctl = ath_ioctl; 565 ifp->if_init = ath_init; 566 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 567 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 568 IFQ_SET_READY(&ifp->if_snd); 569 570 ic->ic_ifp = ifp; 571 /* XXX not right but it's not used anywhere important */ 572 ic->ic_phytype = IEEE80211_T_OFDM; 573 ic->ic_opmode = IEEE80211_M_STA; 574 ic->ic_caps = 575 IEEE80211_C_STA /* station mode */ 576 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 577 | IEEE80211_C_HOSTAP /* hostap mode */ 578 | IEEE80211_C_MONITOR /* monitor mode */ 579 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 580 | IEEE80211_C_WDS /* 4-address traffic works */ 581 | IEEE80211_C_MBSS /* mesh point link mode */ 582 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 583 | IEEE80211_C_SHSLOT /* short slot time supported */ 584 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 585 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 586 | IEEE80211_C_TXFRAG /* handle tx frags */ 587 ; 588 /* 589 * Query the hal to figure out h/w crypto support. 590 */ 591 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 592 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 593 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 594 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 595 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 596 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 597 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 598 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 599 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 600 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 601 /* 602 * Check if h/w does the MIC and/or whether the 603 * separate key cache entries are required to 604 * handle both tx+rx MIC keys. 605 */ 606 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 607 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 608 /* 609 * If the h/w supports storing tx+rx MIC keys 610 * in one cache slot automatically enable use. 611 */ 612 if (ath_hal_hastkipsplit(ah) || 613 !ath_hal_settkipsplit(ah, AH_FALSE)) 614 sc->sc_splitmic = 1; 615 /* 616 * If the h/w can do TKIP MIC together with WME then 617 * we use it; otherwise we force the MIC to be done 618 * in software by the net80211 layer. 619 */ 620 if (ath_hal_haswmetkipmic(ah)) 621 sc->sc_wmetkipmic = 1; 622 } 623 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 624 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 625 /* 626 * Mark key cache slots associated with global keys 627 * as in use. If we knew TKIP was not to be used we 628 * could leave the +32, +64, and +32+64 slots free. 629 */ 630 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 631 setbit(sc->sc_keymap, i); 632 setbit(sc->sc_keymap, i+64); 633 if (sc->sc_splitmic) { 634 setbit(sc->sc_keymap, i+32); 635 setbit(sc->sc_keymap, i+32+64); 636 } 637 } 638 /* 639 * TPC support can be done either with a global cap or 640 * per-packet support. The latter is not available on 641 * all parts. We're a bit pedantic here as all parts 642 * support a global cap. 643 */ 644 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 645 ic->ic_caps |= IEEE80211_C_TXPMGT; 646 647 /* 648 * Mark WME capability only if we have sufficient 649 * hardware queues to do proper priority scheduling. 650 */ 651 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 652 ic->ic_caps |= IEEE80211_C_WME; 653 /* 654 * Check for misc other capabilities. 655 */ 656 if (ath_hal_hasbursting(ah)) 657 ic->ic_caps |= IEEE80211_C_BURST; 658 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 659 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 660 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 661 if (ath_hal_hasfastframes(ah)) 662 ic->ic_caps |= IEEE80211_C_FF; 663 wmodes = ath_hal_getwirelessmodes(ah); 664 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 665 ic->ic_caps |= IEEE80211_C_TURBOP; 666 #ifdef IEEE80211_SUPPORT_TDMA 667 if (ath_hal_macversion(ah) > 0x78) { 668 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 669 ic->ic_tdma_update = ath_tdma_update; 670 } 671 #endif 672 /* 673 * Indicate we need the 802.11 header padded to a 674 * 32-bit boundary for 4-address and QoS frames. 675 */ 676 ic->ic_flags |= IEEE80211_F_DATAPAD; 677 678 /* 679 * Query the hal about antenna support. 680 */ 681 sc->sc_defant = ath_hal_getdefantenna(ah); 682 683 /* 684 * Not all chips have the VEOL support we want to 685 * use with IBSS beacons; check here for it. 686 */ 687 sc->sc_hasveol = ath_hal_hasveol(ah); 688 689 /* get mac address from hardware */ 690 ath_hal_getmac(ah, macaddr); 691 if (sc->sc_hasbmask) 692 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 693 694 /* NB: used to size node table key mapping array */ 695 ic->ic_max_keyix = sc->sc_keymax; 696 /* call MI attach routine. */ 697 ieee80211_ifattach(ic, macaddr); 698 ic->ic_setregdomain = ath_setregdomain; 699 ic->ic_getradiocaps = ath_getradiocaps; 700 sc->sc_opmode = HAL_M_STA; 701 702 /* override default methods */ 703 ic->ic_newassoc = ath_newassoc; 704 ic->ic_updateslot = ath_updateslot; 705 ic->ic_wme.wme_update = ath_wme_update; 706 ic->ic_vap_create = ath_vap_create; 707 ic->ic_vap_delete = ath_vap_delete; 708 ic->ic_raw_xmit = ath_raw_xmit; 709 ic->ic_update_mcast = ath_update_mcast; 710 ic->ic_update_promisc = ath_update_promisc; 711 ic->ic_node_alloc = ath_node_alloc; 712 sc->sc_node_free = ic->ic_node_free; 713 ic->ic_node_free = ath_node_free; 714 ic->ic_node_getsignal = ath_node_getsignal; 715 ic->ic_scan_start = ath_scan_start; 716 ic->ic_scan_end = ath_scan_end; 717 ic->ic_set_channel = ath_set_channel; 718 719 ieee80211_radiotap_attach(ic, 720 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 721 ATH_TX_RADIOTAP_PRESENT, 722 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 723 ATH_RX_RADIOTAP_PRESENT); 724 725 /* 726 * Setup dynamic sysctl's now that country code and 727 * regdomain are available from the hal. 728 */ 729 ath_sysctlattach(sc); 730 731 if (bootverbose) 732 ieee80211_announce(ic); 733 ath_announce(sc); 734 return 0; 735 bad2: 736 ath_tx_cleanup(sc); 737 ath_desc_free(sc); 738 bad: 739 if (ah) 740 ath_hal_detach(ah); 741 if (ifp != NULL) 742 if_free(ifp); 743 sc->sc_invalid = 1; 744 return error; 745 } 746 747 int 748 ath_detach(struct ath_softc *sc) 749 { 750 struct ifnet *ifp = sc->sc_ifp; 751 752 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 753 __func__, ifp->if_flags); 754 755 /* 756 * NB: the order of these is important: 757 * o stop the chip so no more interrupts will fire 758 * o call the 802.11 layer before detaching the hal to 759 * insure callbacks into the driver to delete global 760 * key cache entries can be handled 761 * o free the taskqueue which drains any pending tasks 762 * o reclaim the tx queue data structures after calling 763 * the 802.11 layer as we'll get called back to reclaim 764 * node state and potentially want to use them 765 * o to cleanup the tx queues the hal is called, so detach 766 * it last 767 * Other than that, it's straightforward... 768 */ 769 ath_stop(ifp); 770 ieee80211_ifdetach(ifp->if_l2com); 771 taskqueue_free(sc->sc_tq); 772 #ifdef ATH_TX99_DIAG 773 if (sc->sc_tx99 != NULL) 774 sc->sc_tx99->detach(sc->sc_tx99); 775 #endif 776 ath_rate_detach(sc->sc_rc); 777 ath_desc_free(sc); 778 ath_tx_cleanup(sc); 779 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 780 if_free(ifp); 781 782 return 0; 783 } 784 785 /* 786 * MAC address handling for multiple BSS on the same radio. 787 * The first vap uses the MAC address from the EEPROM. For 788 * subsequent vap's we set the U/L bit (bit 1) in the MAC 789 * address and use the next six bits as an index. 790 */ 791 static void 792 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 793 { 794 int i; 795 796 if (clone && sc->sc_hasbmask) { 797 /* NB: we only do this if h/w supports multiple bssid */ 798 for (i = 0; i < 8; i++) 799 if ((sc->sc_bssidmask & (1<<i)) == 0) 800 break; 801 if (i != 0) 802 mac[0] |= (i << 2)|0x2; 803 } else 804 i = 0; 805 sc->sc_bssidmask |= 1<<i; 806 sc->sc_hwbssidmask[0] &= ~mac[0]; 807 if (i == 0) 808 sc->sc_nbssid0++; 809 } 810 811 static void 812 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 813 { 814 int i = mac[0] >> 2; 815 uint8_t mask; 816 817 if (i != 0 || --sc->sc_nbssid0 == 0) { 818 sc->sc_bssidmask &= ~(1<<i); 819 /* recalculate bssid mask from remaining addresses */ 820 mask = 0xff; 821 for (i = 1; i < 8; i++) 822 if (sc->sc_bssidmask & (1<<i)) 823 mask &= ~((i<<2)|0x2); 824 sc->sc_hwbssidmask[0] |= mask; 825 } 826 } 827 828 /* 829 * Assign a beacon xmit slot. We try to space out 830 * assignments so when beacons are staggered the 831 * traffic coming out of the cab q has maximal time 832 * to go out before the next beacon is scheduled. 833 */ 834 static int 835 assign_bslot(struct ath_softc *sc) 836 { 837 u_int slot, free; 838 839 free = 0; 840 for (slot = 0; slot < ATH_BCBUF; slot++) 841 if (sc->sc_bslot[slot] == NULL) { 842 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 843 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 844 return slot; 845 free = slot; 846 /* NB: keep looking for a double slot */ 847 } 848 return free; 849 } 850 851 static struct ieee80211vap * 852 ath_vap_create(struct ieee80211com *ic, 853 const char name[IFNAMSIZ], int unit, int opmode, int flags, 854 const uint8_t bssid[IEEE80211_ADDR_LEN], 855 const uint8_t mac0[IEEE80211_ADDR_LEN]) 856 { 857 struct ath_softc *sc = ic->ic_ifp->if_softc; 858 struct ath_vap *avp; 859 struct ieee80211vap *vap; 860 uint8_t mac[IEEE80211_ADDR_LEN]; 861 int ic_opmode, needbeacon, error; 862 863 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap), 864 M_80211_VAP, M_WAITOK | M_ZERO); 865 needbeacon = 0; 866 IEEE80211_ADDR_COPY(mac, mac0); 867 868 ATH_LOCK(sc); 869 ic_opmode = opmode; /* default to opmode of new vap */ 870 switch (opmode) { 871 case IEEE80211_M_STA: 872 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 873 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 874 goto bad; 875 } 876 if (sc->sc_nvaps) { 877 /* 878 * With multiple vaps we must fall back 879 * to s/w beacon miss handling. 880 */ 881 flags |= IEEE80211_CLONE_NOBEACONS; 882 } 883 if (flags & IEEE80211_CLONE_NOBEACONS) { 884 /* 885 * Station mode w/o beacons are implemented w/ AP mode. 886 */ 887 ic_opmode = IEEE80211_M_HOSTAP; 888 } 889 break; 890 case IEEE80211_M_IBSS: 891 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 892 device_printf(sc->sc_dev, 893 "only 1 ibss vap supported\n"); 894 goto bad; 895 } 896 needbeacon = 1; 897 break; 898 case IEEE80211_M_AHDEMO: 899 #ifdef IEEE80211_SUPPORT_TDMA 900 if (flags & IEEE80211_CLONE_TDMA) { 901 if (sc->sc_nvaps != 0) { 902 device_printf(sc->sc_dev, 903 "only 1 tdma vap supported\n"); 904 goto bad; 905 } 906 needbeacon = 1; 907 flags |= IEEE80211_CLONE_NOBEACONS; 908 } 909 /* fall thru... */ 910 #endif 911 case IEEE80211_M_MONITOR: 912 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 913 /* 914 * Adopt existing mode. Adding a monitor or ahdemo 915 * vap to an existing configuration is of dubious 916 * value but should be ok. 917 */ 918 /* XXX not right for monitor mode */ 919 ic_opmode = ic->ic_opmode; 920 } 921 break; 922 case IEEE80211_M_HOSTAP: 923 case IEEE80211_M_MBSS: 924 needbeacon = 1; 925 break; 926 case IEEE80211_M_WDS: 927 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 928 device_printf(sc->sc_dev, 929 "wds not supported in sta mode\n"); 930 goto bad; 931 } 932 /* 933 * Silently remove any request for a unique 934 * bssid; WDS vap's always share the local 935 * mac address. 936 */ 937 flags &= ~IEEE80211_CLONE_BSSID; 938 if (sc->sc_nvaps == 0) 939 ic_opmode = IEEE80211_M_HOSTAP; 940 else 941 ic_opmode = ic->ic_opmode; 942 break; 943 default: 944 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 945 goto bad; 946 } 947 /* 948 * Check that a beacon buffer is available; the code below assumes it. 949 */ 950 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) { 951 device_printf(sc->sc_dev, "no beacon buffer available\n"); 952 goto bad; 953 } 954 955 /* STA, AHDEMO? */ 956 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 957 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 958 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 959 } 960 961 vap = &avp->av_vap; 962 /* XXX can't hold mutex across if_alloc */ 963 ATH_UNLOCK(sc); 964 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 965 bssid, mac); 966 ATH_LOCK(sc); 967 if (error != 0) { 968 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 969 __func__, error); 970 goto bad2; 971 } 972 973 /* h/w crypto support */ 974 vap->iv_key_alloc = ath_key_alloc; 975 vap->iv_key_delete = ath_key_delete; 976 vap->iv_key_set = ath_key_set; 977 vap->iv_key_update_begin = ath_key_update_begin; 978 vap->iv_key_update_end = ath_key_update_end; 979 980 /* override various methods */ 981 avp->av_recv_mgmt = vap->iv_recv_mgmt; 982 vap->iv_recv_mgmt = ath_recv_mgmt; 983 vap->iv_reset = ath_reset_vap; 984 vap->iv_update_beacon = ath_beacon_update; 985 avp->av_newstate = vap->iv_newstate; 986 vap->iv_newstate = ath_newstate; 987 avp->av_bmiss = vap->iv_bmiss; 988 vap->iv_bmiss = ath_bmiss_vap; 989 990 avp->av_bslot = -1; 991 if (needbeacon) { 992 /* 993 * Allocate beacon state and setup the q for buffered 994 * multicast frames. We know a beacon buffer is 995 * available because we checked above. 996 */ 997 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf); 998 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list); 999 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1000 /* 1001 * Assign the vap to a beacon xmit slot. As above 1002 * this cannot fail to find a free one. 1003 */ 1004 avp->av_bslot = assign_bslot(sc); 1005 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1006 ("beacon slot %u not empty", avp->av_bslot)); 1007 sc->sc_bslot[avp->av_bslot] = vap; 1008 sc->sc_nbcnvaps++; 1009 } 1010 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1011 /* 1012 * Multple vaps are to transmit beacons and we 1013 * have h/w support for TSF adjusting; enable 1014 * use of staggered beacons. 1015 */ 1016 sc->sc_stagbeacons = 1; 1017 } 1018 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1019 } 1020 1021 ic->ic_opmode = ic_opmode; 1022 if (opmode != IEEE80211_M_WDS) { 1023 sc->sc_nvaps++; 1024 if (opmode == IEEE80211_M_STA) 1025 sc->sc_nstavaps++; 1026 if (opmode == IEEE80211_M_MBSS) 1027 sc->sc_nmeshvaps++; 1028 } 1029 switch (ic_opmode) { 1030 case IEEE80211_M_IBSS: 1031 sc->sc_opmode = HAL_M_IBSS; 1032 break; 1033 case IEEE80211_M_STA: 1034 sc->sc_opmode = HAL_M_STA; 1035 break; 1036 case IEEE80211_M_AHDEMO: 1037 #ifdef IEEE80211_SUPPORT_TDMA 1038 if (vap->iv_caps & IEEE80211_C_TDMA) { 1039 sc->sc_tdma = 1; 1040 /* NB: disable tsf adjust */ 1041 sc->sc_stagbeacons = 0; 1042 } 1043 /* 1044 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1045 * just ap mode. 1046 */ 1047 /* fall thru... */ 1048 #endif 1049 case IEEE80211_M_HOSTAP: 1050 case IEEE80211_M_MBSS: 1051 sc->sc_opmode = HAL_M_HOSTAP; 1052 break; 1053 case IEEE80211_M_MONITOR: 1054 sc->sc_opmode = HAL_M_MONITOR; 1055 break; 1056 default: 1057 /* XXX should not happen */ 1058 break; 1059 } 1060 if (sc->sc_hastsfadd) { 1061 /* 1062 * Configure whether or not TSF adjust should be done. 1063 */ 1064 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1065 } 1066 if (flags & IEEE80211_CLONE_NOBEACONS) { 1067 /* 1068 * Enable s/w beacon miss handling. 1069 */ 1070 sc->sc_swbmiss = 1; 1071 } 1072 ATH_UNLOCK(sc); 1073 1074 /* complete setup */ 1075 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1076 return vap; 1077 bad2: 1078 reclaim_address(sc, mac); 1079 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1080 bad: 1081 free(avp, M_80211_VAP); 1082 ATH_UNLOCK(sc); 1083 return NULL; 1084 } 1085 1086 static void 1087 ath_vap_delete(struct ieee80211vap *vap) 1088 { 1089 struct ieee80211com *ic = vap->iv_ic; 1090 struct ifnet *ifp = ic->ic_ifp; 1091 struct ath_softc *sc = ifp->if_softc; 1092 struct ath_hal *ah = sc->sc_ah; 1093 struct ath_vap *avp = ATH_VAP(vap); 1094 1095 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1096 /* 1097 * Quiesce the hardware while we remove the vap. In 1098 * particular we need to reclaim all references to 1099 * the vap state by any frames pending on the tx queues. 1100 */ 1101 ath_hal_intrset(ah, 0); /* disable interrupts */ 1102 ath_draintxq(sc); /* stop xmit side */ 1103 ath_stoprecv(sc); /* stop recv side */ 1104 } 1105 1106 ieee80211_vap_detach(vap); 1107 ATH_LOCK(sc); 1108 /* 1109 * Reclaim beacon state. Note this must be done before 1110 * the vap instance is reclaimed as we may have a reference 1111 * to it in the buffer for the beacon frame. 1112 */ 1113 if (avp->av_bcbuf != NULL) { 1114 if (avp->av_bslot != -1) { 1115 sc->sc_bslot[avp->av_bslot] = NULL; 1116 sc->sc_nbcnvaps--; 1117 } 1118 ath_beacon_return(sc, avp->av_bcbuf); 1119 avp->av_bcbuf = NULL; 1120 if (sc->sc_nbcnvaps == 0) { 1121 sc->sc_stagbeacons = 0; 1122 if (sc->sc_hastsfadd) 1123 ath_hal_settsfadjust(sc->sc_ah, 0); 1124 } 1125 /* 1126 * Reclaim any pending mcast frames for the vap. 1127 */ 1128 ath_tx_draintxq(sc, &avp->av_mcastq); 1129 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq); 1130 } 1131 /* 1132 * Update bookkeeping. 1133 */ 1134 if (vap->iv_opmode == IEEE80211_M_STA) { 1135 sc->sc_nstavaps--; 1136 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1137 sc->sc_swbmiss = 0; 1138 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1139 vap->iv_opmode == IEEE80211_M_MBSS) { 1140 reclaim_address(sc, vap->iv_myaddr); 1141 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1142 if (vap->iv_opmode == IEEE80211_M_MBSS) 1143 sc->sc_nmeshvaps--; 1144 } 1145 if (vap->iv_opmode != IEEE80211_M_WDS) 1146 sc->sc_nvaps--; 1147 #ifdef IEEE80211_SUPPORT_TDMA 1148 /* TDMA operation ceases when the last vap is destroyed */ 1149 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1150 sc->sc_tdma = 0; 1151 sc->sc_swbmiss = 0; 1152 } 1153 #endif 1154 ATH_UNLOCK(sc); 1155 free(avp, M_80211_VAP); 1156 1157 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1158 /* 1159 * Restart rx+tx machines if still running (RUNNING will 1160 * be reset if we just destroyed the last vap). 1161 */ 1162 if (ath_startrecv(sc) != 0) 1163 if_printf(ifp, "%s: unable to restart recv logic\n", 1164 __func__); 1165 if (sc->sc_beacons) { /* restart beacons */ 1166 #ifdef IEEE80211_SUPPORT_TDMA 1167 if (sc->sc_tdma) 1168 ath_tdma_config(sc, NULL); 1169 else 1170 #endif 1171 ath_beacon_config(sc, NULL); 1172 } 1173 ath_hal_intrset(ah, sc->sc_imask); 1174 } 1175 } 1176 1177 void 1178 ath_suspend(struct ath_softc *sc) 1179 { 1180 struct ifnet *ifp = sc->sc_ifp; 1181 struct ieee80211com *ic = ifp->if_l2com; 1182 1183 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1184 __func__, ifp->if_flags); 1185 1186 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1187 if (ic->ic_opmode == IEEE80211_M_STA) 1188 ath_stop(ifp); 1189 else 1190 ieee80211_suspend_all(ic); 1191 /* 1192 * NB: don't worry about putting the chip in low power 1193 * mode; pci will power off our socket on suspend and 1194 * cardbus detaches the device. 1195 */ 1196 } 1197 1198 /* 1199 * Reset the key cache since some parts do not reset the 1200 * contents on resume. First we clear all entries, then 1201 * re-load keys that the 802.11 layer assumes are setup 1202 * in h/w. 1203 */ 1204 static void 1205 ath_reset_keycache(struct ath_softc *sc) 1206 { 1207 struct ifnet *ifp = sc->sc_ifp; 1208 struct ieee80211com *ic = ifp->if_l2com; 1209 struct ath_hal *ah = sc->sc_ah; 1210 int i; 1211 1212 for (i = 0; i < sc->sc_keymax; i++) 1213 ath_hal_keyreset(ah, i); 1214 ieee80211_crypto_reload_keys(ic); 1215 } 1216 1217 void 1218 ath_resume(struct ath_softc *sc) 1219 { 1220 struct ifnet *ifp = sc->sc_ifp; 1221 struct ieee80211com *ic = ifp->if_l2com; 1222 struct ath_hal *ah = sc->sc_ah; 1223 HAL_STATUS status; 1224 1225 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1226 __func__, ifp->if_flags); 1227 1228 /* 1229 * Must reset the chip before we reload the 1230 * keycache as we were powered down on suspend. 1231 */ 1232 ath_hal_reset(ah, sc->sc_opmode, 1233 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1234 AH_FALSE, &status); 1235 ath_reset_keycache(sc); 1236 if (sc->sc_resume_up) { 1237 if (ic->ic_opmode == IEEE80211_M_STA) { 1238 ath_init(sc); 1239 /* 1240 * Program the beacon registers using the last rx'd 1241 * beacon frame and enable sync on the next beacon 1242 * we see. This should handle the case where we 1243 * wakeup and find the same AP and also the case where 1244 * we wakeup and need to roam. For the latter we 1245 * should get bmiss events that trigger a roam. 1246 */ 1247 ath_beacon_config(sc, NULL); 1248 sc->sc_syncbeacon = 1; 1249 } else 1250 ieee80211_resume_all(ic); 1251 } 1252 if (sc->sc_softled) { 1253 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 1254 HAL_GPIO_MUX_MAC_NETWORK_LED); 1255 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 1256 } 1257 } 1258 1259 void 1260 ath_shutdown(struct ath_softc *sc) 1261 { 1262 struct ifnet *ifp = sc->sc_ifp; 1263 1264 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1265 __func__, ifp->if_flags); 1266 1267 ath_stop(ifp); 1268 /* NB: no point powering down chip as we're about to reboot */ 1269 } 1270 1271 /* 1272 * Interrupt handler. Most of the actual processing is deferred. 1273 */ 1274 void 1275 ath_intr(void *arg) 1276 { 1277 struct ath_softc *sc = arg; 1278 struct ifnet *ifp = sc->sc_ifp; 1279 struct ath_hal *ah = sc->sc_ah; 1280 HAL_INT status; 1281 1282 if (sc->sc_invalid) { 1283 /* 1284 * The hardware is not ready/present, don't touch anything. 1285 * Note this can happen early on if the IRQ is shared. 1286 */ 1287 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1288 return; 1289 } 1290 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 1291 return; 1292 if ((ifp->if_flags & IFF_UP) == 0 || 1293 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1294 HAL_INT status; 1295 1296 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1297 __func__, ifp->if_flags); 1298 ath_hal_getisr(ah, &status); /* clear ISR */ 1299 ath_hal_intrset(ah, 0); /* disable further intr's */ 1300 return; 1301 } 1302 /* 1303 * Figure out the reason(s) for the interrupt. Note 1304 * that the hal returns a pseudo-ISR that may include 1305 * bits we haven't explicitly enabled so we mask the 1306 * value to insure we only process bits we requested. 1307 */ 1308 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 1309 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 1310 status &= sc->sc_imask; /* discard unasked for bits */ 1311 if (status & HAL_INT_FATAL) { 1312 sc->sc_stats.ast_hardware++; 1313 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1314 ath_fatal_proc(sc, 0); 1315 } else { 1316 if (status & HAL_INT_SWBA) { 1317 /* 1318 * Software beacon alert--time to send a beacon. 1319 * Handle beacon transmission directly; deferring 1320 * this is too slow to meet timing constraints 1321 * under load. 1322 */ 1323 #ifdef IEEE80211_SUPPORT_TDMA 1324 if (sc->sc_tdma) { 1325 if (sc->sc_tdmaswba == 0) { 1326 struct ieee80211com *ic = ifp->if_l2com; 1327 struct ieee80211vap *vap = 1328 TAILQ_FIRST(&ic->ic_vaps); 1329 ath_tdma_beacon_send(sc, vap); 1330 sc->sc_tdmaswba = 1331 vap->iv_tdma->tdma_bintval; 1332 } else 1333 sc->sc_tdmaswba--; 1334 } else 1335 #endif 1336 { 1337 ath_beacon_proc(sc, 0); 1338 #ifdef IEEE80211_SUPPORT_SUPERG 1339 /* 1340 * Schedule the rx taskq in case there's no 1341 * traffic so any frames held on the staging 1342 * queue are aged and potentially flushed. 1343 */ 1344 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1345 #endif 1346 } 1347 } 1348 if (status & HAL_INT_RXEOL) { 1349 /* 1350 * NB: the hardware should re-read the link when 1351 * RXE bit is written, but it doesn't work at 1352 * least on older hardware revs. 1353 */ 1354 sc->sc_stats.ast_rxeol++; 1355 sc->sc_rxlink = NULL; 1356 } 1357 if (status & HAL_INT_TXURN) { 1358 sc->sc_stats.ast_txurn++; 1359 /* bump tx trigger level */ 1360 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1361 } 1362 if (status & HAL_INT_RX) 1363 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1364 if (status & HAL_INT_TX) 1365 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1366 if (status & HAL_INT_BMISS) { 1367 sc->sc_stats.ast_bmiss++; 1368 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1369 } 1370 if (status & HAL_INT_MIB) { 1371 sc->sc_stats.ast_mib++; 1372 /* 1373 * Disable interrupts until we service the MIB 1374 * interrupt; otherwise it will continue to fire. 1375 */ 1376 ath_hal_intrset(ah, 0); 1377 /* 1378 * Let the hal handle the event. We assume it will 1379 * clear whatever condition caused the interrupt. 1380 */ 1381 ath_hal_mibevent(ah, &sc->sc_halstats); 1382 ath_hal_intrset(ah, sc->sc_imask); 1383 } 1384 if (status & HAL_INT_RXORN) { 1385 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1386 sc->sc_stats.ast_rxorn++; 1387 } 1388 } 1389 } 1390 1391 static void 1392 ath_fatal_proc(void *arg, int pending) 1393 { 1394 struct ath_softc *sc = arg; 1395 struct ifnet *ifp = sc->sc_ifp; 1396 u_int32_t *state; 1397 u_int32_t len; 1398 void *sp; 1399 1400 if_printf(ifp, "hardware error; resetting\n"); 1401 /* 1402 * Fatal errors are unrecoverable. Typically these 1403 * are caused by DMA errors. Collect h/w state from 1404 * the hal so we can diagnose what's going on. 1405 */ 1406 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1407 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1408 state = sp; 1409 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1410 state[0], state[1] , state[2], state[3], 1411 state[4], state[5]); 1412 } 1413 ath_reset(ifp); 1414 } 1415 1416 static void 1417 ath_bmiss_vap(struct ieee80211vap *vap) 1418 { 1419 /* 1420 * Workaround phantom bmiss interrupts by sanity-checking 1421 * the time of our last rx'd frame. If it is within the 1422 * beacon miss interval then ignore the interrupt. If it's 1423 * truly a bmiss we'll get another interrupt soon and that'll 1424 * be dispatched up for processing. Note this applies only 1425 * for h/w beacon miss events. 1426 */ 1427 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1428 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1429 struct ath_softc *sc = ifp->if_softc; 1430 u_int64_t lastrx = sc->sc_lastrx; 1431 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1432 u_int bmisstimeout = 1433 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1434 1435 DPRINTF(sc, ATH_DEBUG_BEACON, 1436 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1437 __func__, (unsigned long long) tsf, 1438 (unsigned long long)(tsf - lastrx), 1439 (unsigned long long) lastrx, bmisstimeout); 1440 1441 if (tsf - lastrx <= bmisstimeout) { 1442 sc->sc_stats.ast_bmiss_phantom++; 1443 return; 1444 } 1445 } 1446 ATH_VAP(vap)->av_bmiss(vap); 1447 } 1448 1449 static int 1450 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1451 { 1452 uint32_t rsize; 1453 void *sp; 1454 1455 if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(&mask), &sp, &rsize)) 1456 return 0; 1457 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1458 *hangs = *(uint32_t *)sp; 1459 return 1; 1460 } 1461 1462 static void 1463 ath_bmiss_proc(void *arg, int pending) 1464 { 1465 struct ath_softc *sc = arg; 1466 struct ifnet *ifp = sc->sc_ifp; 1467 uint32_t hangs; 1468 1469 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1470 1471 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1472 if_printf(ifp, "bb hang detected (0x%x), reseting\n", hangs); 1473 ath_reset(ifp); 1474 } else 1475 ieee80211_beacon_miss(ifp->if_l2com); 1476 } 1477 1478 /* 1479 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1480 * calcs together with WME. If necessary disable the crypto 1481 * hardware and mark the 802.11 state so keys will be setup 1482 * with the MIC work done in software. 1483 */ 1484 static void 1485 ath_settkipmic(struct ath_softc *sc) 1486 { 1487 struct ifnet *ifp = sc->sc_ifp; 1488 struct ieee80211com *ic = ifp->if_l2com; 1489 1490 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1491 if (ic->ic_flags & IEEE80211_F_WME) { 1492 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1493 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1494 } else { 1495 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1496 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1497 } 1498 } 1499 } 1500 1501 static void 1502 ath_init(void *arg) 1503 { 1504 struct ath_softc *sc = (struct ath_softc *) arg; 1505 struct ifnet *ifp = sc->sc_ifp; 1506 struct ieee80211com *ic = ifp->if_l2com; 1507 struct ath_hal *ah = sc->sc_ah; 1508 HAL_STATUS status; 1509 1510 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1511 __func__, ifp->if_flags); 1512 1513 ATH_LOCK(sc); 1514 /* 1515 * Stop anything previously setup. This is safe 1516 * whether this is the first time through or not. 1517 */ 1518 ath_stop_locked(ifp); 1519 1520 /* 1521 * The basic interface to setting the hardware in a good 1522 * state is ``reset''. On return the hardware is known to 1523 * be powered up and with interrupts disabled. This must 1524 * be followed by initialization of the appropriate bits 1525 * and then setup of the interrupt mask. 1526 */ 1527 ath_settkipmic(sc); 1528 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 1529 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1530 status); 1531 ATH_UNLOCK(sc); 1532 return; 1533 } 1534 ath_chan_change(sc, ic->ic_curchan); 1535 1536 /* 1537 * Likewise this is set during reset so update 1538 * state cached in the driver. 1539 */ 1540 sc->sc_diversity = ath_hal_getdiversity(ah); 1541 sc->sc_lastlongcal = 0; 1542 sc->sc_resetcal = 1; 1543 sc->sc_lastcalreset = 0; 1544 1545 /* 1546 * Setup the hardware after reset: the key cache 1547 * is filled as needed and the receive engine is 1548 * set going. Frame transmit is handled entirely 1549 * in the frame output path; there's nothing to do 1550 * here except setup the interrupt mask. 1551 */ 1552 if (ath_startrecv(sc) != 0) { 1553 if_printf(ifp, "unable to start recv logic\n"); 1554 ATH_UNLOCK(sc); 1555 return; 1556 } 1557 1558 /* 1559 * Enable interrupts. 1560 */ 1561 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1562 | HAL_INT_RXEOL | HAL_INT_RXORN 1563 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1564 /* 1565 * Enable MIB interrupts when there are hardware phy counters. 1566 * Note we only do this (at the moment) for station mode. 1567 */ 1568 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1569 sc->sc_imask |= HAL_INT_MIB; 1570 1571 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1572 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 1573 ath_hal_intrset(ah, sc->sc_imask); 1574 1575 ATH_UNLOCK(sc); 1576 1577 #ifdef ATH_TX99_DIAG 1578 if (sc->sc_tx99 != NULL) 1579 sc->sc_tx99->start(sc->sc_tx99); 1580 else 1581 #endif 1582 ieee80211_start_all(ic); /* start all vap's */ 1583 } 1584 1585 static void 1586 ath_stop_locked(struct ifnet *ifp) 1587 { 1588 struct ath_softc *sc = ifp->if_softc; 1589 struct ath_hal *ah = sc->sc_ah; 1590 1591 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1592 __func__, sc->sc_invalid, ifp->if_flags); 1593 1594 ATH_LOCK_ASSERT(sc); 1595 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1596 /* 1597 * Shutdown the hardware and driver: 1598 * reset 802.11 state machine 1599 * turn off timers 1600 * disable interrupts 1601 * turn off the radio 1602 * clear transmit machinery 1603 * clear receive machinery 1604 * drain and release tx queues 1605 * reclaim beacon resources 1606 * power down hardware 1607 * 1608 * Note that some of this work is not possible if the 1609 * hardware is gone (invalid). 1610 */ 1611 #ifdef ATH_TX99_DIAG 1612 if (sc->sc_tx99 != NULL) 1613 sc->sc_tx99->stop(sc->sc_tx99); 1614 #endif 1615 callout_stop(&sc->sc_wd_ch); 1616 sc->sc_wd_timer = 0; 1617 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1618 if (!sc->sc_invalid) { 1619 if (sc->sc_softled) { 1620 callout_stop(&sc->sc_ledtimer); 1621 ath_hal_gpioset(ah, sc->sc_ledpin, 1622 !sc->sc_ledon); 1623 sc->sc_blinking = 0; 1624 } 1625 ath_hal_intrset(ah, 0); 1626 } 1627 ath_draintxq(sc); 1628 if (!sc->sc_invalid) { 1629 ath_stoprecv(sc); 1630 ath_hal_phydisable(ah); 1631 } else 1632 sc->sc_rxlink = NULL; 1633 ath_beacon_free(sc); /* XXX not needed */ 1634 } 1635 } 1636 1637 static void 1638 ath_stop(struct ifnet *ifp) 1639 { 1640 struct ath_softc *sc = ifp->if_softc; 1641 1642 ATH_LOCK(sc); 1643 ath_stop_locked(ifp); 1644 ATH_UNLOCK(sc); 1645 } 1646 1647 /* 1648 * Reset the hardware w/o losing operational state. This is 1649 * basically a more efficient way of doing ath_stop, ath_init, 1650 * followed by state transitions to the current 802.11 1651 * operational state. Used to recover from various errors and 1652 * to reset or reload hardware state. 1653 */ 1654 static int 1655 ath_reset(struct ifnet *ifp) 1656 { 1657 struct ath_softc *sc = ifp->if_softc; 1658 struct ieee80211com *ic = ifp->if_l2com; 1659 struct ath_hal *ah = sc->sc_ah; 1660 HAL_STATUS status; 1661 1662 ath_hal_intrset(ah, 0); /* disable interrupts */ 1663 ath_draintxq(sc); /* stop xmit side */ 1664 ath_stoprecv(sc); /* stop recv side */ 1665 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1666 /* NB: indicate channel change so we do a full reset */ 1667 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 1668 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1669 __func__, status); 1670 sc->sc_diversity = ath_hal_getdiversity(ah); 1671 if (ath_startrecv(sc) != 0) /* restart recv */ 1672 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1673 /* 1674 * We may be doing a reset in response to an ioctl 1675 * that changes the channel so update any state that 1676 * might change as a result. 1677 */ 1678 ath_chan_change(sc, ic->ic_curchan); 1679 if (sc->sc_beacons) { /* restart beacons */ 1680 #ifdef IEEE80211_SUPPORT_TDMA 1681 if (sc->sc_tdma) 1682 ath_tdma_config(sc, NULL); 1683 else 1684 #endif 1685 ath_beacon_config(sc, NULL); 1686 } 1687 ath_hal_intrset(ah, sc->sc_imask); 1688 1689 ath_start(ifp); /* restart xmit */ 1690 return 0; 1691 } 1692 1693 static int 1694 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 1695 { 1696 struct ieee80211com *ic = vap->iv_ic; 1697 struct ifnet *ifp = ic->ic_ifp; 1698 struct ath_softc *sc = ifp->if_softc; 1699 struct ath_hal *ah = sc->sc_ah; 1700 1701 switch (cmd) { 1702 case IEEE80211_IOC_TXPOWER: 1703 /* 1704 * If per-packet TPC is enabled, then we have nothing 1705 * to do; otherwise we need to force the global limit. 1706 * All this can happen directly; no need to reset. 1707 */ 1708 if (!ath_hal_gettpc(ah)) 1709 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 1710 return 0; 1711 } 1712 return ath_reset(ifp); 1713 } 1714 1715 static struct ath_buf * 1716 _ath_getbuf_locked(struct ath_softc *sc) 1717 { 1718 struct ath_buf *bf; 1719 1720 ATH_TXBUF_LOCK_ASSERT(sc); 1721 1722 bf = STAILQ_FIRST(&sc->sc_txbuf); 1723 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) 1724 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1725 else 1726 bf = NULL; 1727 if (bf == NULL) { 1728 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 1729 STAILQ_FIRST(&sc->sc_txbuf) == NULL ? 1730 "out of xmit buffers" : "xmit buffer busy"); 1731 } 1732 return bf; 1733 } 1734 1735 static struct ath_buf * 1736 ath_getbuf(struct ath_softc *sc) 1737 { 1738 struct ath_buf *bf; 1739 1740 ATH_TXBUF_LOCK(sc); 1741 bf = _ath_getbuf_locked(sc); 1742 if (bf == NULL) { 1743 struct ifnet *ifp = sc->sc_ifp; 1744 1745 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 1746 sc->sc_stats.ast_tx_qstop++; 1747 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1748 } 1749 ATH_TXBUF_UNLOCK(sc); 1750 return bf; 1751 } 1752 1753 /* 1754 * Cleanup driver resources when we run out of buffers 1755 * while processing fragments; return the tx buffers 1756 * allocated and drop node references. 1757 */ 1758 static void 1759 ath_txfrag_cleanup(struct ath_softc *sc, 1760 ath_bufhead *frags, struct ieee80211_node *ni) 1761 { 1762 struct ath_buf *bf, *next; 1763 1764 ATH_TXBUF_LOCK_ASSERT(sc); 1765 1766 STAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 1767 /* NB: bf assumed clean */ 1768 STAILQ_REMOVE_HEAD(frags, bf_list); 1769 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1770 ieee80211_node_decref(ni); 1771 } 1772 } 1773 1774 /* 1775 * Setup xmit of a fragmented frame. Allocate a buffer 1776 * for each frag and bump the node reference count to 1777 * reflect the held reference to be setup by ath_tx_start. 1778 */ 1779 static int 1780 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1781 struct mbuf *m0, struct ieee80211_node *ni) 1782 { 1783 struct mbuf *m; 1784 struct ath_buf *bf; 1785 1786 ATH_TXBUF_LOCK(sc); 1787 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1788 bf = _ath_getbuf_locked(sc); 1789 if (bf == NULL) { /* out of buffers, cleanup */ 1790 ath_txfrag_cleanup(sc, frags, ni); 1791 break; 1792 } 1793 ieee80211_node_incref(ni); 1794 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1795 } 1796 ATH_TXBUF_UNLOCK(sc); 1797 1798 return !STAILQ_EMPTY(frags); 1799 } 1800 1801 static void 1802 ath_start(struct ifnet *ifp) 1803 { 1804 struct ath_softc *sc = ifp->if_softc; 1805 struct ieee80211_node *ni; 1806 struct ath_buf *bf; 1807 struct mbuf *m, *next; 1808 ath_bufhead frags; 1809 1810 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 1811 return; 1812 for (;;) { 1813 /* 1814 * Grab a TX buffer and associated resources. 1815 */ 1816 bf = ath_getbuf(sc); 1817 if (bf == NULL) 1818 break; 1819 1820 IFQ_DEQUEUE(&ifp->if_snd, m); 1821 if (m == NULL) { 1822 ATH_TXBUF_LOCK(sc); 1823 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1824 ATH_TXBUF_UNLOCK(sc); 1825 break; 1826 } 1827 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1828 /* 1829 * Check for fragmentation. If this frame 1830 * has been broken up verify we have enough 1831 * buffers to send all the fragments so all 1832 * go out or none... 1833 */ 1834 STAILQ_INIT(&frags); 1835 if ((m->m_flags & M_FRAG) && 1836 !ath_txfrag_setup(sc, &frags, m, ni)) { 1837 DPRINTF(sc, ATH_DEBUG_XMIT, 1838 "%s: out of txfrag buffers\n", __func__); 1839 sc->sc_stats.ast_tx_nofrag++; 1840 ifp->if_oerrors++; 1841 ath_freetx(m); 1842 goto bad; 1843 } 1844 ifp->if_opackets++; 1845 nextfrag: 1846 /* 1847 * Pass the frame to the h/w for transmission. 1848 * Fragmented frames have each frag chained together 1849 * with m_nextpkt. We know there are sufficient ath_buf's 1850 * to send all the frags because of work done by 1851 * ath_txfrag_setup. We leave m_nextpkt set while 1852 * calling ath_tx_start so it can use it to extend the 1853 * the tx duration to cover the subsequent frag and 1854 * so it can reclaim all the mbufs in case of an error; 1855 * ath_tx_start clears m_nextpkt once it commits to 1856 * handing the frame to the hardware. 1857 */ 1858 next = m->m_nextpkt; 1859 if (ath_tx_start(sc, ni, bf, m)) { 1860 bad: 1861 ifp->if_oerrors++; 1862 reclaim: 1863 bf->bf_m = NULL; 1864 bf->bf_node = NULL; 1865 ATH_TXBUF_LOCK(sc); 1866 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1867 ath_txfrag_cleanup(sc, &frags, ni); 1868 ATH_TXBUF_UNLOCK(sc); 1869 if (ni != NULL) 1870 ieee80211_free_node(ni); 1871 continue; 1872 } 1873 if (next != NULL) { 1874 /* 1875 * Beware of state changing between frags. 1876 * XXX check sta power-save state? 1877 */ 1878 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 1879 DPRINTF(sc, ATH_DEBUG_XMIT, 1880 "%s: flush fragmented packet, state %s\n", 1881 __func__, 1882 ieee80211_state_name[ni->ni_vap->iv_state]); 1883 ath_freetx(next); 1884 goto reclaim; 1885 } 1886 m = next; 1887 bf = STAILQ_FIRST(&frags); 1888 KASSERT(bf != NULL, ("no buf for txfrag")); 1889 STAILQ_REMOVE_HEAD(&frags, bf_list); 1890 goto nextfrag; 1891 } 1892 1893 sc->sc_wd_timer = 5; 1894 } 1895 } 1896 1897 static int 1898 ath_media_change(struct ifnet *ifp) 1899 { 1900 int error = ieee80211_media_change(ifp); 1901 /* NB: only the fixed rate can change and that doesn't need a reset */ 1902 return (error == ENETRESET ? 0 : error); 1903 } 1904 1905 #ifdef ATH_DEBUG 1906 static void 1907 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 1908 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1909 { 1910 static const char *ciphers[] = { 1911 "WEP", 1912 "AES-OCB", 1913 "AES-CCM", 1914 "CKIP", 1915 "TKIP", 1916 "CLR", 1917 }; 1918 int i, n; 1919 1920 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1921 for (i = 0, n = hk->kv_len; i < n; i++) 1922 printf("%02x", hk->kv_val[i]); 1923 printf(" mac %s", ether_sprintf(mac)); 1924 if (hk->kv_type == HAL_CIPHER_TKIP) { 1925 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 1926 for (i = 0; i < sizeof(hk->kv_mic); i++) 1927 printf("%02x", hk->kv_mic[i]); 1928 if (!sc->sc_splitmic) { 1929 printf(" txmic "); 1930 for (i = 0; i < sizeof(hk->kv_txmic); i++) 1931 printf("%02x", hk->kv_txmic[i]); 1932 } 1933 } 1934 printf("\n"); 1935 } 1936 #endif 1937 1938 /* 1939 * Set a TKIP key into the hardware. This handles the 1940 * potential distribution of key state to multiple key 1941 * cache slots for TKIP. 1942 */ 1943 static int 1944 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1945 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1946 { 1947 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1948 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1949 struct ath_hal *ah = sc->sc_ah; 1950 1951 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1952 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1953 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1954 if (sc->sc_splitmic) { 1955 /* 1956 * TX key goes at first index, RX key at the rx index. 1957 * The hal handles the MIC keys at index+64. 1958 */ 1959 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1960 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1961 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1962 return 0; 1963 1964 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1965 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1966 /* XXX delete tx key on failure? */ 1967 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1968 } else { 1969 /* 1970 * Room for both TX+RX MIC keys in one key cache 1971 * slot, just set key at the first index; the hal 1972 * will handle the rest. 1973 */ 1974 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1975 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1976 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1977 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1978 } 1979 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 1980 if (sc->sc_splitmic) { 1981 /* 1982 * NB: must pass MIC key in expected location when 1983 * the keycache only holds one MIC key per entry. 1984 */ 1985 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 1986 } else 1987 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1988 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1989 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1990 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 1991 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1992 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1993 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1994 } 1995 return 0; 1996 #undef IEEE80211_KEY_XR 1997 } 1998 1999 /* 2000 * Set a net80211 key into the hardware. This handles the 2001 * potential distribution of key state to multiple key 2002 * cache slots for TKIP with hardware MIC support. 2003 */ 2004 static int 2005 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 2006 struct ieee80211_node *bss) 2007 { 2008 #define N(a) (sizeof(a)/sizeof(a[0])) 2009 static const u_int8_t ciphermap[] = { 2010 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 2011 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 2012 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 2013 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 2014 (u_int8_t) -1, /* 4 is not allocated */ 2015 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 2016 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 2017 }; 2018 struct ath_hal *ah = sc->sc_ah; 2019 const struct ieee80211_cipher *cip = k->wk_cipher; 2020 u_int8_t gmac[IEEE80211_ADDR_LEN]; 2021 const u_int8_t *mac; 2022 HAL_KEYVAL hk; 2023 2024 memset(&hk, 0, sizeof(hk)); 2025 /* 2026 * Software crypto uses a "clear key" so non-crypto 2027 * state kept in the key cache are maintained and 2028 * so that rx frames have an entry to match. 2029 */ 2030 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 2031 KASSERT(cip->ic_cipher < N(ciphermap), 2032 ("invalid cipher type %u", cip->ic_cipher)); 2033 hk.kv_type = ciphermap[cip->ic_cipher]; 2034 hk.kv_len = k->wk_keylen; 2035 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 2036 } else 2037 hk.kv_type = HAL_CIPHER_CLR; 2038 2039 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 2040 /* 2041 * Group keys on hardware that supports multicast frame 2042 * key search use a mac that is the sender's address with 2043 * the high bit set instead of the app-specified address. 2044 */ 2045 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 2046 gmac[0] |= 0x80; 2047 mac = gmac; 2048 } else 2049 mac = k->wk_macaddr; 2050 2051 if (hk.kv_type == HAL_CIPHER_TKIP && 2052 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2053 return ath_keyset_tkip(sc, k, &hk, mac); 2054 } else { 2055 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 2056 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 2057 } 2058 #undef N 2059 } 2060 2061 /* 2062 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2063 * each key, one for decrypt/encrypt and the other for the MIC. 2064 */ 2065 static u_int16_t 2066 key_alloc_2pair(struct ath_softc *sc, 2067 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2068 { 2069 #define N(a) (sizeof(a)/sizeof(a[0])) 2070 u_int i, keyix; 2071 2072 KASSERT(sc->sc_splitmic, ("key cache !split")); 2073 /* XXX could optimize */ 2074 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2075 u_int8_t b = sc->sc_keymap[i]; 2076 if (b != 0xff) { 2077 /* 2078 * One or more slots in this byte are free. 2079 */ 2080 keyix = i*NBBY; 2081 while (b & 1) { 2082 again: 2083 keyix++; 2084 b >>= 1; 2085 } 2086 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 2087 if (isset(sc->sc_keymap, keyix+32) || 2088 isset(sc->sc_keymap, keyix+64) || 2089 isset(sc->sc_keymap, keyix+32+64)) { 2090 /* full pair unavailable */ 2091 /* XXX statistic */ 2092 if (keyix == (i+1)*NBBY) { 2093 /* no slots were appropriate, advance */ 2094 continue; 2095 } 2096 goto again; 2097 } 2098 setbit(sc->sc_keymap, keyix); 2099 setbit(sc->sc_keymap, keyix+64); 2100 setbit(sc->sc_keymap, keyix+32); 2101 setbit(sc->sc_keymap, keyix+32+64); 2102 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2103 "%s: key pair %u,%u %u,%u\n", 2104 __func__, keyix, keyix+64, 2105 keyix+32, keyix+32+64); 2106 *txkeyix = keyix; 2107 *rxkeyix = keyix+32; 2108 return 1; 2109 } 2110 } 2111 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2112 return 0; 2113 #undef N 2114 } 2115 2116 /* 2117 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2118 * each key, one for decrypt/encrypt and the other for the MIC. 2119 */ 2120 static u_int16_t 2121 key_alloc_pair(struct ath_softc *sc, 2122 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2123 { 2124 #define N(a) (sizeof(a)/sizeof(a[0])) 2125 u_int i, keyix; 2126 2127 KASSERT(!sc->sc_splitmic, ("key cache split")); 2128 /* XXX could optimize */ 2129 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2130 u_int8_t b = sc->sc_keymap[i]; 2131 if (b != 0xff) { 2132 /* 2133 * One or more slots in this byte are free. 2134 */ 2135 keyix = i*NBBY; 2136 while (b & 1) { 2137 again: 2138 keyix++; 2139 b >>= 1; 2140 } 2141 if (isset(sc->sc_keymap, keyix+64)) { 2142 /* full pair unavailable */ 2143 /* XXX statistic */ 2144 if (keyix == (i+1)*NBBY) { 2145 /* no slots were appropriate, advance */ 2146 continue; 2147 } 2148 goto again; 2149 } 2150 setbit(sc->sc_keymap, keyix); 2151 setbit(sc->sc_keymap, keyix+64); 2152 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2153 "%s: key pair %u,%u\n", 2154 __func__, keyix, keyix+64); 2155 *txkeyix = *rxkeyix = keyix; 2156 return 1; 2157 } 2158 } 2159 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2160 return 0; 2161 #undef N 2162 } 2163 2164 /* 2165 * Allocate a single key cache slot. 2166 */ 2167 static int 2168 key_alloc_single(struct ath_softc *sc, 2169 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2170 { 2171 #define N(a) (sizeof(a)/sizeof(a[0])) 2172 u_int i, keyix; 2173 2174 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 2175 for (i = 0; i < N(sc->sc_keymap); i++) { 2176 u_int8_t b = sc->sc_keymap[i]; 2177 if (b != 0xff) { 2178 /* 2179 * One or more slots are free. 2180 */ 2181 keyix = i*NBBY; 2182 while (b & 1) 2183 keyix++, b >>= 1; 2184 setbit(sc->sc_keymap, keyix); 2185 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 2186 __func__, keyix); 2187 *txkeyix = *rxkeyix = keyix; 2188 return 1; 2189 } 2190 } 2191 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 2192 return 0; 2193 #undef N 2194 } 2195 2196 /* 2197 * Allocate one or more key cache slots for a uniacst key. The 2198 * key itself is needed only to identify the cipher. For hardware 2199 * TKIP with split cipher+MIC keys we allocate two key cache slot 2200 * pairs so that we can setup separate TX and RX MIC keys. Note 2201 * that the MIC key for a TKIP key at slot i is assumed by the 2202 * hardware to be at slot i+64. This limits TKIP keys to the first 2203 * 64 entries. 2204 */ 2205 static int 2206 ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2207 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2208 { 2209 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2210 2211 /* 2212 * Group key allocation must be handled specially for 2213 * parts that do not support multicast key cache search 2214 * functionality. For those parts the key id must match 2215 * the h/w key index so lookups find the right key. On 2216 * parts w/ the key search facility we install the sender's 2217 * mac address (with the high bit set) and let the hardware 2218 * find the key w/o using the key id. This is preferred as 2219 * it permits us to support multiple users for adhoc and/or 2220 * multi-station operation. 2221 */ 2222 if (k->wk_keyix != IEEE80211_KEYIX_NONE || /* global key */ 2223 ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey)) { 2224 if (!(&vap->iv_nw_keys[0] <= k && 2225 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2226 /* should not happen */ 2227 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2228 "%s: bogus group key\n", __func__); 2229 return 0; 2230 } 2231 /* 2232 * XXX we pre-allocate the global keys so 2233 * have no way to check if they've already been allocated. 2234 */ 2235 *keyix = *rxkeyix = k - vap->iv_nw_keys; 2236 return 1; 2237 } 2238 2239 /* 2240 * We allocate two pair for TKIP when using the h/w to do 2241 * the MIC. For everything else, including software crypto, 2242 * we allocate a single entry. Note that s/w crypto requires 2243 * a pass-through slot on the 5211 and 5212. The 5210 does 2244 * not support pass-through cache entries and we map all 2245 * those requests to slot 0. 2246 */ 2247 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2248 return key_alloc_single(sc, keyix, rxkeyix); 2249 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 2250 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2251 if (sc->sc_splitmic) 2252 return key_alloc_2pair(sc, keyix, rxkeyix); 2253 else 2254 return key_alloc_pair(sc, keyix, rxkeyix); 2255 } else { 2256 return key_alloc_single(sc, keyix, rxkeyix); 2257 } 2258 } 2259 2260 /* 2261 * Delete an entry in the key cache allocated by ath_key_alloc. 2262 */ 2263 static int 2264 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2265 { 2266 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2267 struct ath_hal *ah = sc->sc_ah; 2268 const struct ieee80211_cipher *cip = k->wk_cipher; 2269 u_int keyix = k->wk_keyix; 2270 2271 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 2272 2273 ath_hal_keyreset(ah, keyix); 2274 /* 2275 * Handle split tx/rx keying required for TKIP with h/w MIC. 2276 */ 2277 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2278 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 2279 ath_hal_keyreset(ah, keyix+32); /* RX key */ 2280 if (keyix >= IEEE80211_WEP_NKID) { 2281 /* 2282 * Don't touch keymap entries for global keys so 2283 * they are never considered for dynamic allocation. 2284 */ 2285 clrbit(sc->sc_keymap, keyix); 2286 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2287 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2288 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 2289 if (sc->sc_splitmic) { 2290 /* +32 for RX key, +32+64 for RX key MIC */ 2291 clrbit(sc->sc_keymap, keyix+32); 2292 clrbit(sc->sc_keymap, keyix+32+64); 2293 } 2294 } 2295 } 2296 return 1; 2297 } 2298 2299 /* 2300 * Set the key cache contents for the specified key. Key cache 2301 * slot(s) must already have been allocated by ath_key_alloc. 2302 */ 2303 static int 2304 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 2305 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2306 { 2307 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2308 2309 return ath_keyset(sc, k, vap->iv_bss); 2310 } 2311 2312 /* 2313 * Block/unblock tx+rx processing while a key change is done. 2314 * We assume the caller serializes key management operations 2315 * so we only need to worry about synchronization with other 2316 * uses that originate in the driver. 2317 */ 2318 static void 2319 ath_key_update_begin(struct ieee80211vap *vap) 2320 { 2321 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2322 struct ath_softc *sc = ifp->if_softc; 2323 2324 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2325 taskqueue_block(sc->sc_tq); 2326 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2327 } 2328 2329 static void 2330 ath_key_update_end(struct ieee80211vap *vap) 2331 { 2332 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2333 struct ath_softc *sc = ifp->if_softc; 2334 2335 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2336 IF_UNLOCK(&ifp->if_snd); 2337 taskqueue_unblock(sc->sc_tq); 2338 } 2339 2340 /* 2341 * Calculate the receive filter according to the 2342 * operating mode and state: 2343 * 2344 * o always accept unicast, broadcast, and multicast traffic 2345 * o accept PHY error frames when hardware doesn't have MIB support 2346 * to count and we need them for ANI (sta mode only until recently) 2347 * and we are not scanning (ANI is disabled) 2348 * NB: older hal's add rx filter bits out of sight and we need to 2349 * blindly preserve them 2350 * o probe request frames are accepted only when operating in 2351 * hostap, adhoc, mesh, or monitor modes 2352 * o enable promiscuous mode 2353 * - when in monitor mode 2354 * - if interface marked PROMISC (assumes bridge setting is filtered) 2355 * o accept beacons: 2356 * - when operating in station mode for collecting rssi data when 2357 * the station is otherwise quiet, or 2358 * - when operating in adhoc mode so the 802.11 layer creates 2359 * node table entries for peers, 2360 * - when scanning 2361 * - when doing s/w beacon miss (e.g. for ap+sta) 2362 * - when operating in ap mode in 11g to detect overlapping bss that 2363 * require protection 2364 * - when operating in mesh mode to detect neighbors 2365 * o accept control frames: 2366 * - when in monitor mode 2367 * XXX BAR frames for 11n 2368 * XXX HT protection for 11n 2369 */ 2370 static u_int32_t 2371 ath_calcrxfilter(struct ath_softc *sc) 2372 { 2373 struct ifnet *ifp = sc->sc_ifp; 2374 struct ieee80211com *ic = ifp->if_l2com; 2375 u_int32_t rfilt; 2376 2377 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2378 if (!sc->sc_needmib && !sc->sc_scanning) 2379 rfilt |= HAL_RX_FILTER_PHYERR; 2380 if (ic->ic_opmode != IEEE80211_M_STA) 2381 rfilt |= HAL_RX_FILTER_PROBEREQ; 2382 /* XXX ic->ic_monvaps != 0? */ 2383 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 2384 rfilt |= HAL_RX_FILTER_PROM; 2385 if (ic->ic_opmode == IEEE80211_M_STA || 2386 ic->ic_opmode == IEEE80211_M_IBSS || 2387 sc->sc_swbmiss || sc->sc_scanning) 2388 rfilt |= HAL_RX_FILTER_BEACON; 2389 /* 2390 * NB: We don't recalculate the rx filter when 2391 * ic_protmode changes; otherwise we could do 2392 * this only when ic_protmode != NONE. 2393 */ 2394 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 2395 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 2396 rfilt |= HAL_RX_FILTER_BEACON; 2397 if (sc->sc_nmeshvaps) { 2398 rfilt |= HAL_RX_FILTER_BEACON; 2399 if (sc->sc_hasbmatch) 2400 rfilt |= HAL_RX_FILTER_BSSID; 2401 else 2402 rfilt |= HAL_RX_FILTER_PROM; 2403 } 2404 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2405 rfilt |= HAL_RX_FILTER_CONTROL; 2406 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 2407 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 2408 return rfilt; 2409 } 2410 2411 static void 2412 ath_update_promisc(struct ifnet *ifp) 2413 { 2414 struct ath_softc *sc = ifp->if_softc; 2415 u_int32_t rfilt; 2416 2417 /* configure rx filter */ 2418 rfilt = ath_calcrxfilter(sc); 2419 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2420 2421 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2422 } 2423 2424 static void 2425 ath_update_mcast(struct ifnet *ifp) 2426 { 2427 struct ath_softc *sc = ifp->if_softc; 2428 u_int32_t mfilt[2]; 2429 2430 /* calculate and install multicast filter */ 2431 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2432 struct ifmultiaddr *ifma; 2433 /* 2434 * Merge multicast addresses to form the hardware filter. 2435 */ 2436 mfilt[0] = mfilt[1] = 0; 2437 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */ 2438 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2439 caddr_t dl; 2440 u_int32_t val; 2441 u_int8_t pos; 2442 2443 /* calculate XOR of eight 6bit values */ 2444 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2445 val = LE_READ_4(dl + 0); 2446 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2447 val = LE_READ_4(dl + 3); 2448 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2449 pos &= 0x3f; 2450 mfilt[pos / 32] |= (1 << (pos % 32)); 2451 } 2452 if_maddr_runlock(ifp); 2453 } else 2454 mfilt[0] = mfilt[1] = ~0; 2455 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2456 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2457 __func__, mfilt[0], mfilt[1]); 2458 } 2459 2460 static void 2461 ath_mode_init(struct ath_softc *sc) 2462 { 2463 struct ifnet *ifp = sc->sc_ifp; 2464 struct ath_hal *ah = sc->sc_ah; 2465 u_int32_t rfilt; 2466 2467 /* configure rx filter */ 2468 rfilt = ath_calcrxfilter(sc); 2469 ath_hal_setrxfilter(ah, rfilt); 2470 2471 /* configure operational mode */ 2472 ath_hal_setopmode(ah); 2473 2474 /* handle any link-level address change */ 2475 ath_hal_setmac(ah, IF_LLADDR(ifp)); 2476 2477 /* calculate and install multicast filter */ 2478 ath_update_mcast(ifp); 2479 } 2480 2481 /* 2482 * Set the slot time based on the current setting. 2483 */ 2484 static void 2485 ath_setslottime(struct ath_softc *sc) 2486 { 2487 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2488 struct ath_hal *ah = sc->sc_ah; 2489 u_int usec; 2490 2491 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2492 usec = 13; 2493 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2494 usec = 21; 2495 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2496 /* honor short/long slot time only in 11g */ 2497 /* XXX shouldn't honor on pure g or turbo g channel */ 2498 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2499 usec = HAL_SLOT_TIME_9; 2500 else 2501 usec = HAL_SLOT_TIME_20; 2502 } else 2503 usec = HAL_SLOT_TIME_9; 2504 2505 DPRINTF(sc, ATH_DEBUG_RESET, 2506 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2507 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2508 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2509 2510 ath_hal_setslottime(ah, usec); 2511 sc->sc_updateslot = OK; 2512 } 2513 2514 /* 2515 * Callback from the 802.11 layer to update the 2516 * slot time based on the current setting. 2517 */ 2518 static void 2519 ath_updateslot(struct ifnet *ifp) 2520 { 2521 struct ath_softc *sc = ifp->if_softc; 2522 struct ieee80211com *ic = ifp->if_l2com; 2523 2524 /* 2525 * When not coordinating the BSS, change the hardware 2526 * immediately. For other operation we defer the change 2527 * until beacon updates have propagated to the stations. 2528 */ 2529 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2530 ic->ic_opmode == IEEE80211_M_MBSS) 2531 sc->sc_updateslot = UPDATE; 2532 else 2533 ath_setslottime(sc); 2534 } 2535 2536 /* 2537 * Setup a h/w transmit queue for beacons. 2538 */ 2539 static int 2540 ath_beaconq_setup(struct ath_hal *ah) 2541 { 2542 HAL_TXQ_INFO qi; 2543 2544 memset(&qi, 0, sizeof(qi)); 2545 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2546 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2547 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2548 /* NB: for dynamic turbo, don't enable any other interrupts */ 2549 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2550 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2551 } 2552 2553 /* 2554 * Setup the transmit queue parameters for the beacon queue. 2555 */ 2556 static int 2557 ath_beaconq_config(struct ath_softc *sc) 2558 { 2559 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2560 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2561 struct ath_hal *ah = sc->sc_ah; 2562 HAL_TXQ_INFO qi; 2563 2564 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2565 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2566 ic->ic_opmode == IEEE80211_M_MBSS) { 2567 /* 2568 * Always burst out beacon and CAB traffic. 2569 */ 2570 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2571 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2572 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2573 } else { 2574 struct wmeParams *wmep = 2575 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2576 /* 2577 * Adhoc mode; important thing is to use 2x cwmin. 2578 */ 2579 qi.tqi_aifs = wmep->wmep_aifsn; 2580 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2581 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2582 } 2583 2584 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2585 device_printf(sc->sc_dev, "unable to update parameters for " 2586 "beacon hardware queue!\n"); 2587 return 0; 2588 } else { 2589 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2590 return 1; 2591 } 2592 #undef ATH_EXPONENT_TO_VALUE 2593 } 2594 2595 /* 2596 * Allocate and setup an initial beacon frame. 2597 */ 2598 static int 2599 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2600 { 2601 struct ieee80211vap *vap = ni->ni_vap; 2602 struct ath_vap *avp = ATH_VAP(vap); 2603 struct ath_buf *bf; 2604 struct mbuf *m; 2605 int error; 2606 2607 bf = avp->av_bcbuf; 2608 if (bf->bf_m != NULL) { 2609 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2610 m_freem(bf->bf_m); 2611 bf->bf_m = NULL; 2612 } 2613 if (bf->bf_node != NULL) { 2614 ieee80211_free_node(bf->bf_node); 2615 bf->bf_node = NULL; 2616 } 2617 2618 /* 2619 * NB: the beacon data buffer must be 32-bit aligned; 2620 * we assume the mbuf routines will return us something 2621 * with this alignment (perhaps should assert). 2622 */ 2623 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 2624 if (m == NULL) { 2625 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 2626 sc->sc_stats.ast_be_nombuf++; 2627 return ENOMEM; 2628 } 2629 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2630 bf->bf_segs, &bf->bf_nseg, 2631 BUS_DMA_NOWAIT); 2632 if (error != 0) { 2633 device_printf(sc->sc_dev, 2634 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 2635 __func__, error); 2636 m_freem(m); 2637 return error; 2638 } 2639 2640 /* 2641 * Calculate a TSF adjustment factor required for staggered 2642 * beacons. Note that we assume the format of the beacon 2643 * frame leaves the tstamp field immediately following the 2644 * header. 2645 */ 2646 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 2647 uint64_t tsfadjust; 2648 struct ieee80211_frame *wh; 2649 2650 /* 2651 * The beacon interval is in TU's; the TSF is in usecs. 2652 * We figure out how many TU's to add to align the timestamp 2653 * then convert to TSF units and handle byte swapping before 2654 * inserting it in the frame. The hardware will then add this 2655 * each time a beacon frame is sent. Note that we align vap's 2656 * 1..N and leave vap 0 untouched. This means vap 0 has a 2657 * timestamp in one beacon interval while the others get a 2658 * timstamp aligned to the next interval. 2659 */ 2660 tsfadjust = ni->ni_intval * 2661 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 2662 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 2663 2664 DPRINTF(sc, ATH_DEBUG_BEACON, 2665 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 2666 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 2667 avp->av_bslot, ni->ni_intval, 2668 (long long unsigned) le64toh(tsfadjust)); 2669 2670 wh = mtod(m, struct ieee80211_frame *); 2671 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 2672 } 2673 bf->bf_m = m; 2674 bf->bf_node = ieee80211_ref_node(ni); 2675 2676 return 0; 2677 } 2678 2679 /* 2680 * Setup the beacon frame for transmit. 2681 */ 2682 static void 2683 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2684 { 2685 #define USE_SHPREAMBLE(_ic) \ 2686 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2687 == IEEE80211_F_SHPREAMBLE) 2688 struct ieee80211_node *ni = bf->bf_node; 2689 struct ieee80211com *ic = ni->ni_ic; 2690 struct mbuf *m = bf->bf_m; 2691 struct ath_hal *ah = sc->sc_ah; 2692 struct ath_desc *ds; 2693 int flags, antenna; 2694 const HAL_RATE_TABLE *rt; 2695 u_int8_t rix, rate; 2696 2697 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2698 __func__, m, m->m_len); 2699 2700 /* setup descriptors */ 2701 ds = bf->bf_desc; 2702 2703 flags = HAL_TXDESC_NOACK; 2704 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2705 ds->ds_link = bf->bf_daddr; /* self-linked */ 2706 flags |= HAL_TXDESC_VEOL; 2707 /* 2708 * Let hardware handle antenna switching. 2709 */ 2710 antenna = sc->sc_txantenna; 2711 } else { 2712 ds->ds_link = 0; 2713 /* 2714 * Switch antenna every 4 beacons. 2715 * XXX assumes two antenna 2716 */ 2717 if (sc->sc_txantenna != 0) 2718 antenna = sc->sc_txantenna; 2719 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 2720 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 2721 else 2722 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2723 } 2724 2725 KASSERT(bf->bf_nseg == 1, 2726 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2727 ds->ds_data = bf->bf_segs[0].ds_addr; 2728 /* 2729 * Calculate rate code. 2730 * XXX everything at min xmit rate 2731 */ 2732 rix = 0; 2733 rt = sc->sc_currates; 2734 rate = rt->info[rix].rateCode; 2735 if (USE_SHPREAMBLE(ic)) 2736 rate |= rt->info[rix].shortPreamble; 2737 ath_hal_setuptxdesc(ah, ds 2738 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2739 , sizeof(struct ieee80211_frame)/* header length */ 2740 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2741 , ni->ni_txpower /* txpower XXX */ 2742 , rate, 1 /* series 0 rate/tries */ 2743 , HAL_TXKEYIX_INVALID /* no encryption */ 2744 , antenna /* antenna mode */ 2745 , flags /* no ack, veol for beacons */ 2746 , 0 /* rts/cts rate */ 2747 , 0 /* rts/cts duration */ 2748 ); 2749 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2750 ath_hal_filltxdesc(ah, ds 2751 , roundup(m->m_len, 4) /* buffer length */ 2752 , AH_TRUE /* first segment */ 2753 , AH_TRUE /* last segment */ 2754 , ds /* first descriptor */ 2755 ); 2756 #if 0 2757 ath_desc_swap(ds); 2758 #endif 2759 #undef USE_SHPREAMBLE 2760 } 2761 2762 static void 2763 ath_beacon_update(struct ieee80211vap *vap, int item) 2764 { 2765 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 2766 2767 setbit(bo->bo_flags, item); 2768 } 2769 2770 /* 2771 * Append the contents of src to dst; both queues 2772 * are assumed to be locked. 2773 */ 2774 static void 2775 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2776 { 2777 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 2778 dst->axq_link = src->axq_link; 2779 src->axq_link = NULL; 2780 dst->axq_depth += src->axq_depth; 2781 src->axq_depth = 0; 2782 } 2783 2784 /* 2785 * Transmit a beacon frame at SWBA. Dynamic updates to the 2786 * frame contents are done as needed and the slot time is 2787 * also adjusted based on current state. 2788 */ 2789 static void 2790 ath_beacon_proc(void *arg, int pending) 2791 { 2792 struct ath_softc *sc = arg; 2793 struct ath_hal *ah = sc->sc_ah; 2794 struct ieee80211vap *vap; 2795 struct ath_buf *bf; 2796 int slot, otherant; 2797 uint32_t bfaddr; 2798 2799 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2800 __func__, pending); 2801 /* 2802 * Check if the previous beacon has gone out. If 2803 * not don't try to post another, skip this period 2804 * and wait for the next. Missed beacons indicate 2805 * a problem and should not occur. If we miss too 2806 * many consecutive beacons reset the device. 2807 */ 2808 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2809 sc->sc_bmisscount++; 2810 DPRINTF(sc, ATH_DEBUG_BEACON, 2811 "%s: missed %u consecutive beacons\n", 2812 __func__, sc->sc_bmisscount); 2813 if (sc->sc_bmisscount >= ath_bstuck_threshold) 2814 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2815 return; 2816 } 2817 if (sc->sc_bmisscount != 0) { 2818 DPRINTF(sc, ATH_DEBUG_BEACON, 2819 "%s: resume beacon xmit after %u misses\n", 2820 __func__, sc->sc_bmisscount); 2821 sc->sc_bmisscount = 0; 2822 } 2823 2824 if (sc->sc_stagbeacons) { /* staggered beacons */ 2825 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2826 uint32_t tsftu; 2827 2828 tsftu = ath_hal_gettsf32(ah) >> 10; 2829 /* XXX lintval */ 2830 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 2831 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 2832 bfaddr = 0; 2833 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2834 bf = ath_beacon_generate(sc, vap); 2835 if (bf != NULL) 2836 bfaddr = bf->bf_daddr; 2837 } 2838 } else { /* burst'd beacons */ 2839 uint32_t *bflink = &bfaddr; 2840 2841 for (slot = 0; slot < ATH_BCBUF; slot++) { 2842 vap = sc->sc_bslot[slot]; 2843 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2844 bf = ath_beacon_generate(sc, vap); 2845 if (bf != NULL) { 2846 *bflink = bf->bf_daddr; 2847 bflink = &bf->bf_desc->ds_link; 2848 } 2849 } 2850 } 2851 *bflink = 0; /* terminate list */ 2852 } 2853 2854 /* 2855 * Handle slot time change when a non-ERP station joins/leaves 2856 * an 11g network. The 802.11 layer notifies us via callback, 2857 * we mark updateslot, then wait one beacon before effecting 2858 * the change. This gives associated stations at least one 2859 * beacon interval to note the state change. 2860 */ 2861 /* XXX locking */ 2862 if (sc->sc_updateslot == UPDATE) { 2863 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2864 sc->sc_slotupdate = slot; 2865 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 2866 ath_setslottime(sc); /* commit change to h/w */ 2867 2868 /* 2869 * Check recent per-antenna transmit statistics and flip 2870 * the default antenna if noticeably more frames went out 2871 * on the non-default antenna. 2872 * XXX assumes 2 anntenae 2873 */ 2874 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 2875 otherant = sc->sc_defant & 1 ? 2 : 1; 2876 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2877 ath_setdefantenna(sc, otherant); 2878 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2879 } 2880 2881 if (bfaddr != 0) { 2882 /* 2883 * Stop any current dma and put the new frame on the queue. 2884 * This should never fail since we check above that no frames 2885 * are still pending on the queue. 2886 */ 2887 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2888 DPRINTF(sc, ATH_DEBUG_ANY, 2889 "%s: beacon queue %u did not stop?\n", 2890 __func__, sc->sc_bhalq); 2891 } 2892 /* NB: cabq traffic should already be queued and primed */ 2893 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 2894 ath_hal_txstart(ah, sc->sc_bhalq); 2895 2896 sc->sc_stats.ast_be_xmit++; 2897 } 2898 } 2899 2900 static struct ath_buf * 2901 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 2902 { 2903 struct ath_vap *avp = ATH_VAP(vap); 2904 struct ath_txq *cabq = sc->sc_cabq; 2905 struct ath_buf *bf; 2906 struct mbuf *m; 2907 int nmcastq, error; 2908 2909 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 2910 ("not running, state %d", vap->iv_state)); 2911 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 2912 2913 /* 2914 * Update dynamic beacon contents. If this returns 2915 * non-zero then we need to remap the memory because 2916 * the beacon frame changed size (probably because 2917 * of the TIM bitmap). 2918 */ 2919 bf = avp->av_bcbuf; 2920 m = bf->bf_m; 2921 nmcastq = avp->av_mcastq.axq_depth; 2922 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 2923 /* XXX too conservative? */ 2924 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2925 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2926 bf->bf_segs, &bf->bf_nseg, 2927 BUS_DMA_NOWAIT); 2928 if (error != 0) { 2929 if_printf(vap->iv_ifp, 2930 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 2931 __func__, error); 2932 return NULL; 2933 } 2934 } 2935 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 2936 DPRINTF(sc, ATH_DEBUG_BEACON, 2937 "%s: cabq did not drain, mcastq %u cabq %u\n", 2938 __func__, nmcastq, cabq->axq_depth); 2939 sc->sc_stats.ast_cabq_busy++; 2940 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 2941 /* 2942 * CABQ traffic from a previous vap is still pending. 2943 * We must drain the q before this beacon frame goes 2944 * out as otherwise this vap's stations will get cab 2945 * frames from a different vap. 2946 * XXX could be slow causing us to miss DBA 2947 */ 2948 ath_tx_draintxq(sc, cabq); 2949 } 2950 } 2951 ath_beacon_setup(sc, bf); 2952 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2953 2954 /* 2955 * Enable the CAB queue before the beacon queue to 2956 * insure cab frames are triggered by this beacon. 2957 */ 2958 if (avp->av_boff.bo_tim[4] & 1) { 2959 struct ath_hal *ah = sc->sc_ah; 2960 2961 /* NB: only at DTIM */ 2962 ATH_TXQ_LOCK(cabq); 2963 ATH_TXQ_LOCK(&avp->av_mcastq); 2964 if (nmcastq) { 2965 struct ath_buf *bfm; 2966 2967 /* 2968 * Move frames from the s/w mcast q to the h/w cab q. 2969 * XXX MORE_DATA bit 2970 */ 2971 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q); 2972 if (cabq->axq_link != NULL) { 2973 *cabq->axq_link = bfm->bf_daddr; 2974 } else 2975 ath_hal_puttxbuf(ah, cabq->axq_qnum, 2976 bfm->bf_daddr); 2977 ath_txqmove(cabq, &avp->av_mcastq); 2978 2979 sc->sc_stats.ast_cabq_xmit += nmcastq; 2980 } 2981 /* NB: gated by beacon so safe to start here */ 2982 ath_hal_txstart(ah, cabq->axq_qnum); 2983 ATH_TXQ_UNLOCK(cabq); 2984 ATH_TXQ_UNLOCK(&avp->av_mcastq); 2985 } 2986 return bf; 2987 } 2988 2989 static void 2990 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 2991 { 2992 struct ath_vap *avp = ATH_VAP(vap); 2993 struct ath_hal *ah = sc->sc_ah; 2994 struct ath_buf *bf; 2995 struct mbuf *m; 2996 int error; 2997 2998 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 2999 3000 /* 3001 * Update dynamic beacon contents. If this returns 3002 * non-zero then we need to remap the memory because 3003 * the beacon frame changed size (probably because 3004 * of the TIM bitmap). 3005 */ 3006 bf = avp->av_bcbuf; 3007 m = bf->bf_m; 3008 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 3009 /* XXX too conservative? */ 3010 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3011 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 3012 bf->bf_segs, &bf->bf_nseg, 3013 BUS_DMA_NOWAIT); 3014 if (error != 0) { 3015 if_printf(vap->iv_ifp, 3016 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 3017 __func__, error); 3018 return; 3019 } 3020 } 3021 ath_beacon_setup(sc, bf); 3022 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3023 3024 /* NB: caller is known to have already stopped tx dma */ 3025 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 3026 ath_hal_txstart(ah, sc->sc_bhalq); 3027 } 3028 3029 /* 3030 * Reset the hardware after detecting beacons have stopped. 3031 */ 3032 static void 3033 ath_bstuck_proc(void *arg, int pending) 3034 { 3035 struct ath_softc *sc = arg; 3036 struct ifnet *ifp = sc->sc_ifp; 3037 3038 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3039 sc->sc_bmisscount); 3040 sc->sc_stats.ast_bstuck++; 3041 ath_reset(ifp); 3042 } 3043 3044 /* 3045 * Reclaim beacon resources and return buffer to the pool. 3046 */ 3047 static void 3048 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 3049 { 3050 3051 if (bf->bf_m != NULL) { 3052 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3053 m_freem(bf->bf_m); 3054 bf->bf_m = NULL; 3055 } 3056 if (bf->bf_node != NULL) { 3057 ieee80211_free_node(bf->bf_node); 3058 bf->bf_node = NULL; 3059 } 3060 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 3061 } 3062 3063 /* 3064 * Reclaim beacon resources. 3065 */ 3066 static void 3067 ath_beacon_free(struct ath_softc *sc) 3068 { 3069 struct ath_buf *bf; 3070 3071 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 3072 if (bf->bf_m != NULL) { 3073 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3074 m_freem(bf->bf_m); 3075 bf->bf_m = NULL; 3076 } 3077 if (bf->bf_node != NULL) { 3078 ieee80211_free_node(bf->bf_node); 3079 bf->bf_node = NULL; 3080 } 3081 } 3082 } 3083 3084 /* 3085 * Configure the beacon and sleep timers. 3086 * 3087 * When operating as an AP this resets the TSF and sets 3088 * up the hardware to notify us when we need to issue beacons. 3089 * 3090 * When operating in station mode this sets up the beacon 3091 * timers according to the timestamp of the last received 3092 * beacon and the current TSF, configures PCF and DTIM 3093 * handling, programs the sleep registers so the hardware 3094 * will wakeup in time to receive beacons, and configures 3095 * the beacon miss handling so we'll receive a BMISS 3096 * interrupt when we stop seeing beacons from the AP 3097 * we've associated with. 3098 */ 3099 static void 3100 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 3101 { 3102 #define TSF_TO_TU(_h,_l) \ 3103 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 3104 #define FUDGE 2 3105 struct ath_hal *ah = sc->sc_ah; 3106 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3107 struct ieee80211_node *ni; 3108 u_int32_t nexttbtt, intval, tsftu; 3109 u_int64_t tsf; 3110 3111 if (vap == NULL) 3112 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 3113 ni = vap->iv_bss; 3114 3115 /* extract tstamp from last beacon and convert to TU */ 3116 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 3117 LE_READ_4(ni->ni_tstamp.data)); 3118 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3119 ic->ic_opmode == IEEE80211_M_MBSS) { 3120 /* 3121 * For multi-bss ap/mesh support beacons are either staggered 3122 * evenly over N slots or burst together. For the former 3123 * arrange for the SWBA to be delivered for each slot. 3124 * Slots that are not occupied will generate nothing. 3125 */ 3126 /* NB: the beacon interval is kept internally in TU's */ 3127 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3128 if (sc->sc_stagbeacons) 3129 intval /= ATH_BCBUF; 3130 } else { 3131 /* NB: the beacon interval is kept internally in TU's */ 3132 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3133 } 3134 if (nexttbtt == 0) /* e.g. for ap mode */ 3135 nexttbtt = intval; 3136 else if (intval) /* NB: can be 0 for monitor mode */ 3137 nexttbtt = roundup(nexttbtt, intval); 3138 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 3139 __func__, nexttbtt, intval, ni->ni_intval); 3140 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 3141 HAL_BEACON_STATE bs; 3142 int dtimperiod, dtimcount; 3143 int cfpperiod, cfpcount; 3144 3145 /* 3146 * Setup dtim and cfp parameters according to 3147 * last beacon we received (which may be none). 3148 */ 3149 dtimperiod = ni->ni_dtim_period; 3150 if (dtimperiod <= 0) /* NB: 0 if not known */ 3151 dtimperiod = 1; 3152 dtimcount = ni->ni_dtim_count; 3153 if (dtimcount >= dtimperiod) /* NB: sanity check */ 3154 dtimcount = 0; /* XXX? */ 3155 cfpperiod = 1; /* NB: no PCF support yet */ 3156 cfpcount = 0; 3157 /* 3158 * Pull nexttbtt forward to reflect the current 3159 * TSF and calculate dtim+cfp state for the result. 3160 */ 3161 tsf = ath_hal_gettsf64(ah); 3162 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3163 do { 3164 nexttbtt += intval; 3165 if (--dtimcount < 0) { 3166 dtimcount = dtimperiod - 1; 3167 if (--cfpcount < 0) 3168 cfpcount = cfpperiod - 1; 3169 } 3170 } while (nexttbtt < tsftu); 3171 memset(&bs, 0, sizeof(bs)); 3172 bs.bs_intval = intval; 3173 bs.bs_nexttbtt = nexttbtt; 3174 bs.bs_dtimperiod = dtimperiod*intval; 3175 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 3176 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 3177 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 3178 bs.bs_cfpmaxduration = 0; 3179 #if 0 3180 /* 3181 * The 802.11 layer records the offset to the DTIM 3182 * bitmap while receiving beacons; use it here to 3183 * enable h/w detection of our AID being marked in 3184 * the bitmap vector (to indicate frames for us are 3185 * pending at the AP). 3186 * XXX do DTIM handling in s/w to WAR old h/w bugs 3187 * XXX enable based on h/w rev for newer chips 3188 */ 3189 bs.bs_timoffset = ni->ni_timoff; 3190 #endif 3191 /* 3192 * Calculate the number of consecutive beacons to miss 3193 * before taking a BMISS interrupt. 3194 * Note that we clamp the result to at most 10 beacons. 3195 */ 3196 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 3197 if (bs.bs_bmissthreshold > 10) 3198 bs.bs_bmissthreshold = 10; 3199 else if (bs.bs_bmissthreshold <= 0) 3200 bs.bs_bmissthreshold = 1; 3201 3202 /* 3203 * Calculate sleep duration. The configuration is 3204 * given in ms. We insure a multiple of the beacon 3205 * period is used. Also, if the sleep duration is 3206 * greater than the DTIM period then it makes senses 3207 * to make it a multiple of that. 3208 * 3209 * XXX fixed at 100ms 3210 */ 3211 bs.bs_sleepduration = 3212 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 3213 if (bs.bs_sleepduration > bs.bs_dtimperiod) 3214 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 3215 3216 DPRINTF(sc, ATH_DEBUG_BEACON, 3217 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 3218 , __func__ 3219 , tsf, tsftu 3220 , bs.bs_intval 3221 , bs.bs_nexttbtt 3222 , bs.bs_dtimperiod 3223 , bs.bs_nextdtim 3224 , bs.bs_bmissthreshold 3225 , bs.bs_sleepduration 3226 , bs.bs_cfpperiod 3227 , bs.bs_cfpmaxduration 3228 , bs.bs_cfpnext 3229 , bs.bs_timoffset 3230 ); 3231 ath_hal_intrset(ah, 0); 3232 ath_hal_beacontimers(ah, &bs); 3233 sc->sc_imask |= HAL_INT_BMISS; 3234 ath_hal_intrset(ah, sc->sc_imask); 3235 } else { 3236 ath_hal_intrset(ah, 0); 3237 if (nexttbtt == intval) 3238 intval |= HAL_BEACON_RESET_TSF; 3239 if (ic->ic_opmode == IEEE80211_M_IBSS) { 3240 /* 3241 * In IBSS mode enable the beacon timers but only 3242 * enable SWBA interrupts if we need to manually 3243 * prepare beacon frames. Otherwise we use a 3244 * self-linked tx descriptor and let the hardware 3245 * deal with things. 3246 */ 3247 intval |= HAL_BEACON_ENA; 3248 if (!sc->sc_hasveol) 3249 sc->sc_imask |= HAL_INT_SWBA; 3250 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 3251 /* 3252 * Pull nexttbtt forward to reflect 3253 * the current TSF. 3254 */ 3255 tsf = ath_hal_gettsf64(ah); 3256 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3257 do { 3258 nexttbtt += intval; 3259 } while (nexttbtt < tsftu); 3260 } 3261 ath_beaconq_config(sc); 3262 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3263 ic->ic_opmode == IEEE80211_M_MBSS) { 3264 /* 3265 * In AP/mesh mode we enable the beacon timers 3266 * and SWBA interrupts to prepare beacon frames. 3267 */ 3268 intval |= HAL_BEACON_ENA; 3269 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 3270 ath_beaconq_config(sc); 3271 } 3272 ath_hal_beaconinit(ah, nexttbtt, intval); 3273 sc->sc_bmisscount = 0; 3274 ath_hal_intrset(ah, sc->sc_imask); 3275 /* 3276 * When using a self-linked beacon descriptor in 3277 * ibss mode load it once here. 3278 */ 3279 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 3280 ath_beacon_start_adhoc(sc, vap); 3281 } 3282 sc->sc_syncbeacon = 0; 3283 #undef FUDGE 3284 #undef TSF_TO_TU 3285 } 3286 3287 static void 3288 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3289 { 3290 bus_addr_t *paddr = (bus_addr_t*) arg; 3291 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3292 *paddr = segs->ds_addr; 3293 } 3294 3295 static int 3296 ath_descdma_setup(struct ath_softc *sc, 3297 struct ath_descdma *dd, ath_bufhead *head, 3298 const char *name, int nbuf, int ndesc) 3299 { 3300 #define DS2PHYS(_dd, _ds) \ 3301 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3302 struct ifnet *ifp = sc->sc_ifp; 3303 struct ath_desc *ds; 3304 struct ath_buf *bf; 3305 int i, bsize, error; 3306 3307 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 3308 __func__, name, nbuf, ndesc); 3309 3310 dd->dd_name = name; 3311 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 3312 3313 /* 3314 * Setup DMA descriptor area. 3315 */ 3316 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 3317 PAGE_SIZE, 0, /* alignment, bounds */ 3318 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3319 BUS_SPACE_MAXADDR, /* highaddr */ 3320 NULL, NULL, /* filter, filterarg */ 3321 dd->dd_desc_len, /* maxsize */ 3322 1, /* nsegments */ 3323 dd->dd_desc_len, /* maxsegsize */ 3324 BUS_DMA_ALLOCNOW, /* flags */ 3325 NULL, /* lockfunc */ 3326 NULL, /* lockarg */ 3327 &dd->dd_dmat); 3328 if (error != 0) { 3329 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3330 return error; 3331 } 3332 3333 /* allocate descriptors */ 3334 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3335 if (error != 0) { 3336 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3337 "error %u\n", dd->dd_name, error); 3338 goto fail0; 3339 } 3340 3341 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3342 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3343 &dd->dd_dmamap); 3344 if (error != 0) { 3345 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3346 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3347 goto fail1; 3348 } 3349 3350 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3351 dd->dd_desc, dd->dd_desc_len, 3352 ath_load_cb, &dd->dd_desc_paddr, 3353 BUS_DMA_NOWAIT); 3354 if (error != 0) { 3355 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3356 dd->dd_name, error); 3357 goto fail2; 3358 } 3359 3360 ds = dd->dd_desc; 3361 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3362 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3363 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3364 3365 /* allocate rx buffers */ 3366 bsize = sizeof(struct ath_buf) * nbuf; 3367 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3368 if (bf == NULL) { 3369 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3370 dd->dd_name, bsize); 3371 goto fail3; 3372 } 3373 dd->dd_bufptr = bf; 3374 3375 STAILQ_INIT(head); 3376 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 3377 bf->bf_desc = ds; 3378 bf->bf_daddr = DS2PHYS(dd, ds); 3379 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3380 &bf->bf_dmamap); 3381 if (error != 0) { 3382 if_printf(ifp, "unable to create dmamap for %s " 3383 "buffer %u, error %u\n", dd->dd_name, i, error); 3384 ath_descdma_cleanup(sc, dd, head); 3385 return error; 3386 } 3387 STAILQ_INSERT_TAIL(head, bf, bf_list); 3388 } 3389 return 0; 3390 fail3: 3391 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3392 fail2: 3393 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3394 fail1: 3395 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3396 fail0: 3397 bus_dma_tag_destroy(dd->dd_dmat); 3398 memset(dd, 0, sizeof(*dd)); 3399 return error; 3400 #undef DS2PHYS 3401 } 3402 3403 static void 3404 ath_descdma_cleanup(struct ath_softc *sc, 3405 struct ath_descdma *dd, ath_bufhead *head) 3406 { 3407 struct ath_buf *bf; 3408 struct ieee80211_node *ni; 3409 3410 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3411 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3412 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3413 bus_dma_tag_destroy(dd->dd_dmat); 3414 3415 STAILQ_FOREACH(bf, head, bf_list) { 3416 if (bf->bf_m) { 3417 m_freem(bf->bf_m); 3418 bf->bf_m = NULL; 3419 } 3420 if (bf->bf_dmamap != NULL) { 3421 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3422 bf->bf_dmamap = NULL; 3423 } 3424 ni = bf->bf_node; 3425 bf->bf_node = NULL; 3426 if (ni != NULL) { 3427 /* 3428 * Reclaim node reference. 3429 */ 3430 ieee80211_free_node(ni); 3431 } 3432 } 3433 3434 STAILQ_INIT(head); 3435 free(dd->dd_bufptr, M_ATHDEV); 3436 memset(dd, 0, sizeof(*dd)); 3437 } 3438 3439 static int 3440 ath_desc_alloc(struct ath_softc *sc) 3441 { 3442 int error; 3443 3444 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3445 "rx", ath_rxbuf, 1); 3446 if (error != 0) 3447 return error; 3448 3449 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3450 "tx", ath_txbuf, ATH_TXDESC); 3451 if (error != 0) { 3452 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3453 return error; 3454 } 3455 3456 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3457 "beacon", ATH_BCBUF, 1); 3458 if (error != 0) { 3459 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3460 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3461 return error; 3462 } 3463 return 0; 3464 } 3465 3466 static void 3467 ath_desc_free(struct ath_softc *sc) 3468 { 3469 3470 if (sc->sc_bdma.dd_desc_len != 0) 3471 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3472 if (sc->sc_txdma.dd_desc_len != 0) 3473 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3474 if (sc->sc_rxdma.dd_desc_len != 0) 3475 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3476 } 3477 3478 static struct ieee80211_node * 3479 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3480 { 3481 struct ieee80211com *ic = vap->iv_ic; 3482 struct ath_softc *sc = ic->ic_ifp->if_softc; 3483 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3484 struct ath_node *an; 3485 3486 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3487 if (an == NULL) { 3488 /* XXX stat+msg */ 3489 return NULL; 3490 } 3491 ath_rate_node_init(sc, an); 3492 3493 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3494 return &an->an_node; 3495 } 3496 3497 static void 3498 ath_node_free(struct ieee80211_node *ni) 3499 { 3500 struct ieee80211com *ic = ni->ni_ic; 3501 struct ath_softc *sc = ic->ic_ifp->if_softc; 3502 3503 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3504 3505 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3506 sc->sc_node_free(ni); 3507 } 3508 3509 static void 3510 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3511 { 3512 struct ieee80211com *ic = ni->ni_ic; 3513 struct ath_softc *sc = ic->ic_ifp->if_softc; 3514 struct ath_hal *ah = sc->sc_ah; 3515 3516 *rssi = ic->ic_node_getrssi(ni); 3517 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3518 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3519 else 3520 *noise = -95; /* nominally correct */ 3521 } 3522 3523 static int 3524 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3525 { 3526 struct ath_hal *ah = sc->sc_ah; 3527 int error; 3528 struct mbuf *m; 3529 struct ath_desc *ds; 3530 3531 m = bf->bf_m; 3532 if (m == NULL) { 3533 /* 3534 * NB: by assigning a page to the rx dma buffer we 3535 * implicitly satisfy the Atheros requirement that 3536 * this buffer be cache-line-aligned and sized to be 3537 * multiple of the cache line size. Not doing this 3538 * causes weird stuff to happen (for the 5210 at least). 3539 */ 3540 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3541 if (m == NULL) { 3542 DPRINTF(sc, ATH_DEBUG_ANY, 3543 "%s: no mbuf/cluster\n", __func__); 3544 sc->sc_stats.ast_rx_nombuf++; 3545 return ENOMEM; 3546 } 3547 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3548 3549 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 3550 bf->bf_dmamap, m, 3551 bf->bf_segs, &bf->bf_nseg, 3552 BUS_DMA_NOWAIT); 3553 if (error != 0) { 3554 DPRINTF(sc, ATH_DEBUG_ANY, 3555 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 3556 __func__, error); 3557 sc->sc_stats.ast_rx_busdma++; 3558 m_freem(m); 3559 return error; 3560 } 3561 KASSERT(bf->bf_nseg == 1, 3562 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3563 bf->bf_m = m; 3564 } 3565 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3566 3567 /* 3568 * Setup descriptors. For receive we always terminate 3569 * the descriptor list with a self-linked entry so we'll 3570 * not get overrun under high load (as can happen with a 3571 * 5212 when ANI processing enables PHY error frames). 3572 * 3573 * To insure the last descriptor is self-linked we create 3574 * each descriptor as self-linked and add it to the end. As 3575 * each additional descriptor is added the previous self-linked 3576 * entry is ``fixed'' naturally. This should be safe even 3577 * if DMA is happening. When processing RX interrupts we 3578 * never remove/process the last, self-linked, entry on the 3579 * descriptor list. This insures the hardware always has 3580 * someplace to write a new frame. 3581 */ 3582 ds = bf->bf_desc; 3583 ds->ds_link = bf->bf_daddr; /* link to self */ 3584 ds->ds_data = bf->bf_segs[0].ds_addr; 3585 ath_hal_setuprxdesc(ah, ds 3586 , m->m_len /* buffer size */ 3587 , 0 3588 ); 3589 3590 if (sc->sc_rxlink != NULL) 3591 *sc->sc_rxlink = bf->bf_daddr; 3592 sc->sc_rxlink = &ds->ds_link; 3593 return 0; 3594 } 3595 3596 /* 3597 * Extend 15-bit time stamp from rx descriptor to 3598 * a full 64-bit TSF using the specified TSF. 3599 */ 3600 static __inline u_int64_t 3601 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 3602 { 3603 if ((tsf & 0x7fff) < rstamp) 3604 tsf -= 0x8000; 3605 return ((tsf &~ 0x7fff) | rstamp); 3606 } 3607 3608 /* 3609 * Intercept management frames to collect beacon rssi data 3610 * and to do ibss merges. 3611 */ 3612 static void 3613 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 3614 int subtype, int rssi, int nf) 3615 { 3616 struct ieee80211vap *vap = ni->ni_vap; 3617 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 3618 3619 /* 3620 * Call up first so subsequent work can use information 3621 * potentially stored in the node (e.g. for ibss merge). 3622 */ 3623 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 3624 switch (subtype) { 3625 case IEEE80211_FC0_SUBTYPE_BEACON: 3626 /* update rssi statistics for use by the hal */ 3627 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3628 if (sc->sc_syncbeacon && 3629 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 3630 /* 3631 * Resync beacon timers using the tsf of the beacon 3632 * frame we just received. 3633 */ 3634 ath_beacon_config(sc, vap); 3635 } 3636 /* fall thru... */ 3637 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3638 if (vap->iv_opmode == IEEE80211_M_IBSS && 3639 vap->iv_state == IEEE80211_S_RUN) { 3640 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 3641 u_int64_t tsf = ath_extend_tsf(rstamp, 3642 ath_hal_gettsf64(sc->sc_ah)); 3643 /* 3644 * Handle ibss merge as needed; check the tsf on the 3645 * frame before attempting the merge. The 802.11 spec 3646 * says the station should change it's bssid to match 3647 * the oldest station with the same ssid, where oldest 3648 * is determined by the tsf. Note that hardware 3649 * reconfiguration happens through callback to 3650 * ath_newstate as the state machine will go from 3651 * RUN -> RUN when this happens. 3652 */ 3653 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3654 DPRINTF(sc, ATH_DEBUG_STATE, 3655 "ibss merge, rstamp %u tsf %ju " 3656 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3657 (uintmax_t)ni->ni_tstamp.tsf); 3658 (void) ieee80211_ibss_merge(ni); 3659 } 3660 } 3661 break; 3662 } 3663 } 3664 3665 /* 3666 * Set the default antenna. 3667 */ 3668 static void 3669 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3670 { 3671 struct ath_hal *ah = sc->sc_ah; 3672 3673 /* XXX block beacon interrupts */ 3674 ath_hal_setdefantenna(ah, antenna); 3675 if (sc->sc_defant != antenna) 3676 sc->sc_stats.ast_ant_defswitch++; 3677 sc->sc_defant = antenna; 3678 sc->sc_rxotherant = 0; 3679 } 3680 3681 static void 3682 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 3683 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 3684 { 3685 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 3686 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 3687 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 3688 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 3689 struct ath_softc *sc = ifp->if_softc; 3690 const HAL_RATE_TABLE *rt; 3691 uint8_t rix; 3692 3693 rt = sc->sc_currates; 3694 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3695 rix = rt->rateCodeToIndex[rs->rs_rate]; 3696 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3697 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3698 #ifdef AH_SUPPORT_AR5416 3699 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 3700 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 3701 struct ieee80211com *ic = ifp->if_l2com; 3702 3703 if ((rs->rs_flags & HAL_RX_2040) == 0) 3704 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 3705 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 3706 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 3707 else 3708 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 3709 if ((rs->rs_flags & HAL_RX_GI) == 0) 3710 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 3711 } 3712 #endif 3713 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 3714 if (rs->rs_status & HAL_RXERR_CRC) 3715 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3716 /* XXX propagate other error flags from descriptor */ 3717 sc->sc_rx_th.wr_antnoise = nf; 3718 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 3719 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 3720 #undef CHAN_HT 3721 #undef CHAN_HT20 3722 #undef CHAN_HT40U 3723 #undef CHAN_HT40D 3724 } 3725 3726 static void 3727 ath_handle_micerror(struct ieee80211com *ic, 3728 struct ieee80211_frame *wh, int keyix) 3729 { 3730 struct ieee80211_node *ni; 3731 3732 /* XXX recheck MIC to deal w/ chips that lie */ 3733 /* XXX discard MIC errors on !data frames */ 3734 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 3735 if (ni != NULL) { 3736 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 3737 ieee80211_free_node(ni); 3738 } 3739 } 3740 3741 static void 3742 ath_rx_proc(void *arg, int npending) 3743 { 3744 #define PA2DESC(_sc, _pa) \ 3745 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3746 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3747 struct ath_softc *sc = arg; 3748 struct ath_buf *bf; 3749 struct ifnet *ifp = sc->sc_ifp; 3750 struct ieee80211com *ic = ifp->if_l2com; 3751 struct ath_hal *ah = sc->sc_ah; 3752 struct ath_desc *ds; 3753 struct ath_rx_status *rs; 3754 struct mbuf *m; 3755 struct ieee80211_node *ni; 3756 int len, type, ngood; 3757 u_int phyerr; 3758 HAL_STATUS status; 3759 int16_t nf; 3760 u_int64_t tsf; 3761 3762 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3763 ngood = 0; 3764 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 3765 sc->sc_stats.ast_rx_noise = nf; 3766 tsf = ath_hal_gettsf64(ah); 3767 do { 3768 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3769 if (bf == NULL) { /* NB: shouldn't happen */ 3770 if_printf(ifp, "%s: no buffer!\n", __func__); 3771 break; 3772 } 3773 m = bf->bf_m; 3774 if (m == NULL) { /* NB: shouldn't happen */ 3775 /* 3776 * If mbuf allocation failed previously there 3777 * will be no mbuf; try again to re-populate it. 3778 */ 3779 /* XXX make debug msg */ 3780 if_printf(ifp, "%s: no mbuf!\n", __func__); 3781 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3782 goto rx_next; 3783 } 3784 ds = bf->bf_desc; 3785 if (ds->ds_link == bf->bf_daddr) { 3786 /* NB: never process the self-linked entry at the end */ 3787 break; 3788 } 3789 /* XXX sync descriptor memory */ 3790 /* 3791 * Must provide the virtual address of the current 3792 * descriptor, the physical address, and the virtual 3793 * address of the next descriptor in the h/w chain. 3794 * This allows the HAL to look ahead to see if the 3795 * hardware is done with a descriptor by checking the 3796 * done bit in the following descriptor and the address 3797 * of the current descriptor the DMA engine is working 3798 * on. All this is necessary because of our use of 3799 * a self-linked list to avoid rx overruns. 3800 */ 3801 rs = &bf->bf_status.ds_rxstat; 3802 status = ath_hal_rxprocdesc(ah, ds, 3803 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 3804 #ifdef ATH_DEBUG 3805 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3806 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 3807 #endif 3808 if (status == HAL_EINPROGRESS) 3809 break; 3810 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3811 if (rs->rs_status != 0) { 3812 if (rs->rs_status & HAL_RXERR_CRC) 3813 sc->sc_stats.ast_rx_crcerr++; 3814 if (rs->rs_status & HAL_RXERR_FIFO) 3815 sc->sc_stats.ast_rx_fifoerr++; 3816 if (rs->rs_status & HAL_RXERR_PHY) { 3817 sc->sc_stats.ast_rx_phyerr++; 3818 phyerr = rs->rs_phyerr & 0x1f; 3819 sc->sc_stats.ast_rx_phy[phyerr]++; 3820 goto rx_error; /* NB: don't count in ierrors */ 3821 } 3822 if (rs->rs_status & HAL_RXERR_DECRYPT) { 3823 /* 3824 * Decrypt error. If the error occurred 3825 * because there was no hardware key, then 3826 * let the frame through so the upper layers 3827 * can process it. This is necessary for 5210 3828 * parts which have no way to setup a ``clear'' 3829 * key cache entry. 3830 * 3831 * XXX do key cache faulting 3832 */ 3833 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 3834 goto rx_accept; 3835 sc->sc_stats.ast_rx_badcrypt++; 3836 } 3837 if (rs->rs_status & HAL_RXERR_MIC) { 3838 sc->sc_stats.ast_rx_badmic++; 3839 /* 3840 * Do minimal work required to hand off 3841 * the 802.11 header for notification. 3842 */ 3843 /* XXX frag's and qos frames */ 3844 len = rs->rs_datalen; 3845 if (len >= sizeof (struct ieee80211_frame)) { 3846 bus_dmamap_sync(sc->sc_dmat, 3847 bf->bf_dmamap, 3848 BUS_DMASYNC_POSTREAD); 3849 ath_handle_micerror(ic, 3850 mtod(m, struct ieee80211_frame *), 3851 sc->sc_splitmic ? 3852 rs->rs_keyix-32 : rs->rs_keyix); 3853 } 3854 } 3855 ifp->if_ierrors++; 3856 rx_error: 3857 /* 3858 * Cleanup any pending partial frame. 3859 */ 3860 if (sc->sc_rxpending != NULL) { 3861 m_freem(sc->sc_rxpending); 3862 sc->sc_rxpending = NULL; 3863 } 3864 /* 3865 * When a tap is present pass error frames 3866 * that have been requested. By default we 3867 * pass decrypt+mic errors but others may be 3868 * interesting (e.g. crc). 3869 */ 3870 if (ieee80211_radiotap_active(ic) && 3871 (rs->rs_status & sc->sc_monpass)) { 3872 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3873 BUS_DMASYNC_POSTREAD); 3874 /* NB: bpf needs the mbuf length setup */ 3875 len = rs->rs_datalen; 3876 m->m_pkthdr.len = m->m_len = len; 3877 ath_rx_tap(ifp, m, rs, tsf, nf); 3878 ieee80211_radiotap_rx_all(ic, m); 3879 } 3880 /* XXX pass MIC errors up for s/w reclaculation */ 3881 goto rx_next; 3882 } 3883 rx_accept: 3884 /* 3885 * Sync and unmap the frame. At this point we're 3886 * committed to passing the mbuf somewhere so clear 3887 * bf_m; this means a new mbuf must be allocated 3888 * when the rx descriptor is setup again to receive 3889 * another frame. 3890 */ 3891 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3892 BUS_DMASYNC_POSTREAD); 3893 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3894 bf->bf_m = NULL; 3895 3896 len = rs->rs_datalen; 3897 m->m_len = len; 3898 3899 if (rs->rs_more) { 3900 /* 3901 * Frame spans multiple descriptors; save 3902 * it for the next completed descriptor, it 3903 * will be used to construct a jumbogram. 3904 */ 3905 if (sc->sc_rxpending != NULL) { 3906 /* NB: max frame size is currently 2 clusters */ 3907 sc->sc_stats.ast_rx_toobig++; 3908 m_freem(sc->sc_rxpending); 3909 } 3910 m->m_pkthdr.rcvif = ifp; 3911 m->m_pkthdr.len = len; 3912 sc->sc_rxpending = m; 3913 goto rx_next; 3914 } else if (sc->sc_rxpending != NULL) { 3915 /* 3916 * This is the second part of a jumbogram, 3917 * chain it to the first mbuf, adjust the 3918 * frame length, and clear the rxpending state. 3919 */ 3920 sc->sc_rxpending->m_next = m; 3921 sc->sc_rxpending->m_pkthdr.len += len; 3922 m = sc->sc_rxpending; 3923 sc->sc_rxpending = NULL; 3924 } else { 3925 /* 3926 * Normal single-descriptor receive; setup 3927 * the rcvif and packet length. 3928 */ 3929 m->m_pkthdr.rcvif = ifp; 3930 m->m_pkthdr.len = len; 3931 } 3932 3933 ifp->if_ipackets++; 3934 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 3935 3936 /* 3937 * Populate the rx status block. When there are bpf 3938 * listeners we do the additional work to provide 3939 * complete status. Otherwise we fill in only the 3940 * material required by ieee80211_input. Note that 3941 * noise setting is filled in above. 3942 */ 3943 if (ieee80211_radiotap_active(ic)) 3944 ath_rx_tap(ifp, m, rs, tsf, nf); 3945 3946 /* 3947 * From this point on we assume the frame is at least 3948 * as large as ieee80211_frame_min; verify that. 3949 */ 3950 if (len < IEEE80211_MIN_LEN) { 3951 if (!ieee80211_radiotap_active(ic)) { 3952 DPRINTF(sc, ATH_DEBUG_RECV, 3953 "%s: short packet %d\n", __func__, len); 3954 sc->sc_stats.ast_rx_tooshort++; 3955 } else { 3956 /* NB: in particular this captures ack's */ 3957 ieee80211_radiotap_rx_all(ic, m); 3958 } 3959 m_freem(m); 3960 goto rx_next; 3961 } 3962 3963 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3964 const HAL_RATE_TABLE *rt = sc->sc_currates; 3965 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 3966 3967 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 3968 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 3969 } 3970 3971 m_adj(m, -IEEE80211_CRC_LEN); 3972 3973 /* 3974 * Locate the node for sender, track state, and then 3975 * pass the (referenced) node up to the 802.11 layer 3976 * for its use. 3977 */ 3978 ni = ieee80211_find_rxnode_withkey(ic, 3979 mtod(m, const struct ieee80211_frame_min *), 3980 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 3981 IEEE80211_KEYIX_NONE : rs->rs_keyix); 3982 if (ni != NULL) { 3983 /* 3984 * Sending station is known, dispatch directly. 3985 */ 3986 sc->sc_lastrs = rs; 3987 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 3988 ieee80211_free_node(ni); 3989 /* 3990 * Arrange to update the last rx timestamp only for 3991 * frames from our ap when operating in station mode. 3992 * This assumes the rx key is always setup when 3993 * associated. 3994 */ 3995 if (ic->ic_opmode == IEEE80211_M_STA && 3996 rs->rs_keyix != HAL_RXKEYIX_INVALID) 3997 ngood++; 3998 } else { 3999 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 4000 } 4001 /* 4002 * Track rx rssi and do any rx antenna management. 4003 */ 4004 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 4005 if (sc->sc_diversity) { 4006 /* 4007 * When using fast diversity, change the default rx 4008 * antenna if diversity chooses the other antenna 3 4009 * times in a row. 4010 */ 4011 if (sc->sc_defant != rs->rs_antenna) { 4012 if (++sc->sc_rxotherant >= 3) 4013 ath_setdefantenna(sc, rs->rs_antenna); 4014 } else 4015 sc->sc_rxotherant = 0; 4016 } 4017 if (sc->sc_softled) { 4018 /* 4019 * Blink for any data frame. Otherwise do a 4020 * heartbeat-style blink when idle. The latter 4021 * is mainly for station mode where we depend on 4022 * periodic beacon frames to trigger the poll event. 4023 */ 4024 if (type == IEEE80211_FC0_TYPE_DATA) { 4025 const HAL_RATE_TABLE *rt = sc->sc_currates; 4026 ath_led_event(sc, 4027 rt->rateCodeToIndex[rs->rs_rate]); 4028 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 4029 ath_led_event(sc, 0); 4030 } 4031 rx_next: 4032 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 4033 } while (ath_rxbuf_init(sc, bf) == 0); 4034 4035 /* rx signal state monitoring */ 4036 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 4037 if (ngood) 4038 sc->sc_lastrx = tsf; 4039 4040 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 4041 #ifdef IEEE80211_SUPPORT_SUPERG 4042 ieee80211_ff_age_all(ic, 100); 4043 #endif 4044 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4045 ath_start(ifp); 4046 } 4047 #undef PA2DESC 4048 } 4049 4050 static void 4051 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 4052 { 4053 txq->axq_qnum = qnum; 4054 txq->axq_ac = 0; 4055 txq->axq_depth = 0; 4056 txq->axq_intrcnt = 0; 4057 txq->axq_link = NULL; 4058 STAILQ_INIT(&txq->axq_q); 4059 ATH_TXQ_LOCK_INIT(sc, txq); 4060 } 4061 4062 /* 4063 * Setup a h/w transmit queue. 4064 */ 4065 static struct ath_txq * 4066 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 4067 { 4068 #define N(a) (sizeof(a)/sizeof(a[0])) 4069 struct ath_hal *ah = sc->sc_ah; 4070 HAL_TXQ_INFO qi; 4071 int qnum; 4072 4073 memset(&qi, 0, sizeof(qi)); 4074 qi.tqi_subtype = subtype; 4075 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 4076 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 4077 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 4078 /* 4079 * Enable interrupts only for EOL and DESC conditions. 4080 * We mark tx descriptors to receive a DESC interrupt 4081 * when a tx queue gets deep; otherwise waiting for the 4082 * EOL to reap descriptors. Note that this is done to 4083 * reduce interrupt load and this only defers reaping 4084 * descriptors, never transmitting frames. Aside from 4085 * reducing interrupts this also permits more concurrency. 4086 * The only potential downside is if the tx queue backs 4087 * up in which case the top half of the kernel may backup 4088 * due to a lack of tx descriptors. 4089 */ 4090 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 4091 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 4092 if (qnum == -1) { 4093 /* 4094 * NB: don't print a message, this happens 4095 * normally on parts with too few tx queues 4096 */ 4097 return NULL; 4098 } 4099 if (qnum >= N(sc->sc_txq)) { 4100 device_printf(sc->sc_dev, 4101 "hal qnum %u out of range, max %zu!\n", 4102 qnum, N(sc->sc_txq)); 4103 ath_hal_releasetxqueue(ah, qnum); 4104 return NULL; 4105 } 4106 if (!ATH_TXQ_SETUP(sc, qnum)) { 4107 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4108 sc->sc_txqsetup |= 1<<qnum; 4109 } 4110 return &sc->sc_txq[qnum]; 4111 #undef N 4112 } 4113 4114 /* 4115 * Setup a hardware data transmit queue for the specified 4116 * access control. The hal may not support all requested 4117 * queues in which case it will return a reference to a 4118 * previously setup queue. We record the mapping from ac's 4119 * to h/w queues for use by ath_tx_start and also track 4120 * the set of h/w queues being used to optimize work in the 4121 * transmit interrupt handler and related routines. 4122 */ 4123 static int 4124 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4125 { 4126 #define N(a) (sizeof(a)/sizeof(a[0])) 4127 struct ath_txq *txq; 4128 4129 if (ac >= N(sc->sc_ac2q)) { 4130 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4131 ac, N(sc->sc_ac2q)); 4132 return 0; 4133 } 4134 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4135 if (txq != NULL) { 4136 txq->axq_ac = ac; 4137 sc->sc_ac2q[ac] = txq; 4138 return 1; 4139 } else 4140 return 0; 4141 #undef N 4142 } 4143 4144 /* 4145 * Update WME parameters for a transmit queue. 4146 */ 4147 static int 4148 ath_txq_update(struct ath_softc *sc, int ac) 4149 { 4150 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4151 #define ATH_TXOP_TO_US(v) (v<<5) 4152 struct ifnet *ifp = sc->sc_ifp; 4153 struct ieee80211com *ic = ifp->if_l2com; 4154 struct ath_txq *txq = sc->sc_ac2q[ac]; 4155 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4156 struct ath_hal *ah = sc->sc_ah; 4157 HAL_TXQ_INFO qi; 4158 4159 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4160 #ifdef IEEE80211_SUPPORT_TDMA 4161 if (sc->sc_tdma) { 4162 /* 4163 * AIFS is zero so there's no pre-transmit wait. The 4164 * burst time defines the slot duration and is configured 4165 * through net80211. The QCU is setup to not do post-xmit 4166 * back off, lockout all lower-priority QCU's, and fire 4167 * off the DMA beacon alert timer which is setup based 4168 * on the slot configuration. 4169 */ 4170 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4171 | HAL_TXQ_TXERRINT_ENABLE 4172 | HAL_TXQ_TXURNINT_ENABLE 4173 | HAL_TXQ_TXEOLINT_ENABLE 4174 | HAL_TXQ_DBA_GATED 4175 | HAL_TXQ_BACKOFF_DISABLE 4176 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4177 ; 4178 qi.tqi_aifs = 0; 4179 /* XXX +dbaprep? */ 4180 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4181 qi.tqi_burstTime = qi.tqi_readyTime; 4182 } else { 4183 #endif 4184 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4185 | HAL_TXQ_TXERRINT_ENABLE 4186 | HAL_TXQ_TXDESCINT_ENABLE 4187 | HAL_TXQ_TXURNINT_ENABLE 4188 ; 4189 qi.tqi_aifs = wmep->wmep_aifsn; 4190 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4191 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4192 qi.tqi_readyTime = 0; 4193 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 4194 #ifdef IEEE80211_SUPPORT_TDMA 4195 } 4196 #endif 4197 4198 DPRINTF(sc, ATH_DEBUG_RESET, 4199 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4200 __func__, txq->axq_qnum, qi.tqi_qflags, 4201 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4202 4203 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4204 if_printf(ifp, "unable to update hardware queue " 4205 "parameters for %s traffic!\n", 4206 ieee80211_wme_acnames[ac]); 4207 return 0; 4208 } else { 4209 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4210 return 1; 4211 } 4212 #undef ATH_TXOP_TO_US 4213 #undef ATH_EXPONENT_TO_VALUE 4214 } 4215 4216 /* 4217 * Callback from the 802.11 layer to update WME parameters. 4218 */ 4219 static int 4220 ath_wme_update(struct ieee80211com *ic) 4221 { 4222 struct ath_softc *sc = ic->ic_ifp->if_softc; 4223 4224 return !ath_txq_update(sc, WME_AC_BE) || 4225 !ath_txq_update(sc, WME_AC_BK) || 4226 !ath_txq_update(sc, WME_AC_VI) || 4227 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4228 } 4229 4230 /* 4231 * Reclaim resources for a setup queue. 4232 */ 4233 static void 4234 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4235 { 4236 4237 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4238 ATH_TXQ_LOCK_DESTROY(txq); 4239 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4240 } 4241 4242 /* 4243 * Reclaim all tx queue resources. 4244 */ 4245 static void 4246 ath_tx_cleanup(struct ath_softc *sc) 4247 { 4248 int i; 4249 4250 ATH_TXBUF_LOCK_DESTROY(sc); 4251 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4252 if (ATH_TXQ_SETUP(sc, i)) 4253 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4254 } 4255 4256 /* 4257 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 4258 * using the current rates in sc_rixmap. 4259 */ 4260 static __inline int 4261 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 4262 { 4263 int rix = sc->sc_rixmap[rate]; 4264 /* NB: return lowest rix for invalid rate */ 4265 return (rix == 0xff ? 0 : rix); 4266 } 4267 4268 /* 4269 * Reclaim mbuf resources. For fragmented frames we 4270 * need to claim each frag chained with m_nextpkt. 4271 */ 4272 static void 4273 ath_freetx(struct mbuf *m) 4274 { 4275 struct mbuf *next; 4276 4277 do { 4278 next = m->m_nextpkt; 4279 m->m_nextpkt = NULL; 4280 m_freem(m); 4281 } while ((m = next) != NULL); 4282 } 4283 4284 static int 4285 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 4286 { 4287 struct mbuf *m; 4288 int error; 4289 4290 /* 4291 * Load the DMA map so any coalescing is done. This 4292 * also calculates the number of descriptors we need. 4293 */ 4294 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4295 bf->bf_segs, &bf->bf_nseg, 4296 BUS_DMA_NOWAIT); 4297 if (error == EFBIG) { 4298 /* XXX packet requires too many descriptors */ 4299 bf->bf_nseg = ATH_TXDESC+1; 4300 } else if (error != 0) { 4301 sc->sc_stats.ast_tx_busdma++; 4302 ath_freetx(m0); 4303 return error; 4304 } 4305 /* 4306 * Discard null packets and check for packets that 4307 * require too many TX descriptors. We try to convert 4308 * the latter to a cluster. 4309 */ 4310 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 4311 sc->sc_stats.ast_tx_linear++; 4312 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); 4313 if (m == NULL) { 4314 ath_freetx(m0); 4315 sc->sc_stats.ast_tx_nombuf++; 4316 return ENOMEM; 4317 } 4318 m0 = m; 4319 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4320 bf->bf_segs, &bf->bf_nseg, 4321 BUS_DMA_NOWAIT); 4322 if (error != 0) { 4323 sc->sc_stats.ast_tx_busdma++; 4324 ath_freetx(m0); 4325 return error; 4326 } 4327 KASSERT(bf->bf_nseg <= ATH_TXDESC, 4328 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 4329 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 4330 sc->sc_stats.ast_tx_nodata++; 4331 ath_freetx(m0); 4332 return EIO; 4333 } 4334 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 4335 __func__, m0, m0->m_pkthdr.len); 4336 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 4337 bf->bf_m = m0; 4338 4339 return 0; 4340 } 4341 4342 static void 4343 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 4344 { 4345 struct ath_hal *ah = sc->sc_ah; 4346 struct ath_desc *ds, *ds0; 4347 int i; 4348 4349 /* 4350 * Fillin the remainder of the descriptor info. 4351 */ 4352 ds0 = ds = bf->bf_desc; 4353 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4354 ds->ds_data = bf->bf_segs[i].ds_addr; 4355 if (i == bf->bf_nseg - 1) 4356 ds->ds_link = 0; 4357 else 4358 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4359 ath_hal_filltxdesc(ah, ds 4360 , bf->bf_segs[i].ds_len /* segment length */ 4361 , i == 0 /* first segment */ 4362 , i == bf->bf_nseg - 1 /* last segment */ 4363 , ds0 /* first descriptor */ 4364 ); 4365 DPRINTF(sc, ATH_DEBUG_XMIT, 4366 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4367 __func__, i, ds->ds_link, ds->ds_data, 4368 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4369 } 4370 /* 4371 * Insert the frame on the outbound list and pass it on 4372 * to the hardware. Multicast frames buffered for power 4373 * save stations and transmit from the CAB queue are stored 4374 * on a s/w only queue and loaded on to the CAB queue in 4375 * the SWBA handler since frames only go out on DTIM and 4376 * to avoid possible races. 4377 */ 4378 ATH_TXQ_LOCK(txq); 4379 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 4380 ("busy status 0x%x", bf->bf_flags)); 4381 if (txq->axq_qnum != ATH_TXQ_SWQ) { 4382 #ifdef IEEE80211_SUPPORT_TDMA 4383 int qbusy; 4384 4385 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4386 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 4387 if (txq->axq_link == NULL) { 4388 /* 4389 * Be careful writing the address to TXDP. If 4390 * the tx q is enabled then this write will be 4391 * ignored. Normally this is not an issue but 4392 * when tdma is in use and the q is beacon gated 4393 * this race can occur. If the q is busy then 4394 * defer the work to later--either when another 4395 * packet comes along or when we prepare a beacon 4396 * frame at SWBA. 4397 */ 4398 if (!qbusy) { 4399 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4400 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 4401 DPRINTF(sc, ATH_DEBUG_XMIT, 4402 "%s: TXDP[%u] = %p (%p) depth %d\n", 4403 __func__, txq->axq_qnum, 4404 (caddr_t)bf->bf_daddr, bf->bf_desc, 4405 txq->axq_depth); 4406 } else { 4407 txq->axq_flags |= ATH_TXQ_PUTPENDING; 4408 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 4409 "%s: Q%u busy, defer enable\n", __func__, 4410 txq->axq_qnum); 4411 } 4412 } else { 4413 *txq->axq_link = bf->bf_daddr; 4414 DPRINTF(sc, ATH_DEBUG_XMIT, 4415 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4416 txq->axq_qnum, txq->axq_link, 4417 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4418 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) { 4419 /* 4420 * The q was busy when we previously tried 4421 * to write the address of the first buffer 4422 * in the chain. Since it's not busy now 4423 * handle this chore. We are certain the 4424 * buffer at the front is the right one since 4425 * axq_link is NULL only when the buffer list 4426 * is/was empty. 4427 */ 4428 ath_hal_puttxbuf(ah, txq->axq_qnum, 4429 STAILQ_FIRST(&txq->axq_q)->bf_daddr); 4430 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 4431 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 4432 "%s: Q%u restarted\n", __func__, 4433 txq->axq_qnum); 4434 } 4435 } 4436 #else 4437 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4438 if (txq->axq_link == NULL) { 4439 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4440 DPRINTF(sc, ATH_DEBUG_XMIT, 4441 "%s: TXDP[%u] = %p (%p) depth %d\n", 4442 __func__, txq->axq_qnum, 4443 (caddr_t)bf->bf_daddr, bf->bf_desc, 4444 txq->axq_depth); 4445 } else { 4446 *txq->axq_link = bf->bf_daddr; 4447 DPRINTF(sc, ATH_DEBUG_XMIT, 4448 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4449 txq->axq_qnum, txq->axq_link, 4450 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4451 } 4452 #endif /* IEEE80211_SUPPORT_TDMA */ 4453 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4454 ath_hal_txstart(ah, txq->axq_qnum); 4455 } else { 4456 if (txq->axq_link != NULL) { 4457 struct ath_buf *last = ATH_TXQ_LAST(txq); 4458 struct ieee80211_frame *wh; 4459 4460 /* mark previous frame */ 4461 wh = mtod(last->bf_m, struct ieee80211_frame *); 4462 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 4463 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 4464 BUS_DMASYNC_PREWRITE); 4465 4466 /* link descriptor */ 4467 *txq->axq_link = bf->bf_daddr; 4468 } 4469 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4470 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4471 } 4472 ATH_TXQ_UNLOCK(txq); 4473 } 4474 4475 static int 4476 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 4477 struct mbuf *m0) 4478 { 4479 struct ieee80211vap *vap = ni->ni_vap; 4480 struct ath_vap *avp = ATH_VAP(vap); 4481 struct ath_hal *ah = sc->sc_ah; 4482 struct ifnet *ifp = sc->sc_ifp; 4483 struct ieee80211com *ic = ifp->if_l2com; 4484 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 4485 int error, iswep, ismcast, isfrag, ismrr; 4486 int keyix, hdrlen, pktlen, try0; 4487 u_int8_t rix, txrate, ctsrate; 4488 u_int8_t cix = 0xff; /* NB: silence compiler */ 4489 struct ath_desc *ds; 4490 struct ath_txq *txq; 4491 struct ieee80211_frame *wh; 4492 u_int subtype, flags, ctsduration; 4493 HAL_PKT_TYPE atype; 4494 const HAL_RATE_TABLE *rt; 4495 HAL_BOOL shortPreamble; 4496 struct ath_node *an; 4497 u_int pri; 4498 4499 wh = mtod(m0, struct ieee80211_frame *); 4500 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 4501 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 4502 isfrag = m0->m_flags & M_FRAG; 4503 hdrlen = ieee80211_anyhdrsize(wh); 4504 /* 4505 * Packet length must not include any 4506 * pad bytes; deduct them here. 4507 */ 4508 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 4509 4510 if (iswep) { 4511 const struct ieee80211_cipher *cip; 4512 struct ieee80211_key *k; 4513 4514 /* 4515 * Construct the 802.11 header+trailer for an encrypted 4516 * frame. The only reason this can fail is because of an 4517 * unknown or unsupported cipher/key type. 4518 */ 4519 k = ieee80211_crypto_encap(ni, m0); 4520 if (k == NULL) { 4521 /* 4522 * This can happen when the key is yanked after the 4523 * frame was queued. Just discard the frame; the 4524 * 802.11 layer counts failures and provides 4525 * debugging/diagnostics. 4526 */ 4527 ath_freetx(m0); 4528 return EIO; 4529 } 4530 /* 4531 * Adjust the packet + header lengths for the crypto 4532 * additions and calculate the h/w key index. When 4533 * a s/w mic is done the frame will have had any mic 4534 * added to it prior to entry so m0->m_pkthdr.len will 4535 * account for it. Otherwise we need to add it to the 4536 * packet length. 4537 */ 4538 cip = k->wk_cipher; 4539 hdrlen += cip->ic_header; 4540 pktlen += cip->ic_header + cip->ic_trailer; 4541 /* NB: frags always have any TKIP MIC done in s/w */ 4542 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 4543 pktlen += cip->ic_miclen; 4544 keyix = k->wk_keyix; 4545 4546 /* packet header may have moved, reset our local pointer */ 4547 wh = mtod(m0, struct ieee80211_frame *); 4548 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 4549 /* 4550 * Use station key cache slot, if assigned. 4551 */ 4552 keyix = ni->ni_ucastkey.wk_keyix; 4553 if (keyix == IEEE80211_KEYIX_NONE) 4554 keyix = HAL_TXKEYIX_INVALID; 4555 } else 4556 keyix = HAL_TXKEYIX_INVALID; 4557 4558 pktlen += IEEE80211_CRC_LEN; 4559 4560 /* 4561 * Load the DMA map so any coalescing is done. This 4562 * also calculates the number of descriptors we need. 4563 */ 4564 error = ath_tx_dmasetup(sc, bf, m0); 4565 if (error != 0) 4566 return error; 4567 bf->bf_node = ni; /* NB: held reference */ 4568 m0 = bf->bf_m; /* NB: may have changed */ 4569 wh = mtod(m0, struct ieee80211_frame *); 4570 4571 /* setup descriptors */ 4572 ds = bf->bf_desc; 4573 rt = sc->sc_currates; 4574 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 4575 4576 /* 4577 * NB: the 802.11 layer marks whether or not we should 4578 * use short preamble based on the current mode and 4579 * negotiated parameters. 4580 */ 4581 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 4582 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 4583 shortPreamble = AH_TRUE; 4584 sc->sc_stats.ast_tx_shortpre++; 4585 } else { 4586 shortPreamble = AH_FALSE; 4587 } 4588 4589 an = ATH_NODE(ni); 4590 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 4591 ismrr = 0; /* default no multi-rate retry*/ 4592 pri = M_WME_GETAC(m0); /* honor classification */ 4593 /* XXX use txparams instead of fixed values */ 4594 /* 4595 * Calculate Atheros packet type from IEEE80211 packet header, 4596 * setup for rate calculations, and select h/w transmit queue. 4597 */ 4598 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 4599 case IEEE80211_FC0_TYPE_MGT: 4600 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4601 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 4602 atype = HAL_PKT_TYPE_BEACON; 4603 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4604 atype = HAL_PKT_TYPE_PROBE_RESP; 4605 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 4606 atype = HAL_PKT_TYPE_ATIM; 4607 else 4608 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 4609 rix = an->an_mgmtrix; 4610 txrate = rt->info[rix].rateCode; 4611 if (shortPreamble) 4612 txrate |= rt->info[rix].shortPreamble; 4613 try0 = ATH_TXMGTTRY; 4614 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4615 break; 4616 case IEEE80211_FC0_TYPE_CTL: 4617 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 4618 rix = an->an_mgmtrix; 4619 txrate = rt->info[rix].rateCode; 4620 if (shortPreamble) 4621 txrate |= rt->info[rix].shortPreamble; 4622 try0 = ATH_TXMGTTRY; 4623 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4624 break; 4625 case IEEE80211_FC0_TYPE_DATA: 4626 atype = HAL_PKT_TYPE_NORMAL; /* default */ 4627 /* 4628 * Data frames: multicast frames go out at a fixed rate, 4629 * EAPOL frames use the mgmt frame rate; otherwise consult 4630 * the rate control module for the rate to use. 4631 */ 4632 if (ismcast) { 4633 rix = an->an_mcastrix; 4634 txrate = rt->info[rix].rateCode; 4635 if (shortPreamble) 4636 txrate |= rt->info[rix].shortPreamble; 4637 try0 = 1; 4638 } else if (m0->m_flags & M_EAPOL) { 4639 /* XXX? maybe always use long preamble? */ 4640 rix = an->an_mgmtrix; 4641 txrate = rt->info[rix].rateCode; 4642 if (shortPreamble) 4643 txrate |= rt->info[rix].shortPreamble; 4644 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 4645 } else { 4646 ath_rate_findrate(sc, an, shortPreamble, pktlen, 4647 &rix, &try0, &txrate); 4648 sc->sc_txrix = rix; /* for LED blinking */ 4649 sc->sc_lastdatarix = rix; /* for fast frames */ 4650 if (try0 != ATH_TXMAXTRY) 4651 ismrr = 1; 4652 } 4653 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 4654 flags |= HAL_TXDESC_NOACK; 4655 break; 4656 default: 4657 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 4658 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 4659 /* XXX statistic */ 4660 ath_freetx(m0); 4661 return EIO; 4662 } 4663 txq = sc->sc_ac2q[pri]; 4664 4665 /* 4666 * When servicing one or more stations in power-save mode 4667 * (or) if there is some mcast data waiting on the mcast 4668 * queue (to prevent out of order delivery) multicast 4669 * frames must be buffered until after the beacon. 4670 */ 4671 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 4672 txq = &avp->av_mcastq; 4673 4674 /* 4675 * Calculate miscellaneous flags. 4676 */ 4677 if (ismcast) { 4678 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 4679 } else if (pktlen > vap->iv_rtsthreshold && 4680 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 4681 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 4682 cix = rt->info[rix].controlRate; 4683 sc->sc_stats.ast_tx_rts++; 4684 } 4685 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 4686 sc->sc_stats.ast_tx_noack++; 4687 #ifdef IEEE80211_SUPPORT_TDMA 4688 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 4689 DPRINTF(sc, ATH_DEBUG_TDMA, 4690 "%s: discard frame, ACK required w/ TDMA\n", __func__); 4691 sc->sc_stats.ast_tdma_ack++; 4692 ath_freetx(m0); 4693 return EIO; 4694 } 4695 #endif 4696 4697 /* 4698 * If 802.11g protection is enabled, determine whether 4699 * to use RTS/CTS or just CTS. Note that this is only 4700 * done for OFDM unicast frames. 4701 */ 4702 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 4703 rt->info[rix].phy == IEEE80211_T_OFDM && 4704 (flags & HAL_TXDESC_NOACK) == 0) { 4705 /* XXX fragments must use CCK rates w/ protection */ 4706 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4707 flags |= HAL_TXDESC_RTSENA; 4708 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4709 flags |= HAL_TXDESC_CTSENA; 4710 if (isfrag) { 4711 /* 4712 * For frags it would be desirable to use the 4713 * highest CCK rate for RTS/CTS. But stations 4714 * farther away may detect it at a lower CCK rate 4715 * so use the configured protection rate instead 4716 * (for now). 4717 */ 4718 cix = rt->info[sc->sc_protrix].controlRate; 4719 } else 4720 cix = rt->info[sc->sc_protrix].controlRate; 4721 sc->sc_stats.ast_tx_protect++; 4722 } 4723 4724 /* 4725 * Calculate duration. This logically belongs in the 802.11 4726 * layer but it lacks sufficient information to calculate it. 4727 */ 4728 if ((flags & HAL_TXDESC_NOACK) == 0 && 4729 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 4730 u_int16_t dur; 4731 if (shortPreamble) 4732 dur = rt->info[rix].spAckDuration; 4733 else 4734 dur = rt->info[rix].lpAckDuration; 4735 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 4736 dur += dur; /* additional SIFS+ACK */ 4737 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 4738 /* 4739 * Include the size of next fragment so NAV is 4740 * updated properly. The last fragment uses only 4741 * the ACK duration 4742 */ 4743 dur += ath_hal_computetxtime(ah, rt, 4744 m0->m_nextpkt->m_pkthdr.len, 4745 rix, shortPreamble); 4746 } 4747 if (isfrag) { 4748 /* 4749 * Force hardware to use computed duration for next 4750 * fragment by disabling multi-rate retry which updates 4751 * duration based on the multi-rate duration table. 4752 */ 4753 ismrr = 0; 4754 try0 = ATH_TXMGTTRY; /* XXX? */ 4755 } 4756 *(u_int16_t *)wh->i_dur = htole16(dur); 4757 } 4758 4759 /* 4760 * Calculate RTS/CTS rate and duration if needed. 4761 */ 4762 ctsduration = 0; 4763 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 4764 /* 4765 * CTS transmit rate is derived from the transmit rate 4766 * by looking in the h/w rate table. We must also factor 4767 * in whether or not a short preamble is to be used. 4768 */ 4769 /* NB: cix is set above where RTS/CTS is enabled */ 4770 KASSERT(cix != 0xff, ("cix not setup")); 4771 ctsrate = rt->info[cix].rateCode; 4772 /* 4773 * Compute the transmit duration based on the frame 4774 * size and the size of an ACK frame. We call into the 4775 * HAL to do the computation since it depends on the 4776 * characteristics of the actual PHY being used. 4777 * 4778 * NB: CTS is assumed the same size as an ACK so we can 4779 * use the precalculated ACK durations. 4780 */ 4781 if (shortPreamble) { 4782 ctsrate |= rt->info[cix].shortPreamble; 4783 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4784 ctsduration += rt->info[cix].spAckDuration; 4785 ctsduration += ath_hal_computetxtime(ah, 4786 rt, pktlen, rix, AH_TRUE); 4787 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4788 ctsduration += rt->info[rix].spAckDuration; 4789 } else { 4790 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4791 ctsduration += rt->info[cix].lpAckDuration; 4792 ctsduration += ath_hal_computetxtime(ah, 4793 rt, pktlen, rix, AH_FALSE); 4794 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4795 ctsduration += rt->info[rix].lpAckDuration; 4796 } 4797 /* 4798 * Must disable multi-rate retry when using RTS/CTS. 4799 */ 4800 ismrr = 0; 4801 try0 = ATH_TXMGTTRY; /* XXX */ 4802 } else 4803 ctsrate = 0; 4804 4805 /* 4806 * At this point we are committed to sending the frame 4807 * and we don't need to look at m_nextpkt; clear it in 4808 * case this frame is part of frag chain. 4809 */ 4810 m0->m_nextpkt = NULL; 4811 4812 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 4813 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 4814 sc->sc_hwmap[rix].ieeerate, -1); 4815 4816 if (ieee80211_radiotap_active_vap(vap)) { 4817 u_int64_t tsf = ath_hal_gettsf64(ah); 4818 4819 sc->sc_tx_th.wt_tsf = htole64(tsf); 4820 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 4821 if (iswep) 4822 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4823 if (isfrag) 4824 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 4825 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 4826 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 4827 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 4828 4829 ieee80211_radiotap_tx(vap, m0); 4830 } 4831 4832 /* 4833 * Determine if a tx interrupt should be generated for 4834 * this descriptor. We take a tx interrupt to reap 4835 * descriptors when the h/w hits an EOL condition or 4836 * when the descriptor is specifically marked to generate 4837 * an interrupt. We periodically mark descriptors in this 4838 * way to insure timely replenishing of the supply needed 4839 * for sending frames. Defering interrupts reduces system 4840 * load and potentially allows more concurrent work to be 4841 * done but if done to aggressively can cause senders to 4842 * backup. 4843 * 4844 * NB: use >= to deal with sc_txintrperiod changing 4845 * dynamically through sysctl. 4846 */ 4847 if (flags & HAL_TXDESC_INTREQ) { 4848 txq->axq_intrcnt = 0; 4849 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 4850 flags |= HAL_TXDESC_INTREQ; 4851 txq->axq_intrcnt = 0; 4852 } 4853 4854 /* 4855 * Formulate first tx descriptor with tx controls. 4856 */ 4857 /* XXX check return value? */ 4858 ath_hal_setuptxdesc(ah, ds 4859 , pktlen /* packet length */ 4860 , hdrlen /* header length */ 4861 , atype /* Atheros packet type */ 4862 , ni->ni_txpower /* txpower */ 4863 , txrate, try0 /* series 0 rate/tries */ 4864 , keyix /* key cache index */ 4865 , sc->sc_txantenna /* antenna mode */ 4866 , flags /* flags */ 4867 , ctsrate /* rts/cts rate */ 4868 , ctsduration /* rts/cts duration */ 4869 ); 4870 bf->bf_txflags = flags; 4871 /* 4872 * Setup the multi-rate retry state only when we're 4873 * going to use it. This assumes ath_hal_setuptxdesc 4874 * initializes the descriptors (so we don't have to) 4875 * when the hardware supports multi-rate retry and 4876 * we don't use it. 4877 */ 4878 if (ismrr) 4879 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4880 4881 ath_tx_handoff(sc, txq, bf); 4882 return 0; 4883 } 4884 4885 /* 4886 * Process completed xmit descriptors from the specified queue. 4887 */ 4888 static int 4889 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4890 { 4891 struct ath_hal *ah = sc->sc_ah; 4892 struct ifnet *ifp = sc->sc_ifp; 4893 struct ieee80211com *ic = ifp->if_l2com; 4894 struct ath_buf *bf, *last; 4895 struct ath_desc *ds, *ds0; 4896 struct ath_tx_status *ts; 4897 struct ieee80211_node *ni; 4898 struct ath_node *an; 4899 int sr, lr, pri, nacked; 4900 HAL_STATUS status; 4901 4902 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4903 __func__, txq->axq_qnum, 4904 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4905 txq->axq_link); 4906 nacked = 0; 4907 for (;;) { 4908 ATH_TXQ_LOCK(txq); 4909 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4910 bf = STAILQ_FIRST(&txq->axq_q); 4911 if (bf == NULL) { 4912 ATH_TXQ_UNLOCK(txq); 4913 break; 4914 } 4915 ds0 = &bf->bf_desc[0]; 4916 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4917 ts = &bf->bf_status.ds_txstat; 4918 status = ath_hal_txprocdesc(ah, ds, ts); 4919 #ifdef ATH_DEBUG 4920 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4921 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4922 status == HAL_OK); 4923 #endif 4924 if (status == HAL_EINPROGRESS) { 4925 ATH_TXQ_UNLOCK(txq); 4926 break; 4927 } 4928 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4929 #ifdef IEEE80211_SUPPORT_TDMA 4930 if (txq->axq_depth > 0) { 4931 /* 4932 * More frames follow. Mark the buffer busy 4933 * so it's not re-used while the hardware may 4934 * still re-read the link field in the descriptor. 4935 */ 4936 bf->bf_flags |= ATH_BUF_BUSY; 4937 } else 4938 #else 4939 if (txq->axq_depth == 0) 4940 #endif 4941 txq->axq_link = NULL; 4942 ATH_TXQ_UNLOCK(txq); 4943 4944 ni = bf->bf_node; 4945 if (ni != NULL) { 4946 an = ATH_NODE(ni); 4947 if (ts->ts_status == 0) { 4948 u_int8_t txant = ts->ts_antenna; 4949 sc->sc_stats.ast_ant_tx[txant]++; 4950 sc->sc_ant_tx[txant]++; 4951 if (ts->ts_finaltsi != 0) 4952 sc->sc_stats.ast_tx_altrate++; 4953 pri = M_WME_GETAC(bf->bf_m); 4954 if (pri >= WME_AC_VO) 4955 ic->ic_wme.wme_hipri_traffic++; 4956 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0) 4957 ni->ni_inact = ni->ni_inact_reload; 4958 } else { 4959 if (ts->ts_status & HAL_TXERR_XRETRY) 4960 sc->sc_stats.ast_tx_xretries++; 4961 if (ts->ts_status & HAL_TXERR_FIFO) 4962 sc->sc_stats.ast_tx_fifoerr++; 4963 if (ts->ts_status & HAL_TXERR_FILT) 4964 sc->sc_stats.ast_tx_filtered++; 4965 if (bf->bf_m->m_flags & M_FF) 4966 sc->sc_stats.ast_ff_txerr++; 4967 } 4968 sr = ts->ts_shortretry; 4969 lr = ts->ts_longretry; 4970 sc->sc_stats.ast_tx_shortretry += sr; 4971 sc->sc_stats.ast_tx_longretry += lr; 4972 /* 4973 * Hand the descriptor to the rate control algorithm. 4974 */ 4975 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4976 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) { 4977 /* 4978 * If frame was ack'd update statistics, 4979 * including the last rx time used to 4980 * workaround phantom bmiss interrupts. 4981 */ 4982 if (ts->ts_status == 0) { 4983 nacked++; 4984 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4985 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4986 ts->ts_rssi); 4987 } 4988 ath_rate_tx_complete(sc, an, bf); 4989 } 4990 /* 4991 * Do any tx complete callback. Note this must 4992 * be done before releasing the node reference. 4993 */ 4994 if (bf->bf_m->m_flags & M_TXCB) 4995 ieee80211_process_callback(ni, bf->bf_m, 4996 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ? 4997 ts->ts_status : HAL_TXERR_XRETRY); 4998 ieee80211_free_node(ni); 4999 } 5000 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 5001 BUS_DMASYNC_POSTWRITE); 5002 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5003 5004 m_freem(bf->bf_m); 5005 bf->bf_m = NULL; 5006 bf->bf_node = NULL; 5007 5008 ATH_TXBUF_LOCK(sc); 5009 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5010 if (last != NULL) 5011 last->bf_flags &= ~ATH_BUF_BUSY; 5012 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5013 ATH_TXBUF_UNLOCK(sc); 5014 } 5015 #ifdef IEEE80211_SUPPORT_SUPERG 5016 /* 5017 * Flush fast-frame staging queue when traffic slows. 5018 */ 5019 if (txq->axq_depth <= 1) 5020 ieee80211_ff_flush(ic, txq->axq_ac); 5021 #endif 5022 return nacked; 5023 } 5024 5025 static __inline int 5026 txqactive(struct ath_hal *ah, int qnum) 5027 { 5028 u_int32_t txqs = 1<<qnum; 5029 ath_hal_gettxintrtxqs(ah, &txqs); 5030 return (txqs & (1<<qnum)); 5031 } 5032 5033 /* 5034 * Deferred processing of transmit interrupt; special-cased 5035 * for a single hardware transmit queue (e.g. 5210 and 5211). 5036 */ 5037 static void 5038 ath_tx_proc_q0(void *arg, int npending) 5039 { 5040 struct ath_softc *sc = arg; 5041 struct ifnet *ifp = sc->sc_ifp; 5042 5043 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 5044 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5045 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5046 ath_tx_processq(sc, sc->sc_cabq); 5047 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5048 sc->sc_wd_timer = 0; 5049 5050 if (sc->sc_softled) 5051 ath_led_event(sc, sc->sc_txrix); 5052 5053 ath_start(ifp); 5054 } 5055 5056 /* 5057 * Deferred processing of transmit interrupt; special-cased 5058 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 5059 */ 5060 static void 5061 ath_tx_proc_q0123(void *arg, int npending) 5062 { 5063 struct ath_softc *sc = arg; 5064 struct ifnet *ifp = sc->sc_ifp; 5065 int nacked; 5066 5067 /* 5068 * Process each active queue. 5069 */ 5070 nacked = 0; 5071 if (txqactive(sc->sc_ah, 0)) 5072 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 5073 if (txqactive(sc->sc_ah, 1)) 5074 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 5075 if (txqactive(sc->sc_ah, 2)) 5076 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 5077 if (txqactive(sc->sc_ah, 3)) 5078 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 5079 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5080 ath_tx_processq(sc, sc->sc_cabq); 5081 if (nacked) 5082 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5083 5084 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5085 sc->sc_wd_timer = 0; 5086 5087 if (sc->sc_softled) 5088 ath_led_event(sc, sc->sc_txrix); 5089 5090 ath_start(ifp); 5091 } 5092 5093 /* 5094 * Deferred processing of transmit interrupt. 5095 */ 5096 static void 5097 ath_tx_proc(void *arg, int npending) 5098 { 5099 struct ath_softc *sc = arg; 5100 struct ifnet *ifp = sc->sc_ifp; 5101 int i, nacked; 5102 5103 /* 5104 * Process each active queue. 5105 */ 5106 nacked = 0; 5107 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5108 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 5109 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 5110 if (nacked) 5111 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5112 5113 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5114 sc->sc_wd_timer = 0; 5115 5116 if (sc->sc_softled) 5117 ath_led_event(sc, sc->sc_txrix); 5118 5119 ath_start(ifp); 5120 } 5121 5122 static void 5123 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 5124 { 5125 #ifdef ATH_DEBUG 5126 struct ath_hal *ah = sc->sc_ah; 5127 #endif 5128 struct ieee80211_node *ni; 5129 struct ath_buf *bf; 5130 u_int ix; 5131 5132 /* 5133 * NB: this assumes output has been stopped and 5134 * we do not need to block ath_tx_proc 5135 */ 5136 ATH_TXBUF_LOCK(sc); 5137 bf = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5138 if (bf != NULL) 5139 bf->bf_flags &= ~ATH_BUF_BUSY; 5140 ATH_TXBUF_UNLOCK(sc); 5141 for (ix = 0;; ix++) { 5142 ATH_TXQ_LOCK(txq); 5143 bf = STAILQ_FIRST(&txq->axq_q); 5144 if (bf == NULL) { 5145 txq->axq_link = NULL; 5146 ATH_TXQ_UNLOCK(txq); 5147 break; 5148 } 5149 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 5150 ATH_TXQ_UNLOCK(txq); 5151 #ifdef ATH_DEBUG 5152 if (sc->sc_debug & ATH_DEBUG_RESET) { 5153 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5154 5155 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, 5156 ath_hal_txprocdesc(ah, bf->bf_desc, 5157 &bf->bf_status.ds_txstat) == HAL_OK); 5158 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 5159 bf->bf_m->m_len, 0, -1); 5160 } 5161 #endif /* ATH_DEBUG */ 5162 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5163 ni = bf->bf_node; 5164 bf->bf_node = NULL; 5165 if (ni != NULL) { 5166 /* 5167 * Do any callback and reclaim the node reference. 5168 */ 5169 if (bf->bf_m->m_flags & M_TXCB) 5170 ieee80211_process_callback(ni, bf->bf_m, -1); 5171 ieee80211_free_node(ni); 5172 } 5173 m_freem(bf->bf_m); 5174 bf->bf_m = NULL; 5175 bf->bf_flags &= ~ATH_BUF_BUSY; 5176 5177 ATH_TXBUF_LOCK(sc); 5178 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5179 ATH_TXBUF_UNLOCK(sc); 5180 } 5181 } 5182 5183 static void 5184 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5185 { 5186 struct ath_hal *ah = sc->sc_ah; 5187 5188 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5189 __func__, txq->axq_qnum, 5190 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5191 txq->axq_link); 5192 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5193 } 5194 5195 /* 5196 * Drain the transmit queues and reclaim resources. 5197 */ 5198 static void 5199 ath_draintxq(struct ath_softc *sc) 5200 { 5201 struct ath_hal *ah = sc->sc_ah; 5202 struct ifnet *ifp = sc->sc_ifp; 5203 int i; 5204 5205 /* XXX return value */ 5206 if (!sc->sc_invalid) { 5207 /* don't touch the hardware if marked invalid */ 5208 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5209 __func__, sc->sc_bhalq, 5210 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5211 NULL); 5212 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5213 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5214 if (ATH_TXQ_SETUP(sc, i)) 5215 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5216 } 5217 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5218 if (ATH_TXQ_SETUP(sc, i)) 5219 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5220 #ifdef ATH_DEBUG 5221 if (sc->sc_debug & ATH_DEBUG_RESET) { 5222 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 5223 if (bf != NULL && bf->bf_m != NULL) { 5224 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5225 ath_hal_txprocdesc(ah, bf->bf_desc, 5226 &bf->bf_status.ds_txstat) == HAL_OK); 5227 ieee80211_dump_pkt(ifp->if_l2com, 5228 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 5229 0, -1); 5230 } 5231 } 5232 #endif /* ATH_DEBUG */ 5233 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5234 sc->sc_wd_timer = 0; 5235 } 5236 5237 /* 5238 * Disable the receive h/w in preparation for a reset. 5239 */ 5240 static void 5241 ath_stoprecv(struct ath_softc *sc) 5242 { 5243 #define PA2DESC(_sc, _pa) \ 5244 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 5245 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 5246 struct ath_hal *ah = sc->sc_ah; 5247 5248 ath_hal_stoppcurecv(ah); /* disable PCU */ 5249 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 5250 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 5251 DELAY(3000); /* 3ms is long enough for 1 frame */ 5252 #ifdef ATH_DEBUG 5253 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 5254 struct ath_buf *bf; 5255 u_int ix; 5256 5257 printf("%s: rx queue %p, link %p\n", __func__, 5258 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 5259 ix = 0; 5260 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5261 struct ath_desc *ds = bf->bf_desc; 5262 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5263 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 5264 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 5265 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 5266 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 5267 ix++; 5268 } 5269 } 5270 #endif 5271 if (sc->sc_rxpending != NULL) { 5272 m_freem(sc->sc_rxpending); 5273 sc->sc_rxpending = NULL; 5274 } 5275 sc->sc_rxlink = NULL; /* just in case */ 5276 #undef PA2DESC 5277 } 5278 5279 /* 5280 * Enable the receive h/w following a reset. 5281 */ 5282 static int 5283 ath_startrecv(struct ath_softc *sc) 5284 { 5285 struct ath_hal *ah = sc->sc_ah; 5286 struct ath_buf *bf; 5287 5288 sc->sc_rxlink = NULL; 5289 sc->sc_rxpending = NULL; 5290 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5291 int error = ath_rxbuf_init(sc, bf); 5292 if (error != 0) { 5293 DPRINTF(sc, ATH_DEBUG_RECV, 5294 "%s: ath_rxbuf_init failed %d\n", 5295 __func__, error); 5296 return error; 5297 } 5298 } 5299 5300 bf = STAILQ_FIRST(&sc->sc_rxbuf); 5301 ath_hal_putrxbuf(ah, bf->bf_daddr); 5302 ath_hal_rxena(ah); /* enable recv descriptors */ 5303 ath_mode_init(sc); /* set filters, etc. */ 5304 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 5305 return 0; 5306 } 5307 5308 /* 5309 * Update internal state after a channel change. 5310 */ 5311 static void 5312 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5313 { 5314 enum ieee80211_phymode mode; 5315 5316 /* 5317 * Change channels and update the h/w rate map 5318 * if we're switching; e.g. 11a to 11b/g. 5319 */ 5320 mode = ieee80211_chan2mode(chan); 5321 if (mode != sc->sc_curmode) 5322 ath_setcurmode(sc, mode); 5323 sc->sc_curchan = chan; 5324 } 5325 5326 /* 5327 * Set/change channels. If the channel is really being changed, 5328 * it's done by reseting the chip. To accomplish this we must 5329 * first cleanup any pending DMA, then restart stuff after a la 5330 * ath_init. 5331 */ 5332 static int 5333 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5334 { 5335 struct ifnet *ifp = sc->sc_ifp; 5336 struct ieee80211com *ic = ifp->if_l2com; 5337 struct ath_hal *ah = sc->sc_ah; 5338 5339 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 5340 __func__, ieee80211_chan2ieee(ic, chan), 5341 chan->ic_freq, chan->ic_flags); 5342 if (chan != sc->sc_curchan) { 5343 HAL_STATUS status; 5344 /* 5345 * To switch channels clear any pending DMA operations; 5346 * wait long enough for the RX fifo to drain, reset the 5347 * hardware at the new frequency, and then re-enable 5348 * the relevant bits of the h/w. 5349 */ 5350 ath_hal_intrset(ah, 0); /* disable interrupts */ 5351 ath_draintxq(sc); /* clear pending tx frames */ 5352 ath_stoprecv(sc); /* turn off frame recv */ 5353 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 5354 if_printf(ifp, "%s: unable to reset " 5355 "channel %u (%u Mhz, flags 0x%x), hal status %u\n", 5356 __func__, ieee80211_chan2ieee(ic, chan), 5357 chan->ic_freq, chan->ic_flags, status); 5358 return EIO; 5359 } 5360 sc->sc_diversity = ath_hal_getdiversity(ah); 5361 5362 /* 5363 * Re-enable rx framework. 5364 */ 5365 if (ath_startrecv(sc) != 0) { 5366 if_printf(ifp, "%s: unable to restart recv logic\n", 5367 __func__); 5368 return EIO; 5369 } 5370 5371 /* 5372 * Change channels and update the h/w rate map 5373 * if we're switching; e.g. 11a to 11b/g. 5374 */ 5375 ath_chan_change(sc, chan); 5376 5377 /* 5378 * Re-enable interrupts. 5379 */ 5380 ath_hal_intrset(ah, sc->sc_imask); 5381 } 5382 return 0; 5383 } 5384 5385 /* 5386 * Periodically recalibrate the PHY to account 5387 * for temperature/environment changes. 5388 */ 5389 static void 5390 ath_calibrate(void *arg) 5391 { 5392 struct ath_softc *sc = arg; 5393 struct ath_hal *ah = sc->sc_ah; 5394 struct ifnet *ifp = sc->sc_ifp; 5395 struct ieee80211com *ic = ifp->if_l2com; 5396 HAL_BOOL longCal, isCalDone; 5397 int nextcal; 5398 5399 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 5400 goto restart; 5401 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5402 if (longCal) { 5403 sc->sc_stats.ast_per_cal++; 5404 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5405 /* 5406 * Rfgain is out of bounds, reset the chip 5407 * to load new gain values. 5408 */ 5409 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5410 "%s: rfgain change\n", __func__); 5411 sc->sc_stats.ast_per_rfgain++; 5412 ath_reset(ifp); 5413 } 5414 /* 5415 * If this long cal is after an idle period, then 5416 * reset the data collection state so we start fresh. 5417 */ 5418 if (sc->sc_resetcal) { 5419 (void) ath_hal_calreset(ah, sc->sc_curchan); 5420 sc->sc_lastcalreset = ticks; 5421 sc->sc_resetcal = 0; 5422 } 5423 } 5424 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 5425 if (longCal) { 5426 /* 5427 * Calibrate noise floor data again in case of change. 5428 */ 5429 ath_hal_process_noisefloor(ah); 5430 } 5431 } else { 5432 DPRINTF(sc, ATH_DEBUG_ANY, 5433 "%s: calibration of channel %u failed\n", 5434 __func__, sc->sc_curchan->ic_freq); 5435 sc->sc_stats.ast_per_calfail++; 5436 } 5437 if (!isCalDone) { 5438 restart: 5439 /* 5440 * Use a shorter interval to potentially collect multiple 5441 * data samples required to complete calibration. Once 5442 * we're told the work is done we drop back to a longer 5443 * interval between requests. We're more aggressive doing 5444 * work when operating as an AP to improve operation right 5445 * after startup. 5446 */ 5447 nextcal = (1000*ath_shortcalinterval)/hz; 5448 if (sc->sc_opmode != HAL_M_HOSTAP) 5449 nextcal *= 10; 5450 } else { 5451 nextcal = ath_longcalinterval*hz; 5452 sc->sc_lastlongcal = ticks; 5453 if (sc->sc_lastcalreset == 0) 5454 sc->sc_lastcalreset = sc->sc_lastlongcal; 5455 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 5456 sc->sc_resetcal = 1; /* setup reset next trip */ 5457 } 5458 5459 if (nextcal != 0) { 5460 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 5461 __func__, nextcal, isCalDone ? "" : "!"); 5462 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 5463 } else { 5464 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 5465 __func__); 5466 /* NB: don't rearm timer */ 5467 } 5468 } 5469 5470 static void 5471 ath_scan_start(struct ieee80211com *ic) 5472 { 5473 struct ifnet *ifp = ic->ic_ifp; 5474 struct ath_softc *sc = ifp->if_softc; 5475 struct ath_hal *ah = sc->sc_ah; 5476 u_int32_t rfilt; 5477 5478 /* XXX calibration timer? */ 5479 5480 sc->sc_scanning = 1; 5481 sc->sc_syncbeacon = 0; 5482 rfilt = ath_calcrxfilter(sc); 5483 ath_hal_setrxfilter(ah, rfilt); 5484 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 5485 5486 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5487 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 5488 } 5489 5490 static void 5491 ath_scan_end(struct ieee80211com *ic) 5492 { 5493 struct ifnet *ifp = ic->ic_ifp; 5494 struct ath_softc *sc = ifp->if_softc; 5495 struct ath_hal *ah = sc->sc_ah; 5496 u_int32_t rfilt; 5497 5498 sc->sc_scanning = 0; 5499 rfilt = ath_calcrxfilter(sc); 5500 ath_hal_setrxfilter(ah, rfilt); 5501 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5502 5503 ath_hal_process_noisefloor(ah); 5504 5505 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5506 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5507 sc->sc_curaid); 5508 } 5509 5510 static void 5511 ath_set_channel(struct ieee80211com *ic) 5512 { 5513 struct ifnet *ifp = ic->ic_ifp; 5514 struct ath_softc *sc = ifp->if_softc; 5515 5516 (void) ath_chan_set(sc, ic->ic_curchan); 5517 /* 5518 * If we are returning to our bss channel then mark state 5519 * so the next recv'd beacon's tsf will be used to sync the 5520 * beacon timers. Note that since we only hear beacons in 5521 * sta/ibss mode this has no effect in other operating modes. 5522 */ 5523 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5524 sc->sc_syncbeacon = 1; 5525 } 5526 5527 /* 5528 * Walk the vap list and check if there any vap's in RUN state. 5529 */ 5530 static int 5531 ath_isanyrunningvaps(struct ieee80211vap *this) 5532 { 5533 struct ieee80211com *ic = this->iv_ic; 5534 struct ieee80211vap *vap; 5535 5536 IEEE80211_LOCK_ASSERT(ic); 5537 5538 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5539 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 5540 return 1; 5541 } 5542 return 0; 5543 } 5544 5545 static int 5546 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5547 { 5548 struct ieee80211com *ic = vap->iv_ic; 5549 struct ath_softc *sc = ic->ic_ifp->if_softc; 5550 struct ath_vap *avp = ATH_VAP(vap); 5551 struct ath_hal *ah = sc->sc_ah; 5552 struct ieee80211_node *ni = NULL; 5553 int i, error, stamode; 5554 u_int32_t rfilt; 5555 static const HAL_LED_STATE leds[] = { 5556 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5557 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5558 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5559 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5560 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5561 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5562 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5563 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5564 }; 5565 5566 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5567 ieee80211_state_name[vap->iv_state], 5568 ieee80211_state_name[nstate]); 5569 5570 callout_drain(&sc->sc_cal_ch); 5571 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5572 5573 if (nstate == IEEE80211_S_SCAN) { 5574 /* 5575 * Scanning: turn off beacon miss and don't beacon. 5576 * Mark beacon state so when we reach RUN state we'll 5577 * [re]setup beacons. Unblock the task q thread so 5578 * deferred interrupt processing is done. 5579 */ 5580 ath_hal_intrset(ah, 5581 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5582 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5583 sc->sc_beacons = 0; 5584 taskqueue_unblock(sc->sc_tq); 5585 } 5586 5587 ni = vap->iv_bss; 5588 rfilt = ath_calcrxfilter(sc); 5589 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5590 vap->iv_opmode == IEEE80211_M_AHDEMO || 5591 vap->iv_opmode == IEEE80211_M_IBSS); 5592 if (stamode && nstate == IEEE80211_S_RUN) { 5593 sc->sc_curaid = ni->ni_associd; 5594 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5595 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5596 } 5597 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5598 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5599 ath_hal_setrxfilter(ah, rfilt); 5600 5601 /* XXX is this to restore keycache on resume? */ 5602 if (vap->iv_opmode != IEEE80211_M_STA && 5603 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5604 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5605 if (ath_hal_keyisvalid(ah, i)) 5606 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5607 } 5608 5609 /* 5610 * Invoke the parent method to do net80211 work. 5611 */ 5612 error = avp->av_newstate(vap, nstate, arg); 5613 if (error != 0) 5614 goto bad; 5615 5616 if (nstate == IEEE80211_S_RUN) { 5617 /* NB: collect bss node again, it may have changed */ 5618 ni = vap->iv_bss; 5619 5620 DPRINTF(sc, ATH_DEBUG_STATE, 5621 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5622 "capinfo 0x%04x chan %d\n", __func__, 5623 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5624 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5625 5626 switch (vap->iv_opmode) { 5627 #ifdef IEEE80211_SUPPORT_TDMA 5628 case IEEE80211_M_AHDEMO: 5629 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5630 break; 5631 /* fall thru... */ 5632 #endif 5633 case IEEE80211_M_HOSTAP: 5634 case IEEE80211_M_IBSS: 5635 case IEEE80211_M_MBSS: 5636 /* 5637 * Allocate and setup the beacon frame. 5638 * 5639 * Stop any previous beacon DMA. This may be 5640 * necessary, for example, when an ibss merge 5641 * causes reconfiguration; there will be a state 5642 * transition from RUN->RUN that means we may 5643 * be called with beacon transmission active. 5644 */ 5645 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5646 5647 error = ath_beacon_alloc(sc, ni); 5648 if (error != 0) 5649 goto bad; 5650 /* 5651 * If joining an adhoc network defer beacon timer 5652 * configuration to the next beacon frame so we 5653 * have a current TSF to use. Otherwise we're 5654 * starting an ibss/bss so there's no need to delay; 5655 * if this is the first vap moving to RUN state, then 5656 * beacon state needs to be [re]configured. 5657 */ 5658 if (vap->iv_opmode == IEEE80211_M_IBSS && 5659 ni->ni_tstamp.tsf != 0) { 5660 sc->sc_syncbeacon = 1; 5661 } else if (!sc->sc_beacons) { 5662 #ifdef IEEE80211_SUPPORT_TDMA 5663 if (vap->iv_caps & IEEE80211_C_TDMA) 5664 ath_tdma_config(sc, vap); 5665 else 5666 #endif 5667 ath_beacon_config(sc, vap); 5668 sc->sc_beacons = 1; 5669 } 5670 break; 5671 case IEEE80211_M_STA: 5672 /* 5673 * Defer beacon timer configuration to the next 5674 * beacon frame so we have a current TSF to use 5675 * (any TSF collected when scanning is likely old). 5676 */ 5677 sc->sc_syncbeacon = 1; 5678 break; 5679 case IEEE80211_M_MONITOR: 5680 /* 5681 * Monitor mode vaps have only INIT->RUN and RUN->RUN 5682 * transitions so we must re-enable interrupts here to 5683 * handle the case of a single monitor mode vap. 5684 */ 5685 ath_hal_intrset(ah, sc->sc_imask); 5686 break; 5687 case IEEE80211_M_WDS: 5688 break; 5689 default: 5690 break; 5691 } 5692 /* 5693 * Let the hal process statistics collected during a 5694 * scan so it can provide calibrated noise floor data. 5695 */ 5696 ath_hal_process_noisefloor(ah); 5697 /* 5698 * Reset rssi stats; maybe not the best place... 5699 */ 5700 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5701 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5702 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5703 /* 5704 * Finally, start any timers and the task q thread 5705 * (in case we didn't go through SCAN state). 5706 */ 5707 if (ath_longcalinterval != 0) { 5708 /* start periodic recalibration timer */ 5709 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 5710 } else { 5711 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5712 "%s: calibration disabled\n", __func__); 5713 } 5714 taskqueue_unblock(sc->sc_tq); 5715 } else if (nstate == IEEE80211_S_INIT) { 5716 /* 5717 * If there are no vaps left in RUN state then 5718 * shutdown host/driver operation: 5719 * o disable interrupts 5720 * o disable the task queue thread 5721 * o mark beacon processing as stopped 5722 */ 5723 if (!ath_isanyrunningvaps(vap)) { 5724 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5725 /* disable interrupts */ 5726 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5727 taskqueue_block(sc->sc_tq); 5728 sc->sc_beacons = 0; 5729 } 5730 #ifdef IEEE80211_SUPPORT_TDMA 5731 ath_hal_setcca(ah, AH_TRUE); 5732 #endif 5733 } 5734 bad: 5735 return error; 5736 } 5737 5738 /* 5739 * Allocate a key cache slot to the station so we can 5740 * setup a mapping from key index to node. The key cache 5741 * slot is needed for managing antenna state and for 5742 * compression when stations do not use crypto. We do 5743 * it uniliaterally here; if crypto is employed this slot 5744 * will be reassigned. 5745 */ 5746 static void 5747 ath_setup_stationkey(struct ieee80211_node *ni) 5748 { 5749 struct ieee80211vap *vap = ni->ni_vap; 5750 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5751 ieee80211_keyix keyix, rxkeyix; 5752 5753 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5754 /* 5755 * Key cache is full; we'll fall back to doing 5756 * the more expensive lookup in software. Note 5757 * this also means no h/w compression. 5758 */ 5759 /* XXX msg+statistic */ 5760 } else { 5761 /* XXX locking? */ 5762 ni->ni_ucastkey.wk_keyix = keyix; 5763 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5764 /* NB: must mark device key to get called back on delete */ 5765 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 5766 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 5767 /* NB: this will create a pass-thru key entry */ 5768 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss); 5769 } 5770 } 5771 5772 /* 5773 * Setup driver-specific state for a newly associated node. 5774 * Note that we're called also on a re-associate, the isnew 5775 * param tells us if this is the first time or not. 5776 */ 5777 static void 5778 ath_newassoc(struct ieee80211_node *ni, int isnew) 5779 { 5780 struct ath_node *an = ATH_NODE(ni); 5781 struct ieee80211vap *vap = ni->ni_vap; 5782 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5783 const struct ieee80211_txparam *tp = ni->ni_txparms; 5784 5785 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 5786 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 5787 5788 ath_rate_newassoc(sc, an, isnew); 5789 if (isnew && 5790 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 5791 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5792 ath_setup_stationkey(ni); 5793 } 5794 5795 static int 5796 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 5797 int nchans, struct ieee80211_channel chans[]) 5798 { 5799 struct ath_softc *sc = ic->ic_ifp->if_softc; 5800 struct ath_hal *ah = sc->sc_ah; 5801 HAL_STATUS status; 5802 5803 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5804 "%s: rd %u cc %u location %c%s\n", 5805 __func__, reg->regdomain, reg->country, reg->location, 5806 reg->ecm ? " ecm" : ""); 5807 5808 status = ath_hal_set_channels(ah, chans, nchans, 5809 reg->country, reg->regdomain); 5810 if (status != HAL_OK) { 5811 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 5812 __func__, status); 5813 return EINVAL; /* XXX */ 5814 } 5815 return 0; 5816 } 5817 5818 static void 5819 ath_getradiocaps(struct ieee80211com *ic, 5820 int maxchans, int *nchans, struct ieee80211_channel chans[]) 5821 { 5822 struct ath_softc *sc = ic->ic_ifp->if_softc; 5823 struct ath_hal *ah = sc->sc_ah; 5824 5825 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 5826 __func__, SKU_DEBUG, CTRY_DEFAULT); 5827 5828 /* XXX check return */ 5829 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 5830 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 5831 5832 } 5833 5834 static int 5835 ath_getchannels(struct ath_softc *sc) 5836 { 5837 struct ifnet *ifp = sc->sc_ifp; 5838 struct ieee80211com *ic = ifp->if_l2com; 5839 struct ath_hal *ah = sc->sc_ah; 5840 HAL_STATUS status; 5841 5842 /* 5843 * Collect channel set based on EEPROM contents. 5844 */ 5845 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 5846 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 5847 if (status != HAL_OK) { 5848 if_printf(ifp, "%s: unable to collect channel list from hal, " 5849 "status %d\n", __func__, status); 5850 return EINVAL; 5851 } 5852 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 5853 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 5854 /* XXX map Atheros sku's to net80211 SKU's */ 5855 /* XXX net80211 types too small */ 5856 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 5857 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 5858 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 5859 ic->ic_regdomain.isocc[1] = ' '; 5860 5861 ic->ic_regdomain.ecm = 1; 5862 ic->ic_regdomain.location = 'I'; 5863 5864 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5865 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 5866 __func__, sc->sc_eerd, sc->sc_eecc, 5867 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 5868 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 5869 return 0; 5870 } 5871 5872 static void 5873 ath_led_done(void *arg) 5874 { 5875 struct ath_softc *sc = arg; 5876 5877 sc->sc_blinking = 0; 5878 } 5879 5880 /* 5881 * Turn the LED off: flip the pin and then set a timer so no 5882 * update will happen for the specified duration. 5883 */ 5884 static void 5885 ath_led_off(void *arg) 5886 { 5887 struct ath_softc *sc = arg; 5888 5889 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5890 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 5891 } 5892 5893 /* 5894 * Blink the LED according to the specified on/off times. 5895 */ 5896 static void 5897 ath_led_blink(struct ath_softc *sc, int on, int off) 5898 { 5899 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 5900 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 5901 sc->sc_blinking = 1; 5902 sc->sc_ledoff = off; 5903 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 5904 } 5905 5906 static void 5907 ath_led_event(struct ath_softc *sc, int rix) 5908 { 5909 sc->sc_ledevent = ticks; /* time of last event */ 5910 if (sc->sc_blinking) /* don't interrupt active blink */ 5911 return; 5912 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff); 5913 } 5914 5915 static int 5916 ath_rate_setup(struct ath_softc *sc, u_int mode) 5917 { 5918 struct ath_hal *ah = sc->sc_ah; 5919 const HAL_RATE_TABLE *rt; 5920 5921 switch (mode) { 5922 case IEEE80211_MODE_11A: 5923 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5924 break; 5925 case IEEE80211_MODE_HALF: 5926 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 5927 break; 5928 case IEEE80211_MODE_QUARTER: 5929 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 5930 break; 5931 case IEEE80211_MODE_11B: 5932 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5933 break; 5934 case IEEE80211_MODE_11G: 5935 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5936 break; 5937 case IEEE80211_MODE_TURBO_A: 5938 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 5939 break; 5940 case IEEE80211_MODE_TURBO_G: 5941 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5942 break; 5943 case IEEE80211_MODE_STURBO_A: 5944 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5945 break; 5946 case IEEE80211_MODE_11NA: 5947 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 5948 break; 5949 case IEEE80211_MODE_11NG: 5950 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 5951 break; 5952 default: 5953 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5954 __func__, mode); 5955 return 0; 5956 } 5957 sc->sc_rates[mode] = rt; 5958 return (rt != NULL); 5959 } 5960 5961 static void 5962 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5963 { 5964 #define N(a) (sizeof(a)/sizeof(a[0])) 5965 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5966 static const struct { 5967 u_int rate; /* tx/rx 802.11 rate */ 5968 u_int16_t timeOn; /* LED on time (ms) */ 5969 u_int16_t timeOff; /* LED off time (ms) */ 5970 } blinkrates[] = { 5971 { 108, 40, 10 }, 5972 { 96, 44, 11 }, 5973 { 72, 50, 13 }, 5974 { 48, 57, 14 }, 5975 { 36, 67, 16 }, 5976 { 24, 80, 20 }, 5977 { 22, 100, 25 }, 5978 { 18, 133, 34 }, 5979 { 12, 160, 40 }, 5980 { 10, 200, 50 }, 5981 { 6, 240, 58 }, 5982 { 4, 267, 66 }, 5983 { 2, 400, 100 }, 5984 { 0, 500, 130 }, 5985 /* XXX half/quarter rates */ 5986 }; 5987 const HAL_RATE_TABLE *rt; 5988 int i, j; 5989 5990 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5991 rt = sc->sc_rates[mode]; 5992 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5993 for (i = 0; i < rt->rateCount; i++) { 5994 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 5995 if (rt->info[i].phy != IEEE80211_T_HT) 5996 sc->sc_rixmap[ieeerate] = i; 5997 else 5998 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 5999 } 6000 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6001 for (i = 0; i < N(sc->sc_hwmap); i++) { 6002 if (i >= rt->rateCount) { 6003 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6004 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6005 continue; 6006 } 6007 sc->sc_hwmap[i].ieeerate = 6008 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6009 if (rt->info[i].phy == IEEE80211_T_HT) 6010 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 6011 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6012 if (rt->info[i].shortPreamble || 6013 rt->info[i].phy == IEEE80211_T_OFDM) 6014 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6015 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 6016 for (j = 0; j < N(blinkrates)-1; j++) 6017 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6018 break; 6019 /* NB: this uses the last entry if the rate isn't found */ 6020 /* XXX beware of overlow */ 6021 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6022 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6023 } 6024 sc->sc_currates = rt; 6025 sc->sc_curmode = mode; 6026 /* 6027 * All protection frames are transmited at 2Mb/s for 6028 * 11g, otherwise at 1Mb/s. 6029 */ 6030 if (mode == IEEE80211_MODE_11G) 6031 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 6032 else 6033 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 6034 /* NB: caller is responsible for reseting rate control state */ 6035 #undef N 6036 } 6037 6038 #ifdef ATH_DEBUG 6039 static void 6040 ath_printrxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6041 u_int ix, int done) 6042 { 6043 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 6044 struct ath_hal *ah = sc->sc_ah; 6045 const struct ath_desc *ds; 6046 int i; 6047 6048 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6049 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 6050 " %08x %08x %08x %08x\n", 6051 ix, ds, (const struct ath_desc *)bf->bf_daddr + i, 6052 ds->ds_link, ds->ds_data, 6053 !done ? "" : (rs->rs_status == 0) ? " *" : " !", 6054 ds->ds_ctl0, ds->ds_ctl1, 6055 ds->ds_hw[0], ds->ds_hw[1]); 6056 if (ah->ah_magic == 0x20065416) { 6057 printf(" %08x %08x %08x %08x %08x %08x %08x\n", 6058 ds->ds_hw[2], ds->ds_hw[3], ds->ds_hw[4], 6059 ds->ds_hw[5], ds->ds_hw[6], ds->ds_hw[7], 6060 ds->ds_hw[8]); 6061 } 6062 } 6063 } 6064 6065 static void 6066 ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6067 u_int qnum, u_int ix, int done) 6068 { 6069 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 6070 struct ath_hal *ah = sc->sc_ah; 6071 const struct ath_desc *ds; 6072 int i; 6073 6074 printf("Q%u[%3u]", qnum, ix); 6075 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6076 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 6077 " %08x %08x %08x %08x %08x %08x\n", 6078 ds, (const struct ath_desc *)bf->bf_daddr + i, 6079 ds->ds_link, ds->ds_data, bf->bf_txflags, 6080 !done ? "" : (ts->ts_status == 0) ? " *" : " !", 6081 ds->ds_ctl0, ds->ds_ctl1, 6082 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 6083 if (ah->ah_magic == 0x20065416) { 6084 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6085 ds->ds_hw[4], ds->ds_hw[5], ds->ds_hw[6], 6086 ds->ds_hw[7], ds->ds_hw[8], ds->ds_hw[9], 6087 ds->ds_hw[10],ds->ds_hw[11]); 6088 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6089 ds->ds_hw[12],ds->ds_hw[13],ds->ds_hw[14], 6090 ds->ds_hw[15],ds->ds_hw[16],ds->ds_hw[17], 6091 ds->ds_hw[18], ds->ds_hw[19]); 6092 } 6093 } 6094 } 6095 #endif /* ATH_DEBUG */ 6096 6097 static void 6098 ath_watchdog(void *arg) 6099 { 6100 struct ath_softc *sc = arg; 6101 6102 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 6103 struct ifnet *ifp = sc->sc_ifp; 6104 uint32_t hangs; 6105 6106 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 6107 hangs != 0) { 6108 if_printf(ifp, "%s hang detected (0x%x)\n", 6109 hangs & 0xff ? "bb" : "mac", hangs); 6110 } else 6111 if_printf(ifp, "device timeout\n"); 6112 ath_reset(ifp); 6113 ifp->if_oerrors++; 6114 sc->sc_stats.ast_watchdog++; 6115 } 6116 callout_schedule(&sc->sc_wd_ch, hz); 6117 } 6118 6119 #ifdef ATH_DIAGAPI 6120 /* 6121 * Diagnostic interface to the HAL. This is used by various 6122 * tools to do things like retrieve register contents for 6123 * debugging. The mechanism is intentionally opaque so that 6124 * it can change frequently w/o concern for compatiblity. 6125 */ 6126 static int 6127 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 6128 { 6129 struct ath_hal *ah = sc->sc_ah; 6130 u_int id = ad->ad_id & ATH_DIAG_ID; 6131 void *indata = NULL; 6132 void *outdata = NULL; 6133 u_int32_t insize = ad->ad_in_size; 6134 u_int32_t outsize = ad->ad_out_size; 6135 int error = 0; 6136 6137 if (ad->ad_id & ATH_DIAG_IN) { 6138 /* 6139 * Copy in data. 6140 */ 6141 indata = malloc(insize, M_TEMP, M_NOWAIT); 6142 if (indata == NULL) { 6143 error = ENOMEM; 6144 goto bad; 6145 } 6146 error = copyin(ad->ad_in_data, indata, insize); 6147 if (error) 6148 goto bad; 6149 } 6150 if (ad->ad_id & ATH_DIAG_DYN) { 6151 /* 6152 * Allocate a buffer for the results (otherwise the HAL 6153 * returns a pointer to a buffer where we can read the 6154 * results). Note that we depend on the HAL leaving this 6155 * pointer for us to use below in reclaiming the buffer; 6156 * may want to be more defensive. 6157 */ 6158 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 6159 if (outdata == NULL) { 6160 error = ENOMEM; 6161 goto bad; 6162 } 6163 } 6164 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 6165 if (outsize < ad->ad_out_size) 6166 ad->ad_out_size = outsize; 6167 if (outdata != NULL) 6168 error = copyout(outdata, ad->ad_out_data, 6169 ad->ad_out_size); 6170 } else { 6171 error = EINVAL; 6172 } 6173 bad: 6174 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 6175 free(indata, M_TEMP); 6176 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 6177 free(outdata, M_TEMP); 6178 return error; 6179 } 6180 #endif /* ATH_DIAGAPI */ 6181 6182 static int 6183 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 6184 { 6185 #define IS_RUNNING(ifp) \ 6186 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 6187 struct ath_softc *sc = ifp->if_softc; 6188 struct ieee80211com *ic = ifp->if_l2com; 6189 struct ifreq *ifr = (struct ifreq *)data; 6190 const HAL_RATE_TABLE *rt; 6191 int error = 0; 6192 6193 switch (cmd) { 6194 case SIOCSIFFLAGS: 6195 ATH_LOCK(sc); 6196 if (IS_RUNNING(ifp)) { 6197 /* 6198 * To avoid rescanning another access point, 6199 * do not call ath_init() here. Instead, 6200 * only reflect promisc mode settings. 6201 */ 6202 ath_mode_init(sc); 6203 } else if (ifp->if_flags & IFF_UP) { 6204 /* 6205 * Beware of being called during attach/detach 6206 * to reset promiscuous mode. In that case we 6207 * will still be marked UP but not RUNNING. 6208 * However trying to re-init the interface 6209 * is the wrong thing to do as we've already 6210 * torn down much of our state. There's 6211 * probably a better way to deal with this. 6212 */ 6213 if (!sc->sc_invalid) 6214 ath_init(sc); /* XXX lose error */ 6215 } else { 6216 ath_stop_locked(ifp); 6217 #ifdef notyet 6218 /* XXX must wakeup in places like ath_vap_delete */ 6219 if (!sc->sc_invalid) 6220 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 6221 #endif 6222 } 6223 ATH_UNLOCK(sc); 6224 break; 6225 case SIOCGIFMEDIA: 6226 case SIOCSIFMEDIA: 6227 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 6228 break; 6229 case SIOCGATHSTATS: 6230 /* NB: embed these numbers to get a consistent view */ 6231 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 6232 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 6233 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 6234 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 6235 #ifdef IEEE80211_SUPPORT_TDMA 6236 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 6237 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 6238 #endif 6239 rt = sc->sc_currates; 6240 /* XXX HT rates */ 6241 sc->sc_stats.ast_tx_rate = 6242 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 6243 return copyout(&sc->sc_stats, 6244 ifr->ifr_data, sizeof (sc->sc_stats)); 6245 case SIOCZATHSTATS: 6246 error = priv_check(curthread, PRIV_DRIVER); 6247 if (error == 0) 6248 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 6249 break; 6250 #ifdef ATH_DIAGAPI 6251 case SIOCGATHDIAG: 6252 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 6253 break; 6254 #endif 6255 case SIOCGIFADDR: 6256 error = ether_ioctl(ifp, cmd, data); 6257 break; 6258 default: 6259 error = EINVAL; 6260 break; 6261 } 6262 return error; 6263 #undef IS_RUNNING 6264 } 6265 6266 static int 6267 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 6268 { 6269 struct ath_softc *sc = arg1; 6270 u_int slottime = ath_hal_getslottime(sc->sc_ah); 6271 int error; 6272 6273 error = sysctl_handle_int(oidp, &slottime, 0, req); 6274 if (error || !req->newptr) 6275 return error; 6276 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 6277 } 6278 6279 static int 6280 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 6281 { 6282 struct ath_softc *sc = arg1; 6283 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 6284 int error; 6285 6286 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 6287 if (error || !req->newptr) 6288 return error; 6289 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 6290 } 6291 6292 static int 6293 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 6294 { 6295 struct ath_softc *sc = arg1; 6296 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 6297 int error; 6298 6299 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 6300 if (error || !req->newptr) 6301 return error; 6302 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 6303 } 6304 6305 static int 6306 ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 6307 { 6308 struct ath_softc *sc = arg1; 6309 int softled = sc->sc_softled; 6310 int error; 6311 6312 error = sysctl_handle_int(oidp, &softled, 0, req); 6313 if (error || !req->newptr) 6314 return error; 6315 softled = (softled != 0); 6316 if (softled != sc->sc_softled) { 6317 if (softled) { 6318 /* NB: handle any sc_ledpin change */ 6319 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6320 HAL_GPIO_MUX_MAC_NETWORK_LED); 6321 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6322 !sc->sc_ledon); 6323 } 6324 sc->sc_softled = softled; 6325 } 6326 return 0; 6327 } 6328 6329 static int 6330 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) 6331 { 6332 struct ath_softc *sc = arg1; 6333 int ledpin = sc->sc_ledpin; 6334 int error; 6335 6336 error = sysctl_handle_int(oidp, &ledpin, 0, req); 6337 if (error || !req->newptr) 6338 return error; 6339 if (ledpin != sc->sc_ledpin) { 6340 sc->sc_ledpin = ledpin; 6341 if (sc->sc_softled) { 6342 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6343 HAL_GPIO_MUX_MAC_NETWORK_LED); 6344 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6345 !sc->sc_ledon); 6346 } 6347 } 6348 return 0; 6349 } 6350 6351 static int 6352 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) 6353 { 6354 struct ath_softc *sc = arg1; 6355 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah); 6356 int error; 6357 6358 error = sysctl_handle_int(oidp, &txantenna, 0, req); 6359 if (!error && req->newptr) { 6360 /* XXX assumes 2 antenna ports */ 6361 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B) 6362 return EINVAL; 6363 ath_hal_setantennaswitch(sc->sc_ah, txantenna); 6364 /* 6365 * NB: with the switch locked this isn't meaningful, 6366 * but set it anyway so things like radiotap get 6367 * consistent info in their data. 6368 */ 6369 sc->sc_txantenna = txantenna; 6370 } 6371 return error; 6372 } 6373 6374 static int 6375 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 6376 { 6377 struct ath_softc *sc = arg1; 6378 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 6379 int error; 6380 6381 error = sysctl_handle_int(oidp, &defantenna, 0, req); 6382 if (!error && req->newptr) 6383 ath_hal_setdefantenna(sc->sc_ah, defantenna); 6384 return error; 6385 } 6386 6387 static int 6388 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 6389 { 6390 struct ath_softc *sc = arg1; 6391 u_int diversity = ath_hal_getdiversity(sc->sc_ah); 6392 int error; 6393 6394 error = sysctl_handle_int(oidp, &diversity, 0, req); 6395 if (error || !req->newptr) 6396 return error; 6397 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 6398 return EINVAL; 6399 sc->sc_diversity = diversity; 6400 return 0; 6401 } 6402 6403 static int 6404 ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 6405 { 6406 struct ath_softc *sc = arg1; 6407 u_int32_t diag; 6408 int error; 6409 6410 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 6411 return EINVAL; 6412 error = sysctl_handle_int(oidp, &diag, 0, req); 6413 if (error || !req->newptr) 6414 return error; 6415 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 6416 } 6417 6418 static int 6419 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 6420 { 6421 struct ath_softc *sc = arg1; 6422 struct ifnet *ifp = sc->sc_ifp; 6423 u_int32_t scale; 6424 int error; 6425 6426 (void) ath_hal_gettpscale(sc->sc_ah, &scale); 6427 error = sysctl_handle_int(oidp, &scale, 0, req); 6428 if (error || !req->newptr) 6429 return error; 6430 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : 6431 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6432 } 6433 6434 static int 6435 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 6436 { 6437 struct ath_softc *sc = arg1; 6438 u_int tpc = ath_hal_gettpc(sc->sc_ah); 6439 int error; 6440 6441 error = sysctl_handle_int(oidp, &tpc, 0, req); 6442 if (error || !req->newptr) 6443 return error; 6444 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 6445 } 6446 6447 static int 6448 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 6449 { 6450 struct ath_softc *sc = arg1; 6451 struct ifnet *ifp = sc->sc_ifp; 6452 struct ath_hal *ah = sc->sc_ah; 6453 u_int rfkill = ath_hal_getrfkill(ah); 6454 int error; 6455 6456 error = sysctl_handle_int(oidp, &rfkill, 0, req); 6457 if (error || !req->newptr) 6458 return error; 6459 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */ 6460 return 0; 6461 if (!ath_hal_setrfkill(ah, rfkill)) 6462 return EINVAL; 6463 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6464 } 6465 6466 static int 6467 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 6468 { 6469 struct ath_softc *sc = arg1; 6470 u_int rfsilent; 6471 int error; 6472 6473 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 6474 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 6475 if (error || !req->newptr) 6476 return error; 6477 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) 6478 return EINVAL; 6479 sc->sc_rfsilentpin = rfsilent & 0x1c; 6480 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 6481 return 0; 6482 } 6483 6484 static int 6485 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 6486 { 6487 struct ath_softc *sc = arg1; 6488 u_int32_t tpack; 6489 int error; 6490 6491 (void) ath_hal_gettpack(sc->sc_ah, &tpack); 6492 error = sysctl_handle_int(oidp, &tpack, 0, req); 6493 if (error || !req->newptr) 6494 return error; 6495 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0; 6496 } 6497 6498 static int 6499 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 6500 { 6501 struct ath_softc *sc = arg1; 6502 u_int32_t tpcts; 6503 int error; 6504 6505 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts); 6506 error = sysctl_handle_int(oidp, &tpcts, 0, req); 6507 if (error || !req->newptr) 6508 return error; 6509 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0; 6510 } 6511 6512 static int 6513 ath_sysctl_intmit(SYSCTL_HANDLER_ARGS) 6514 { 6515 struct ath_softc *sc = arg1; 6516 int intmit, error; 6517 6518 intmit = ath_hal_getintmit(sc->sc_ah); 6519 error = sysctl_handle_int(oidp, &intmit, 0, req); 6520 if (error || !req->newptr) 6521 return error; 6522 return !ath_hal_setintmit(sc->sc_ah, intmit) ? EINVAL : 0; 6523 } 6524 6525 #ifdef IEEE80211_SUPPORT_TDMA 6526 static int 6527 ath_sysctl_setcca(SYSCTL_HANDLER_ARGS) 6528 { 6529 struct ath_softc *sc = arg1; 6530 int setcca, error; 6531 6532 setcca = sc->sc_setcca; 6533 error = sysctl_handle_int(oidp, &setcca, 0, req); 6534 if (error || !req->newptr) 6535 return error; 6536 sc->sc_setcca = (setcca != 0); 6537 return 0; 6538 } 6539 #endif /* IEEE80211_SUPPORT_TDMA */ 6540 6541 static void 6542 ath_sysctlattach(struct ath_softc *sc) 6543 { 6544 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 6545 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 6546 struct ath_hal *ah = sc->sc_ah; 6547 6548 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6549 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0, 6550 "EEPROM country code"); 6551 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6552 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0, 6553 "EEPROM regdomain code"); 6554 #ifdef ATH_DEBUG 6555 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6556 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 6557 "control debugging printfs"); 6558 #endif 6559 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6560 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6561 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 6562 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6563 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6564 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 6565 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6566 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6567 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 6568 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6569 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6570 ath_sysctl_softled, "I", "enable/disable software LED support"); 6571 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6572 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6573 ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); 6574 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6575 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 6576 "setting to turn LED on"); 6577 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6578 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 6579 "idle time for inactivity LED (ticks)"); 6580 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6581 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6582 ath_sysctl_txantenna, "I", "antenna switch"); 6583 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6584 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6585 ath_sysctl_rxantenna, "I", "default/rx antenna"); 6586 if (ath_hal_hasdiversity(ah)) 6587 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6588 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6589 ath_sysctl_diversity, "I", "antenna diversity"); 6590 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 6591 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6592 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 6593 "tx descriptor batching"); 6594 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6595 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6596 ath_sysctl_diag, "I", "h/w diagnostic control"); 6597 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6598 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6599 ath_sysctl_tpscale, "I", "tx power scaling"); 6600 if (ath_hal_hastpc(ah)) { 6601 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6602 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6603 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 6604 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6605 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6606 ath_sysctl_tpack, "I", "tx power for ack frames"); 6607 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6608 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6609 ath_sysctl_tpcts, "I", "tx power for cts frames"); 6610 } 6611 if (ath_hal_hasrfsilent(ah)) { 6612 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6613 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6614 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 6615 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6616 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6617 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 6618 } 6619 if (ath_hal_hasintmit(ah)) { 6620 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6621 "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6622 ath_sysctl_intmit, "I", "interference mitigation"); 6623 } 6624 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 6625 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6626 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 6627 "mask of error frames to pass when monitoring"); 6628 #ifdef IEEE80211_SUPPORT_TDMA 6629 if (ath_hal_macversion(ah) > 0x78) { 6630 sc->sc_tdmadbaprep = 2; 6631 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6632 "dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0, 6633 "TDMA DBA preparation time"); 6634 sc->sc_tdmaswbaprep = 10; 6635 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6636 "swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0, 6637 "TDMA SWBA preparation time"); 6638 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6639 "guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0, 6640 "TDMA slot guard time"); 6641 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6642 "superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0, 6643 "TDMA calculated super frame"); 6644 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6645 "setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6646 ath_sysctl_setcca, "I", "enable CCA control"); 6647 } 6648 #endif 6649 } 6650 6651 static int 6652 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 6653 struct ath_buf *bf, struct mbuf *m0, 6654 const struct ieee80211_bpf_params *params) 6655 { 6656 struct ifnet *ifp = sc->sc_ifp; 6657 struct ieee80211com *ic = ifp->if_l2com; 6658 struct ath_hal *ah = sc->sc_ah; 6659 struct ieee80211vap *vap = ni->ni_vap; 6660 int error, ismcast, ismrr; 6661 int keyix, hdrlen, pktlen, try0, txantenna; 6662 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3; 6663 struct ieee80211_frame *wh; 6664 u_int flags, ctsduration; 6665 HAL_PKT_TYPE atype; 6666 const HAL_RATE_TABLE *rt; 6667 struct ath_desc *ds; 6668 u_int pri; 6669 6670 wh = mtod(m0, struct ieee80211_frame *); 6671 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6672 hdrlen = ieee80211_anyhdrsize(wh); 6673 /* 6674 * Packet length must not include any 6675 * pad bytes; deduct them here. 6676 */ 6677 /* XXX honor IEEE80211_BPF_DATAPAD */ 6678 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 6679 6680 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 6681 const struct ieee80211_cipher *cip; 6682 struct ieee80211_key *k; 6683 6684 /* 6685 * Construct the 802.11 header+trailer for an encrypted 6686 * frame. The only reason this can fail is because of an 6687 * unknown or unsupported cipher/key type. 6688 */ 6689 k = ieee80211_crypto_encap(ni, m0); 6690 if (k == NULL) { 6691 /* 6692 * This can happen when the key is yanked after the 6693 * frame was queued. Just discard the frame; the 6694 * 802.11 layer counts failures and provides 6695 * debugging/diagnostics. 6696 */ 6697 ath_freetx(m0); 6698 return EIO; 6699 } 6700 /* 6701 * Adjust the packet + header lengths for the crypto 6702 * additions and calculate the h/w key index. When 6703 * a s/w mic is done the frame will have had any mic 6704 * added to it prior to entry so m0->m_pkthdr.len will 6705 * account for it. Otherwise we need to add it to the 6706 * packet length. 6707 */ 6708 cip = k->wk_cipher; 6709 hdrlen += cip->ic_header; 6710 pktlen += cip->ic_header + cip->ic_trailer; 6711 /* NB: frags always have any TKIP MIC done in s/w */ 6712 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 6713 pktlen += cip->ic_miclen; 6714 keyix = k->wk_keyix; 6715 6716 /* packet header may have moved, reset our local pointer */ 6717 wh = mtod(m0, struct ieee80211_frame *); 6718 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 6719 /* 6720 * Use station key cache slot, if assigned. 6721 */ 6722 keyix = ni->ni_ucastkey.wk_keyix; 6723 if (keyix == IEEE80211_KEYIX_NONE) 6724 keyix = HAL_TXKEYIX_INVALID; 6725 } else 6726 keyix = HAL_TXKEYIX_INVALID; 6727 6728 error = ath_tx_dmasetup(sc, bf, m0); 6729 if (error != 0) 6730 return error; 6731 m0 = bf->bf_m; /* NB: may have changed */ 6732 wh = mtod(m0, struct ieee80211_frame *); 6733 bf->bf_node = ni; /* NB: held reference */ 6734 6735 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 6736 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 6737 if (params->ibp_flags & IEEE80211_BPF_RTS) 6738 flags |= HAL_TXDESC_RTSENA; 6739 else if (params->ibp_flags & IEEE80211_BPF_CTS) 6740 flags |= HAL_TXDESC_CTSENA; 6741 /* XXX leave ismcast to injector? */ 6742 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 6743 flags |= HAL_TXDESC_NOACK; 6744 6745 rt = sc->sc_currates; 6746 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 6747 rix = ath_tx_findrix(sc, params->ibp_rate0); 6748 txrate = rt->info[rix].rateCode; 6749 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6750 txrate |= rt->info[rix].shortPreamble; 6751 sc->sc_txrix = rix; 6752 try0 = params->ibp_try0; 6753 ismrr = (params->ibp_try1 != 0); 6754 txantenna = params->ibp_pri >> 2; 6755 if (txantenna == 0) /* XXX? */ 6756 txantenna = sc->sc_txantenna; 6757 ctsduration = 0; 6758 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { 6759 cix = ath_tx_findrix(sc, params->ibp_ctsrate); 6760 ctsrate = rt->info[cix].rateCode; 6761 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) { 6762 ctsrate |= rt->info[cix].shortPreamble; 6763 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6764 ctsduration += rt->info[cix].spAckDuration; 6765 ctsduration += ath_hal_computetxtime(ah, 6766 rt, pktlen, rix, AH_TRUE); 6767 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6768 ctsduration += rt->info[rix].spAckDuration; 6769 } else { 6770 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6771 ctsduration += rt->info[cix].lpAckDuration; 6772 ctsduration += ath_hal_computetxtime(ah, 6773 rt, pktlen, rix, AH_FALSE); 6774 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6775 ctsduration += rt->info[rix].lpAckDuration; 6776 } 6777 ismrr = 0; /* XXX */ 6778 } else 6779 ctsrate = 0; 6780 pri = params->ibp_pri & 3; 6781 /* 6782 * NB: we mark all packets as type PSPOLL so the h/w won't 6783 * set the sequence number, duration, etc. 6784 */ 6785 atype = HAL_PKT_TYPE_PSPOLL; 6786 6787 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 6788 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 6789 sc->sc_hwmap[rix].ieeerate, -1); 6790 6791 if (ieee80211_radiotap_active_vap(vap)) { 6792 u_int64_t tsf = ath_hal_gettsf64(ah); 6793 6794 sc->sc_tx_th.wt_tsf = htole64(tsf); 6795 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 6796 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 6797 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6798 if (m0->m_flags & M_FRAG) 6799 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 6800 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 6801 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 6802 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 6803 6804 ieee80211_radiotap_tx(vap, m0); 6805 } 6806 6807 /* 6808 * Formulate first tx descriptor with tx controls. 6809 */ 6810 ds = bf->bf_desc; 6811 /* XXX check return value? */ 6812 ath_hal_setuptxdesc(ah, ds 6813 , pktlen /* packet length */ 6814 , hdrlen /* header length */ 6815 , atype /* Atheros packet type */ 6816 , params->ibp_power /* txpower */ 6817 , txrate, try0 /* series 0 rate/tries */ 6818 , keyix /* key cache index */ 6819 , txantenna /* antenna mode */ 6820 , flags /* flags */ 6821 , ctsrate /* rts/cts rate */ 6822 , ctsduration /* rts/cts duration */ 6823 ); 6824 bf->bf_txflags = flags; 6825 6826 if (ismrr) { 6827 rix = ath_tx_findrix(sc, params->ibp_rate1); 6828 rate1 = rt->info[rix].rateCode; 6829 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6830 rate1 |= rt->info[rix].shortPreamble; 6831 if (params->ibp_try2) { 6832 rix = ath_tx_findrix(sc, params->ibp_rate2); 6833 rate2 = rt->info[rix].rateCode; 6834 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6835 rate2 |= rt->info[rix].shortPreamble; 6836 } else 6837 rate2 = 0; 6838 if (params->ibp_try3) { 6839 rix = ath_tx_findrix(sc, params->ibp_rate3); 6840 rate3 = rt->info[rix].rateCode; 6841 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6842 rate3 |= rt->info[rix].shortPreamble; 6843 } else 6844 rate3 = 0; 6845 ath_hal_setupxtxdesc(ah, ds 6846 , rate1, params->ibp_try1 /* series 1 */ 6847 , rate2, params->ibp_try2 /* series 2 */ 6848 , rate3, params->ibp_try3 /* series 3 */ 6849 ); 6850 } 6851 6852 /* NB: no buffered multicast in power save support */ 6853 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf); 6854 return 0; 6855 } 6856 6857 static int 6858 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 6859 const struct ieee80211_bpf_params *params) 6860 { 6861 struct ieee80211com *ic = ni->ni_ic; 6862 struct ifnet *ifp = ic->ic_ifp; 6863 struct ath_softc *sc = ifp->if_softc; 6864 struct ath_buf *bf; 6865 int error; 6866 6867 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 6868 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 6869 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ? 6870 "!running" : "invalid"); 6871 m_freem(m); 6872 error = ENETDOWN; 6873 goto bad; 6874 } 6875 /* 6876 * Grab a TX buffer and associated resources. 6877 */ 6878 bf = ath_getbuf(sc); 6879 if (bf == NULL) { 6880 sc->sc_stats.ast_tx_nobuf++; 6881 m_freem(m); 6882 error = ENOBUFS; 6883 goto bad; 6884 } 6885 6886 if (params == NULL) { 6887 /* 6888 * Legacy path; interpret frame contents to decide 6889 * precisely how to send the frame. 6890 */ 6891 if (ath_tx_start(sc, ni, bf, m)) { 6892 error = EIO; /* XXX */ 6893 goto bad2; 6894 } 6895 } else { 6896 /* 6897 * Caller supplied explicit parameters to use in 6898 * sending the frame. 6899 */ 6900 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 6901 error = EIO; /* XXX */ 6902 goto bad2; 6903 } 6904 } 6905 sc->sc_wd_timer = 5; 6906 ifp->if_opackets++; 6907 sc->sc_stats.ast_tx_raw++; 6908 6909 return 0; 6910 bad2: 6911 ATH_TXBUF_LOCK(sc); 6912 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 6913 ATH_TXBUF_UNLOCK(sc); 6914 bad: 6915 ifp->if_oerrors++; 6916 sc->sc_stats.ast_tx_raw_fail++; 6917 ieee80211_free_node(ni); 6918 return error; 6919 } 6920 6921 /* 6922 * Announce various information on device/driver attach. 6923 */ 6924 static void 6925 ath_announce(struct ath_softc *sc) 6926 { 6927 struct ifnet *ifp = sc->sc_ifp; 6928 struct ath_hal *ah = sc->sc_ah; 6929 6930 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 6931 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 6932 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 6933 if (bootverbose) { 6934 int i; 6935 for (i = 0; i <= WME_AC_VO; i++) { 6936 struct ath_txq *txq = sc->sc_ac2q[i]; 6937 if_printf(ifp, "Use hw queue %u for %s traffic\n", 6938 txq->axq_qnum, ieee80211_wme_acnames[i]); 6939 } 6940 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 6941 sc->sc_cabq->axq_qnum); 6942 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 6943 } 6944 if (ath_rxbuf != ATH_RXBUF) 6945 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 6946 if (ath_txbuf != ATH_TXBUF) 6947 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 6948 } 6949 6950 #ifdef IEEE80211_SUPPORT_TDMA 6951 static __inline uint32_t 6952 ath_hal_getnexttbtt(struct ath_hal *ah) 6953 { 6954 #define AR_TIMER0 0x8028 6955 return OS_REG_READ(ah, AR_TIMER0); 6956 } 6957 6958 static __inline void 6959 ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta) 6960 { 6961 /* XXX handle wrap/overflow */ 6962 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta); 6963 } 6964 6965 static void 6966 ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval) 6967 { 6968 struct ath_hal *ah = sc->sc_ah; 6969 HAL_BEACON_TIMERS bt; 6970 6971 bt.bt_intval = bintval | HAL_BEACON_ENA; 6972 bt.bt_nexttbtt = nexttbtt; 6973 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep; 6974 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep; 6975 bt.bt_nextatim = nexttbtt+1; 6976 ath_hal_beaconsettimers(ah, &bt); 6977 } 6978 6979 /* 6980 * Calculate the beacon interval. This is periodic in the 6981 * superframe for the bss. We assume each station is configured 6982 * identically wrt transmit rate so the guard time we calculate 6983 * above will be the same on all stations. Note we need to 6984 * factor in the xmit time because the hardware will schedule 6985 * a frame for transmit if the start of the frame is within 6986 * the burst time. When we get hardware that properly kills 6987 * frames in the PCU we can reduce/eliminate the guard time. 6988 * 6989 * Roundup to 1024 is so we have 1 TU buffer in the guard time 6990 * to deal with the granularity of the nexttbtt timer. 11n MAC's 6991 * with 1us timer granularity should allow us to reduce/eliminate 6992 * this. 6993 */ 6994 static void 6995 ath_tdma_bintvalsetup(struct ath_softc *sc, 6996 const struct ieee80211_tdma_state *tdma) 6997 { 6998 /* copy from vap state (XXX check all vaps have same value?) */ 6999 sc->sc_tdmaslotlen = tdma->tdma_slotlen; 7000 7001 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) * 7002 tdma->tdma_slotcnt, 1024); 7003 sc->sc_tdmabintval >>= 10; /* TSF -> TU */ 7004 if (sc->sc_tdmabintval & 1) 7005 sc->sc_tdmabintval++; 7006 7007 if (tdma->tdma_slot == 0) { 7008 /* 7009 * Only slot 0 beacons; other slots respond. 7010 */ 7011 sc->sc_imask |= HAL_INT_SWBA; 7012 sc->sc_tdmaswba = 0; /* beacon immediately */ 7013 } else { 7014 /* XXX all vaps must be slot 0 or slot !0 */ 7015 sc->sc_imask &= ~HAL_INT_SWBA; 7016 } 7017 } 7018 7019 /* 7020 * Max 802.11 overhead. This assumes no 4-address frames and 7021 * the encapsulation done by ieee80211_encap (llc). We also 7022 * include potential crypto overhead. 7023 */ 7024 #define IEEE80211_MAXOVERHEAD \ 7025 (sizeof(struct ieee80211_qosframe) \ 7026 + sizeof(struct llc) \ 7027 + IEEE80211_ADDR_LEN \ 7028 + IEEE80211_WEP_IVLEN \ 7029 + IEEE80211_WEP_KIDLEN \ 7030 + IEEE80211_WEP_CRCLEN \ 7031 + IEEE80211_WEP_MICLEN \ 7032 + IEEE80211_CRC_LEN) 7033 7034 /* 7035 * Setup initially for tdma operation. Start the beacon 7036 * timers and enable SWBA if we are slot 0. Otherwise 7037 * we wait for slot 0 to arrive so we can sync up before 7038 * starting to transmit. 7039 */ 7040 static void 7041 ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap) 7042 { 7043 struct ath_hal *ah = sc->sc_ah; 7044 struct ifnet *ifp = sc->sc_ifp; 7045 struct ieee80211com *ic = ifp->if_l2com; 7046 const struct ieee80211_txparam *tp; 7047 const struct ieee80211_tdma_state *tdma = NULL; 7048 int rix; 7049 7050 if (vap == NULL) { 7051 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 7052 if (vap == NULL) { 7053 if_printf(ifp, "%s: no vaps?\n", __func__); 7054 return; 7055 } 7056 } 7057 tp = vap->iv_bss->ni_txparms; 7058 /* 7059 * Calculate the guard time for each slot. This is the 7060 * time to send a maximal-size frame according to the 7061 * fixed/lowest transmit rate. Note that the interface 7062 * mtu does not include the 802.11 overhead so we must 7063 * tack that on (ath_hal_computetxtime includes the 7064 * preamble and plcp in it's calculation). 7065 */ 7066 tdma = vap->iv_tdma; 7067 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 7068 rix = ath_tx_findrix(sc, tp->ucastrate); 7069 else 7070 rix = ath_tx_findrix(sc, tp->mcastrate); 7071 /* XXX short preamble assumed */ 7072 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates, 7073 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE); 7074 7075 ath_hal_intrset(ah, 0); 7076 7077 ath_beaconq_config(sc); /* setup h/w beacon q */ 7078 if (sc->sc_setcca) 7079 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */ 7080 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */ 7081 ath_tdma_settimers(sc, sc->sc_tdmabintval, 7082 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF); 7083 sc->sc_syncbeacon = 0; 7084 7085 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER; 7086 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER; 7087 7088 ath_hal_intrset(ah, sc->sc_imask); 7089 7090 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u " 7091 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__, 7092 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt, 7093 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval, 7094 sc->sc_tdmadbaprep); 7095 } 7096 7097 /* 7098 * Update tdma operation. Called from the 802.11 layer 7099 * when a beacon is received from the TDMA station operating 7100 * in the slot immediately preceding us in the bss. Use 7101 * the rx timestamp for the beacon frame to update our 7102 * beacon timers so we follow their schedule. Note that 7103 * by using the rx timestamp we implicitly include the 7104 * propagation delay in our schedule. 7105 */ 7106 static void 7107 ath_tdma_update(struct ieee80211_node *ni, 7108 const struct ieee80211_tdma_param *tdma, int changed) 7109 { 7110 #define TSF_TO_TU(_h,_l) \ 7111 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 7112 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 7113 struct ieee80211vap *vap = ni->ni_vap; 7114 struct ieee80211com *ic = ni->ni_ic; 7115 struct ath_softc *sc = ic->ic_ifp->if_softc; 7116 struct ath_hal *ah = sc->sc_ah; 7117 const HAL_RATE_TABLE *rt = sc->sc_currates; 7118 u_int64_t tsf, rstamp, nextslot; 7119 u_int32_t txtime, nextslottu, timer0; 7120 int32_t tudelta, tsfdelta; 7121 const struct ath_rx_status *rs; 7122 int rix; 7123 7124 sc->sc_stats.ast_tdma_update++; 7125 7126 /* 7127 * Check for and adopt configuration changes. 7128 */ 7129 if (changed != 0) { 7130 const struct ieee80211_tdma_state *ts = vap->iv_tdma; 7131 7132 ath_tdma_bintvalsetup(sc, ts); 7133 if (changed & TDMA_UPDATE_SLOTLEN) 7134 ath_wme_update(ic); 7135 7136 DPRINTF(sc, ATH_DEBUG_TDMA, 7137 "%s: adopt slot %u slotcnt %u slotlen %u us " 7138 "bintval %u TU\n", __func__, 7139 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen, 7140 sc->sc_tdmabintval); 7141 7142 /* XXX right? */ 7143 ath_hal_intrset(ah, sc->sc_imask); 7144 /* NB: beacon timers programmed below */ 7145 } 7146 7147 /* extend rx timestamp to 64 bits */ 7148 rs = sc->sc_lastrs; 7149 tsf = ath_hal_gettsf64(ah); 7150 rstamp = ath_extend_tsf(rs->rs_tstamp, tsf); 7151 /* 7152 * The rx timestamp is set by the hardware on completing 7153 * reception (at the point where the rx descriptor is DMA'd 7154 * to the host). To find the start of our next slot we 7155 * must adjust this time by the time required to send 7156 * the packet just received. 7157 */ 7158 rix = rt->rateCodeToIndex[rs->rs_rate]; 7159 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix, 7160 rt->info[rix].shortPreamble); 7161 /* NB: << 9 is to cvt to TU and /2 */ 7162 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9); 7163 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD; 7164 7165 /* 7166 * TIMER0 is the h/w's idea of NextTBTT (in TU's). Convert 7167 * to usecs and calculate the difference between what the 7168 * other station thinks and what we have programmed. This 7169 * lets us figure how to adjust our timers to match. The 7170 * adjustments are done by pulling the TSF forward and possibly 7171 * rewriting the beacon timers. 7172 */ 7173 timer0 = ath_hal_getnexttbtt(ah); 7174 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD+1)) - TU_TO_TSF(timer0)); 7175 7176 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7177 "tsfdelta %d avg +%d/-%d\n", tsfdelta, 7178 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam)); 7179 7180 if (tsfdelta < 0) { 7181 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7182 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta); 7183 tsfdelta = -tsfdelta % 1024; 7184 nextslottu++; 7185 } else if (tsfdelta > 0) { 7186 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta); 7187 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7188 tsfdelta = 1024 - (tsfdelta % 1024); 7189 nextslottu++; 7190 } else { 7191 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7192 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7193 } 7194 tudelta = nextslottu - timer0; 7195 7196 /* 7197 * Copy sender's timetstamp into tdma ie so they can 7198 * calculate roundtrip time. We submit a beacon frame 7199 * below after any timer adjustment. The frame goes out 7200 * at the next TBTT so the sender can calculate the 7201 * roundtrip by inspecting the tdma ie in our beacon frame. 7202 * 7203 * NB: This tstamp is subtlely preserved when 7204 * IEEE80211_BEACON_TDMA is marked (e.g. when the 7205 * slot position changes) because ieee80211_add_tdma 7206 * skips over the data. 7207 */ 7208 memcpy(ATH_VAP(vap)->av_boff.bo_tdma + 7209 __offsetof(struct ieee80211_tdma_param, tdma_tstamp), 7210 &ni->ni_tstamp.data, 8); 7211 #if 0 7212 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7213 "tsf %llu nextslot %llu (%d, %d) nextslottu %u timer0 %u (%d)\n", 7214 (unsigned long long) tsf, (unsigned long long) nextslot, 7215 (int)(nextslot - tsf), tsfdelta, 7216 nextslottu, timer0, tudelta); 7217 #endif 7218 /* 7219 * Adjust the beacon timers only when pulling them forward 7220 * or when going back by less than the beacon interval. 7221 * Negative jumps larger than the beacon interval seem to 7222 * cause the timers to stop and generally cause instability. 7223 * This basically filters out jumps due to missed beacons. 7224 */ 7225 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) { 7226 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval); 7227 sc->sc_stats.ast_tdma_timers++; 7228 } 7229 if (tsfdelta > 0) { 7230 ath_hal_adjusttsf(ah, tsfdelta); 7231 sc->sc_stats.ast_tdma_tsf++; 7232 } 7233 ath_tdma_beacon_send(sc, vap); /* prepare response */ 7234 #undef TU_TO_TSF 7235 #undef TSF_TO_TU 7236 } 7237 7238 /* 7239 * Transmit a beacon frame at SWBA. Dynamic updates 7240 * to the frame contents are done as needed. 7241 */ 7242 static void 7243 ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap) 7244 { 7245 struct ath_hal *ah = sc->sc_ah; 7246 struct ath_buf *bf; 7247 int otherant; 7248 7249 /* 7250 * Check if the previous beacon has gone out. If 7251 * not don't try to post another, skip this period 7252 * and wait for the next. Missed beacons indicate 7253 * a problem and should not occur. If we miss too 7254 * many consecutive beacons reset the device. 7255 */ 7256 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 7257 sc->sc_bmisscount++; 7258 DPRINTF(sc, ATH_DEBUG_BEACON, 7259 "%s: missed %u consecutive beacons\n", 7260 __func__, sc->sc_bmisscount); 7261 if (sc->sc_bmisscount >= ath_bstuck_threshold) 7262 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 7263 return; 7264 } 7265 if (sc->sc_bmisscount != 0) { 7266 DPRINTF(sc, ATH_DEBUG_BEACON, 7267 "%s: resume beacon xmit after %u misses\n", 7268 __func__, sc->sc_bmisscount); 7269 sc->sc_bmisscount = 0; 7270 } 7271 7272 /* 7273 * Check recent per-antenna transmit statistics and flip 7274 * the default antenna if noticeably more frames went out 7275 * on the non-default antenna. 7276 * XXX assumes 2 anntenae 7277 */ 7278 if (!sc->sc_diversity) { 7279 otherant = sc->sc_defant & 1 ? 2 : 1; 7280 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 7281 ath_setdefantenna(sc, otherant); 7282 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 7283 } 7284 7285 bf = ath_beacon_generate(sc, vap); 7286 if (bf != NULL) { 7287 /* 7288 * Stop any current dma and put the new frame on the queue. 7289 * This should never fail since we check above that no frames 7290 * are still pending on the queue. 7291 */ 7292 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 7293 DPRINTF(sc, ATH_DEBUG_ANY, 7294 "%s: beacon queue %u did not stop?\n", 7295 __func__, sc->sc_bhalq); 7296 /* NB: the HAL still stops DMA, so proceed */ 7297 } 7298 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 7299 ath_hal_txstart(ah, sc->sc_bhalq); 7300 7301 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */ 7302 7303 /* 7304 * Record local TSF for our last send for use 7305 * in arbitrating slot collisions. 7306 */ 7307 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah); 7308 } 7309 } 7310 #endif /* IEEE80211_SUPPORT_TDMA */ 7311