1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42 #include "opt_inet.h" 43 #include "opt_ath.h" 44 /* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51 #include "opt_ah.h" 52 #include "opt_wlan.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysctl.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/kernel.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 #include <sys/errno.h> 65 #include <sys/callout.h> 66 #include <sys/bus.h> 67 #include <sys/endian.h> 68 #include <sys/kthread.h> 69 #include <sys/taskqueue.h> 70 #include <sys/priv.h> 71 #include <sys/module.h> 72 #include <sys/ktr.h> 73 #include <sys/smp.h> /* for mp_ncpus */ 74 75 #include <machine/bus.h> 76 77 #include <net/if.h> 78 #include <net/if_var.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_var.h> 87 #include <net80211/ieee80211_regdomain.h> 88 #ifdef IEEE80211_SUPPORT_SUPERG 89 #include <net80211/ieee80211_superg.h> 90 #endif 91 #ifdef IEEE80211_SUPPORT_TDMA 92 #include <net80211/ieee80211_tdma.h> 93 #endif 94 95 #include <net/bpf.h> 96 97 #ifdef INET 98 #include <netinet/in.h> 99 #include <netinet/if_ether.h> 100 #endif 101 102 #include <dev/ath/if_athvar.h> 103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 104 #include <dev/ath/ath_hal/ah_diagcodes.h> 105 106 #include <dev/ath/if_ath_debug.h> 107 #include <dev/ath/if_ath_misc.h> 108 #include <dev/ath/if_ath_tsf.h> 109 #include <dev/ath/if_ath_tx.h> 110 #include <dev/ath/if_ath_sysctl.h> 111 #include <dev/ath/if_ath_led.h> 112 #include <dev/ath/if_ath_keycache.h> 113 #include <dev/ath/if_ath_rx.h> 114 #include <dev/ath/if_ath_rx_edma.h> 115 #include <dev/ath/if_ath_tx_edma.h> 116 #include <dev/ath/if_ath_beacon.h> 117 #include <dev/ath/if_ath_btcoex.h> 118 #include <dev/ath/if_ath_btcoex_mci.h> 119 #include <dev/ath/if_ath_spectral.h> 120 #include <dev/ath/if_ath_lna_div.h> 121 #include <dev/ath/if_athdfs.h> 122 #include <dev/ath/if_ath_ioctl.h> 123 #include <dev/ath/if_ath_descdma.h> 124 125 #ifdef ATH_TX99_DIAG 126 #include <dev/ath/ath_tx99/ath_tx99.h> 127 #endif 128 129 #ifdef ATH_DEBUG_ALQ 130 #include <dev/ath/if_ath_alq.h> 131 #endif 132 133 /* 134 * Only enable this if you're working on PS-POLL support. 135 */ 136 #define ATH_SW_PSQ 137 138 /* 139 * ATH_BCBUF determines the number of vap's that can transmit 140 * beacons and also (currently) the number of vap's that can 141 * have unique mac addresses/bssid. When staggering beacons 142 * 4 is probably a good max as otherwise the beacons become 143 * very closely spaced and there is limited time for cab q traffic 144 * to go out. You can burst beacons instead but that is not good 145 * for stations in power save and at some point you really want 146 * another radio (and channel). 147 * 148 * The limit on the number of mac addresses is tied to our use of 149 * the U/L bit and tracking addresses in a byte; it would be 150 * worthwhile to allow more for applications like proxy sta. 151 */ 152 CTASSERT(ATH_BCBUF <= 8); 153 154 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 155 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 156 const uint8_t [IEEE80211_ADDR_LEN], 157 const uint8_t [IEEE80211_ADDR_LEN]); 158 static void ath_vap_delete(struct ieee80211vap *); 159 static int ath_init(struct ath_softc *); 160 static void ath_stop(struct ath_softc *); 161 static int ath_reset_vap(struct ieee80211vap *, u_long); 162 static int ath_transmit(struct ieee80211com *, struct mbuf *); 163 static int ath_media_change(struct ifnet *); 164 static void ath_watchdog(void *); 165 static void ath_parent(struct ieee80211com *); 166 static void ath_fatal_proc(void *, int); 167 static void ath_bmiss_vap(struct ieee80211vap *); 168 static void ath_bmiss_proc(void *, int); 169 static void ath_key_update_begin(struct ieee80211vap *); 170 static void ath_key_update_end(struct ieee80211vap *); 171 static void ath_update_mcast_hw(struct ath_softc *); 172 static void ath_update_mcast(struct ieee80211com *); 173 static void ath_update_promisc(struct ieee80211com *); 174 static void ath_updateslot(struct ieee80211com *); 175 static void ath_bstuck_proc(void *, int); 176 static void ath_reset_proc(void *, int); 177 static int ath_desc_alloc(struct ath_softc *); 178 static void ath_desc_free(struct ath_softc *); 179 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 180 const uint8_t [IEEE80211_ADDR_LEN]); 181 static void ath_node_cleanup(struct ieee80211_node *); 182 static void ath_node_free(struct ieee80211_node *); 183 static void ath_node_getsignal(const struct ieee80211_node *, 184 int8_t *, int8_t *); 185 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 186 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 187 static int ath_tx_setup(struct ath_softc *, int, int); 188 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 189 static void ath_tx_cleanup(struct ath_softc *); 190 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, 191 int dosched); 192 static void ath_tx_proc_q0(void *, int); 193 static void ath_tx_proc_q0123(void *, int); 194 static void ath_tx_proc(void *, int); 195 static void ath_txq_sched_tasklet(void *, int); 196 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 197 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 198 static void ath_scan_start(struct ieee80211com *); 199 static void ath_scan_end(struct ieee80211com *); 200 static void ath_set_channel(struct ieee80211com *); 201 #ifdef ATH_ENABLE_11N 202 static void ath_update_chw(struct ieee80211com *); 203 #endif /* ATH_ENABLE_11N */ 204 static int ath_set_quiet_ie(struct ieee80211_node *, uint8_t *); 205 static void ath_calibrate(void *); 206 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 207 static void ath_setup_stationkey(struct ieee80211_node *); 208 static void ath_newassoc(struct ieee80211_node *, int); 209 static int ath_setregdomain(struct ieee80211com *, 210 struct ieee80211_regdomain *, int, 211 struct ieee80211_channel []); 212 static void ath_getradiocaps(struct ieee80211com *, int, int *, 213 struct ieee80211_channel []); 214 static int ath_getchannels(struct ath_softc *); 215 216 static int ath_rate_setup(struct ath_softc *, u_int mode); 217 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 218 219 static void ath_announce(struct ath_softc *); 220 221 static void ath_dfs_tasklet(void *, int); 222 static void ath_node_powersave(struct ieee80211_node *, int); 223 static int ath_node_set_tim(struct ieee80211_node *, int); 224 static void ath_node_recv_pspoll(struct ieee80211_node *, struct mbuf *); 225 226 #ifdef IEEE80211_SUPPORT_TDMA 227 #include <dev/ath/if_ath_tdma.h> 228 #endif 229 230 SYSCTL_DECL(_hw_ath); 231 232 /* XXX validate sysctl values */ 233 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 234 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 235 0, "long chip calibration interval (secs)"); 236 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 237 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 238 0, "short chip calibration interval (msecs)"); 239 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 240 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 241 0, "reset chip calibration results (secs)"); 242 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */ 243 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval, 244 0, "ANI calibration (msecs)"); 245 246 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 247 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &ath_rxbuf, 248 0, "rx buffers allocated"); 249 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 250 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RWTUN, &ath_txbuf, 251 0, "tx buffers allocated"); 252 int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */ 253 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RWTUN, &ath_txbuf_mgmt, 254 0, "tx (mgmt) buffers allocated"); 255 256 int ath_bstuck_threshold = 4; /* max missed beacons */ 257 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 258 0, "max missed beacon xmits before chip reset"); 259 260 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 261 262 void 263 ath_legacy_attach_comp_func(struct ath_softc *sc) 264 { 265 266 /* 267 * Special case certain configurations. Note the 268 * CAB queue is handled by these specially so don't 269 * include them when checking the txq setup mask. 270 */ 271 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 272 case 0x01: 273 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 274 break; 275 case 0x0f: 276 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 277 break; 278 default: 279 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 280 break; 281 } 282 } 283 284 /* 285 * Set the target power mode. 286 * 287 * If this is called during a point in time where 288 * the hardware is being programmed elsewhere, it will 289 * simply store it away and update it when all current 290 * uses of the hardware are completed. 291 * 292 * If the chip is going into network sleep or power off, then 293 * we will wait until all uses of the chip are done before 294 * going into network sleep or power off. 295 * 296 * If the chip is being programmed full-awake, then immediately 297 * program it full-awake so we can actually stay awake rather than 298 * the chip potentially going to sleep underneath us. 299 */ 300 void 301 _ath_power_setpower(struct ath_softc *sc, int power_state, int selfgen, 302 const char *file, int line) 303 { 304 ATH_LOCK_ASSERT(sc); 305 306 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d, target=%d, cur=%d\n", 307 __func__, 308 file, 309 line, 310 power_state, 311 sc->sc_powersave_refcnt, 312 sc->sc_target_powerstate, 313 sc->sc_cur_powerstate); 314 315 sc->sc_target_powerstate = power_state; 316 317 /* 318 * Don't program the chip into network sleep if the chip 319 * is being programmed elsewhere. 320 * 321 * However, if the chip is being programmed /awake/, force 322 * the chip awake so we stay awake. 323 */ 324 if ((sc->sc_powersave_refcnt == 0 || power_state == HAL_PM_AWAKE) && 325 power_state != sc->sc_cur_powerstate) { 326 sc->sc_cur_powerstate = power_state; 327 ath_hal_setpower(sc->sc_ah, power_state); 328 329 /* 330 * If the NIC is force-awake, then set the 331 * self-gen frame state appropriately. 332 * 333 * If the nic is in network sleep or full-sleep, 334 * we let the above call leave the self-gen 335 * state as "sleep". 336 */ 337 if (selfgen && 338 sc->sc_cur_powerstate == HAL_PM_AWAKE && 339 sc->sc_target_selfgen_state != HAL_PM_AWAKE) { 340 ath_hal_setselfgenpower(sc->sc_ah, 341 sc->sc_target_selfgen_state); 342 } 343 } 344 } 345 346 /* 347 * Set the current self-generated frames state. 348 * 349 * This is separate from the target power mode. The chip may be 350 * awake but the desired state is "sleep", so frames sent to the 351 * destination has PWRMGT=1 in the 802.11 header. The NIC also 352 * needs to know to set PWRMGT=1 in self-generated frames. 353 */ 354 void 355 _ath_power_set_selfgen(struct ath_softc *sc, int power_state, const char *file, int line) 356 { 357 358 ATH_LOCK_ASSERT(sc); 359 360 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n", 361 __func__, 362 file, 363 line, 364 power_state, 365 sc->sc_target_selfgen_state); 366 367 sc->sc_target_selfgen_state = power_state; 368 369 /* 370 * If the NIC is force-awake, then set the power state. 371 * Network-state and full-sleep will already transition it to 372 * mark self-gen frames as sleeping - and we can't 373 * guarantee the NIC is awake to program the self-gen frame 374 * setting anyway. 375 */ 376 if (sc->sc_cur_powerstate == HAL_PM_AWAKE) { 377 ath_hal_setselfgenpower(sc->sc_ah, power_state); 378 } 379 } 380 381 /* 382 * Set the hardware power mode and take a reference. 383 * 384 * This doesn't update the target power mode in the driver; 385 * it just updates the hardware power state. 386 * 387 * XXX it should only ever force the hardware awake; it should 388 * never be called to set it asleep. 389 */ 390 void 391 _ath_power_set_power_state(struct ath_softc *sc, int power_state, const char *file, int line) 392 { 393 ATH_LOCK_ASSERT(sc); 394 395 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n", 396 __func__, 397 file, 398 line, 399 power_state, 400 sc->sc_powersave_refcnt); 401 402 sc->sc_powersave_refcnt++; 403 404 /* 405 * Only do the power state change if we're not programming 406 * it elsewhere. 407 */ 408 if (power_state != sc->sc_cur_powerstate) { 409 ath_hal_setpower(sc->sc_ah, power_state); 410 sc->sc_cur_powerstate = power_state; 411 /* 412 * Adjust the self-gen powerstate if appropriate. 413 */ 414 if (sc->sc_cur_powerstate == HAL_PM_AWAKE && 415 sc->sc_target_selfgen_state != HAL_PM_AWAKE) { 416 ath_hal_setselfgenpower(sc->sc_ah, 417 sc->sc_target_selfgen_state); 418 } 419 } 420 } 421 422 /* 423 * Restore the power save mode to what it once was. 424 * 425 * This will decrement the reference counter and once it hits 426 * zero, it'll restore the powersave state. 427 */ 428 void 429 _ath_power_restore_power_state(struct ath_softc *sc, const char *file, int line) 430 { 431 432 ATH_LOCK_ASSERT(sc); 433 434 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) refcnt=%d, target state=%d\n", 435 __func__, 436 file, 437 line, 438 sc->sc_powersave_refcnt, 439 sc->sc_target_powerstate); 440 441 if (sc->sc_powersave_refcnt == 0) 442 device_printf(sc->sc_dev, "%s: refcnt=0?\n", __func__); 443 else 444 sc->sc_powersave_refcnt--; 445 446 if (sc->sc_powersave_refcnt == 0 && 447 sc->sc_target_powerstate != sc->sc_cur_powerstate) { 448 sc->sc_cur_powerstate = sc->sc_target_powerstate; 449 ath_hal_setpower(sc->sc_ah, sc->sc_target_powerstate); 450 } 451 452 /* 453 * Adjust the self-gen powerstate if appropriate. 454 */ 455 if (sc->sc_cur_powerstate == HAL_PM_AWAKE && 456 sc->sc_target_selfgen_state != HAL_PM_AWAKE) { 457 ath_hal_setselfgenpower(sc->sc_ah, 458 sc->sc_target_selfgen_state); 459 } 460 461 } 462 463 /* 464 * Configure the initial HAL configuration values based on bus 465 * specific parameters. 466 * 467 * Some PCI IDs and other information may need tweaking. 468 * 469 * XXX TODO: ath9k and the Atheros HAL only program comm2g_switch_enable 470 * if BT antenna diversity isn't enabled. 471 * 472 * So, let's also figure out how to enable BT diversity for AR9485. 473 */ 474 static void 475 ath_setup_hal_config(struct ath_softc *sc, HAL_OPS_CONFIG *ah_config) 476 { 477 /* XXX TODO: only for PCI devices? */ 478 479 if (sc->sc_pci_devinfo & (ATH_PCI_CUS198 | ATH_PCI_CUS230)) { 480 ah_config->ath_hal_ext_lna_ctl_gpio = 0x200; /* bit 9 */ 481 ah_config->ath_hal_ext_atten_margin_cfg = AH_TRUE; 482 ah_config->ath_hal_min_gainidx = AH_TRUE; 483 ah_config->ath_hal_ant_ctrl_comm2g_switch_enable = 0x000bbb88; 484 /* XXX low_rssi_thresh */ 485 /* XXX fast_div_bias */ 486 device_printf(sc->sc_dev, "configuring for %s\n", 487 (sc->sc_pci_devinfo & ATH_PCI_CUS198) ? 488 "CUS198" : "CUS230"); 489 } 490 491 if (sc->sc_pci_devinfo & ATH_PCI_CUS217) 492 device_printf(sc->sc_dev, "CUS217 card detected\n"); 493 494 if (sc->sc_pci_devinfo & ATH_PCI_CUS252) 495 device_printf(sc->sc_dev, "CUS252 card detected\n"); 496 497 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_1ANT) 498 device_printf(sc->sc_dev, "WB335 1-ANT card detected\n"); 499 500 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_2ANT) 501 device_printf(sc->sc_dev, "WB335 2-ANT card detected\n"); 502 503 if (sc->sc_pci_devinfo & ATH_PCI_BT_ANT_DIV) 504 device_printf(sc->sc_dev, 505 "Bluetooth Antenna Diversity card detected\n"); 506 507 if (sc->sc_pci_devinfo & ATH_PCI_KILLER) 508 device_printf(sc->sc_dev, "Killer Wireless card detected\n"); 509 510 #if 0 511 /* 512 * Some WB335 cards do not support antenna diversity. Since 513 * we use a hardcoded value for AR9565 instead of using the 514 * EEPROM/OTP data, remove the combining feature from 515 * the HW capabilities bitmap. 516 */ 517 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 518 if (!(sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV)) 519 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 520 } 521 522 if (sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV) { 523 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 524 device_printf(sc->sc_dev, "Set BT/WLAN RX diversity capability\n"); 525 } 526 #endif 527 528 if (sc->sc_pci_devinfo & ATH_PCI_D3_L1_WAR) { 529 ah_config->ath_hal_pcie_waen = 0x0040473b; 530 device_printf(sc->sc_dev, "Enable WAR for ASPM D3/L1\n"); 531 } 532 533 #if 0 534 if (sc->sc_pci_devinfo & ATH9K_PCI_NO_PLL_PWRSAVE) { 535 ah->config.no_pll_pwrsave = true; 536 device_printf(sc->sc_dev, "Disable PLL PowerSave\n"); 537 } 538 #endif 539 540 } 541 542 /* 543 * Attempt to fetch the MAC address from the kernel environment. 544 * 545 * Returns 0, macaddr in macaddr if successful; -1 otherwise. 546 */ 547 static int 548 ath_fetch_mac_kenv(struct ath_softc *sc, uint8_t *macaddr) 549 { 550 char devid_str[32]; 551 int local_mac = 0; 552 char *local_macstr; 553 554 /* 555 * Fetch from the kenv rather than using hints. 556 * 557 * Hints would be nice but the transition to dynamic 558 * hints/kenv doesn't happen early enough for this 559 * to work reliably (eg on anything embedded.) 560 */ 561 snprintf(devid_str, 32, "hint.%s.%d.macaddr", 562 device_get_name(sc->sc_dev), 563 device_get_unit(sc->sc_dev)); 564 565 if ((local_macstr = kern_getenv(devid_str)) != NULL) { 566 uint32_t tmpmac[ETHER_ADDR_LEN]; 567 int count; 568 int i; 569 570 /* Have a MAC address; should use it */ 571 device_printf(sc->sc_dev, 572 "Overriding MAC address from environment: '%s'\n", 573 local_macstr); 574 575 /* Extract out the MAC address */ 576 count = sscanf(local_macstr, "%x%*c%x%*c%x%*c%x%*c%x%*c%x", 577 &tmpmac[0], &tmpmac[1], 578 &tmpmac[2], &tmpmac[3], 579 &tmpmac[4], &tmpmac[5]); 580 if (count == 6) { 581 /* Valid! */ 582 local_mac = 1; 583 for (i = 0; i < ETHER_ADDR_LEN; i++) 584 macaddr[i] = tmpmac[i]; 585 } 586 /* Done! */ 587 freeenv(local_macstr); 588 local_macstr = NULL; 589 } 590 591 if (local_mac) 592 return (0); 593 return (-1); 594 } 595 596 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20) 597 #define HAL_MODE_HT40 \ 598 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \ 599 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS) 600 int 601 ath_attach(u_int16_t devid, struct ath_softc *sc) 602 { 603 struct ieee80211com *ic = &sc->sc_ic; 604 struct ath_hal *ah = NULL; 605 HAL_STATUS status; 606 int error = 0, i; 607 u_int wmodes; 608 int rx_chainmask, tx_chainmask; 609 HAL_OPS_CONFIG ah_config; 610 611 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 612 613 ic->ic_softc = sc; 614 ic->ic_name = device_get_nameunit(sc->sc_dev); 615 616 /* 617 * Configure the initial configuration data. 618 * 619 * This is stuff that may be needed early during attach 620 * rather than done via configuration calls later. 621 */ 622 bzero(&ah_config, sizeof(ah_config)); 623 ath_setup_hal_config(sc, &ah_config); 624 625 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, 626 sc->sc_eepromdata, &ah_config, &status); 627 if (ah == NULL) { 628 device_printf(sc->sc_dev, 629 "unable to attach hardware; HAL status %u\n", status); 630 error = ENXIO; 631 goto bad; 632 } 633 sc->sc_ah = ah; 634 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 635 #ifdef ATH_DEBUG 636 sc->sc_debug = ath_debug; 637 #endif 638 639 /* 640 * Force the chip awake during setup, just to keep 641 * the HAL/driver power tracking happy. 642 * 643 * There are some methods (eg ath_hal_setmac()) 644 * that poke the hardware. 645 */ 646 ATH_LOCK(sc); 647 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 648 ATH_UNLOCK(sc); 649 650 /* 651 * Setup the DMA/EDMA functions based on the current 652 * hardware support. 653 * 654 * This is required before the descriptors are allocated. 655 */ 656 if (ath_hal_hasedma(sc->sc_ah)) { 657 sc->sc_isedma = 1; 658 ath_recv_setup_edma(sc); 659 ath_xmit_setup_edma(sc); 660 } else { 661 ath_recv_setup_legacy(sc); 662 ath_xmit_setup_legacy(sc); 663 } 664 665 if (ath_hal_hasmybeacon(sc->sc_ah)) { 666 sc->sc_do_mybeacon = 1; 667 } 668 669 /* 670 * Check if the MAC has multi-rate retry support. 671 * We do this by trying to setup a fake extended 672 * descriptor. MAC's that don't have support will 673 * return false w/o doing anything. MAC's that do 674 * support it will return true w/o doing anything. 675 */ 676 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 677 678 /* 679 * Check if the device has hardware counters for PHY 680 * errors. If so we need to enable the MIB interrupt 681 * so we can act on stat triggers. 682 */ 683 if (ath_hal_hwphycounters(ah)) 684 sc->sc_needmib = 1; 685 686 /* 687 * Get the hardware key cache size. 688 */ 689 sc->sc_keymax = ath_hal_keycachesize(ah); 690 if (sc->sc_keymax > ATH_KEYMAX) { 691 device_printf(sc->sc_dev, 692 "Warning, using only %u of %u key cache slots\n", 693 ATH_KEYMAX, sc->sc_keymax); 694 sc->sc_keymax = ATH_KEYMAX; 695 } 696 /* 697 * Reset the key cache since some parts do not 698 * reset the contents on initial power up. 699 */ 700 for (i = 0; i < sc->sc_keymax; i++) 701 ath_hal_keyreset(ah, i); 702 703 /* 704 * Collect the default channel list. 705 */ 706 error = ath_getchannels(sc); 707 if (error != 0) 708 goto bad; 709 710 /* 711 * Setup rate tables for all potential media types. 712 */ 713 ath_rate_setup(sc, IEEE80211_MODE_11A); 714 ath_rate_setup(sc, IEEE80211_MODE_11B); 715 ath_rate_setup(sc, IEEE80211_MODE_11G); 716 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 717 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 718 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 719 ath_rate_setup(sc, IEEE80211_MODE_11NA); 720 ath_rate_setup(sc, IEEE80211_MODE_11NG); 721 ath_rate_setup(sc, IEEE80211_MODE_HALF); 722 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 723 724 /* NB: setup here so ath_rate_update is happy */ 725 ath_setcurmode(sc, IEEE80211_MODE_11A); 726 727 /* 728 * Allocate TX descriptors and populate the lists. 729 */ 730 error = ath_desc_alloc(sc); 731 if (error != 0) { 732 device_printf(sc->sc_dev, 733 "failed to allocate TX descriptors: %d\n", error); 734 goto bad; 735 } 736 error = ath_txdma_setup(sc); 737 if (error != 0) { 738 device_printf(sc->sc_dev, 739 "failed to allocate TX descriptors: %d\n", error); 740 goto bad; 741 } 742 743 /* 744 * Allocate RX descriptors and populate the lists. 745 */ 746 error = ath_rxdma_setup(sc); 747 if (error != 0) { 748 device_printf(sc->sc_dev, 749 "failed to allocate RX descriptors: %d\n", error); 750 goto bad; 751 } 752 753 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 754 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 755 756 ATH_TXBUF_LOCK_INIT(sc); 757 758 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 759 taskqueue_thread_enqueue, &sc->sc_tq); 760 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 761 device_get_nameunit(sc->sc_dev)); 762 763 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc); 764 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 765 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 766 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc); 767 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc); 768 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 769 770 /* 771 * Allocate hardware transmit queues: one queue for 772 * beacon frames and one data queue for each QoS 773 * priority. Note that the hal handles resetting 774 * these queues at the needed time. 775 * 776 * XXX PS-Poll 777 */ 778 sc->sc_bhalq = ath_beaconq_setup(sc); 779 if (sc->sc_bhalq == (u_int) -1) { 780 device_printf(sc->sc_dev, 781 "unable to setup a beacon xmit queue!\n"); 782 error = EIO; 783 goto bad2; 784 } 785 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 786 if (sc->sc_cabq == NULL) { 787 device_printf(sc->sc_dev, "unable to setup CAB xmit queue!\n"); 788 error = EIO; 789 goto bad2; 790 } 791 /* NB: insure BK queue is the lowest priority h/w queue */ 792 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 793 device_printf(sc->sc_dev, 794 "unable to setup xmit queue for %s traffic!\n", 795 ieee80211_wme_acnames[WME_AC_BK]); 796 error = EIO; 797 goto bad2; 798 } 799 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 800 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 801 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 802 /* 803 * Not enough hardware tx queues to properly do WME; 804 * just punt and assign them all to the same h/w queue. 805 * We could do a better job of this if, for example, 806 * we allocate queues when we switch from station to 807 * AP mode. 808 */ 809 if (sc->sc_ac2q[WME_AC_VI] != NULL) 810 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 811 if (sc->sc_ac2q[WME_AC_BE] != NULL) 812 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 813 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 814 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 815 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 816 } 817 818 /* 819 * Attach the TX completion function. 820 * 821 * The non-EDMA chips may have some special case optimisations; 822 * this method gives everyone a chance to attach cleanly. 823 */ 824 sc->sc_tx.xmit_attach_comp_func(sc); 825 826 /* 827 * Setup rate control. Some rate control modules 828 * call back to change the anntena state so expose 829 * the necessary entry points. 830 * XXX maybe belongs in struct ath_ratectrl? 831 */ 832 sc->sc_setdefantenna = ath_setdefantenna; 833 sc->sc_rc = ath_rate_attach(sc); 834 if (sc->sc_rc == NULL) { 835 error = EIO; 836 goto bad2; 837 } 838 839 /* Attach DFS module */ 840 if (! ath_dfs_attach(sc)) { 841 device_printf(sc->sc_dev, 842 "%s: unable to attach DFS\n", __func__); 843 error = EIO; 844 goto bad2; 845 } 846 847 /* Attach spectral module */ 848 if (ath_spectral_attach(sc) < 0) { 849 device_printf(sc->sc_dev, 850 "%s: unable to attach spectral\n", __func__); 851 error = EIO; 852 goto bad2; 853 } 854 855 /* Attach bluetooth coexistence module */ 856 if (ath_btcoex_attach(sc) < 0) { 857 device_printf(sc->sc_dev, 858 "%s: unable to attach bluetooth coexistence\n", __func__); 859 error = EIO; 860 goto bad2; 861 } 862 863 /* Attach LNA diversity module */ 864 if (ath_lna_div_attach(sc) < 0) { 865 device_printf(sc->sc_dev, 866 "%s: unable to attach LNA diversity\n", __func__); 867 error = EIO; 868 goto bad2; 869 } 870 871 /* Start DFS processing tasklet */ 872 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc); 873 874 /* Configure LED state */ 875 sc->sc_blinking = 0; 876 sc->sc_ledstate = 1; 877 sc->sc_ledon = 0; /* low true */ 878 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 879 callout_init(&sc->sc_ledtimer, 1); 880 881 /* 882 * Don't setup hardware-based blinking. 883 * 884 * Although some NICs may have this configured in the 885 * default reset register values, the user may wish 886 * to alter which pins have which function. 887 * 888 * The reference driver attaches the MAC network LED to GPIO1 and 889 * the MAC power LED to GPIO2. However, the DWA-552 cardbus 890 * NIC has these reversed. 891 */ 892 sc->sc_hardled = (1 == 0); 893 sc->sc_led_net_pin = -1; 894 sc->sc_led_pwr_pin = -1; 895 /* 896 * Auto-enable soft led processing for IBM cards and for 897 * 5211 minipci cards. Users can also manually enable/disable 898 * support with a sysctl. 899 */ 900 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 901 ath_led_config(sc); 902 ath_hal_setledstate(ah, HAL_LED_INIT); 903 904 /* XXX not right but it's not used anywhere important */ 905 ic->ic_phytype = IEEE80211_T_OFDM; 906 ic->ic_opmode = IEEE80211_M_STA; 907 ic->ic_caps = 908 IEEE80211_C_STA /* station mode */ 909 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 910 | IEEE80211_C_HOSTAP /* hostap mode */ 911 | IEEE80211_C_MONITOR /* monitor mode */ 912 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 913 | IEEE80211_C_WDS /* 4-address traffic works */ 914 | IEEE80211_C_MBSS /* mesh point link mode */ 915 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 916 | IEEE80211_C_SHSLOT /* short slot time supported */ 917 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 918 #ifndef ATH_ENABLE_11N 919 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 920 #endif 921 | IEEE80211_C_TXFRAG /* handle tx frags */ 922 #ifdef ATH_ENABLE_DFS 923 | IEEE80211_C_DFS /* Enable radar detection */ 924 #endif 925 | IEEE80211_C_PMGT /* Station side power mgmt */ 926 | IEEE80211_C_SWSLEEP 927 ; 928 /* 929 * Query the hal to figure out h/w crypto support. 930 */ 931 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 932 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 933 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 934 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 935 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 936 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 937 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 938 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 939 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 940 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 941 /* 942 * Check if h/w does the MIC and/or whether the 943 * separate key cache entries are required to 944 * handle both tx+rx MIC keys. 945 */ 946 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 947 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 948 /* 949 * If the h/w supports storing tx+rx MIC keys 950 * in one cache slot automatically enable use. 951 */ 952 if (ath_hal_hastkipsplit(ah) || 953 !ath_hal_settkipsplit(ah, AH_FALSE)) 954 sc->sc_splitmic = 1; 955 /* 956 * If the h/w can do TKIP MIC together with WME then 957 * we use it; otherwise we force the MIC to be done 958 * in software by the net80211 layer. 959 */ 960 if (ath_hal_haswmetkipmic(ah)) 961 sc->sc_wmetkipmic = 1; 962 } 963 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 964 /* 965 * Check for multicast key search support. 966 */ 967 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 968 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 969 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 970 } 971 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 972 /* 973 * Mark key cache slots associated with global keys 974 * as in use. If we knew TKIP was not to be used we 975 * could leave the +32, +64, and +32+64 slots free. 976 */ 977 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 978 setbit(sc->sc_keymap, i); 979 setbit(sc->sc_keymap, i+64); 980 if (sc->sc_splitmic) { 981 setbit(sc->sc_keymap, i+32); 982 setbit(sc->sc_keymap, i+32+64); 983 } 984 } 985 /* 986 * TPC support can be done either with a global cap or 987 * per-packet support. The latter is not available on 988 * all parts. We're a bit pedantic here as all parts 989 * support a global cap. 990 */ 991 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 992 ic->ic_caps |= IEEE80211_C_TXPMGT; 993 994 /* 995 * Mark WME capability only if we have sufficient 996 * hardware queues to do proper priority scheduling. 997 */ 998 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 999 ic->ic_caps |= IEEE80211_C_WME; 1000 /* 1001 * Check for misc other capabilities. 1002 */ 1003 if (ath_hal_hasbursting(ah)) 1004 ic->ic_caps |= IEEE80211_C_BURST; 1005 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 1006 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 1007 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 1008 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah); 1009 1010 /* XXX TODO: just make this a "store tx/rx timestamp length" operation */ 1011 if (ath_hal_get_rx_tsf_prec(ah, &i)) { 1012 if (i == 32) { 1013 sc->sc_rxtsf32 = 1; 1014 } 1015 if (bootverbose) 1016 device_printf(sc->sc_dev, "RX timestamp: %d bits\n", i); 1017 } 1018 if (ath_hal_get_tx_tsf_prec(ah, &i)) { 1019 if (bootverbose) 1020 device_printf(sc->sc_dev, "TX timestamp: %d bits\n", i); 1021 } 1022 1023 sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah); 1024 sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah); 1025 sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah); 1026 1027 /* 1028 * Some WB335 cards do not support antenna diversity. Since 1029 * we use a hardcoded value for AR9565 instead of using the 1030 * EEPROM/OTP data, remove the combining feature from 1031 * the HW capabilities bitmap. 1032 */ 1033 /* 1034 * XXX TODO: check reference driver and ath9k for what to do 1035 * here for WB335. I think we have to actually disable the 1036 * LNA div processing in the HAL and instead use the hard 1037 * coded values; and then use BT diversity. 1038 * 1039 * .. but also need to setup MCI too for WB335.. 1040 */ 1041 #if 0 1042 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 1043 device_printf(sc->sc_dev, "%s: WB335: disabling LNA mixer diversity\n", 1044 __func__); 1045 sc->sc_dolnadiv = 0; 1046 } 1047 #endif 1048 1049 if (ath_hal_hasfastframes(ah)) 1050 ic->ic_caps |= IEEE80211_C_FF; 1051 wmodes = ath_hal_getwirelessmodes(ah); 1052 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 1053 ic->ic_caps |= IEEE80211_C_TURBOP; 1054 #ifdef IEEE80211_SUPPORT_TDMA 1055 if (ath_hal_macversion(ah) > 0x78) { 1056 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 1057 ic->ic_tdma_update = ath_tdma_update; 1058 } 1059 #endif 1060 1061 /* 1062 * TODO: enforce that at least this many frames are available 1063 * in the txbuf list before allowing data frames (raw or 1064 * otherwise) to be transmitted. 1065 */ 1066 sc->sc_txq_data_minfree = 10; 1067 1068 /* 1069 * Shorten this to 64 packets, or 1/4 ath_txbuf, whichever 1070 * is smaller. 1071 * 1072 * Anything bigger can potentially see the cabq consume 1073 * almost all buffers, starving everything else, only to 1074 * see most fail to transmit in the given beacon interval. 1075 */ 1076 sc->sc_txq_mcastq_maxdepth = MIN(64, ath_txbuf / 4); 1077 1078 /* 1079 * How deep can the node software TX queue get whilst it's asleep. 1080 */ 1081 sc->sc_txq_node_psq_maxdepth = 16; 1082 1083 /* 1084 * Default the maximum queue to 1/4'th the TX buffers, or 1085 * 64, whichever is smaller. 1086 */ 1087 sc->sc_txq_node_maxdepth = MIN(64, ath_txbuf / 4); 1088 1089 /* Enable CABQ by default */ 1090 sc->sc_cabq_enable = 1; 1091 1092 /* 1093 * Allow the TX and RX chainmasks to be overridden by 1094 * environment variables and/or device.hints. 1095 * 1096 * This must be done early - before the hardware is 1097 * calibrated or before the 802.11n stream calculation 1098 * is done. 1099 */ 1100 if (resource_int_value(device_get_name(sc->sc_dev), 1101 device_get_unit(sc->sc_dev), "rx_chainmask", 1102 &rx_chainmask) == 0) { 1103 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n", 1104 rx_chainmask); 1105 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask); 1106 } 1107 if (resource_int_value(device_get_name(sc->sc_dev), 1108 device_get_unit(sc->sc_dev), "tx_chainmask", 1109 &tx_chainmask) == 0) { 1110 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n", 1111 tx_chainmask); 1112 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask); 1113 } 1114 1115 /* 1116 * Query the TX/RX chainmask configuration. 1117 * 1118 * This is only relevant for 11n devices. 1119 */ 1120 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask); 1121 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask); 1122 1123 /* 1124 * Disable MRR with protected frames by default. 1125 * Only 802.11n series NICs can handle this. 1126 */ 1127 sc->sc_mrrprot = 0; /* XXX should be a capability */ 1128 1129 /* 1130 * Query the enterprise mode information the HAL. 1131 */ 1132 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0, 1133 &sc->sc_ent_cfg) == HAL_OK) 1134 sc->sc_use_ent = 1; 1135 1136 #ifdef ATH_ENABLE_11N 1137 /* 1138 * Query HT capabilities 1139 */ 1140 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK && 1141 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) { 1142 uint32_t rxs, txs; 1143 uint32_t ldpc; 1144 1145 device_printf(sc->sc_dev, "[HT] enabling HT modes\n"); 1146 1147 sc->sc_mrrprot = 1; /* XXX should be a capability */ 1148 1149 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */ 1150 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */ 1151 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */ 1152 | IEEE80211_HTCAP_MAXAMSDU_3839 1153 /* max A-MSDU length */ 1154 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */ 1155 1156 /* 1157 * Enable short-GI for HT20 only if the hardware 1158 * advertises support. 1159 * Notably, anything earlier than the AR9287 doesn't. 1160 */ 1161 if ((ath_hal_getcapability(ah, 1162 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) && 1163 (wmodes & HAL_MODE_HT20)) { 1164 device_printf(sc->sc_dev, 1165 "[HT] enabling short-GI in 20MHz mode\n"); 1166 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20; 1167 } 1168 1169 if (wmodes & HAL_MODE_HT40) 1170 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40 1171 | IEEE80211_HTCAP_SHORTGI40; 1172 1173 /* 1174 * TX/RX streams need to be taken into account when 1175 * negotiating which MCS rates it'll receive and 1176 * what MCS rates are available for TX. 1177 */ 1178 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs); 1179 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs); 1180 ic->ic_txstream = txs; 1181 ic->ic_rxstream = rxs; 1182 1183 /* 1184 * Setup TX and RX STBC based on what the HAL allows and 1185 * the currently configured chainmask set. 1186 * Ie - don't enable STBC TX if only one chain is enabled. 1187 * STBC RX is fine on a single RX chain; it just won't 1188 * provide any real benefit. 1189 */ 1190 if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0, 1191 NULL) == HAL_OK) { 1192 sc->sc_rx_stbc = 1; 1193 device_printf(sc->sc_dev, 1194 "[HT] 1 stream STBC receive enabled\n"); 1195 ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM; 1196 } 1197 if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0, 1198 NULL) == HAL_OK) { 1199 sc->sc_tx_stbc = 1; 1200 device_printf(sc->sc_dev, 1201 "[HT] 1 stream STBC transmit enabled\n"); 1202 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 1203 } 1204 1205 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1, 1206 &sc->sc_rts_aggr_limit); 1207 if (sc->sc_rts_aggr_limit != (64 * 1024)) 1208 device_printf(sc->sc_dev, 1209 "[HT] RTS aggregates limited to %d KiB\n", 1210 sc->sc_rts_aggr_limit / 1024); 1211 1212 /* 1213 * LDPC 1214 */ 1215 if ((ath_hal_getcapability(ah, HAL_CAP_LDPC, 0, &ldpc)) 1216 == HAL_OK && (ldpc == 1)) { 1217 sc->sc_has_ldpc = 1; 1218 device_printf(sc->sc_dev, 1219 "[HT] LDPC transmit/receive enabled\n"); 1220 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC | 1221 IEEE80211_HTC_TXLDPC; 1222 } 1223 1224 1225 device_printf(sc->sc_dev, 1226 "[HT] %d RX streams; %d TX streams\n", rxs, txs); 1227 } 1228 #endif 1229 1230 /* 1231 * Initial aggregation settings. 1232 */ 1233 sc->sc_hwq_limit_aggr = ATH_AGGR_MIN_QDEPTH; 1234 sc->sc_hwq_limit_nonaggr = ATH_NONAGGR_MIN_QDEPTH; 1235 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW; 1236 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH; 1237 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE; 1238 sc->sc_delim_min_pad = 0; 1239 1240 /* 1241 * Check if the hardware requires PCI register serialisation. 1242 * Some of the Owl based MACs require this. 1243 */ 1244 if (mp_ncpus > 1 && 1245 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR, 1246 0, NULL) == HAL_OK) { 1247 sc->sc_ah->ah_config.ah_serialise_reg_war = 1; 1248 device_printf(sc->sc_dev, 1249 "Enabling register serialisation\n"); 1250 } 1251 1252 /* 1253 * Initialise the deferred completed RX buffer list. 1254 */ 1255 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]); 1256 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]); 1257 1258 /* 1259 * Indicate we need the 802.11 header padded to a 1260 * 32-bit boundary for 4-address and QoS frames. 1261 */ 1262 ic->ic_flags |= IEEE80211_F_DATAPAD; 1263 1264 /* 1265 * Query the hal about antenna support. 1266 */ 1267 sc->sc_defant = ath_hal_getdefantenna(ah); 1268 1269 /* 1270 * Not all chips have the VEOL support we want to 1271 * use with IBSS beacons; check here for it. 1272 */ 1273 sc->sc_hasveol = ath_hal_hasveol(ah); 1274 1275 /* get mac address from kenv first, then hardware */ 1276 if (ath_fetch_mac_kenv(sc, ic->ic_macaddr) == 0) { 1277 /* Tell the HAL now about the new MAC */ 1278 ath_hal_setmac(ah, ic->ic_macaddr); 1279 } else { 1280 ath_hal_getmac(ah, ic->ic_macaddr); 1281 } 1282 1283 if (sc->sc_hasbmask) 1284 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 1285 1286 /* NB: used to size node table key mapping array */ 1287 ic->ic_max_keyix = sc->sc_keymax; 1288 /* call MI attach routine. */ 1289 ieee80211_ifattach(ic); 1290 ic->ic_setregdomain = ath_setregdomain; 1291 ic->ic_getradiocaps = ath_getradiocaps; 1292 sc->sc_opmode = HAL_M_STA; 1293 1294 /* override default methods */ 1295 ic->ic_ioctl = ath_ioctl; 1296 ic->ic_parent = ath_parent; 1297 ic->ic_transmit = ath_transmit; 1298 ic->ic_newassoc = ath_newassoc; 1299 ic->ic_updateslot = ath_updateslot; 1300 ic->ic_wme.wme_update = ath_wme_update; 1301 ic->ic_vap_create = ath_vap_create; 1302 ic->ic_vap_delete = ath_vap_delete; 1303 ic->ic_raw_xmit = ath_raw_xmit; 1304 ic->ic_update_mcast = ath_update_mcast; 1305 ic->ic_update_promisc = ath_update_promisc; 1306 ic->ic_node_alloc = ath_node_alloc; 1307 sc->sc_node_free = ic->ic_node_free; 1308 ic->ic_node_free = ath_node_free; 1309 sc->sc_node_cleanup = ic->ic_node_cleanup; 1310 ic->ic_node_cleanup = ath_node_cleanup; 1311 ic->ic_node_getsignal = ath_node_getsignal; 1312 ic->ic_scan_start = ath_scan_start; 1313 ic->ic_scan_end = ath_scan_end; 1314 ic->ic_set_channel = ath_set_channel; 1315 #ifdef ATH_ENABLE_11N 1316 /* 802.11n specific - but just override anyway */ 1317 sc->sc_addba_request = ic->ic_addba_request; 1318 sc->sc_addba_response = ic->ic_addba_response; 1319 sc->sc_addba_stop = ic->ic_addba_stop; 1320 sc->sc_bar_response = ic->ic_bar_response; 1321 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout; 1322 1323 ic->ic_addba_request = ath_addba_request; 1324 ic->ic_addba_response = ath_addba_response; 1325 ic->ic_addba_response_timeout = ath_addba_response_timeout; 1326 ic->ic_addba_stop = ath_addba_stop; 1327 ic->ic_bar_response = ath_bar_response; 1328 1329 ic->ic_update_chw = ath_update_chw; 1330 #endif /* ATH_ENABLE_11N */ 1331 ic->ic_set_quiet = ath_set_quiet_ie; 1332 1333 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 1334 /* 1335 * There's one vendor bitmap entry in the RX radiotap 1336 * header; make sure that's taken into account. 1337 */ 1338 ieee80211_radiotap_attachv(ic, 1339 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0, 1340 ATH_TX_RADIOTAP_PRESENT, 1341 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1, 1342 ATH_RX_RADIOTAP_PRESENT); 1343 #else 1344 /* 1345 * No vendor bitmap/extensions are present. 1346 */ 1347 ieee80211_radiotap_attach(ic, 1348 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 1349 ATH_TX_RADIOTAP_PRESENT, 1350 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1351 ATH_RX_RADIOTAP_PRESENT); 1352 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 1353 1354 /* 1355 * Setup the ALQ logging if required 1356 */ 1357 #ifdef ATH_DEBUG_ALQ 1358 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev)); 1359 if_ath_alq_setcfg(&sc->sc_alq, 1360 sc->sc_ah->ah_macVersion, 1361 sc->sc_ah->ah_macRev, 1362 sc->sc_ah->ah_phyRev, 1363 sc->sc_ah->ah_magic); 1364 #endif 1365 1366 /* 1367 * Setup dynamic sysctl's now that country code and 1368 * regdomain are available from the hal. 1369 */ 1370 ath_sysctlattach(sc); 1371 ath_sysctl_stats_attach(sc); 1372 ath_sysctl_hal_attach(sc); 1373 1374 if (bootverbose) 1375 ieee80211_announce(ic); 1376 ath_announce(sc); 1377 1378 /* 1379 * Put it to sleep for now. 1380 */ 1381 ATH_LOCK(sc); 1382 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1); 1383 ATH_UNLOCK(sc); 1384 1385 return 0; 1386 bad2: 1387 ath_tx_cleanup(sc); 1388 ath_desc_free(sc); 1389 ath_txdma_teardown(sc); 1390 ath_rxdma_teardown(sc); 1391 1392 bad: 1393 if (ah) 1394 ath_hal_detach(ah); 1395 sc->sc_invalid = 1; 1396 return error; 1397 } 1398 1399 int 1400 ath_detach(struct ath_softc *sc) 1401 { 1402 1403 /* 1404 * NB: the order of these is important: 1405 * o stop the chip so no more interrupts will fire 1406 * o call the 802.11 layer before detaching the hal to 1407 * insure callbacks into the driver to delete global 1408 * key cache entries can be handled 1409 * o free the taskqueue which drains any pending tasks 1410 * o reclaim the tx queue data structures after calling 1411 * the 802.11 layer as we'll get called back to reclaim 1412 * node state and potentially want to use them 1413 * o to cleanup the tx queues the hal is called, so detach 1414 * it last 1415 * Other than that, it's straightforward... 1416 */ 1417 1418 /* 1419 * XXX Wake the hardware up first. ath_stop() will still 1420 * wake it up first, but I'd rather do it here just to 1421 * ensure it's awake. 1422 */ 1423 ATH_LOCK(sc); 1424 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1425 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 1426 1427 /* 1428 * Stop things cleanly. 1429 */ 1430 ath_stop(sc); 1431 ATH_UNLOCK(sc); 1432 1433 ieee80211_ifdetach(&sc->sc_ic); 1434 taskqueue_free(sc->sc_tq); 1435 #ifdef ATH_TX99_DIAG 1436 if (sc->sc_tx99 != NULL) 1437 sc->sc_tx99->detach(sc->sc_tx99); 1438 #endif 1439 ath_rate_detach(sc->sc_rc); 1440 #ifdef ATH_DEBUG_ALQ 1441 if_ath_alq_tidyup(&sc->sc_alq); 1442 #endif 1443 ath_lna_div_detach(sc); 1444 ath_btcoex_detach(sc); 1445 ath_spectral_detach(sc); 1446 ath_dfs_detach(sc); 1447 ath_desc_free(sc); 1448 ath_txdma_teardown(sc); 1449 ath_rxdma_teardown(sc); 1450 ath_tx_cleanup(sc); 1451 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 1452 1453 return 0; 1454 } 1455 1456 /* 1457 * MAC address handling for multiple BSS on the same radio. 1458 * The first vap uses the MAC address from the EEPROM. For 1459 * subsequent vap's we set the U/L bit (bit 1) in the MAC 1460 * address and use the next six bits as an index. 1461 */ 1462 static void 1463 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 1464 { 1465 int i; 1466 1467 if (clone && sc->sc_hasbmask) { 1468 /* NB: we only do this if h/w supports multiple bssid */ 1469 for (i = 0; i < 8; i++) 1470 if ((sc->sc_bssidmask & (1<<i)) == 0) 1471 break; 1472 if (i != 0) 1473 mac[0] |= (i << 2)|0x2; 1474 } else 1475 i = 0; 1476 sc->sc_bssidmask |= 1<<i; 1477 sc->sc_hwbssidmask[0] &= ~mac[0]; 1478 if (i == 0) 1479 sc->sc_nbssid0++; 1480 } 1481 1482 static void 1483 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 1484 { 1485 int i = mac[0] >> 2; 1486 uint8_t mask; 1487 1488 if (i != 0 || --sc->sc_nbssid0 == 0) { 1489 sc->sc_bssidmask &= ~(1<<i); 1490 /* recalculate bssid mask from remaining addresses */ 1491 mask = 0xff; 1492 for (i = 1; i < 8; i++) 1493 if (sc->sc_bssidmask & (1<<i)) 1494 mask &= ~((i<<2)|0x2); 1495 sc->sc_hwbssidmask[0] |= mask; 1496 } 1497 } 1498 1499 /* 1500 * Assign a beacon xmit slot. We try to space out 1501 * assignments so when beacons are staggered the 1502 * traffic coming out of the cab q has maximal time 1503 * to go out before the next beacon is scheduled. 1504 */ 1505 static int 1506 assign_bslot(struct ath_softc *sc) 1507 { 1508 u_int slot, free; 1509 1510 free = 0; 1511 for (slot = 0; slot < ATH_BCBUF; slot++) 1512 if (sc->sc_bslot[slot] == NULL) { 1513 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 1514 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 1515 return slot; 1516 free = slot; 1517 /* NB: keep looking for a double slot */ 1518 } 1519 return free; 1520 } 1521 1522 static struct ieee80211vap * 1523 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1524 enum ieee80211_opmode opmode, int flags, 1525 const uint8_t bssid[IEEE80211_ADDR_LEN], 1526 const uint8_t mac0[IEEE80211_ADDR_LEN]) 1527 { 1528 struct ath_softc *sc = ic->ic_softc; 1529 struct ath_vap *avp; 1530 struct ieee80211vap *vap; 1531 uint8_t mac[IEEE80211_ADDR_LEN]; 1532 int needbeacon, error; 1533 enum ieee80211_opmode ic_opmode; 1534 1535 avp = malloc(sizeof(struct ath_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1536 needbeacon = 0; 1537 IEEE80211_ADDR_COPY(mac, mac0); 1538 1539 ATH_LOCK(sc); 1540 ic_opmode = opmode; /* default to opmode of new vap */ 1541 switch (opmode) { 1542 case IEEE80211_M_STA: 1543 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 1544 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 1545 goto bad; 1546 } 1547 if (sc->sc_nvaps) { 1548 /* 1549 * With multiple vaps we must fall back 1550 * to s/w beacon miss handling. 1551 */ 1552 flags |= IEEE80211_CLONE_NOBEACONS; 1553 } 1554 if (flags & IEEE80211_CLONE_NOBEACONS) { 1555 /* 1556 * Station mode w/o beacons are implemented w/ AP mode. 1557 */ 1558 ic_opmode = IEEE80211_M_HOSTAP; 1559 } 1560 break; 1561 case IEEE80211_M_IBSS: 1562 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 1563 device_printf(sc->sc_dev, 1564 "only 1 ibss vap supported\n"); 1565 goto bad; 1566 } 1567 needbeacon = 1; 1568 break; 1569 case IEEE80211_M_AHDEMO: 1570 #ifdef IEEE80211_SUPPORT_TDMA 1571 if (flags & IEEE80211_CLONE_TDMA) { 1572 if (sc->sc_nvaps != 0) { 1573 device_printf(sc->sc_dev, 1574 "only 1 tdma vap supported\n"); 1575 goto bad; 1576 } 1577 needbeacon = 1; 1578 flags |= IEEE80211_CLONE_NOBEACONS; 1579 } 1580 /* fall thru... */ 1581 #endif 1582 case IEEE80211_M_MONITOR: 1583 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 1584 /* 1585 * Adopt existing mode. Adding a monitor or ahdemo 1586 * vap to an existing configuration is of dubious 1587 * value but should be ok. 1588 */ 1589 /* XXX not right for monitor mode */ 1590 ic_opmode = ic->ic_opmode; 1591 } 1592 break; 1593 case IEEE80211_M_HOSTAP: 1594 case IEEE80211_M_MBSS: 1595 needbeacon = 1; 1596 break; 1597 case IEEE80211_M_WDS: 1598 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 1599 device_printf(sc->sc_dev, 1600 "wds not supported in sta mode\n"); 1601 goto bad; 1602 } 1603 /* 1604 * Silently remove any request for a unique 1605 * bssid; WDS vap's always share the local 1606 * mac address. 1607 */ 1608 flags &= ~IEEE80211_CLONE_BSSID; 1609 if (sc->sc_nvaps == 0) 1610 ic_opmode = IEEE80211_M_HOSTAP; 1611 else 1612 ic_opmode = ic->ic_opmode; 1613 break; 1614 default: 1615 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 1616 goto bad; 1617 } 1618 /* 1619 * Check that a beacon buffer is available; the code below assumes it. 1620 */ 1621 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) { 1622 device_printf(sc->sc_dev, "no beacon buffer available\n"); 1623 goto bad; 1624 } 1625 1626 /* STA, AHDEMO? */ 1627 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS || opmode == IEEE80211_M_STA) { 1628 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 1629 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1630 } 1631 1632 vap = &avp->av_vap; 1633 /* XXX can't hold mutex across if_alloc */ 1634 ATH_UNLOCK(sc); 1635 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1636 ATH_LOCK(sc); 1637 if (error != 0) { 1638 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 1639 __func__, error); 1640 goto bad2; 1641 } 1642 1643 /* h/w crypto support */ 1644 vap->iv_key_alloc = ath_key_alloc; 1645 vap->iv_key_delete = ath_key_delete; 1646 vap->iv_key_set = ath_key_set; 1647 vap->iv_key_update_begin = ath_key_update_begin; 1648 vap->iv_key_update_end = ath_key_update_end; 1649 1650 /* override various methods */ 1651 avp->av_recv_mgmt = vap->iv_recv_mgmt; 1652 vap->iv_recv_mgmt = ath_recv_mgmt; 1653 vap->iv_reset = ath_reset_vap; 1654 vap->iv_update_beacon = ath_beacon_update; 1655 avp->av_newstate = vap->iv_newstate; 1656 vap->iv_newstate = ath_newstate; 1657 avp->av_bmiss = vap->iv_bmiss; 1658 vap->iv_bmiss = ath_bmiss_vap; 1659 1660 avp->av_node_ps = vap->iv_node_ps; 1661 vap->iv_node_ps = ath_node_powersave; 1662 1663 avp->av_set_tim = vap->iv_set_tim; 1664 vap->iv_set_tim = ath_node_set_tim; 1665 1666 avp->av_recv_pspoll = vap->iv_recv_pspoll; 1667 vap->iv_recv_pspoll = ath_node_recv_pspoll; 1668 1669 /* Set default parameters */ 1670 1671 /* 1672 * Anything earlier than some AR9300 series MACs don't 1673 * support a smaller MPDU density. 1674 */ 1675 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8; 1676 /* 1677 * All NICs can handle the maximum size, however 1678 * AR5416 based MACs can only TX aggregates w/ RTS 1679 * protection when the total aggregate size is <= 8k. 1680 * However, for now that's enforced by the TX path. 1681 */ 1682 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1683 vap->iv_ampdu_limit = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1684 1685 avp->av_bslot = -1; 1686 if (needbeacon) { 1687 /* 1688 * Allocate beacon state and setup the q for buffered 1689 * multicast frames. We know a beacon buffer is 1690 * available because we checked above. 1691 */ 1692 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf); 1693 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list); 1694 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1695 /* 1696 * Assign the vap to a beacon xmit slot. As above 1697 * this cannot fail to find a free one. 1698 */ 1699 avp->av_bslot = assign_bslot(sc); 1700 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1701 ("beacon slot %u not empty", avp->av_bslot)); 1702 sc->sc_bslot[avp->av_bslot] = vap; 1703 sc->sc_nbcnvaps++; 1704 } 1705 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1706 /* 1707 * Multple vaps are to transmit beacons and we 1708 * have h/w support for TSF adjusting; enable 1709 * use of staggered beacons. 1710 */ 1711 sc->sc_stagbeacons = 1; 1712 } 1713 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1714 } 1715 1716 ic->ic_opmode = ic_opmode; 1717 if (opmode != IEEE80211_M_WDS) { 1718 sc->sc_nvaps++; 1719 if (opmode == IEEE80211_M_STA) 1720 sc->sc_nstavaps++; 1721 if (opmode == IEEE80211_M_MBSS) 1722 sc->sc_nmeshvaps++; 1723 } 1724 switch (ic_opmode) { 1725 case IEEE80211_M_IBSS: 1726 sc->sc_opmode = HAL_M_IBSS; 1727 break; 1728 case IEEE80211_M_STA: 1729 sc->sc_opmode = HAL_M_STA; 1730 break; 1731 case IEEE80211_M_AHDEMO: 1732 #ifdef IEEE80211_SUPPORT_TDMA 1733 if (vap->iv_caps & IEEE80211_C_TDMA) { 1734 sc->sc_tdma = 1; 1735 /* NB: disable tsf adjust */ 1736 sc->sc_stagbeacons = 0; 1737 } 1738 /* 1739 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1740 * just ap mode. 1741 */ 1742 /* fall thru... */ 1743 #endif 1744 case IEEE80211_M_HOSTAP: 1745 case IEEE80211_M_MBSS: 1746 sc->sc_opmode = HAL_M_HOSTAP; 1747 break; 1748 case IEEE80211_M_MONITOR: 1749 sc->sc_opmode = HAL_M_MONITOR; 1750 break; 1751 default: 1752 /* XXX should not happen */ 1753 break; 1754 } 1755 if (sc->sc_hastsfadd) { 1756 /* 1757 * Configure whether or not TSF adjust should be done. 1758 */ 1759 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1760 } 1761 if (flags & IEEE80211_CLONE_NOBEACONS) { 1762 /* 1763 * Enable s/w beacon miss handling. 1764 */ 1765 sc->sc_swbmiss = 1; 1766 } 1767 ATH_UNLOCK(sc); 1768 1769 /* complete setup */ 1770 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status, 1771 mac); 1772 return vap; 1773 bad2: 1774 reclaim_address(sc, mac); 1775 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1776 bad: 1777 free(avp, M_80211_VAP); 1778 ATH_UNLOCK(sc); 1779 return NULL; 1780 } 1781 1782 static void 1783 ath_vap_delete(struct ieee80211vap *vap) 1784 { 1785 struct ieee80211com *ic = vap->iv_ic; 1786 struct ath_softc *sc = ic->ic_softc; 1787 struct ath_hal *ah = sc->sc_ah; 1788 struct ath_vap *avp = ATH_VAP(vap); 1789 1790 ATH_LOCK(sc); 1791 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1792 ATH_UNLOCK(sc); 1793 1794 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 1795 if (sc->sc_running) { 1796 /* 1797 * Quiesce the hardware while we remove the vap. In 1798 * particular we need to reclaim all references to 1799 * the vap state by any frames pending on the tx queues. 1800 */ 1801 ath_hal_intrset(ah, 0); /* disable interrupts */ 1802 /* XXX Do all frames from all vaps/nodes need draining here? */ 1803 ath_stoprecv(sc, 1); /* stop recv side */ 1804 ath_rx_flush(sc); 1805 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */ 1806 } 1807 1808 /* .. leave the hardware awake for now. */ 1809 1810 ieee80211_vap_detach(vap); 1811 1812 /* 1813 * XXX Danger Will Robinson! Danger! 1814 * 1815 * Because ieee80211_vap_detach() can queue a frame (the station 1816 * diassociate message?) after we've drained the TXQ and 1817 * flushed the software TXQ, we will end up with a frame queued 1818 * to a node whose vap is about to be freed. 1819 * 1820 * To work around this, flush the hardware/software again. 1821 * This may be racy - the ath task may be running and the packet 1822 * may be being scheduled between sw->hw txq. Tsk. 1823 * 1824 * TODO: figure out why a new node gets allocated somewhere around 1825 * here (after the ath_tx_swq() call; and after an ath_stop() 1826 * call!) 1827 */ 1828 1829 ath_draintxq(sc, ATH_RESET_DEFAULT); 1830 1831 ATH_LOCK(sc); 1832 /* 1833 * Reclaim beacon state. Note this must be done before 1834 * the vap instance is reclaimed as we may have a reference 1835 * to it in the buffer for the beacon frame. 1836 */ 1837 if (avp->av_bcbuf != NULL) { 1838 if (avp->av_bslot != -1) { 1839 sc->sc_bslot[avp->av_bslot] = NULL; 1840 sc->sc_nbcnvaps--; 1841 } 1842 ath_beacon_return(sc, avp->av_bcbuf); 1843 avp->av_bcbuf = NULL; 1844 if (sc->sc_nbcnvaps == 0) { 1845 sc->sc_stagbeacons = 0; 1846 if (sc->sc_hastsfadd) 1847 ath_hal_settsfadjust(sc->sc_ah, 0); 1848 } 1849 /* 1850 * Reclaim any pending mcast frames for the vap. 1851 */ 1852 ath_tx_draintxq(sc, &avp->av_mcastq); 1853 } 1854 /* 1855 * Update bookkeeping. 1856 */ 1857 if (vap->iv_opmode == IEEE80211_M_STA) { 1858 sc->sc_nstavaps--; 1859 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1860 sc->sc_swbmiss = 0; 1861 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1862 vap->iv_opmode == IEEE80211_M_STA || 1863 vap->iv_opmode == IEEE80211_M_MBSS) { 1864 reclaim_address(sc, vap->iv_myaddr); 1865 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1866 if (vap->iv_opmode == IEEE80211_M_MBSS) 1867 sc->sc_nmeshvaps--; 1868 } 1869 if (vap->iv_opmode != IEEE80211_M_WDS) 1870 sc->sc_nvaps--; 1871 #ifdef IEEE80211_SUPPORT_TDMA 1872 /* TDMA operation ceases when the last vap is destroyed */ 1873 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1874 sc->sc_tdma = 0; 1875 sc->sc_swbmiss = 0; 1876 } 1877 #endif 1878 free(avp, M_80211_VAP); 1879 1880 if (sc->sc_running) { 1881 /* 1882 * Restart rx+tx machines if still running (RUNNING will 1883 * be reset if we just destroyed the last vap). 1884 */ 1885 if (ath_startrecv(sc) != 0) 1886 device_printf(sc->sc_dev, 1887 "%s: unable to restart recv logic\n", __func__); 1888 if (sc->sc_beacons) { /* restart beacons */ 1889 #ifdef IEEE80211_SUPPORT_TDMA 1890 if (sc->sc_tdma) 1891 ath_tdma_config(sc, NULL); 1892 else 1893 #endif 1894 ath_beacon_config(sc, NULL); 1895 } 1896 ath_hal_intrset(ah, sc->sc_imask); 1897 } 1898 1899 /* Ok, let the hardware asleep. */ 1900 ath_power_restore_power_state(sc); 1901 ATH_UNLOCK(sc); 1902 } 1903 1904 void 1905 ath_suspend(struct ath_softc *sc) 1906 { 1907 struct ieee80211com *ic = &sc->sc_ic; 1908 1909 sc->sc_resume_up = ic->ic_nrunning != 0; 1910 1911 ieee80211_suspend_all(ic); 1912 /* 1913 * NB: don't worry about putting the chip in low power 1914 * mode; pci will power off our socket on suspend and 1915 * CardBus detaches the device. 1916 * 1917 * XXX TODO: well, that's great, except for non-cardbus 1918 * devices! 1919 */ 1920 1921 /* 1922 * XXX This doesn't wait until all pending taskqueue 1923 * items and parallel transmit/receive/other threads 1924 * are running! 1925 */ 1926 ath_hal_intrset(sc->sc_ah, 0); 1927 taskqueue_block(sc->sc_tq); 1928 1929 ATH_LOCK(sc); 1930 callout_stop(&sc->sc_cal_ch); 1931 ATH_UNLOCK(sc); 1932 1933 /* 1934 * XXX ensure sc_invalid is 1 1935 */ 1936 1937 /* Disable the PCIe PHY, complete with workarounds */ 1938 ath_hal_enablepcie(sc->sc_ah, 1, 1); 1939 } 1940 1941 /* 1942 * Reset the key cache since some parts do not reset the 1943 * contents on resume. First we clear all entries, then 1944 * re-load keys that the 802.11 layer assumes are setup 1945 * in h/w. 1946 */ 1947 static void 1948 ath_reset_keycache(struct ath_softc *sc) 1949 { 1950 struct ieee80211com *ic = &sc->sc_ic; 1951 struct ath_hal *ah = sc->sc_ah; 1952 int i; 1953 1954 ATH_LOCK(sc); 1955 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1956 for (i = 0; i < sc->sc_keymax; i++) 1957 ath_hal_keyreset(ah, i); 1958 ath_power_restore_power_state(sc); 1959 ATH_UNLOCK(sc); 1960 ieee80211_crypto_reload_keys(ic); 1961 } 1962 1963 /* 1964 * Fetch the current chainmask configuration based on the current 1965 * operating channel and options. 1966 */ 1967 static void 1968 ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan) 1969 { 1970 1971 /* 1972 * Set TX chainmask to the currently configured chainmask; 1973 * the TX chainmask depends upon the current operating mode. 1974 */ 1975 sc->sc_cur_rxchainmask = sc->sc_rxchainmask; 1976 if (IEEE80211_IS_CHAN_HT(chan)) { 1977 sc->sc_cur_txchainmask = sc->sc_txchainmask; 1978 } else { 1979 sc->sc_cur_txchainmask = 1; 1980 } 1981 1982 DPRINTF(sc, ATH_DEBUG_RESET, 1983 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n", 1984 __func__, 1985 sc->sc_cur_txchainmask, 1986 sc->sc_cur_rxchainmask); 1987 } 1988 1989 void 1990 ath_resume(struct ath_softc *sc) 1991 { 1992 struct ieee80211com *ic = &sc->sc_ic; 1993 struct ath_hal *ah = sc->sc_ah; 1994 HAL_STATUS status; 1995 1996 ath_hal_enablepcie(ah, 0, 0); 1997 1998 /* 1999 * Must reset the chip before we reload the 2000 * keycache as we were powered down on suspend. 2001 */ 2002 ath_update_chainmasks(sc, 2003 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan); 2004 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2005 sc->sc_cur_rxchainmask); 2006 2007 /* Ensure we set the current power state to on */ 2008 ATH_LOCK(sc); 2009 ath_power_setselfgen(sc, HAL_PM_AWAKE); 2010 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2011 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 2012 ATH_UNLOCK(sc); 2013 2014 ath_hal_reset(ah, sc->sc_opmode, 2015 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 2016 AH_FALSE, HAL_RESET_NORMAL, &status); 2017 ath_reset_keycache(sc); 2018 2019 ATH_RX_LOCK(sc); 2020 sc->sc_rx_stopped = 1; 2021 sc->sc_rx_resetted = 1; 2022 ATH_RX_UNLOCK(sc); 2023 2024 /* Let DFS at it in case it's a DFS channel */ 2025 ath_dfs_radar_enable(sc, ic->ic_curchan); 2026 2027 /* Let spectral at in case spectral is enabled */ 2028 ath_spectral_enable(sc, ic->ic_curchan); 2029 2030 /* 2031 * Let bluetooth coexistence at in case it's needed for this channel 2032 */ 2033 ath_btcoex_enable(sc, ic->ic_curchan); 2034 2035 /* 2036 * If we're doing TDMA, enforce the TXOP limitation for chips that 2037 * support it. 2038 */ 2039 if (sc->sc_hasenforcetxop && sc->sc_tdma) 2040 ath_hal_setenforcetxop(sc->sc_ah, 1); 2041 else 2042 ath_hal_setenforcetxop(sc->sc_ah, 0); 2043 2044 /* Restore the LED configuration */ 2045 ath_led_config(sc); 2046 ath_hal_setledstate(ah, HAL_LED_INIT); 2047 2048 if (sc->sc_resume_up) 2049 ieee80211_resume_all(ic); 2050 2051 ATH_LOCK(sc); 2052 ath_power_restore_power_state(sc); 2053 ATH_UNLOCK(sc); 2054 2055 /* XXX beacons ? */ 2056 } 2057 2058 void 2059 ath_shutdown(struct ath_softc *sc) 2060 { 2061 2062 ATH_LOCK(sc); 2063 ath_stop(sc); 2064 ATH_UNLOCK(sc); 2065 /* NB: no point powering down chip as we're about to reboot */ 2066 } 2067 2068 /* 2069 * Interrupt handler. Most of the actual processing is deferred. 2070 */ 2071 void 2072 ath_intr(void *arg) 2073 { 2074 struct ath_softc *sc = arg; 2075 struct ath_hal *ah = sc->sc_ah; 2076 HAL_INT status = 0; 2077 uint32_t txqs; 2078 2079 /* 2080 * If we're inside a reset path, just print a warning and 2081 * clear the ISR. The reset routine will finish it for us. 2082 */ 2083 ATH_PCU_LOCK(sc); 2084 if (sc->sc_inreset_cnt) { 2085 HAL_INT status; 2086 ath_hal_getisr(ah, &status); /* clear ISR */ 2087 ath_hal_intrset(ah, 0); /* disable further intr's */ 2088 DPRINTF(sc, ATH_DEBUG_ANY, 2089 "%s: in reset, ignoring: status=0x%x\n", 2090 __func__, status); 2091 ATH_PCU_UNLOCK(sc); 2092 return; 2093 } 2094 2095 if (sc->sc_invalid) { 2096 /* 2097 * The hardware is not ready/present, don't touch anything. 2098 * Note this can happen early on if the IRQ is shared. 2099 */ 2100 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 2101 ATH_PCU_UNLOCK(sc); 2102 return; 2103 } 2104 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */ 2105 ATH_PCU_UNLOCK(sc); 2106 return; 2107 } 2108 2109 ATH_LOCK(sc); 2110 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2111 ATH_UNLOCK(sc); 2112 2113 if (sc->sc_ic.ic_nrunning == 0 && sc->sc_running == 0) { 2114 HAL_INT status; 2115 2116 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_nrunning %d sc_running %d\n", 2117 __func__, sc->sc_ic.ic_nrunning, sc->sc_running); 2118 ath_hal_getisr(ah, &status); /* clear ISR */ 2119 ath_hal_intrset(ah, 0); /* disable further intr's */ 2120 ATH_PCU_UNLOCK(sc); 2121 2122 ATH_LOCK(sc); 2123 ath_power_restore_power_state(sc); 2124 ATH_UNLOCK(sc); 2125 return; 2126 } 2127 2128 /* 2129 * Figure out the reason(s) for the interrupt. Note 2130 * that the hal returns a pseudo-ISR that may include 2131 * bits we haven't explicitly enabled so we mask the 2132 * value to insure we only process bits we requested. 2133 */ 2134 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 2135 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 2136 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status); 2137 #ifdef ATH_DEBUG_ALQ 2138 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate, 2139 ah->ah_syncstate); 2140 #endif /* ATH_DEBUG_ALQ */ 2141 #ifdef ATH_KTR_INTR_DEBUG 2142 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5, 2143 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x", 2144 ah->ah_intrstate[0], 2145 ah->ah_intrstate[1], 2146 ah->ah_intrstate[2], 2147 ah->ah_intrstate[3], 2148 ah->ah_intrstate[6]); 2149 #endif 2150 2151 /* Squirrel away SYNC interrupt debugging */ 2152 if (ah->ah_syncstate != 0) { 2153 int i; 2154 for (i = 0; i < 32; i++) 2155 if (ah->ah_syncstate & (1 << i)) 2156 sc->sc_intr_stats.sync_intr[i]++; 2157 } 2158 2159 status &= sc->sc_imask; /* discard unasked for bits */ 2160 2161 /* Short-circuit un-handled interrupts */ 2162 if (status == 0x0) { 2163 ATH_PCU_UNLOCK(sc); 2164 2165 ATH_LOCK(sc); 2166 ath_power_restore_power_state(sc); 2167 ATH_UNLOCK(sc); 2168 2169 return; 2170 } 2171 2172 /* 2173 * Take a note that we're inside the interrupt handler, so 2174 * the reset routines know to wait. 2175 */ 2176 sc->sc_intr_cnt++; 2177 ATH_PCU_UNLOCK(sc); 2178 2179 /* 2180 * Handle the interrupt. We won't run concurrent with the reset 2181 * or channel change routines as they'll wait for sc_intr_cnt 2182 * to be 0 before continuing. 2183 */ 2184 if (status & HAL_INT_FATAL) { 2185 sc->sc_stats.ast_hardware++; 2186 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 2187 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask); 2188 } else { 2189 if (status & HAL_INT_SWBA) { 2190 /* 2191 * Software beacon alert--time to send a beacon. 2192 * Handle beacon transmission directly; deferring 2193 * this is too slow to meet timing constraints 2194 * under load. 2195 */ 2196 #ifdef IEEE80211_SUPPORT_TDMA 2197 if (sc->sc_tdma) { 2198 if (sc->sc_tdmaswba == 0) { 2199 struct ieee80211com *ic = &sc->sc_ic; 2200 struct ieee80211vap *vap = 2201 TAILQ_FIRST(&ic->ic_vaps); 2202 ath_tdma_beacon_send(sc, vap); 2203 sc->sc_tdmaswba = 2204 vap->iv_tdma->tdma_bintval; 2205 } else 2206 sc->sc_tdmaswba--; 2207 } else 2208 #endif 2209 { 2210 ath_beacon_proc(sc, 0); 2211 #ifdef IEEE80211_SUPPORT_SUPERG 2212 /* 2213 * Schedule the rx taskq in case there's no 2214 * traffic so any frames held on the staging 2215 * queue are aged and potentially flushed. 2216 */ 2217 sc->sc_rx.recv_sched(sc, 1); 2218 #endif 2219 } 2220 } 2221 if (status & HAL_INT_RXEOL) { 2222 int imask; 2223 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL"); 2224 if (! sc->sc_isedma) { 2225 ATH_PCU_LOCK(sc); 2226 /* 2227 * NB: the hardware should re-read the link when 2228 * RXE bit is written, but it doesn't work at 2229 * least on older hardware revs. 2230 */ 2231 sc->sc_stats.ast_rxeol++; 2232 /* 2233 * Disable RXEOL/RXORN - prevent an interrupt 2234 * storm until the PCU logic can be reset. 2235 * In case the interface is reset some other 2236 * way before "sc_kickpcu" is called, don't 2237 * modify sc_imask - that way if it is reset 2238 * by a call to ath_reset() somehow, the 2239 * interrupt mask will be correctly reprogrammed. 2240 */ 2241 imask = sc->sc_imask; 2242 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN); 2243 ath_hal_intrset(ah, imask); 2244 /* 2245 * Only blank sc_rxlink if we've not yet kicked 2246 * the PCU. 2247 * 2248 * This isn't entirely correct - the correct solution 2249 * would be to have a PCU lock and engage that for 2250 * the duration of the PCU fiddling; which would include 2251 * running the RX process. Otherwise we could end up 2252 * messing up the RX descriptor chain and making the 2253 * RX desc list much shorter. 2254 */ 2255 if (! sc->sc_kickpcu) 2256 sc->sc_rxlink = NULL; 2257 sc->sc_kickpcu = 1; 2258 ATH_PCU_UNLOCK(sc); 2259 } 2260 /* 2261 * Enqueue an RX proc to handle whatever 2262 * is in the RX queue. 2263 * This will then kick the PCU if required. 2264 */ 2265 sc->sc_rx.recv_sched(sc, 1); 2266 } 2267 if (status & HAL_INT_TXURN) { 2268 sc->sc_stats.ast_txurn++; 2269 /* bump tx trigger level */ 2270 ath_hal_updatetxtriglevel(ah, AH_TRUE); 2271 } 2272 /* 2273 * Handle both the legacy and RX EDMA interrupt bits. 2274 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC. 2275 */ 2276 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) { 2277 sc->sc_stats.ast_rx_intr++; 2278 sc->sc_rx.recv_sched(sc, 1); 2279 } 2280 if (status & HAL_INT_TX) { 2281 sc->sc_stats.ast_tx_intr++; 2282 /* 2283 * Grab all the currently set bits in the HAL txq bitmap 2284 * and blank them. This is the only place we should be 2285 * doing this. 2286 */ 2287 if (! sc->sc_isedma) { 2288 ATH_PCU_LOCK(sc); 2289 txqs = 0xffffffff; 2290 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs); 2291 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3, 2292 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x", 2293 txqs, 2294 sc->sc_txq_active, 2295 sc->sc_txq_active | txqs); 2296 sc->sc_txq_active |= txqs; 2297 ATH_PCU_UNLOCK(sc); 2298 } 2299 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 2300 } 2301 if (status & HAL_INT_BMISS) { 2302 sc->sc_stats.ast_bmiss++; 2303 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 2304 } 2305 if (status & HAL_INT_GTT) 2306 sc->sc_stats.ast_tx_timeout++; 2307 if (status & HAL_INT_CST) 2308 sc->sc_stats.ast_tx_cst++; 2309 if (status & HAL_INT_MIB) { 2310 sc->sc_stats.ast_mib++; 2311 ATH_PCU_LOCK(sc); 2312 /* 2313 * Disable interrupts until we service the MIB 2314 * interrupt; otherwise it will continue to fire. 2315 */ 2316 ath_hal_intrset(ah, 0); 2317 /* 2318 * Let the hal handle the event. We assume it will 2319 * clear whatever condition caused the interrupt. 2320 */ 2321 ath_hal_mibevent(ah, &sc->sc_halstats); 2322 /* 2323 * Don't reset the interrupt if we've just 2324 * kicked the PCU, or we may get a nested 2325 * RXEOL before the rxproc has had a chance 2326 * to run. 2327 */ 2328 if (sc->sc_kickpcu == 0) 2329 ath_hal_intrset(ah, sc->sc_imask); 2330 ATH_PCU_UNLOCK(sc); 2331 } 2332 if (status & HAL_INT_RXORN) { 2333 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 2334 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN"); 2335 sc->sc_stats.ast_rxorn++; 2336 } 2337 if (status & HAL_INT_TSFOOR) { 2338 /* out of range beacon - wake the chip up, 2339 * but don't modify self-gen frame config */ 2340 device_printf(sc->sc_dev, "%s: TSFOOR\n", __func__); 2341 sc->sc_syncbeacon = 1; 2342 ATH_LOCK(sc); 2343 ath_power_setpower(sc, HAL_PM_AWAKE, 0); 2344 ATH_UNLOCK(sc); 2345 } 2346 if (status & HAL_INT_MCI) { 2347 ath_btcoex_mci_intr(sc); 2348 } 2349 } 2350 ATH_PCU_LOCK(sc); 2351 sc->sc_intr_cnt--; 2352 ATH_PCU_UNLOCK(sc); 2353 2354 ATH_LOCK(sc); 2355 ath_power_restore_power_state(sc); 2356 ATH_UNLOCK(sc); 2357 } 2358 2359 static void 2360 ath_fatal_proc(void *arg, int pending) 2361 { 2362 struct ath_softc *sc = arg; 2363 u_int32_t *state; 2364 u_int32_t len; 2365 void *sp; 2366 2367 if (sc->sc_invalid) 2368 return; 2369 2370 device_printf(sc->sc_dev, "hardware error; resetting\n"); 2371 /* 2372 * Fatal errors are unrecoverable. Typically these 2373 * are caused by DMA errors. Collect h/w state from 2374 * the hal so we can diagnose what's going on. 2375 */ 2376 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 2377 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 2378 state = sp; 2379 device_printf(sc->sc_dev, 2380 "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", state[0], 2381 state[1] , state[2], state[3], state[4], state[5]); 2382 } 2383 ath_reset(sc, ATH_RESET_NOLOSS); 2384 } 2385 2386 static void 2387 ath_bmiss_vap(struct ieee80211vap *vap) 2388 { 2389 struct ath_softc *sc = vap->iv_ic->ic_softc; 2390 2391 /* 2392 * Workaround phantom bmiss interrupts by sanity-checking 2393 * the time of our last rx'd frame. If it is within the 2394 * beacon miss interval then ignore the interrupt. If it's 2395 * truly a bmiss we'll get another interrupt soon and that'll 2396 * be dispatched up for processing. Note this applies only 2397 * for h/w beacon miss events. 2398 */ 2399 2400 /* 2401 * XXX TODO: Just read the TSF during the interrupt path; 2402 * that way we don't have to wake up again just to read it 2403 * again. 2404 */ 2405 ATH_LOCK(sc); 2406 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2407 ATH_UNLOCK(sc); 2408 2409 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 2410 u_int64_t lastrx = sc->sc_lastrx; 2411 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 2412 /* XXX should take a locked ref to iv_bss */ 2413 u_int bmisstimeout = 2414 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 2415 2416 DPRINTF(sc, ATH_DEBUG_BEACON, 2417 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 2418 __func__, (unsigned long long) tsf, 2419 (unsigned long long)(tsf - lastrx), 2420 (unsigned long long) lastrx, bmisstimeout); 2421 2422 if (tsf - lastrx <= bmisstimeout) { 2423 sc->sc_stats.ast_bmiss_phantom++; 2424 2425 ATH_LOCK(sc); 2426 ath_power_restore_power_state(sc); 2427 ATH_UNLOCK(sc); 2428 2429 return; 2430 } 2431 } 2432 2433 /* 2434 * Keep the hardware awake if it's asleep (and leave self-gen 2435 * frame config alone) until the next beacon, so we can resync 2436 * against the next beacon. 2437 * 2438 * This handles three common beacon miss cases in STA powersave mode - 2439 * (a) the beacon TBTT isnt a multiple of bintval; 2440 * (b) the beacon was missed; and 2441 * (c) the beacons are being delayed because the AP is busy and 2442 * isn't reliably able to meet its TBTT. 2443 */ 2444 ATH_LOCK(sc); 2445 ath_power_setpower(sc, HAL_PM_AWAKE, 0); 2446 ath_power_restore_power_state(sc); 2447 ATH_UNLOCK(sc); 2448 DPRINTF(sc, ATH_DEBUG_BEACON, 2449 "%s: forced awake; force syncbeacon=1\n", __func__); 2450 2451 /* 2452 * Attempt to force a beacon resync. 2453 */ 2454 sc->sc_syncbeacon = 1; 2455 2456 ATH_VAP(vap)->av_bmiss(vap); 2457 } 2458 2459 /* XXX this needs a force wakeup! */ 2460 int 2461 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 2462 { 2463 uint32_t rsize; 2464 void *sp; 2465 2466 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize)) 2467 return 0; 2468 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 2469 *hangs = *(uint32_t *)sp; 2470 return 1; 2471 } 2472 2473 static void 2474 ath_bmiss_proc(void *arg, int pending) 2475 { 2476 struct ath_softc *sc = arg; 2477 uint32_t hangs; 2478 2479 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 2480 2481 ATH_LOCK(sc); 2482 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2483 ATH_UNLOCK(sc); 2484 2485 ath_beacon_miss(sc); 2486 2487 /* 2488 * Do a reset upon any becaon miss event. 2489 * 2490 * It may be a non-recognised RX clear hang which needs a reset 2491 * to clear. 2492 */ 2493 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 2494 ath_reset(sc, ATH_RESET_NOLOSS); 2495 device_printf(sc->sc_dev, 2496 "bb hang detected (0x%x), resetting\n", hangs); 2497 } else { 2498 ath_reset(sc, ATH_RESET_NOLOSS); 2499 ieee80211_beacon_miss(&sc->sc_ic); 2500 } 2501 2502 /* Force a beacon resync, in case they've drifted */ 2503 sc->sc_syncbeacon = 1; 2504 2505 ATH_LOCK(sc); 2506 ath_power_restore_power_state(sc); 2507 ATH_UNLOCK(sc); 2508 } 2509 2510 /* 2511 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 2512 * calcs together with WME. If necessary disable the crypto 2513 * hardware and mark the 802.11 state so keys will be setup 2514 * with the MIC work done in software. 2515 */ 2516 static void 2517 ath_settkipmic(struct ath_softc *sc) 2518 { 2519 struct ieee80211com *ic = &sc->sc_ic; 2520 2521 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 2522 if (ic->ic_flags & IEEE80211_F_WME) { 2523 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 2524 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 2525 } else { 2526 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 2527 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 2528 } 2529 } 2530 } 2531 2532 static void 2533 ath_vap_clear_quiet_ie(struct ath_softc *sc) 2534 { 2535 struct ieee80211com *ic = &sc->sc_ic; 2536 struct ieee80211vap *vap; 2537 struct ath_vap *avp; 2538 2539 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 2540 avp = ATH_VAP(vap); 2541 /* Quiet time handling - ensure we resync */ 2542 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 2543 } 2544 } 2545 2546 static int 2547 ath_init(struct ath_softc *sc) 2548 { 2549 struct ieee80211com *ic = &sc->sc_ic; 2550 struct ath_hal *ah = sc->sc_ah; 2551 HAL_STATUS status; 2552 2553 ATH_LOCK_ASSERT(sc); 2554 2555 /* 2556 * Force the sleep state awake. 2557 */ 2558 ath_power_setselfgen(sc, HAL_PM_AWAKE); 2559 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2560 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 2561 2562 /* 2563 * Stop anything previously setup. This is safe 2564 * whether this is the first time through or not. 2565 */ 2566 ath_stop(sc); 2567 2568 /* 2569 * The basic interface to setting the hardware in a good 2570 * state is ``reset''. On return the hardware is known to 2571 * be powered up and with interrupts disabled. This must 2572 * be followed by initialization of the appropriate bits 2573 * and then setup of the interrupt mask. 2574 */ 2575 ath_settkipmic(sc); 2576 ath_update_chainmasks(sc, ic->ic_curchan); 2577 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2578 sc->sc_cur_rxchainmask); 2579 2580 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, 2581 HAL_RESET_NORMAL, &status)) { 2582 device_printf(sc->sc_dev, 2583 "unable to reset hardware; hal status %u\n", status); 2584 return (ENODEV); 2585 } 2586 2587 ATH_RX_LOCK(sc); 2588 sc->sc_rx_stopped = 1; 2589 sc->sc_rx_resetted = 1; 2590 ATH_RX_UNLOCK(sc); 2591 2592 /* Clear quiet IE state for each VAP */ 2593 ath_vap_clear_quiet_ie(sc); 2594 2595 ath_chan_change(sc, ic->ic_curchan); 2596 2597 /* Let DFS at it in case it's a DFS channel */ 2598 ath_dfs_radar_enable(sc, ic->ic_curchan); 2599 2600 /* Let spectral at in case spectral is enabled */ 2601 ath_spectral_enable(sc, ic->ic_curchan); 2602 2603 /* 2604 * Let bluetooth coexistence at in case it's needed for this channel 2605 */ 2606 ath_btcoex_enable(sc, ic->ic_curchan); 2607 2608 /* 2609 * If we're doing TDMA, enforce the TXOP limitation for chips that 2610 * support it. 2611 */ 2612 if (sc->sc_hasenforcetxop && sc->sc_tdma) 2613 ath_hal_setenforcetxop(sc->sc_ah, 1); 2614 else 2615 ath_hal_setenforcetxop(sc->sc_ah, 0); 2616 2617 /* 2618 * Likewise this is set during reset so update 2619 * state cached in the driver. 2620 */ 2621 sc->sc_diversity = ath_hal_getdiversity(ah); 2622 sc->sc_lastlongcal = ticks; 2623 sc->sc_resetcal = 1; 2624 sc->sc_lastcalreset = 0; 2625 sc->sc_lastani = ticks; 2626 sc->sc_lastshortcal = ticks; 2627 sc->sc_doresetcal = AH_FALSE; 2628 /* 2629 * Beacon timers were cleared here; give ath_newstate() 2630 * a hint that the beacon timers should be poked when 2631 * things transition to the RUN state. 2632 */ 2633 sc->sc_beacons = 0; 2634 2635 /* 2636 * Setup the hardware after reset: the key cache 2637 * is filled as needed and the receive engine is 2638 * set going. Frame transmit is handled entirely 2639 * in the frame output path; there's nothing to do 2640 * here except setup the interrupt mask. 2641 */ 2642 if (ath_startrecv(sc) != 0) { 2643 device_printf(sc->sc_dev, "unable to start recv logic\n"); 2644 ath_power_restore_power_state(sc); 2645 return (ENODEV); 2646 } 2647 2648 /* 2649 * Enable interrupts. 2650 */ 2651 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 2652 | HAL_INT_RXORN | HAL_INT_TXURN 2653 | HAL_INT_FATAL | HAL_INT_GLOBAL; 2654 2655 /* 2656 * Enable RX EDMA bits. Note these overlap with 2657 * HAL_INT_RX and HAL_INT_RXDESC respectively. 2658 */ 2659 if (sc->sc_isedma) 2660 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP); 2661 2662 /* 2663 * If we're an EDMA NIC, we don't care about RXEOL. 2664 * Writing a new descriptor in will simply restart 2665 * RX DMA. 2666 */ 2667 if (! sc->sc_isedma) 2668 sc->sc_imask |= HAL_INT_RXEOL; 2669 2670 /* 2671 * Enable MCI interrupt for MCI devices. 2672 */ 2673 if (sc->sc_btcoex_mci) 2674 sc->sc_imask |= HAL_INT_MCI; 2675 2676 /* 2677 * Enable MIB interrupts when there are hardware phy counters. 2678 * Note we only do this (at the moment) for station mode. 2679 */ 2680 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 2681 sc->sc_imask |= HAL_INT_MIB; 2682 2683 /* 2684 * XXX add capability for this. 2685 * 2686 * If we're in STA mode (and maybe IBSS?) then register for 2687 * TSFOOR interrupts. 2688 */ 2689 if (ic->ic_opmode == IEEE80211_M_STA) 2690 sc->sc_imask |= HAL_INT_TSFOOR; 2691 2692 /* Enable global TX timeout and carrier sense timeout if available */ 2693 if (ath_hal_gtxto_supported(ah)) 2694 sc->sc_imask |= HAL_INT_GTT; 2695 2696 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n", 2697 __func__, sc->sc_imask); 2698 2699 sc->sc_running = 1; 2700 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 2701 ath_hal_intrset(ah, sc->sc_imask); 2702 2703 ath_power_restore_power_state(sc); 2704 2705 return (0); 2706 } 2707 2708 static void 2709 ath_stop(struct ath_softc *sc) 2710 { 2711 struct ath_hal *ah = sc->sc_ah; 2712 2713 ATH_LOCK_ASSERT(sc); 2714 2715 /* 2716 * Wake the hardware up before fiddling with it. 2717 */ 2718 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2719 2720 if (sc->sc_running) { 2721 /* 2722 * Shutdown the hardware and driver: 2723 * reset 802.11 state machine 2724 * turn off timers 2725 * disable interrupts 2726 * turn off the radio 2727 * clear transmit machinery 2728 * clear receive machinery 2729 * drain and release tx queues 2730 * reclaim beacon resources 2731 * power down hardware 2732 * 2733 * Note that some of this work is not possible if the 2734 * hardware is gone (invalid). 2735 */ 2736 #ifdef ATH_TX99_DIAG 2737 if (sc->sc_tx99 != NULL) 2738 sc->sc_tx99->stop(sc->sc_tx99); 2739 #endif 2740 callout_stop(&sc->sc_wd_ch); 2741 sc->sc_wd_timer = 0; 2742 sc->sc_running = 0; 2743 if (!sc->sc_invalid) { 2744 if (sc->sc_softled) { 2745 callout_stop(&sc->sc_ledtimer); 2746 ath_hal_gpioset(ah, sc->sc_ledpin, 2747 !sc->sc_ledon); 2748 sc->sc_blinking = 0; 2749 } 2750 ath_hal_intrset(ah, 0); 2751 } 2752 /* XXX we should stop RX regardless of whether it's valid */ 2753 if (!sc->sc_invalid) { 2754 ath_stoprecv(sc, 1); 2755 ath_hal_phydisable(ah); 2756 } else 2757 sc->sc_rxlink = NULL; 2758 ath_draintxq(sc, ATH_RESET_DEFAULT); 2759 ath_beacon_free(sc); /* XXX not needed */ 2760 } 2761 2762 /* And now, restore the current power state */ 2763 ath_power_restore_power_state(sc); 2764 } 2765 2766 /* 2767 * Wait until all pending TX/RX has completed. 2768 * 2769 * This waits until all existing transmit, receive and interrupts 2770 * have completed. It's assumed that the caller has first 2771 * grabbed the reset lock so it doesn't try to do overlapping 2772 * chip resets. 2773 */ 2774 #define MAX_TXRX_ITERATIONS 100 2775 static void 2776 ath_txrx_stop_locked(struct ath_softc *sc) 2777 { 2778 int i = MAX_TXRX_ITERATIONS; 2779 2780 ATH_UNLOCK_ASSERT(sc); 2781 ATH_PCU_LOCK_ASSERT(sc); 2782 2783 /* 2784 * Sleep until all the pending operations have completed. 2785 * 2786 * The caller must ensure that reset has been incremented 2787 * or the pending operations may continue being queued. 2788 */ 2789 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt || 2790 sc->sc_txstart_cnt || sc->sc_intr_cnt) { 2791 if (i <= 0) 2792 break; 2793 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 2794 msecs_to_ticks(10)); 2795 i--; 2796 } 2797 2798 if (i <= 0) 2799 device_printf(sc->sc_dev, 2800 "%s: didn't finish after %d iterations\n", 2801 __func__, MAX_TXRX_ITERATIONS); 2802 } 2803 #undef MAX_TXRX_ITERATIONS 2804 2805 #if 0 2806 static void 2807 ath_txrx_stop(struct ath_softc *sc) 2808 { 2809 ATH_UNLOCK_ASSERT(sc); 2810 ATH_PCU_UNLOCK_ASSERT(sc); 2811 2812 ATH_PCU_LOCK(sc); 2813 ath_txrx_stop_locked(sc); 2814 ATH_PCU_UNLOCK(sc); 2815 } 2816 #endif 2817 2818 static void 2819 ath_txrx_start(struct ath_softc *sc) 2820 { 2821 2822 taskqueue_unblock(sc->sc_tq); 2823 } 2824 2825 /* 2826 * Grab the reset lock, and wait around until no one else 2827 * is trying to do anything with it. 2828 * 2829 * This is totally horrible but we can't hold this lock for 2830 * long enough to do TX/RX or we end up with net80211/ip stack 2831 * LORs and eventual deadlock. 2832 * 2833 * "dowait" signals whether to spin, waiting for the reset 2834 * lock count to reach 0. This should (for now) only be used 2835 * during the reset path, as the rest of the code may not 2836 * be locking-reentrant enough to behave correctly. 2837 * 2838 * Another, cleaner way should be found to serialise all of 2839 * these operations. 2840 */ 2841 #define MAX_RESET_ITERATIONS 25 2842 static int 2843 ath_reset_grablock(struct ath_softc *sc, int dowait) 2844 { 2845 int w = 0; 2846 int i = MAX_RESET_ITERATIONS; 2847 2848 ATH_PCU_LOCK_ASSERT(sc); 2849 do { 2850 if (sc->sc_inreset_cnt == 0) { 2851 w = 1; 2852 break; 2853 } 2854 if (dowait == 0) { 2855 w = 0; 2856 break; 2857 } 2858 ATH_PCU_UNLOCK(sc); 2859 /* 2860 * 1 tick is likely not enough time for long calibrations 2861 * to complete. So we should wait quite a while. 2862 */ 2863 pause("ath_reset_grablock", msecs_to_ticks(100)); 2864 i--; 2865 ATH_PCU_LOCK(sc); 2866 } while (i > 0); 2867 2868 /* 2869 * We always increment the refcounter, regardless 2870 * of whether we succeeded to get it in an exclusive 2871 * way. 2872 */ 2873 sc->sc_inreset_cnt++; 2874 2875 if (i <= 0) 2876 device_printf(sc->sc_dev, 2877 "%s: didn't finish after %d iterations\n", 2878 __func__, MAX_RESET_ITERATIONS); 2879 2880 if (w == 0) 2881 device_printf(sc->sc_dev, 2882 "%s: warning, recursive reset path!\n", 2883 __func__); 2884 2885 return w; 2886 } 2887 #undef MAX_RESET_ITERATIONS 2888 2889 /* 2890 * Reset the hardware w/o losing operational state. This is 2891 * basically a more efficient way of doing ath_stop, ath_init, 2892 * followed by state transitions to the current 802.11 2893 * operational state. Used to recover from various errors and 2894 * to reset or reload hardware state. 2895 */ 2896 int 2897 ath_reset(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 2898 { 2899 struct ieee80211com *ic = &sc->sc_ic; 2900 struct ath_hal *ah = sc->sc_ah; 2901 HAL_STATUS status; 2902 int i; 2903 2904 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 2905 2906 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */ 2907 ATH_PCU_UNLOCK_ASSERT(sc); 2908 ATH_UNLOCK_ASSERT(sc); 2909 2910 /* Try to (stop any further TX/RX from occurring */ 2911 taskqueue_block(sc->sc_tq); 2912 2913 /* 2914 * Wake the hardware up. 2915 */ 2916 ATH_LOCK(sc); 2917 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2918 ATH_UNLOCK(sc); 2919 2920 ATH_PCU_LOCK(sc); 2921 2922 /* 2923 * Grab the reset lock before TX/RX is stopped. 2924 * 2925 * This is needed to ensure that when the TX/RX actually does finish, 2926 * no further TX/RX/reset runs in parallel with this. 2927 */ 2928 if (ath_reset_grablock(sc, 1) == 0) { 2929 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 2930 __func__); 2931 } 2932 2933 /* disable interrupts */ 2934 ath_hal_intrset(ah, 0); 2935 2936 /* 2937 * Now, ensure that any in progress TX/RX completes before we 2938 * continue. 2939 */ 2940 ath_txrx_stop_locked(sc); 2941 2942 ATH_PCU_UNLOCK(sc); 2943 2944 /* 2945 * Regardless of whether we're doing a no-loss flush or 2946 * not, stop the PCU and handle what's in the RX queue. 2947 * That way frames aren't dropped which shouldn't be. 2948 */ 2949 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS)); 2950 ath_rx_flush(sc); 2951 2952 /* 2953 * Should now wait for pending TX/RX to complete 2954 * and block future ones from occurring. This needs to be 2955 * done before the TX queue is drained. 2956 */ 2957 ath_draintxq(sc, reset_type); /* stop xmit side */ 2958 2959 ath_settkipmic(sc); /* configure TKIP MIC handling */ 2960 /* NB: indicate channel change so we do a full reset */ 2961 ath_update_chainmasks(sc, ic->ic_curchan); 2962 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2963 sc->sc_cur_rxchainmask); 2964 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, 2965 HAL_RESET_NORMAL, &status)) 2966 device_printf(sc->sc_dev, 2967 "%s: unable to reset hardware; hal status %u\n", 2968 __func__, status); 2969 sc->sc_diversity = ath_hal_getdiversity(ah); 2970 2971 ATH_RX_LOCK(sc); 2972 sc->sc_rx_stopped = 1; 2973 sc->sc_rx_resetted = 1; 2974 ATH_RX_UNLOCK(sc); 2975 2976 /* Quiet time handling - ensure we resync */ 2977 ath_vap_clear_quiet_ie(sc); 2978 2979 /* Let DFS at it in case it's a DFS channel */ 2980 ath_dfs_radar_enable(sc, ic->ic_curchan); 2981 2982 /* Let spectral at in case spectral is enabled */ 2983 ath_spectral_enable(sc, ic->ic_curchan); 2984 2985 /* 2986 * Let bluetooth coexistence at in case it's needed for this channel 2987 */ 2988 ath_btcoex_enable(sc, ic->ic_curchan); 2989 2990 /* 2991 * If we're doing TDMA, enforce the TXOP limitation for chips that 2992 * support it. 2993 */ 2994 if (sc->sc_hasenforcetxop && sc->sc_tdma) 2995 ath_hal_setenforcetxop(sc->sc_ah, 1); 2996 else 2997 ath_hal_setenforcetxop(sc->sc_ah, 0); 2998 2999 if (ath_startrecv(sc) != 0) /* restart recv */ 3000 device_printf(sc->sc_dev, 3001 "%s: unable to start recv logic\n", __func__); 3002 /* 3003 * We may be doing a reset in response to an ioctl 3004 * that changes the channel so update any state that 3005 * might change as a result. 3006 */ 3007 ath_chan_change(sc, ic->ic_curchan); 3008 if (sc->sc_beacons) { /* restart beacons */ 3009 #ifdef IEEE80211_SUPPORT_TDMA 3010 if (sc->sc_tdma) 3011 ath_tdma_config(sc, NULL); 3012 else 3013 #endif 3014 ath_beacon_config(sc, NULL); 3015 } 3016 3017 /* 3018 * Release the reset lock and re-enable interrupts here. 3019 * If an interrupt was being processed in ath_intr(), 3020 * it would disable interrupts at this point. So we have 3021 * to atomically enable interrupts and decrement the 3022 * reset counter - this way ath_intr() doesn't end up 3023 * disabling interrupts without a corresponding enable 3024 * in the rest or channel change path. 3025 * 3026 * Grab the TX reference in case we need to transmit. 3027 * That way a parallel transmit doesn't. 3028 */ 3029 ATH_PCU_LOCK(sc); 3030 sc->sc_inreset_cnt--; 3031 sc->sc_txstart_cnt++; 3032 /* XXX only do this if sc_inreset_cnt == 0? */ 3033 ath_hal_intrset(ah, sc->sc_imask); 3034 ATH_PCU_UNLOCK(sc); 3035 3036 /* 3037 * TX and RX can be started here. If it were started with 3038 * sc_inreset_cnt > 0, the TX and RX path would abort. 3039 * Thus if this is a nested call through the reset or 3040 * channel change code, TX completion will occur but 3041 * RX completion and ath_start / ath_tx_start will not 3042 * run. 3043 */ 3044 3045 /* Restart TX/RX as needed */ 3046 ath_txrx_start(sc); 3047 3048 /* XXX TODO: we need to hold the tx refcount here! */ 3049 3050 /* Restart TX completion and pending TX */ 3051 if (reset_type == ATH_RESET_NOLOSS) { 3052 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 3053 if (ATH_TXQ_SETUP(sc, i)) { 3054 ATH_TXQ_LOCK(&sc->sc_txq[i]); 3055 ath_txq_restart_dma(sc, &sc->sc_txq[i]); 3056 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 3057 3058 ATH_TX_LOCK(sc); 3059 ath_txq_sched(sc, &sc->sc_txq[i]); 3060 ATH_TX_UNLOCK(sc); 3061 } 3062 } 3063 } 3064 3065 ATH_LOCK(sc); 3066 ath_power_restore_power_state(sc); 3067 ATH_UNLOCK(sc); 3068 3069 ATH_PCU_LOCK(sc); 3070 sc->sc_txstart_cnt--; 3071 ATH_PCU_UNLOCK(sc); 3072 3073 /* Handle any frames in the TX queue */ 3074 /* 3075 * XXX should this be done by the caller, rather than 3076 * ath_reset() ? 3077 */ 3078 ath_tx_kick(sc); /* restart xmit */ 3079 return 0; 3080 } 3081 3082 static int 3083 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 3084 { 3085 struct ieee80211com *ic = vap->iv_ic; 3086 struct ath_softc *sc = ic->ic_softc; 3087 struct ath_hal *ah = sc->sc_ah; 3088 3089 switch (cmd) { 3090 case IEEE80211_IOC_TXPOWER: 3091 /* 3092 * If per-packet TPC is enabled, then we have nothing 3093 * to do; otherwise we need to force the global limit. 3094 * All this can happen directly; no need to reset. 3095 */ 3096 if (!ath_hal_gettpc(ah)) 3097 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 3098 return 0; 3099 } 3100 /* XXX? Full or NOLOSS? */ 3101 return ath_reset(sc, ATH_RESET_FULL); 3102 } 3103 3104 struct ath_buf * 3105 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype) 3106 { 3107 struct ath_buf *bf; 3108 3109 ATH_TXBUF_LOCK_ASSERT(sc); 3110 3111 if (btype == ATH_BUFTYPE_MGMT) 3112 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt); 3113 else 3114 bf = TAILQ_FIRST(&sc->sc_txbuf); 3115 3116 if (bf == NULL) { 3117 sc->sc_stats.ast_tx_getnobuf++; 3118 } else { 3119 if (bf->bf_flags & ATH_BUF_BUSY) { 3120 sc->sc_stats.ast_tx_getbusybuf++; 3121 bf = NULL; 3122 } 3123 } 3124 3125 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) { 3126 if (btype == ATH_BUFTYPE_MGMT) 3127 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list); 3128 else { 3129 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 3130 sc->sc_txbuf_cnt--; 3131 3132 /* 3133 * This shuldn't happen; however just to be 3134 * safe print a warning and fudge the txbuf 3135 * count. 3136 */ 3137 if (sc->sc_txbuf_cnt < 0) { 3138 device_printf(sc->sc_dev, 3139 "%s: sc_txbuf_cnt < 0?\n", 3140 __func__); 3141 sc->sc_txbuf_cnt = 0; 3142 } 3143 } 3144 } else 3145 bf = NULL; 3146 3147 if (bf == NULL) { 3148 /* XXX should check which list, mgmt or otherwise */ 3149 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 3150 TAILQ_FIRST(&sc->sc_txbuf) == NULL ? 3151 "out of xmit buffers" : "xmit buffer busy"); 3152 return NULL; 3153 } 3154 3155 /* XXX TODO: should do this at buffer list initialisation */ 3156 /* XXX (then, ensure the buffer has the right flag set) */ 3157 bf->bf_flags = 0; 3158 if (btype == ATH_BUFTYPE_MGMT) 3159 bf->bf_flags |= ATH_BUF_MGMT; 3160 else 3161 bf->bf_flags &= (~ATH_BUF_MGMT); 3162 3163 /* Valid bf here; clear some basic fields */ 3164 bf->bf_next = NULL; /* XXX just to be sure */ 3165 bf->bf_last = NULL; /* XXX again, just to be sure */ 3166 bf->bf_comp = NULL; /* XXX again, just to be sure */ 3167 bzero(&bf->bf_state, sizeof(bf->bf_state)); 3168 3169 /* 3170 * Track the descriptor ID only if doing EDMA 3171 */ 3172 if (sc->sc_isedma) { 3173 bf->bf_descid = sc->sc_txbuf_descid; 3174 sc->sc_txbuf_descid++; 3175 } 3176 3177 return bf; 3178 } 3179 3180 /* 3181 * When retrying a software frame, buffers marked ATH_BUF_BUSY 3182 * can't be thrown back on the queue as they could still be 3183 * in use by the hardware. 3184 * 3185 * This duplicates the buffer, or returns NULL. 3186 * 3187 * The descriptor is also copied but the link pointers and 3188 * the DMA segments aren't copied; this frame should thus 3189 * be again passed through the descriptor setup/chain routines 3190 * so the link is correct. 3191 * 3192 * The caller must free the buffer using ath_freebuf(). 3193 */ 3194 struct ath_buf * 3195 ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf) 3196 { 3197 struct ath_buf *tbf; 3198 3199 tbf = ath_getbuf(sc, 3200 (bf->bf_flags & ATH_BUF_MGMT) ? 3201 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL); 3202 if (tbf == NULL) 3203 return NULL; /* XXX failure? Why? */ 3204 3205 /* Copy basics */ 3206 tbf->bf_next = NULL; 3207 tbf->bf_nseg = bf->bf_nseg; 3208 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE; 3209 tbf->bf_status = bf->bf_status; 3210 tbf->bf_m = bf->bf_m; 3211 tbf->bf_node = bf->bf_node; 3212 KASSERT((bf->bf_node != NULL), ("%s: bf_node=NULL!", __func__)); 3213 /* will be setup by the chain/setup function */ 3214 tbf->bf_lastds = NULL; 3215 /* for now, last == self */ 3216 tbf->bf_last = tbf; 3217 tbf->bf_comp = bf->bf_comp; 3218 3219 /* NOTE: DMA segments will be setup by the setup/chain functions */ 3220 3221 /* The caller has to re-init the descriptor + links */ 3222 3223 /* 3224 * Free the DMA mapping here, before we NULL the mbuf. 3225 * We must only call bus_dmamap_unload() once per mbuf chain 3226 * or behaviour is undefined. 3227 */ 3228 if (bf->bf_m != NULL) { 3229 /* 3230 * XXX is this POSTWRITE call required? 3231 */ 3232 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3233 BUS_DMASYNC_POSTWRITE); 3234 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3235 } 3236 3237 bf->bf_m = NULL; 3238 bf->bf_node = NULL; 3239 3240 /* Copy state */ 3241 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state)); 3242 3243 return tbf; 3244 } 3245 3246 struct ath_buf * 3247 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype) 3248 { 3249 struct ath_buf *bf; 3250 3251 ATH_TXBUF_LOCK(sc); 3252 bf = _ath_getbuf_locked(sc, btype); 3253 /* 3254 * If a mgmt buffer was requested but we're out of those, 3255 * try requesting a normal one. 3256 */ 3257 if (bf == NULL && btype == ATH_BUFTYPE_MGMT) 3258 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 3259 ATH_TXBUF_UNLOCK(sc); 3260 if (bf == NULL) { 3261 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 3262 sc->sc_stats.ast_tx_qstop++; 3263 } 3264 return bf; 3265 } 3266 3267 /* 3268 * Transmit a single frame. 3269 * 3270 * net80211 will free the node reference if the transmit 3271 * fails, so don't free the node reference here. 3272 */ 3273 static int 3274 ath_transmit(struct ieee80211com *ic, struct mbuf *m) 3275 { 3276 struct ath_softc *sc = ic->ic_softc; 3277 struct ieee80211_node *ni; 3278 struct mbuf *next; 3279 struct ath_buf *bf; 3280 ath_bufhead frags; 3281 int retval = 0; 3282 3283 /* 3284 * Tell the reset path that we're currently transmitting. 3285 */ 3286 ATH_PCU_LOCK(sc); 3287 if (sc->sc_inreset_cnt > 0) { 3288 DPRINTF(sc, ATH_DEBUG_XMIT, 3289 "%s: sc_inreset_cnt > 0; bailing\n", __func__); 3290 ATH_PCU_UNLOCK(sc); 3291 sc->sc_stats.ast_tx_qstop++; 3292 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish"); 3293 return (ENOBUFS); /* XXX should be EINVAL or? */ 3294 } 3295 sc->sc_txstart_cnt++; 3296 ATH_PCU_UNLOCK(sc); 3297 3298 /* Wake the hardware up already */ 3299 ATH_LOCK(sc); 3300 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3301 ATH_UNLOCK(sc); 3302 3303 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: start"); 3304 /* 3305 * Grab the TX lock - it's ok to do this here; we haven't 3306 * yet started transmitting. 3307 */ 3308 ATH_TX_LOCK(sc); 3309 3310 /* 3311 * Node reference, if there's one. 3312 */ 3313 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 3314 3315 /* 3316 * Enforce how deep a node queue can get. 3317 * 3318 * XXX it would be nicer if we kept an mbuf queue per 3319 * node and only whacked them into ath_bufs when we 3320 * are ready to schedule some traffic from them. 3321 * .. that may come later. 3322 * 3323 * XXX we should also track the per-node hardware queue 3324 * depth so it is easy to limit the _SUM_ of the swq and 3325 * hwq frames. Since we only schedule two HWQ frames 3326 * at a time, this should be OK for now. 3327 */ 3328 if ((!(m->m_flags & M_EAPOL)) && 3329 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) { 3330 sc->sc_stats.ast_tx_nodeq_overflow++; 3331 retval = ENOBUFS; 3332 goto finish; 3333 } 3334 3335 /* 3336 * Check how many TX buffers are available. 3337 * 3338 * If this is for non-EAPOL traffic, just leave some 3339 * space free in order for buffer cloning and raw 3340 * frame transmission to occur. 3341 * 3342 * If it's for EAPOL traffic, ignore this for now. 3343 * Management traffic will be sent via the raw transmit 3344 * method which bypasses this check. 3345 * 3346 * This is needed to ensure that EAPOL frames during 3347 * (re) keying have a chance to go out. 3348 * 3349 * See kern/138379 for more information. 3350 */ 3351 if ((!(m->m_flags & M_EAPOL)) && 3352 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) { 3353 sc->sc_stats.ast_tx_nobuf++; 3354 retval = ENOBUFS; 3355 goto finish; 3356 } 3357 3358 /* 3359 * Grab a TX buffer and associated resources. 3360 * 3361 * If it's an EAPOL frame, allocate a MGMT ath_buf. 3362 * That way even with temporary buffer exhaustion due to 3363 * the data path doesn't leave us without the ability 3364 * to transmit management frames. 3365 * 3366 * Otherwise allocate a normal buffer. 3367 */ 3368 if (m->m_flags & M_EAPOL) 3369 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT); 3370 else 3371 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL); 3372 3373 if (bf == NULL) { 3374 /* 3375 * If we failed to allocate a buffer, fail. 3376 * 3377 * We shouldn't fail normally, due to the check 3378 * above. 3379 */ 3380 sc->sc_stats.ast_tx_nobuf++; 3381 retval = ENOBUFS; 3382 goto finish; 3383 } 3384 3385 /* 3386 * At this point we have a buffer; so we need to free it 3387 * if we hit any error conditions. 3388 */ 3389 3390 /* 3391 * Check for fragmentation. If this frame 3392 * has been broken up verify we have enough 3393 * buffers to send all the fragments so all 3394 * go out or none... 3395 */ 3396 TAILQ_INIT(&frags); 3397 if ((m->m_flags & M_FRAG) && 3398 !ath_txfrag_setup(sc, &frags, m, ni)) { 3399 DPRINTF(sc, ATH_DEBUG_XMIT, 3400 "%s: out of txfrag buffers\n", __func__); 3401 sc->sc_stats.ast_tx_nofrag++; 3402 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 3403 /* 3404 * XXXGL: is mbuf valid after ath_txfrag_setup? If yes, 3405 * we shouldn't free it but return back. 3406 */ 3407 ieee80211_free_mbuf(m); 3408 m = NULL; 3409 goto bad; 3410 } 3411 3412 /* 3413 * At this point if we have any TX fragments, then we will 3414 * have bumped the node reference once for each of those. 3415 */ 3416 3417 /* 3418 * XXX Is there anything actually _enforcing_ that the 3419 * fragments are being transmitted in one hit, rather than 3420 * being interleaved with other transmissions on that 3421 * hardware queue? 3422 * 3423 * The ATH TX output lock is the only thing serialising this 3424 * right now. 3425 */ 3426 3427 /* 3428 * Calculate the "next fragment" length field in ath_buf 3429 * in order to let the transmit path know enough about 3430 * what to next write to the hardware. 3431 */ 3432 if (m->m_flags & M_FRAG) { 3433 struct ath_buf *fbf = bf; 3434 struct ath_buf *n_fbf = NULL; 3435 struct mbuf *fm = m->m_nextpkt; 3436 3437 /* 3438 * We need to walk the list of fragments and set 3439 * the next size to the following buffer. 3440 * However, the first buffer isn't in the frag 3441 * list, so we have to do some gymnastics here. 3442 */ 3443 TAILQ_FOREACH(n_fbf, &frags, bf_list) { 3444 fbf->bf_nextfraglen = fm->m_pkthdr.len; 3445 fbf = n_fbf; 3446 fm = fm->m_nextpkt; 3447 } 3448 } 3449 3450 nextfrag: 3451 /* 3452 * Pass the frame to the h/w for transmission. 3453 * Fragmented frames have each frag chained together 3454 * with m_nextpkt. We know there are sufficient ath_buf's 3455 * to send all the frags because of work done by 3456 * ath_txfrag_setup. We leave m_nextpkt set while 3457 * calling ath_tx_start so it can use it to extend the 3458 * the tx duration to cover the subsequent frag and 3459 * so it can reclaim all the mbufs in case of an error; 3460 * ath_tx_start clears m_nextpkt once it commits to 3461 * handing the frame to the hardware. 3462 * 3463 * Note: if this fails, then the mbufs are freed but 3464 * not the node reference. 3465 * 3466 * So, we now have to free the node reference ourselves here 3467 * and return OK up to the stack. 3468 */ 3469 next = m->m_nextpkt; 3470 if (ath_tx_start(sc, ni, bf, m)) { 3471 bad: 3472 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 3473 reclaim: 3474 bf->bf_m = NULL; 3475 bf->bf_node = NULL; 3476 ATH_TXBUF_LOCK(sc); 3477 ath_returnbuf_head(sc, bf); 3478 /* 3479 * Free the rest of the node references and 3480 * buffers for the fragment list. 3481 */ 3482 ath_txfrag_cleanup(sc, &frags, ni); 3483 ATH_TXBUF_UNLOCK(sc); 3484 3485 /* 3486 * XXX: And free the node/return OK; ath_tx_start() may have 3487 * modified the buffer. We currently have no way to 3488 * signify that the mbuf was freed but there was an error. 3489 */ 3490 ieee80211_free_node(ni); 3491 retval = 0; 3492 goto finish; 3493 } 3494 3495 /* 3496 * Check here if the node is in power save state. 3497 */ 3498 ath_tx_update_tim(sc, ni, 1); 3499 3500 if (next != NULL) { 3501 /* 3502 * Beware of state changing between frags. 3503 * XXX check sta power-save state? 3504 */ 3505 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 3506 DPRINTF(sc, ATH_DEBUG_XMIT, 3507 "%s: flush fragmented packet, state %s\n", 3508 __func__, 3509 ieee80211_state_name[ni->ni_vap->iv_state]); 3510 /* XXX dmamap */ 3511 ieee80211_free_mbuf(next); 3512 goto reclaim; 3513 } 3514 m = next; 3515 bf = TAILQ_FIRST(&frags); 3516 KASSERT(bf != NULL, ("no buf for txfrag")); 3517 TAILQ_REMOVE(&frags, bf, bf_list); 3518 goto nextfrag; 3519 } 3520 3521 /* 3522 * Bump watchdog timer. 3523 */ 3524 sc->sc_wd_timer = 5; 3525 3526 finish: 3527 ATH_TX_UNLOCK(sc); 3528 3529 /* 3530 * Finished transmitting! 3531 */ 3532 ATH_PCU_LOCK(sc); 3533 sc->sc_txstart_cnt--; 3534 ATH_PCU_UNLOCK(sc); 3535 3536 /* Sleep the hardware if required */ 3537 ATH_LOCK(sc); 3538 ath_power_restore_power_state(sc); 3539 ATH_UNLOCK(sc); 3540 3541 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: finished"); 3542 3543 return (retval); 3544 } 3545 3546 static int 3547 ath_media_change(struct ifnet *ifp) 3548 { 3549 int error = ieee80211_media_change(ifp); 3550 /* NB: only the fixed rate can change and that doesn't need a reset */ 3551 return (error == ENETRESET ? 0 : error); 3552 } 3553 3554 /* 3555 * Block/unblock tx+rx processing while a key change is done. 3556 * We assume the caller serializes key management operations 3557 * so we only need to worry about synchronization with other 3558 * uses that originate in the driver. 3559 */ 3560 static void 3561 ath_key_update_begin(struct ieee80211vap *vap) 3562 { 3563 struct ath_softc *sc = vap->iv_ic->ic_softc; 3564 3565 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 3566 taskqueue_block(sc->sc_tq); 3567 } 3568 3569 static void 3570 ath_key_update_end(struct ieee80211vap *vap) 3571 { 3572 struct ath_softc *sc = vap->iv_ic->ic_softc; 3573 3574 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 3575 taskqueue_unblock(sc->sc_tq); 3576 } 3577 3578 static void 3579 ath_update_promisc(struct ieee80211com *ic) 3580 { 3581 struct ath_softc *sc = ic->ic_softc; 3582 u_int32_t rfilt; 3583 3584 /* configure rx filter */ 3585 ATH_LOCK(sc); 3586 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3587 rfilt = ath_calcrxfilter(sc); 3588 ath_hal_setrxfilter(sc->sc_ah, rfilt); 3589 ath_power_restore_power_state(sc); 3590 ATH_UNLOCK(sc); 3591 3592 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 3593 } 3594 3595 static u_int 3596 ath_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3597 { 3598 uint32_t val, *mfilt = arg; 3599 char *dl; 3600 uint8_t pos; 3601 3602 /* calculate XOR of eight 6bit values */ 3603 dl = LLADDR(sdl); 3604 val = le32dec(dl + 0); 3605 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 3606 val = le32dec(dl + 3); 3607 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 3608 pos &= 0x3f; 3609 mfilt[pos / 32] |= (1 << (pos % 32)); 3610 3611 return (1); 3612 } 3613 3614 /* 3615 * Driver-internal mcast update call. 3616 * 3617 * Assumes the hardware is already awake. 3618 */ 3619 static void 3620 ath_update_mcast_hw(struct ath_softc *sc) 3621 { 3622 struct ieee80211com *ic = &sc->sc_ic; 3623 u_int32_t mfilt[2]; 3624 3625 /* calculate and install multicast filter */ 3626 if (ic->ic_allmulti == 0) { 3627 struct ieee80211vap *vap; 3628 3629 /* 3630 * Merge multicast addresses to form the hardware filter. 3631 */ 3632 mfilt[0] = mfilt[1] = 0; 3633 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) 3634 if_foreach_llmaddr(vap->iv_ifp, ath_hash_maddr, &mfilt); 3635 } else 3636 mfilt[0] = mfilt[1] = ~0; 3637 3638 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 3639 3640 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 3641 __func__, mfilt[0], mfilt[1]); 3642 } 3643 3644 /* 3645 * Called from the net80211 layer - force the hardware 3646 * awake before operating. 3647 */ 3648 static void 3649 ath_update_mcast(struct ieee80211com *ic) 3650 { 3651 struct ath_softc *sc = ic->ic_softc; 3652 3653 ATH_LOCK(sc); 3654 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3655 ATH_UNLOCK(sc); 3656 3657 ath_update_mcast_hw(sc); 3658 3659 ATH_LOCK(sc); 3660 ath_power_restore_power_state(sc); 3661 ATH_UNLOCK(sc); 3662 } 3663 3664 void 3665 ath_mode_init(struct ath_softc *sc) 3666 { 3667 struct ieee80211com *ic = &sc->sc_ic; 3668 struct ath_hal *ah = sc->sc_ah; 3669 u_int32_t rfilt; 3670 3671 /* XXX power state? */ 3672 3673 /* configure rx filter */ 3674 rfilt = ath_calcrxfilter(sc); 3675 ath_hal_setrxfilter(ah, rfilt); 3676 3677 /* configure operational mode */ 3678 ath_hal_setopmode(ah); 3679 3680 /* handle any link-level address change */ 3681 ath_hal_setmac(ah, ic->ic_macaddr); 3682 3683 /* calculate and install multicast filter */ 3684 ath_update_mcast_hw(sc); 3685 } 3686 3687 /* 3688 * Set the slot time based on the current setting. 3689 */ 3690 void 3691 ath_setslottime(struct ath_softc *sc) 3692 { 3693 struct ieee80211com *ic = &sc->sc_ic; 3694 struct ath_hal *ah = sc->sc_ah; 3695 u_int usec; 3696 3697 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 3698 usec = 13; 3699 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 3700 usec = 21; 3701 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 3702 /* honor short/long slot time only in 11g */ 3703 /* XXX shouldn't honor on pure g or turbo g channel */ 3704 if (ic->ic_flags & IEEE80211_F_SHSLOT) 3705 usec = HAL_SLOT_TIME_9; 3706 else 3707 usec = HAL_SLOT_TIME_20; 3708 } else 3709 usec = HAL_SLOT_TIME_9; 3710 3711 DPRINTF(sc, ATH_DEBUG_RESET, 3712 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 3713 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 3714 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 3715 3716 /* Wake up the hardware first before updating the slot time */ 3717 ATH_LOCK(sc); 3718 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3719 ath_hal_setslottime(ah, usec); 3720 ath_power_restore_power_state(sc); 3721 sc->sc_updateslot = OK; 3722 ATH_UNLOCK(sc); 3723 } 3724 3725 /* 3726 * Callback from the 802.11 layer to update the 3727 * slot time based on the current setting. 3728 */ 3729 static void 3730 ath_updateslot(struct ieee80211com *ic) 3731 { 3732 struct ath_softc *sc = ic->ic_softc; 3733 3734 /* 3735 * When not coordinating the BSS, change the hardware 3736 * immediately. For other operation we defer the change 3737 * until beacon updates have propagated to the stations. 3738 * 3739 * XXX sc_updateslot isn't changed behind a lock? 3740 */ 3741 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3742 ic->ic_opmode == IEEE80211_M_MBSS) 3743 sc->sc_updateslot = UPDATE; 3744 else 3745 ath_setslottime(sc); 3746 } 3747 3748 /* 3749 * Append the contents of src to dst; both queues 3750 * are assumed to be locked. 3751 */ 3752 void 3753 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 3754 { 3755 3756 ATH_TXQ_LOCK_ASSERT(src); 3757 ATH_TXQ_LOCK_ASSERT(dst); 3758 3759 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list); 3760 dst->axq_link = src->axq_link; 3761 src->axq_link = NULL; 3762 dst->axq_depth += src->axq_depth; 3763 dst->axq_aggr_depth += src->axq_aggr_depth; 3764 src->axq_depth = 0; 3765 src->axq_aggr_depth = 0; 3766 } 3767 3768 /* 3769 * Reset the hardware, with no loss. 3770 * 3771 * This can't be used for a general case reset. 3772 */ 3773 static void 3774 ath_reset_proc(void *arg, int pending) 3775 { 3776 struct ath_softc *sc = arg; 3777 3778 #if 0 3779 device_printf(sc->sc_dev, "%s: resetting\n", __func__); 3780 #endif 3781 ath_reset(sc, ATH_RESET_NOLOSS); 3782 } 3783 3784 /* 3785 * Reset the hardware after detecting beacons have stopped. 3786 */ 3787 static void 3788 ath_bstuck_proc(void *arg, int pending) 3789 { 3790 struct ath_softc *sc = arg; 3791 uint32_t hangs = 0; 3792 3793 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) 3794 device_printf(sc->sc_dev, "bb hang detected (0x%x)\n", hangs); 3795 3796 #ifdef ATH_DEBUG_ALQ 3797 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON)) 3798 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL); 3799 #endif 3800 3801 device_printf(sc->sc_dev, "stuck beacon; resetting (bmiss count %u)\n", 3802 sc->sc_bmisscount); 3803 sc->sc_stats.ast_bstuck++; 3804 /* 3805 * This assumes that there's no simultaneous channel mode change 3806 * occurring. 3807 */ 3808 ath_reset(sc, ATH_RESET_NOLOSS); 3809 } 3810 3811 static int 3812 ath_desc_alloc(struct ath_softc *sc) 3813 { 3814 int error; 3815 3816 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3817 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER); 3818 if (error != 0) { 3819 return error; 3820 } 3821 sc->sc_txbuf_cnt = ath_txbuf; 3822 3823 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt, 3824 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt, 3825 ATH_TXDESC); 3826 if (error != 0) { 3827 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3828 return error; 3829 } 3830 3831 /* 3832 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the 3833 * flag doesn't have to be set in ath_getbuf_locked(). 3834 */ 3835 3836 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3837 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1); 3838 if (error != 0) { 3839 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3840 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3841 &sc->sc_txbuf_mgmt); 3842 return error; 3843 } 3844 return 0; 3845 } 3846 3847 static void 3848 ath_desc_free(struct ath_softc *sc) 3849 { 3850 3851 if (sc->sc_bdma.dd_desc_len != 0) 3852 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3853 if (sc->sc_txdma.dd_desc_len != 0) 3854 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3855 if (sc->sc_txdma_mgmt.dd_desc_len != 0) 3856 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3857 &sc->sc_txbuf_mgmt); 3858 } 3859 3860 static struct ieee80211_node * 3861 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3862 { 3863 struct ieee80211com *ic = vap->iv_ic; 3864 struct ath_softc *sc = ic->ic_softc; 3865 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3866 struct ath_node *an; 3867 3868 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3869 if (an == NULL) { 3870 /* XXX stat+msg */ 3871 return NULL; 3872 } 3873 ath_rate_node_init(sc, an); 3874 3875 /* Setup the mutex - there's no associd yet so set the name to NULL */ 3876 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p", 3877 device_get_nameunit(sc->sc_dev), an); 3878 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF); 3879 3880 /* XXX setup ath_tid */ 3881 ath_tx_tid_init(sc, an); 3882 3883 an->an_node_stats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 3884 an->an_node_stats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 3885 an->an_node_stats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 3886 3887 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an); 3888 return &an->an_node; 3889 } 3890 3891 static void 3892 ath_node_cleanup(struct ieee80211_node *ni) 3893 { 3894 struct ieee80211com *ic = ni->ni_ic; 3895 struct ath_softc *sc = ic->ic_softc; 3896 3897 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, 3898 ni->ni_macaddr, ":", ATH_NODE(ni)); 3899 3900 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */ 3901 ath_tx_node_flush(sc, ATH_NODE(ni)); 3902 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3903 sc->sc_node_cleanup(ni); 3904 } 3905 3906 static void 3907 ath_node_free(struct ieee80211_node *ni) 3908 { 3909 struct ieee80211com *ic = ni->ni_ic; 3910 struct ath_softc *sc = ic->ic_softc; 3911 3912 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, 3913 ni->ni_macaddr, ":", ATH_NODE(ni)); 3914 mtx_destroy(&ATH_NODE(ni)->an_mtx); 3915 sc->sc_node_free(ni); 3916 } 3917 3918 static void 3919 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3920 { 3921 struct ieee80211com *ic = ni->ni_ic; 3922 struct ath_softc *sc = ic->ic_softc; 3923 struct ath_hal *ah = sc->sc_ah; 3924 3925 *rssi = ic->ic_node_getrssi(ni); 3926 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3927 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3928 else 3929 *noise = -95; /* nominally correct */ 3930 } 3931 3932 /* 3933 * Set the default antenna. 3934 */ 3935 void 3936 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3937 { 3938 struct ath_hal *ah = sc->sc_ah; 3939 3940 /* XXX block beacon interrupts */ 3941 ath_hal_setdefantenna(ah, antenna); 3942 if (sc->sc_defant != antenna) 3943 sc->sc_stats.ast_ant_defswitch++; 3944 sc->sc_defant = antenna; 3945 sc->sc_rxotherant = 0; 3946 } 3947 3948 static void 3949 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 3950 { 3951 txq->axq_qnum = qnum; 3952 txq->axq_ac = 0; 3953 txq->axq_depth = 0; 3954 txq->axq_aggr_depth = 0; 3955 txq->axq_intrcnt = 0; 3956 txq->axq_link = NULL; 3957 txq->axq_softc = sc; 3958 TAILQ_INIT(&txq->axq_q); 3959 TAILQ_INIT(&txq->axq_tidq); 3960 TAILQ_INIT(&txq->fifo.axq_q); 3961 ATH_TXQ_LOCK_INIT(sc, txq); 3962 } 3963 3964 /* 3965 * Setup a h/w transmit queue. 3966 */ 3967 static struct ath_txq * 3968 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3969 { 3970 struct ath_hal *ah = sc->sc_ah; 3971 HAL_TXQ_INFO qi; 3972 int qnum; 3973 3974 memset(&qi, 0, sizeof(qi)); 3975 qi.tqi_subtype = subtype; 3976 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3977 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3978 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3979 /* 3980 * Enable interrupts only for EOL and DESC conditions. 3981 * We mark tx descriptors to receive a DESC interrupt 3982 * when a tx queue gets deep; otherwise waiting for the 3983 * EOL to reap descriptors. Note that this is done to 3984 * reduce interrupt load and this only defers reaping 3985 * descriptors, never transmitting frames. Aside from 3986 * reducing interrupts this also permits more concurrency. 3987 * The only potential downside is if the tx queue backs 3988 * up in which case the top half of the kernel may backup 3989 * due to a lack of tx descriptors. 3990 */ 3991 if (sc->sc_isedma) 3992 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | 3993 HAL_TXQ_TXOKINT_ENABLE; 3994 else 3995 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | 3996 HAL_TXQ_TXDESCINT_ENABLE; 3997 3998 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3999 if (qnum == -1) { 4000 /* 4001 * NB: don't print a message, this happens 4002 * normally on parts with too few tx queues 4003 */ 4004 return NULL; 4005 } 4006 if (qnum >= nitems(sc->sc_txq)) { 4007 device_printf(sc->sc_dev, 4008 "hal qnum %u out of range, max %zu!\n", 4009 qnum, nitems(sc->sc_txq)); 4010 ath_hal_releasetxqueue(ah, qnum); 4011 return NULL; 4012 } 4013 if (!ATH_TXQ_SETUP(sc, qnum)) { 4014 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4015 sc->sc_txqsetup |= 1<<qnum; 4016 } 4017 return &sc->sc_txq[qnum]; 4018 } 4019 4020 /* 4021 * Setup a hardware data transmit queue for the specified 4022 * access control. The hal may not support all requested 4023 * queues in which case it will return a reference to a 4024 * previously setup queue. We record the mapping from ac's 4025 * to h/w queues for use by ath_tx_start and also track 4026 * the set of h/w queues being used to optimize work in the 4027 * transmit interrupt handler and related routines. 4028 */ 4029 static int 4030 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4031 { 4032 struct ath_txq *txq; 4033 4034 if (ac >= nitems(sc->sc_ac2q)) { 4035 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4036 ac, nitems(sc->sc_ac2q)); 4037 return 0; 4038 } 4039 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4040 if (txq != NULL) { 4041 txq->axq_ac = ac; 4042 sc->sc_ac2q[ac] = txq; 4043 return 1; 4044 } else 4045 return 0; 4046 } 4047 4048 /* 4049 * Update WME parameters for a transmit queue. 4050 */ 4051 static int 4052 ath_txq_update(struct ath_softc *sc, int ac) 4053 { 4054 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4055 struct ieee80211com *ic = &sc->sc_ic; 4056 struct ath_txq *txq = sc->sc_ac2q[ac]; 4057 struct chanAccParams chp; 4058 struct wmeParams *wmep; 4059 struct ath_hal *ah = sc->sc_ah; 4060 HAL_TXQ_INFO qi; 4061 4062 ieee80211_wme_ic_getparams(ic, &chp); 4063 wmep = &chp.cap_wmeParams[ac]; 4064 4065 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4066 #ifdef IEEE80211_SUPPORT_TDMA 4067 if (sc->sc_tdma) { 4068 /* 4069 * AIFS is zero so there's no pre-transmit wait. The 4070 * burst time defines the slot duration and is configured 4071 * through net80211. The QCU is setup to not do post-xmit 4072 * back off, lockout all lower-priority QCU's, and fire 4073 * off the DMA beacon alert timer which is setup based 4074 * on the slot configuration. 4075 */ 4076 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4077 | HAL_TXQ_TXERRINT_ENABLE 4078 | HAL_TXQ_TXURNINT_ENABLE 4079 | HAL_TXQ_TXEOLINT_ENABLE 4080 | HAL_TXQ_DBA_GATED 4081 | HAL_TXQ_BACKOFF_DISABLE 4082 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4083 ; 4084 qi.tqi_aifs = 0; 4085 /* XXX +dbaprep? */ 4086 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4087 qi.tqi_burstTime = qi.tqi_readyTime; 4088 } else { 4089 #endif 4090 /* 4091 * XXX shouldn't this just use the default flags 4092 * used in the previous queue setup? 4093 */ 4094 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4095 | HAL_TXQ_TXERRINT_ENABLE 4096 | HAL_TXQ_TXDESCINT_ENABLE 4097 | HAL_TXQ_TXURNINT_ENABLE 4098 | HAL_TXQ_TXEOLINT_ENABLE 4099 ; 4100 qi.tqi_aifs = wmep->wmep_aifsn; 4101 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4102 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4103 qi.tqi_readyTime = 0; 4104 qi.tqi_burstTime = IEEE80211_TXOP_TO_US(wmep->wmep_txopLimit); 4105 #ifdef IEEE80211_SUPPORT_TDMA 4106 } 4107 #endif 4108 4109 DPRINTF(sc, ATH_DEBUG_RESET, 4110 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4111 __func__, txq->axq_qnum, qi.tqi_qflags, 4112 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4113 4114 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4115 device_printf(sc->sc_dev, "unable to update hardware queue " 4116 "parameters for %s traffic!\n", ieee80211_wme_acnames[ac]); 4117 return 0; 4118 } else { 4119 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4120 return 1; 4121 } 4122 #undef ATH_EXPONENT_TO_VALUE 4123 } 4124 4125 /* 4126 * Callback from the 802.11 layer to update WME parameters. 4127 */ 4128 int 4129 ath_wme_update(struct ieee80211com *ic) 4130 { 4131 struct ath_softc *sc = ic->ic_softc; 4132 4133 return !ath_txq_update(sc, WME_AC_BE) || 4134 !ath_txq_update(sc, WME_AC_BK) || 4135 !ath_txq_update(sc, WME_AC_VI) || 4136 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4137 } 4138 4139 /* 4140 * Reclaim resources for a setup queue. 4141 */ 4142 static void 4143 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4144 { 4145 4146 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4147 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4148 ATH_TXQ_LOCK_DESTROY(txq); 4149 } 4150 4151 /* 4152 * Reclaim all tx queue resources. 4153 */ 4154 static void 4155 ath_tx_cleanup(struct ath_softc *sc) 4156 { 4157 int i; 4158 4159 ATH_TXBUF_LOCK_DESTROY(sc); 4160 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4161 if (ATH_TXQ_SETUP(sc, i)) 4162 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4163 } 4164 4165 /* 4166 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 4167 * using the current rates in sc_rixmap. 4168 */ 4169 int 4170 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 4171 { 4172 int rix = sc->sc_rixmap[rate]; 4173 /* NB: return lowest rix for invalid rate */ 4174 return (rix == 0xff ? 0 : rix); 4175 } 4176 4177 static void 4178 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts, 4179 struct ath_buf *bf) 4180 { 4181 struct ieee80211_node *ni = bf->bf_node; 4182 struct ieee80211com *ic = &sc->sc_ic; 4183 int sr, lr, pri; 4184 4185 if (ts->ts_status == 0) { 4186 u_int8_t txant = ts->ts_antenna; 4187 sc->sc_stats.ast_ant_tx[txant]++; 4188 sc->sc_ant_tx[txant]++; 4189 if (ts->ts_finaltsi != 0) 4190 sc->sc_stats.ast_tx_altrate++; 4191 4192 /* XXX TODO: should do per-pri conuters */ 4193 pri = M_WME_GETAC(bf->bf_m); 4194 if (pri >= WME_AC_VO) 4195 ic->ic_wme.wme_hipri_traffic++; 4196 4197 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) 4198 ni->ni_inact = ni->ni_inact_reload; 4199 } else { 4200 if (ts->ts_status & HAL_TXERR_XRETRY) 4201 sc->sc_stats.ast_tx_xretries++; 4202 if (ts->ts_status & HAL_TXERR_FIFO) 4203 sc->sc_stats.ast_tx_fifoerr++; 4204 if (ts->ts_status & HAL_TXERR_FILT) 4205 sc->sc_stats.ast_tx_filtered++; 4206 if (ts->ts_status & HAL_TXERR_XTXOP) 4207 sc->sc_stats.ast_tx_xtxop++; 4208 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED) 4209 sc->sc_stats.ast_tx_timerexpired++; 4210 4211 if (bf->bf_m->m_flags & M_FF) 4212 sc->sc_stats.ast_ff_txerr++; 4213 } 4214 /* XXX when is this valid? */ 4215 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR) 4216 sc->sc_stats.ast_tx_desccfgerr++; 4217 /* 4218 * This can be valid for successful frame transmission! 4219 * If there's a TX FIFO underrun during aggregate transmission, 4220 * the MAC will pad the rest of the aggregate with delimiters. 4221 * If a BA is returned, the frame is marked as "OK" and it's up 4222 * to the TX completion code to notice which frames weren't 4223 * successfully transmitted. 4224 */ 4225 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN) 4226 sc->sc_stats.ast_tx_data_underrun++; 4227 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN) 4228 sc->sc_stats.ast_tx_delim_underrun++; 4229 4230 sr = ts->ts_shortretry; 4231 lr = ts->ts_longretry; 4232 sc->sc_stats.ast_tx_shortretry += sr; 4233 sc->sc_stats.ast_tx_longretry += lr; 4234 4235 } 4236 4237 /* 4238 * The default completion. If fail is 1, this means 4239 * "please don't retry the frame, and just return -1 status 4240 * to the net80211 stack. 4241 */ 4242 void 4243 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 4244 { 4245 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 4246 int st; 4247 4248 if (fail == 1) 4249 st = -1; 4250 else 4251 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ? 4252 ts->ts_status : HAL_TXERR_XRETRY; 4253 4254 #if 0 4255 if (bf->bf_state.bfs_dobaw) 4256 device_printf(sc->sc_dev, 4257 "%s: bf %p: seqno %d: dobaw should've been cleared!\n", 4258 __func__, 4259 bf, 4260 SEQNO(bf->bf_state.bfs_seqno)); 4261 #endif 4262 if (bf->bf_next != NULL) 4263 device_printf(sc->sc_dev, 4264 "%s: bf %p: seqno %d: bf_next not NULL!\n", 4265 __func__, 4266 bf, 4267 SEQNO(bf->bf_state.bfs_seqno)); 4268 4269 /* 4270 * Check if the node software queue is empty; if so 4271 * then clear the TIM. 4272 * 4273 * This needs to be done before the buffer is freed as 4274 * otherwise the node reference will have been released 4275 * and the node may not actually exist any longer. 4276 * 4277 * XXX I don't like this belonging here, but it's cleaner 4278 * to do it here right now then all the other places 4279 * where ath_tx_default_comp() is called. 4280 * 4281 * XXX TODO: during drain, ensure that the callback is 4282 * being called so we get a chance to update the TIM. 4283 */ 4284 if (bf->bf_node) { 4285 ATH_TX_LOCK(sc); 4286 ath_tx_update_tim(sc, bf->bf_node, 0); 4287 ATH_TX_UNLOCK(sc); 4288 } 4289 4290 /* 4291 * Do any tx complete callback. Note this must 4292 * be done before releasing the node reference. 4293 * This will free the mbuf, release the net80211 4294 * node and recycle the ath_buf. 4295 */ 4296 ath_tx_freebuf(sc, bf, st); 4297 } 4298 4299 /* 4300 * Update rate control with the given completion status. 4301 */ 4302 void 4303 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 4304 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen, 4305 int rc_framelen, int nframes, int nbad) 4306 { 4307 struct ath_node *an; 4308 4309 /* Only for unicast frames */ 4310 if (ni == NULL) 4311 return; 4312 4313 an = ATH_NODE(ni); 4314 ATH_NODE_UNLOCK_ASSERT(an); 4315 4316 /* 4317 * XXX TODO: teach the rate control about TXERR_FILT and 4318 * see about handling it (eg see how many attempts were 4319 * made before it got filtered and account for that.) 4320 */ 4321 4322 if ((ts->ts_status & HAL_TXERR_FILT) == 0) { 4323 ATH_NODE_LOCK(an); 4324 ath_rate_tx_complete(sc, an, rc, ts, frmlen, rc_framelen, 4325 nframes, nbad); 4326 ATH_NODE_UNLOCK(an); 4327 } 4328 } 4329 4330 /* 4331 * Process the completion of the given buffer. 4332 * 4333 * This calls the rate control update and then the buffer completion. 4334 * This will either free the buffer or requeue it. In any case, the 4335 * bf pointer should be treated as invalid after this function is called. 4336 */ 4337 void 4338 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq, 4339 struct ath_tx_status *ts, struct ath_buf *bf) 4340 { 4341 struct ieee80211_node *ni = bf->bf_node; 4342 4343 ATH_TX_UNLOCK_ASSERT(sc); 4344 ATH_TXQ_UNLOCK_ASSERT(txq); 4345 4346 /* If unicast frame, update general statistics */ 4347 if (ni != NULL) { 4348 /* update statistics */ 4349 ath_tx_update_stats(sc, ts, bf); 4350 } 4351 4352 /* 4353 * Call the completion handler. 4354 * The completion handler is responsible for 4355 * calling the rate control code. 4356 * 4357 * Frames with no completion handler get the 4358 * rate control code called here. 4359 */ 4360 if (bf->bf_comp == NULL) { 4361 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4362 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) { 4363 /* 4364 * XXX assume this isn't an aggregate 4365 * frame. 4366 * 4367 * XXX TODO: also do this for filtered frames? 4368 * Once rate control knows about them? 4369 */ 4370 ath_tx_update_ratectrl(sc, ni, 4371 bf->bf_state.bfs_rc, ts, 4372 bf->bf_state.bfs_pktlen, 4373 bf->bf_state.bfs_pktlen, 4374 1, 4375 (ts->ts_status == 0 ? 0 : 1)); 4376 } 4377 ath_tx_default_comp(sc, bf, 0); 4378 } else 4379 bf->bf_comp(sc, bf, 0); 4380 } 4381 4382 4383 4384 /* 4385 * Process completed xmit descriptors from the specified queue. 4386 * Kick the packet scheduler if needed. This can occur from this 4387 * particular task. 4388 */ 4389 static int 4390 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched) 4391 { 4392 struct ath_hal *ah = sc->sc_ah; 4393 struct ath_buf *bf; 4394 struct ath_desc *ds; 4395 struct ath_tx_status *ts; 4396 struct ieee80211_node *ni; 4397 #ifdef IEEE80211_SUPPORT_SUPERG 4398 struct ieee80211com *ic = &sc->sc_ic; 4399 #endif /* IEEE80211_SUPPORT_SUPERG */ 4400 int nacked; 4401 HAL_STATUS status; 4402 4403 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4404 __func__, txq->axq_qnum, 4405 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4406 txq->axq_link); 4407 4408 ATH_KTR(sc, ATH_KTR_TXCOMP, 4, 4409 "ath_tx_processq: txq=%u head %p link %p depth %p", 4410 txq->axq_qnum, 4411 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4412 txq->axq_link, 4413 txq->axq_depth); 4414 4415 nacked = 0; 4416 for (;;) { 4417 ATH_TXQ_LOCK(txq); 4418 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4419 bf = TAILQ_FIRST(&txq->axq_q); 4420 if (bf == NULL) { 4421 ATH_TXQ_UNLOCK(txq); 4422 break; 4423 } 4424 ds = bf->bf_lastds; /* XXX must be setup correctly! */ 4425 ts = &bf->bf_status.ds_txstat; 4426 4427 status = ath_hal_txprocdesc(ah, ds, ts); 4428 #ifdef ATH_DEBUG 4429 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4430 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4431 status == HAL_OK); 4432 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0)) 4433 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4434 status == HAL_OK); 4435 #endif 4436 #ifdef ATH_DEBUG_ALQ 4437 if (if_ath_alq_checkdebug(&sc->sc_alq, 4438 ATH_ALQ_EDMA_TXSTATUS)) { 4439 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS, 4440 sc->sc_tx_statuslen, 4441 (char *) ds); 4442 } 4443 #endif 4444 4445 if (status == HAL_EINPROGRESS) { 4446 ATH_KTR(sc, ATH_KTR_TXCOMP, 3, 4447 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS", 4448 txq->axq_qnum, bf, ds); 4449 ATH_TXQ_UNLOCK(txq); 4450 break; 4451 } 4452 ATH_TXQ_REMOVE(txq, bf, bf_list); 4453 4454 /* 4455 * Sanity check. 4456 */ 4457 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) { 4458 device_printf(sc->sc_dev, 4459 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n", 4460 __func__, 4461 txq->axq_qnum, 4462 bf, 4463 bf->bf_state.bfs_tx_queue); 4464 } 4465 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) { 4466 device_printf(sc->sc_dev, 4467 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n", 4468 __func__, 4469 txq->axq_qnum, 4470 bf->bf_last, 4471 bf->bf_last->bf_state.bfs_tx_queue); 4472 } 4473 4474 #if 0 4475 if (txq->axq_depth > 0) { 4476 /* 4477 * More frames follow. Mark the buffer busy 4478 * so it's not re-used while the hardware may 4479 * still re-read the link field in the descriptor. 4480 * 4481 * Use the last buffer in an aggregate as that 4482 * is where the hardware may be - intermediate 4483 * descriptors won't be "busy". 4484 */ 4485 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 4486 } else 4487 txq->axq_link = NULL; 4488 #else 4489 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 4490 #endif 4491 if (bf->bf_state.bfs_aggr) 4492 txq->axq_aggr_depth--; 4493 4494 ni = bf->bf_node; 4495 4496 ATH_KTR(sc, ATH_KTR_TXCOMP, 5, 4497 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x", 4498 txq->axq_qnum, bf, ds, ni, ts->ts_status); 4499 /* 4500 * If unicast frame was ack'd update RSSI, 4501 * including the last rx time used to 4502 * workaround phantom bmiss interrupts. 4503 */ 4504 if (ni != NULL && ts->ts_status == 0 && 4505 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 4506 nacked++; 4507 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4508 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4509 ts->ts_rssi); 4510 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgtxrssi, 4511 ts->ts_rssi); 4512 } 4513 ATH_TXQ_UNLOCK(txq); 4514 4515 /* 4516 * Update statistics and call completion 4517 */ 4518 ath_tx_process_buf_completion(sc, txq, ts, bf); 4519 4520 /* XXX at this point, bf and ni may be totally invalid */ 4521 } 4522 #ifdef IEEE80211_SUPPORT_SUPERG 4523 /* 4524 * Flush fast-frame staging queue when traffic slows. 4525 */ 4526 if (txq->axq_depth <= 1) 4527 ieee80211_ff_flush(ic, txq->axq_ac); 4528 #endif 4529 4530 /* Kick the software TXQ scheduler */ 4531 if (dosched) { 4532 ATH_TX_LOCK(sc); 4533 ath_txq_sched(sc, txq); 4534 ATH_TX_UNLOCK(sc); 4535 } 4536 4537 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4538 "ath_tx_processq: txq=%u: done", 4539 txq->axq_qnum); 4540 4541 return nacked; 4542 } 4543 4544 #define TXQACTIVE(t, q) ( (t) & (1 << (q))) 4545 4546 /* 4547 * Deferred processing of transmit interrupt; special-cased 4548 * for a single hardware transmit queue (e.g. 5210 and 5211). 4549 */ 4550 static void 4551 ath_tx_proc_q0(void *arg, int npending) 4552 { 4553 struct ath_softc *sc = arg; 4554 uint32_t txqs; 4555 4556 ATH_PCU_LOCK(sc); 4557 sc->sc_txproc_cnt++; 4558 txqs = sc->sc_txq_active; 4559 sc->sc_txq_active &= ~txqs; 4560 ATH_PCU_UNLOCK(sc); 4561 4562 ATH_LOCK(sc); 4563 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4564 ATH_UNLOCK(sc); 4565 4566 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4567 "ath_tx_proc_q0: txqs=0x%08x", txqs); 4568 4569 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1)) 4570 /* XXX why is lastrx updated in tx code? */ 4571 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4572 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4573 ath_tx_processq(sc, sc->sc_cabq, 1); 4574 sc->sc_wd_timer = 0; 4575 4576 if (sc->sc_softled) 4577 ath_led_event(sc, sc->sc_txrix); 4578 4579 ATH_PCU_LOCK(sc); 4580 sc->sc_txproc_cnt--; 4581 ATH_PCU_UNLOCK(sc); 4582 4583 ATH_LOCK(sc); 4584 ath_power_restore_power_state(sc); 4585 ATH_UNLOCK(sc); 4586 4587 ath_tx_kick(sc); 4588 } 4589 4590 /* 4591 * Deferred processing of transmit interrupt; special-cased 4592 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4593 */ 4594 static void 4595 ath_tx_proc_q0123(void *arg, int npending) 4596 { 4597 struct ath_softc *sc = arg; 4598 int nacked; 4599 uint32_t txqs; 4600 4601 ATH_PCU_LOCK(sc); 4602 sc->sc_txproc_cnt++; 4603 txqs = sc->sc_txq_active; 4604 sc->sc_txq_active &= ~txqs; 4605 ATH_PCU_UNLOCK(sc); 4606 4607 ATH_LOCK(sc); 4608 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4609 ATH_UNLOCK(sc); 4610 4611 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4612 "ath_tx_proc_q0123: txqs=0x%08x", txqs); 4613 4614 /* 4615 * Process each active queue. 4616 */ 4617 nacked = 0; 4618 if (TXQACTIVE(txqs, 0)) 4619 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1); 4620 if (TXQACTIVE(txqs, 1)) 4621 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1); 4622 if (TXQACTIVE(txqs, 2)) 4623 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1); 4624 if (TXQACTIVE(txqs, 3)) 4625 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1); 4626 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4627 ath_tx_processq(sc, sc->sc_cabq, 1); 4628 if (nacked) 4629 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4630 4631 sc->sc_wd_timer = 0; 4632 4633 if (sc->sc_softled) 4634 ath_led_event(sc, sc->sc_txrix); 4635 4636 ATH_PCU_LOCK(sc); 4637 sc->sc_txproc_cnt--; 4638 ATH_PCU_UNLOCK(sc); 4639 4640 ATH_LOCK(sc); 4641 ath_power_restore_power_state(sc); 4642 ATH_UNLOCK(sc); 4643 4644 ath_tx_kick(sc); 4645 } 4646 4647 /* 4648 * Deferred processing of transmit interrupt. 4649 */ 4650 static void 4651 ath_tx_proc(void *arg, int npending) 4652 { 4653 struct ath_softc *sc = arg; 4654 int i, nacked; 4655 uint32_t txqs; 4656 4657 ATH_PCU_LOCK(sc); 4658 sc->sc_txproc_cnt++; 4659 txqs = sc->sc_txq_active; 4660 sc->sc_txq_active &= ~txqs; 4661 ATH_PCU_UNLOCK(sc); 4662 4663 ATH_LOCK(sc); 4664 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4665 ATH_UNLOCK(sc); 4666 4667 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs); 4668 4669 /* 4670 * Process each active queue. 4671 */ 4672 nacked = 0; 4673 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4674 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i)) 4675 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1); 4676 if (nacked) 4677 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4678 4679 sc->sc_wd_timer = 0; 4680 4681 if (sc->sc_softled) 4682 ath_led_event(sc, sc->sc_txrix); 4683 4684 ATH_PCU_LOCK(sc); 4685 sc->sc_txproc_cnt--; 4686 ATH_PCU_UNLOCK(sc); 4687 4688 ATH_LOCK(sc); 4689 ath_power_restore_power_state(sc); 4690 ATH_UNLOCK(sc); 4691 4692 ath_tx_kick(sc); 4693 } 4694 #undef TXQACTIVE 4695 4696 /* 4697 * Deferred processing of TXQ rescheduling. 4698 */ 4699 static void 4700 ath_txq_sched_tasklet(void *arg, int npending) 4701 { 4702 struct ath_softc *sc = arg; 4703 int i; 4704 4705 /* XXX is skipping ok? */ 4706 ATH_PCU_LOCK(sc); 4707 #if 0 4708 if (sc->sc_inreset_cnt > 0) { 4709 device_printf(sc->sc_dev, 4710 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 4711 ATH_PCU_UNLOCK(sc); 4712 return; 4713 } 4714 #endif 4715 sc->sc_txproc_cnt++; 4716 ATH_PCU_UNLOCK(sc); 4717 4718 ATH_LOCK(sc); 4719 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4720 ATH_UNLOCK(sc); 4721 4722 ATH_TX_LOCK(sc); 4723 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 4724 if (ATH_TXQ_SETUP(sc, i)) { 4725 ath_txq_sched(sc, &sc->sc_txq[i]); 4726 } 4727 } 4728 ATH_TX_UNLOCK(sc); 4729 4730 ATH_LOCK(sc); 4731 ath_power_restore_power_state(sc); 4732 ATH_UNLOCK(sc); 4733 4734 ATH_PCU_LOCK(sc); 4735 sc->sc_txproc_cnt--; 4736 ATH_PCU_UNLOCK(sc); 4737 } 4738 4739 void 4740 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf) 4741 { 4742 4743 ATH_TXBUF_LOCK_ASSERT(sc); 4744 4745 if (bf->bf_flags & ATH_BUF_MGMT) 4746 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list); 4747 else { 4748 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4749 sc->sc_txbuf_cnt++; 4750 if (sc->sc_txbuf_cnt > ath_txbuf) { 4751 device_printf(sc->sc_dev, 4752 "%s: sc_txbuf_cnt > %d?\n", 4753 __func__, 4754 ath_txbuf); 4755 sc->sc_txbuf_cnt = ath_txbuf; 4756 } 4757 } 4758 } 4759 4760 void 4761 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf) 4762 { 4763 4764 ATH_TXBUF_LOCK_ASSERT(sc); 4765 4766 if (bf->bf_flags & ATH_BUF_MGMT) 4767 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list); 4768 else { 4769 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 4770 sc->sc_txbuf_cnt++; 4771 if (sc->sc_txbuf_cnt > ATH_TXBUF) { 4772 device_printf(sc->sc_dev, 4773 "%s: sc_txbuf_cnt > %d?\n", 4774 __func__, 4775 ATH_TXBUF); 4776 sc->sc_txbuf_cnt = ATH_TXBUF; 4777 } 4778 } 4779 } 4780 4781 /* 4782 * Free the holding buffer if it exists 4783 */ 4784 void 4785 ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq) 4786 { 4787 ATH_TXBUF_UNLOCK_ASSERT(sc); 4788 ATH_TXQ_LOCK_ASSERT(txq); 4789 4790 if (txq->axq_holdingbf == NULL) 4791 return; 4792 4793 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY; 4794 4795 ATH_TXBUF_LOCK(sc); 4796 ath_returnbuf_tail(sc, txq->axq_holdingbf); 4797 ATH_TXBUF_UNLOCK(sc); 4798 4799 txq->axq_holdingbf = NULL; 4800 } 4801 4802 /* 4803 * Add this buffer to the holding queue, freeing the previous 4804 * one if it exists. 4805 */ 4806 static void 4807 ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf) 4808 { 4809 struct ath_txq *txq; 4810 4811 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue]; 4812 4813 ATH_TXBUF_UNLOCK_ASSERT(sc); 4814 ATH_TXQ_LOCK_ASSERT(txq); 4815 4816 /* XXX assert ATH_BUF_BUSY is set */ 4817 4818 /* XXX assert the tx queue is under the max number */ 4819 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) { 4820 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n", 4821 __func__, 4822 bf, 4823 bf->bf_state.bfs_tx_queue); 4824 bf->bf_flags &= ~ATH_BUF_BUSY; 4825 ath_returnbuf_tail(sc, bf); 4826 return; 4827 } 4828 ath_txq_freeholdingbuf(sc, txq); 4829 txq->axq_holdingbf = bf; 4830 } 4831 4832 /* 4833 * Return a buffer to the pool and update the 'busy' flag on the 4834 * previous 'tail' entry. 4835 * 4836 * This _must_ only be called when the buffer is involved in a completed 4837 * TX. The logic is that if it was part of an active TX, the previous 4838 * buffer on the list is now not involved in a halted TX DMA queue, waiting 4839 * for restart (eg for TDMA.) 4840 * 4841 * The caller must free the mbuf and recycle the node reference. 4842 * 4843 * XXX This method of handling busy / holding buffers is insanely stupid. 4844 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would 4845 * be much nicer if buffers in the processq() methods would instead be 4846 * always completed there (pushed onto a txq or ath_bufhead) so we knew 4847 * exactly what hardware queue they came from in the first place. 4848 */ 4849 void 4850 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf) 4851 { 4852 struct ath_txq *txq; 4853 4854 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue]; 4855 4856 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__)); 4857 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__)); 4858 4859 /* 4860 * If this buffer is busy, push it onto the holding queue. 4861 */ 4862 if (bf->bf_flags & ATH_BUF_BUSY) { 4863 ATH_TXQ_LOCK(txq); 4864 ath_txq_addholdingbuf(sc, bf); 4865 ATH_TXQ_UNLOCK(txq); 4866 return; 4867 } 4868 4869 /* 4870 * Not a busy buffer, so free normally 4871 */ 4872 ATH_TXBUF_LOCK(sc); 4873 ath_returnbuf_tail(sc, bf); 4874 ATH_TXBUF_UNLOCK(sc); 4875 } 4876 4877 /* 4878 * This is currently used by ath_tx_draintxq() and 4879 * ath_tx_tid_free_pkts(). 4880 * 4881 * It recycles a single ath_buf. 4882 */ 4883 void 4884 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status) 4885 { 4886 struct ieee80211_node *ni = bf->bf_node; 4887 struct mbuf *m0 = bf->bf_m; 4888 4889 /* 4890 * Make sure that we only sync/unload if there's an mbuf. 4891 * If not (eg we cloned a buffer), the unload will have already 4892 * occurred. 4893 */ 4894 if (bf->bf_m != NULL) { 4895 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4896 BUS_DMASYNC_POSTWRITE); 4897 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4898 } 4899 4900 bf->bf_node = NULL; 4901 bf->bf_m = NULL; 4902 4903 /* Free the buffer, it's not needed any longer */ 4904 ath_freebuf(sc, bf); 4905 4906 /* Pass the buffer back to net80211 - completing it */ 4907 ieee80211_tx_complete(ni, m0, status); 4908 } 4909 4910 static struct ath_buf * 4911 ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq) 4912 { 4913 struct ath_buf *bf; 4914 4915 ATH_TXQ_LOCK_ASSERT(txq); 4916 4917 /* 4918 * Drain the FIFO queue first, then if it's 4919 * empty, move to the normal frame queue. 4920 */ 4921 bf = TAILQ_FIRST(&txq->fifo.axq_q); 4922 if (bf != NULL) { 4923 /* 4924 * Is it the last buffer in this set? 4925 * Decrement the FIFO counter. 4926 */ 4927 if (bf->bf_flags & ATH_BUF_FIFOEND) { 4928 if (txq->axq_fifo_depth == 0) { 4929 device_printf(sc->sc_dev, 4930 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n", 4931 __func__, 4932 txq->axq_qnum, 4933 txq->fifo.axq_depth); 4934 } else 4935 txq->axq_fifo_depth--; 4936 } 4937 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list); 4938 return (bf); 4939 } 4940 4941 /* 4942 * Debugging! 4943 */ 4944 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) { 4945 device_printf(sc->sc_dev, 4946 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n", 4947 __func__, 4948 txq->axq_qnum, 4949 txq->axq_fifo_depth, 4950 txq->fifo.axq_depth); 4951 } 4952 4953 /* 4954 * Now drain the pending queue. 4955 */ 4956 bf = TAILQ_FIRST(&txq->axq_q); 4957 if (bf == NULL) { 4958 txq->axq_link = NULL; 4959 return (NULL); 4960 } 4961 ATH_TXQ_REMOVE(txq, bf, bf_list); 4962 return (bf); 4963 } 4964 4965 void 4966 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4967 { 4968 #ifdef ATH_DEBUG 4969 struct ath_hal *ah = sc->sc_ah; 4970 #endif 4971 struct ath_buf *bf; 4972 u_int ix; 4973 4974 /* 4975 * NB: this assumes output has been stopped and 4976 * we do not need to block ath_tx_proc 4977 */ 4978 for (ix = 0;; ix++) { 4979 ATH_TXQ_LOCK(txq); 4980 bf = ath_tx_draintxq_get_one(sc, txq); 4981 if (bf == NULL) { 4982 ATH_TXQ_UNLOCK(txq); 4983 break; 4984 } 4985 if (bf->bf_state.bfs_aggr) 4986 txq->axq_aggr_depth--; 4987 #ifdef ATH_DEBUG 4988 if (sc->sc_debug & ATH_DEBUG_RESET) { 4989 struct ieee80211com *ic = &sc->sc_ic; 4990 int status = 0; 4991 4992 /* 4993 * EDMA operation has a TX completion FIFO 4994 * separate from the TX descriptor, so this 4995 * method of checking the "completion" status 4996 * is wrong. 4997 */ 4998 if (! sc->sc_isedma) { 4999 status = (ath_hal_txprocdesc(ah, 5000 bf->bf_lastds, 5001 &bf->bf_status.ds_txstat) == HAL_OK); 5002 } 5003 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status); 5004 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 5005 bf->bf_m->m_len, 0, -1); 5006 } 5007 #endif /* ATH_DEBUG */ 5008 /* 5009 * Since we're now doing magic in the completion 5010 * functions, we -must- call it for aggregation 5011 * destinations or BAW tracking will get upset. 5012 */ 5013 /* 5014 * Clear ATH_BUF_BUSY; the completion handler 5015 * will free the buffer. 5016 */ 5017 ATH_TXQ_UNLOCK(txq); 5018 bf->bf_flags &= ~ATH_BUF_BUSY; 5019 if (bf->bf_comp) 5020 bf->bf_comp(sc, bf, 1); 5021 else 5022 ath_tx_default_comp(sc, bf, 1); 5023 } 5024 5025 /* 5026 * Free the holding buffer if it exists 5027 */ 5028 ATH_TXQ_LOCK(txq); 5029 ath_txq_freeholdingbuf(sc, txq); 5030 ATH_TXQ_UNLOCK(txq); 5031 5032 /* 5033 * Drain software queued frames which are on 5034 * active TIDs. 5035 */ 5036 ath_tx_txq_drain(sc, txq); 5037 } 5038 5039 static void 5040 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5041 { 5042 struct ath_hal *ah = sc->sc_ah; 5043 5044 ATH_TXQ_LOCK_ASSERT(txq); 5045 5046 DPRINTF(sc, ATH_DEBUG_RESET, 5047 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, " 5048 "link %p, holdingbf=%p\n", 5049 __func__, 5050 txq->axq_qnum, 5051 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5052 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)), 5053 (int) ath_hal_numtxpending(ah, txq->axq_qnum), 5054 txq->axq_flags, 5055 txq->axq_link, 5056 txq->axq_holdingbf); 5057 5058 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5059 /* We've stopped TX DMA, so mark this as stopped. */ 5060 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING; 5061 5062 #ifdef ATH_DEBUG 5063 if ((sc->sc_debug & ATH_DEBUG_RESET) 5064 && (txq->axq_holdingbf != NULL)) { 5065 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0); 5066 } 5067 #endif 5068 } 5069 5070 int 5071 ath_stoptxdma(struct ath_softc *sc) 5072 { 5073 struct ath_hal *ah = sc->sc_ah; 5074 int i; 5075 5076 /* XXX return value */ 5077 if (sc->sc_invalid) 5078 return 0; 5079 5080 if (!sc->sc_invalid) { 5081 /* don't touch the hardware if marked invalid */ 5082 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5083 __func__, sc->sc_bhalq, 5084 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5085 NULL); 5086 5087 /* stop the beacon queue */ 5088 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5089 5090 /* Stop the data queues */ 5091 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5092 if (ATH_TXQ_SETUP(sc, i)) { 5093 ATH_TXQ_LOCK(&sc->sc_txq[i]); 5094 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5095 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 5096 } 5097 } 5098 } 5099 5100 return 1; 5101 } 5102 5103 #ifdef ATH_DEBUG 5104 void 5105 ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq) 5106 { 5107 struct ath_hal *ah = sc->sc_ah; 5108 struct ath_buf *bf; 5109 int i = 0; 5110 5111 if (! (sc->sc_debug & ATH_DEBUG_RESET)) 5112 return; 5113 5114 device_printf(sc->sc_dev, "%s: Q%d: begin\n", 5115 __func__, txq->axq_qnum); 5116 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) { 5117 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 5118 ath_hal_txprocdesc(ah, bf->bf_lastds, 5119 &bf->bf_status.ds_txstat) == HAL_OK); 5120 i++; 5121 } 5122 device_printf(sc->sc_dev, "%s: Q%d: end\n", 5123 __func__, txq->axq_qnum); 5124 } 5125 #endif /* ATH_DEBUG */ 5126 5127 /* 5128 * Drain the transmit queues and reclaim resources. 5129 */ 5130 void 5131 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 5132 { 5133 struct ath_hal *ah = sc->sc_ah; 5134 struct ath_buf *bf_last; 5135 int i; 5136 5137 (void) ath_stoptxdma(sc); 5138 5139 /* 5140 * Dump the queue contents 5141 */ 5142 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5143 /* 5144 * XXX TODO: should we just handle the completed TX frames 5145 * here, whether or not the reset is a full one or not? 5146 */ 5147 if (ATH_TXQ_SETUP(sc, i)) { 5148 #ifdef ATH_DEBUG 5149 if (sc->sc_debug & ATH_DEBUG_RESET) 5150 ath_tx_dump(sc, &sc->sc_txq[i]); 5151 #endif /* ATH_DEBUG */ 5152 if (reset_type == ATH_RESET_NOLOSS) { 5153 ath_tx_processq(sc, &sc->sc_txq[i], 0); 5154 ATH_TXQ_LOCK(&sc->sc_txq[i]); 5155 /* 5156 * Free the holding buffer; DMA is now 5157 * stopped. 5158 */ 5159 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]); 5160 /* 5161 * Setup the link pointer to be the 5162 * _last_ buffer/descriptor in the list. 5163 * If there's nothing in the list, set it 5164 * to NULL. 5165 */ 5166 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i], 5167 axq_q_s); 5168 if (bf_last != NULL) { 5169 ath_hal_gettxdesclinkptr(ah, 5170 bf_last->bf_lastds, 5171 &sc->sc_txq[i].axq_link); 5172 } else { 5173 sc->sc_txq[i].axq_link = NULL; 5174 } 5175 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 5176 } else 5177 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5178 } 5179 } 5180 #ifdef ATH_DEBUG 5181 if (sc->sc_debug & ATH_DEBUG_RESET) { 5182 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf); 5183 if (bf != NULL && bf->bf_m != NULL) { 5184 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5185 ath_hal_txprocdesc(ah, bf->bf_lastds, 5186 &bf->bf_status.ds_txstat) == HAL_OK); 5187 ieee80211_dump_pkt(&sc->sc_ic, 5188 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 5189 0, -1); 5190 } 5191 } 5192 #endif /* ATH_DEBUG */ 5193 sc->sc_wd_timer = 0; 5194 } 5195 5196 /* 5197 * Update internal state after a channel change. 5198 */ 5199 static void 5200 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5201 { 5202 enum ieee80211_phymode mode; 5203 5204 /* 5205 * Change channels and update the h/w rate map 5206 * if we're switching; e.g. 11a to 11b/g. 5207 */ 5208 mode = ieee80211_chan2mode(chan); 5209 if (mode != sc->sc_curmode) 5210 ath_setcurmode(sc, mode); 5211 sc->sc_curchan = chan; 5212 } 5213 5214 /* 5215 * Set/change channels. If the channel is really being changed, 5216 * it's done by resetting the chip. To accomplish this we must 5217 * first cleanup any pending DMA, then restart stuff after a la 5218 * ath_init. 5219 */ 5220 static int 5221 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5222 { 5223 struct ieee80211com *ic = &sc->sc_ic; 5224 struct ath_hal *ah = sc->sc_ah; 5225 int ret = 0; 5226 5227 /* Treat this as an interface reset */ 5228 ATH_PCU_UNLOCK_ASSERT(sc); 5229 ATH_UNLOCK_ASSERT(sc); 5230 5231 /* (Try to) stop TX/RX from occurring */ 5232 taskqueue_block(sc->sc_tq); 5233 5234 ATH_PCU_LOCK(sc); 5235 5236 /* Disable interrupts */ 5237 ath_hal_intrset(ah, 0); 5238 5239 /* Stop new RX/TX/interrupt completion */ 5240 if (ath_reset_grablock(sc, 1) == 0) { 5241 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 5242 __func__); 5243 } 5244 5245 /* Stop pending RX/TX completion */ 5246 ath_txrx_stop_locked(sc); 5247 5248 ATH_PCU_UNLOCK(sc); 5249 5250 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 5251 __func__, ieee80211_chan2ieee(ic, chan), 5252 chan->ic_freq, chan->ic_flags); 5253 if (chan != sc->sc_curchan) { 5254 HAL_STATUS status; 5255 /* 5256 * To switch channels clear any pending DMA operations; 5257 * wait long enough for the RX fifo to drain, reset the 5258 * hardware at the new frequency, and then re-enable 5259 * the relevant bits of the h/w. 5260 */ 5261 #if 0 5262 ath_hal_intrset(ah, 0); /* disable interrupts */ 5263 #endif 5264 ath_stoprecv(sc, 1); /* turn off frame recv */ 5265 /* 5266 * First, handle completed TX/RX frames. 5267 */ 5268 ath_rx_flush(sc); 5269 ath_draintxq(sc, ATH_RESET_NOLOSS); 5270 /* 5271 * Next, flush the non-scheduled frames. 5272 */ 5273 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */ 5274 5275 ath_update_chainmasks(sc, chan); 5276 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 5277 sc->sc_cur_rxchainmask); 5278 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, 5279 HAL_RESET_NORMAL, &status)) { 5280 device_printf(sc->sc_dev, "%s: unable to reset " 5281 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 5282 __func__, ieee80211_chan2ieee(ic, chan), 5283 chan->ic_freq, chan->ic_flags, status); 5284 ret = EIO; 5285 goto finish; 5286 } 5287 sc->sc_diversity = ath_hal_getdiversity(ah); 5288 5289 ATH_RX_LOCK(sc); 5290 sc->sc_rx_stopped = 1; 5291 sc->sc_rx_resetted = 1; 5292 ATH_RX_UNLOCK(sc); 5293 5294 /* Quiet time handling - ensure we resync */ 5295 ath_vap_clear_quiet_ie(sc); 5296 5297 /* Let DFS at it in case it's a DFS channel */ 5298 ath_dfs_radar_enable(sc, chan); 5299 5300 /* Let spectral at in case spectral is enabled */ 5301 ath_spectral_enable(sc, chan); 5302 5303 /* 5304 * Let bluetooth coexistence at in case it's needed for this 5305 * channel 5306 */ 5307 ath_btcoex_enable(sc, ic->ic_curchan); 5308 5309 /* 5310 * If we're doing TDMA, enforce the TXOP limitation for chips 5311 * that support it. 5312 */ 5313 if (sc->sc_hasenforcetxop && sc->sc_tdma) 5314 ath_hal_setenforcetxop(sc->sc_ah, 1); 5315 else 5316 ath_hal_setenforcetxop(sc->sc_ah, 0); 5317 5318 /* 5319 * Re-enable rx framework. 5320 */ 5321 if (ath_startrecv(sc) != 0) { 5322 device_printf(sc->sc_dev, 5323 "%s: unable to restart recv logic\n", __func__); 5324 ret = EIO; 5325 goto finish; 5326 } 5327 5328 /* 5329 * Change channels and update the h/w rate map 5330 * if we're switching; e.g. 11a to 11b/g. 5331 */ 5332 ath_chan_change(sc, chan); 5333 5334 /* 5335 * Reset clears the beacon timers; reset them 5336 * here if needed. 5337 */ 5338 if (sc->sc_beacons) { /* restart beacons */ 5339 #ifdef IEEE80211_SUPPORT_TDMA 5340 if (sc->sc_tdma) 5341 ath_tdma_config(sc, NULL); 5342 else 5343 #endif 5344 ath_beacon_config(sc, NULL); 5345 } 5346 5347 /* 5348 * Re-enable interrupts. 5349 */ 5350 #if 0 5351 ath_hal_intrset(ah, sc->sc_imask); 5352 #endif 5353 } 5354 5355 finish: 5356 ATH_PCU_LOCK(sc); 5357 sc->sc_inreset_cnt--; 5358 /* XXX only do this if sc_inreset_cnt == 0? */ 5359 ath_hal_intrset(ah, sc->sc_imask); 5360 ATH_PCU_UNLOCK(sc); 5361 5362 ath_txrx_start(sc); 5363 /* XXX ath_start? */ 5364 5365 return ret; 5366 } 5367 5368 /* 5369 * Periodically recalibrate the PHY to account 5370 * for temperature/environment changes. 5371 */ 5372 static void 5373 ath_calibrate(void *arg) 5374 { 5375 struct ath_softc *sc = arg; 5376 struct ath_hal *ah = sc->sc_ah; 5377 struct ieee80211com *ic = &sc->sc_ic; 5378 HAL_BOOL longCal, isCalDone = AH_TRUE; 5379 HAL_BOOL aniCal, shortCal = AH_FALSE; 5380 int nextcal; 5381 5382 ATH_LOCK_ASSERT(sc); 5383 5384 /* 5385 * Force the hardware awake for ANI work. 5386 */ 5387 ath_power_set_power_state(sc, HAL_PM_AWAKE); 5388 5389 /* Skip trying to do this if we're in reset */ 5390 if (sc->sc_inreset_cnt) 5391 goto restart; 5392 5393 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 5394 goto restart; 5395 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5396 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000); 5397 if (sc->sc_doresetcal) 5398 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000); 5399 5400 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal); 5401 if (aniCal) { 5402 sc->sc_stats.ast_ani_cal++; 5403 sc->sc_lastani = ticks; 5404 ath_hal_ani_poll(ah, sc->sc_curchan); 5405 } 5406 5407 if (longCal) { 5408 sc->sc_stats.ast_per_cal++; 5409 sc->sc_lastlongcal = ticks; 5410 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5411 /* 5412 * Rfgain is out of bounds, reset the chip 5413 * to load new gain values. 5414 */ 5415 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5416 "%s: rfgain change\n", __func__); 5417 sc->sc_stats.ast_per_rfgain++; 5418 sc->sc_resetcal = 0; 5419 sc->sc_doresetcal = AH_TRUE; 5420 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 5421 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 5422 ath_power_restore_power_state(sc); 5423 return; 5424 } 5425 /* 5426 * If this long cal is after an idle period, then 5427 * reset the data collection state so we start fresh. 5428 */ 5429 if (sc->sc_resetcal) { 5430 (void) ath_hal_calreset(ah, sc->sc_curchan); 5431 sc->sc_lastcalreset = ticks; 5432 sc->sc_lastshortcal = ticks; 5433 sc->sc_resetcal = 0; 5434 sc->sc_doresetcal = AH_TRUE; 5435 } 5436 } 5437 5438 /* Only call if we're doing a short/long cal, not for ANI calibration */ 5439 if (shortCal || longCal) { 5440 isCalDone = AH_FALSE; 5441 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 5442 if (longCal) { 5443 /* 5444 * Calibrate noise floor data again in case of change. 5445 */ 5446 ath_hal_process_noisefloor(ah); 5447 } 5448 } else { 5449 DPRINTF(sc, ATH_DEBUG_ANY, 5450 "%s: calibration of channel %u failed\n", 5451 __func__, sc->sc_curchan->ic_freq); 5452 sc->sc_stats.ast_per_calfail++; 5453 } 5454 /* 5455 * XXX TODO: get the NF calibration results from the HAL. 5456 * If we failed NF cal then schedule a hard reset to potentially 5457 * un-freeze the PHY. 5458 * 5459 * Note we have to be careful here to not get stuck in an 5460 * infinite NIC restart. Ideally we'd not restart if we 5461 * failed the first NF cal - that /can/ fail sometimes in 5462 * a noisy environment. 5463 */ 5464 if (shortCal) 5465 sc->sc_lastshortcal = ticks; 5466 } 5467 if (!isCalDone) { 5468 restart: 5469 /* 5470 * Use a shorter interval to potentially collect multiple 5471 * data samples required to complete calibration. Once 5472 * we're told the work is done we drop back to a longer 5473 * interval between requests. We're more aggressive doing 5474 * work when operating as an AP to improve operation right 5475 * after startup. 5476 */ 5477 sc->sc_lastshortcal = ticks; 5478 nextcal = ath_shortcalinterval*hz/1000; 5479 if (sc->sc_opmode != HAL_M_HOSTAP) 5480 nextcal *= 10; 5481 sc->sc_doresetcal = AH_TRUE; 5482 } else { 5483 /* nextcal should be the shortest time for next event */ 5484 nextcal = ath_longcalinterval*hz; 5485 if (sc->sc_lastcalreset == 0) 5486 sc->sc_lastcalreset = sc->sc_lastlongcal; 5487 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 5488 sc->sc_resetcal = 1; /* setup reset next trip */ 5489 sc->sc_doresetcal = AH_FALSE; 5490 } 5491 /* ANI calibration may occur more often than short/long/resetcal */ 5492 if (ath_anicalinterval > 0) 5493 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000); 5494 5495 if (nextcal != 0) { 5496 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 5497 __func__, nextcal, isCalDone ? "" : "!"); 5498 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 5499 } else { 5500 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 5501 __func__); 5502 /* NB: don't rearm timer */ 5503 } 5504 /* 5505 * Restore power state now that we're done. 5506 */ 5507 ath_power_restore_power_state(sc); 5508 } 5509 5510 static void 5511 ath_scan_start(struct ieee80211com *ic) 5512 { 5513 struct ath_softc *sc = ic->ic_softc; 5514 struct ath_hal *ah = sc->sc_ah; 5515 u_int32_t rfilt; 5516 5517 /* XXX calibration timer? */ 5518 /* XXXGL: is constant ieee80211broadcastaddr a correct choice? */ 5519 5520 ATH_LOCK(sc); 5521 sc->sc_scanning = 1; 5522 sc->sc_syncbeacon = 0; 5523 rfilt = ath_calcrxfilter(sc); 5524 ATH_UNLOCK(sc); 5525 5526 ATH_PCU_LOCK(sc); 5527 ath_hal_setrxfilter(ah, rfilt); 5528 ath_hal_setassocid(ah, ieee80211broadcastaddr, 0); 5529 ATH_PCU_UNLOCK(sc); 5530 5531 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5532 __func__, rfilt, ether_sprintf(ieee80211broadcastaddr)); 5533 } 5534 5535 static void 5536 ath_scan_end(struct ieee80211com *ic) 5537 { 5538 struct ath_softc *sc = ic->ic_softc; 5539 struct ath_hal *ah = sc->sc_ah; 5540 u_int32_t rfilt; 5541 5542 ATH_LOCK(sc); 5543 sc->sc_scanning = 0; 5544 rfilt = ath_calcrxfilter(sc); 5545 ATH_UNLOCK(sc); 5546 5547 ATH_PCU_LOCK(sc); 5548 ath_hal_setrxfilter(ah, rfilt); 5549 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5550 5551 ath_hal_process_noisefloor(ah); 5552 ATH_PCU_UNLOCK(sc); 5553 5554 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5555 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5556 sc->sc_curaid); 5557 } 5558 5559 #ifdef ATH_ENABLE_11N 5560 /* 5561 * For now, just do a channel change. 5562 * 5563 * Later, we'll go through the hard slog of suspending tx/rx, changing rate 5564 * control state and resetting the hardware without dropping frames out 5565 * of the queue. 5566 * 5567 * The unfortunate trouble here is making absolutely sure that the 5568 * channel width change has propagated enough so the hardware 5569 * absolutely isn't handed bogus frames for it's current operating 5570 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and 5571 * does occur in parallel, we need to make certain we've blocked 5572 * any further ongoing TX (and RX, that can cause raw TX) 5573 * before we do this. 5574 */ 5575 static void 5576 ath_update_chw(struct ieee80211com *ic) 5577 { 5578 struct ath_softc *sc = ic->ic_softc; 5579 5580 //DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__); 5581 device_printf(sc->sc_dev, "%s: called\n", __func__); 5582 5583 /* 5584 * XXX TODO: schedule a tasklet that stops things without freeing, 5585 * walks the now stopped TX queue(s) looking for frames to retry 5586 * as if we TX filtered them (whch may mean dropping non-ampdu frames!) 5587 * but okay) then place them back on the software queue so they 5588 * can have the rate control lookup done again. 5589 */ 5590 ath_set_channel(ic); 5591 } 5592 #endif /* ATH_ENABLE_11N */ 5593 5594 /* 5595 * This is called by the beacon parsing routine in the receive 5596 * path to update the current quiet time information provided by 5597 * an AP. 5598 * 5599 * This is STA specific, it doesn't take the AP TBTT/beacon slot 5600 * offset into account. 5601 * 5602 * The quiet IE doesn't control the /now/ beacon interval - it 5603 * controls the upcoming beacon interval. So, when tbtt=1, 5604 * the quiet element programming shall be for the next beacon 5605 * interval. There's no tbtt=0 behaviour defined, so don't. 5606 * 5607 * Since we're programming the next quiet interval, we have 5608 * to keep in mind what we will see when the next beacon 5609 * is received with potentially a quiet IE. For example, if 5610 * quiet_period is 1, then we are always getting a quiet interval 5611 * each TBTT - so if we just program it in upon each beacon received, 5612 * it will constantly reflect the "next" TBTT and we will never 5613 * let the counter stay programmed correctly. 5614 * 5615 * So: 5616 * + the first time we see the quiet IE, program it and store 5617 * the details somewhere; 5618 * + if the quiet parameters don't change (ie, period/duration/offset) 5619 * then just leave the programming enabled; 5620 * + (we can "skip" beacons, so don't try to enforce tbttcount unless 5621 * you're willing to also do the skipped beacon math); 5622 * + if the quiet IE is removed, then halt quiet time. 5623 */ 5624 static int 5625 ath_set_quiet_ie(struct ieee80211_node *ni, uint8_t *ie) 5626 { 5627 struct ieee80211_quiet_ie *q; 5628 struct ieee80211vap *vap = ni->ni_vap; 5629 struct ath_vap *avp = ATH_VAP(vap); 5630 struct ieee80211com *ic = vap->iv_ic; 5631 struct ath_softc *sc = ic->ic_softc; 5632 5633 if (vap->iv_opmode != IEEE80211_M_STA) 5634 return (0); 5635 5636 /* Verify we have a quiet time IE */ 5637 if (ie == NULL) { 5638 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5639 "%s: called; NULL IE, disabling\n", __func__); 5640 5641 ath_hal_set_quiet(sc->sc_ah, 0, 0, 0, HAL_QUIET_DISABLE); 5642 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 5643 return (0); 5644 } 5645 5646 /* If we do, verify it's actually legit */ 5647 if (ie[0] != IEEE80211_ELEMID_QUIET) 5648 return 0; 5649 if (ie[1] != 6) 5650 return 0; 5651 5652 /* Note: this belongs in net80211, parsed out and everything */ 5653 q = (void *) ie; 5654 5655 /* 5656 * Compare what we have stored to what we last saw. 5657 * If they're the same then don't program in anything. 5658 */ 5659 if ((q->period == avp->quiet_ie.period) && 5660 (le16dec(&q->duration) == le16dec(&avp->quiet_ie.duration)) && 5661 (le16dec(&q->offset) == le16dec(&avp->quiet_ie.offset))) 5662 return (0); 5663 5664 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5665 "%s: called; tbttcount=%d, period=%d, duration=%d, offset=%d\n", 5666 __func__, 5667 (int) q->tbttcount, 5668 (int) q->period, 5669 (int) le16dec(&q->duration), 5670 (int) le16dec(&q->offset)); 5671 5672 /* 5673 * Don't program in garbage values. 5674 */ 5675 if ((le16dec(&q->duration) == 0) || 5676 (le16dec(&q->duration) >= ni->ni_intval)) { 5677 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5678 "%s: invalid duration (%d)\n", __func__, 5679 le16dec(&q->duration)); 5680 return (0); 5681 } 5682 /* 5683 * Can have a 0 offset, but not a duration - so just check 5684 * they don't exceed the intval. 5685 */ 5686 if (le16dec(&q->duration) + le16dec(&q->offset) >= ni->ni_intval) { 5687 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5688 "%s: invalid duration + offset (%d+%d)\n", __func__, 5689 le16dec(&q->duration), 5690 le16dec(&q->offset)); 5691 return (0); 5692 } 5693 if (q->tbttcount == 0) { 5694 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5695 "%s: invalid tbttcount (0)\n", __func__); 5696 return (0); 5697 } 5698 if (q->period == 0) { 5699 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5700 "%s: invalid period (0)\n", __func__); 5701 return (0); 5702 } 5703 5704 /* 5705 * This is a new quiet time IE config, so wait until tbttcount 5706 * is equal to 1, and program it in. 5707 */ 5708 if (q->tbttcount == 1) { 5709 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5710 "%s: programming\n", __func__); 5711 ath_hal_set_quiet(sc->sc_ah, 5712 q->period * ni->ni_intval, /* convert to TU */ 5713 le16dec(&q->duration), /* already in TU */ 5714 le16dec(&q->offset) + ni->ni_intval, 5715 HAL_QUIET_ENABLE | HAL_QUIET_ADD_CURRENT_TSF); 5716 /* 5717 * Note: no HAL_QUIET_ADD_SWBA_RESP_TIME; as this is for 5718 * STA mode 5719 */ 5720 5721 /* Update local state */ 5722 memcpy(&avp->quiet_ie, ie, sizeof(struct ieee80211_quiet_ie)); 5723 } 5724 5725 return (0); 5726 } 5727 5728 static void 5729 ath_set_channel(struct ieee80211com *ic) 5730 { 5731 struct ath_softc *sc = ic->ic_softc; 5732 5733 ATH_LOCK(sc); 5734 ath_power_set_power_state(sc, HAL_PM_AWAKE); 5735 ATH_UNLOCK(sc); 5736 5737 (void) ath_chan_set(sc, ic->ic_curchan); 5738 /* 5739 * If we are returning to our bss channel then mark state 5740 * so the next recv'd beacon's tsf will be used to sync the 5741 * beacon timers. Note that since we only hear beacons in 5742 * sta/ibss mode this has no effect in other operating modes. 5743 */ 5744 ATH_LOCK(sc); 5745 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5746 sc->sc_syncbeacon = 1; 5747 ath_power_restore_power_state(sc); 5748 ATH_UNLOCK(sc); 5749 } 5750 5751 /* 5752 * Walk the vap list and check if there any vap's in RUN state. 5753 */ 5754 static int 5755 ath_isanyrunningvaps(struct ieee80211vap *this) 5756 { 5757 struct ieee80211com *ic = this->iv_ic; 5758 struct ieee80211vap *vap; 5759 5760 IEEE80211_LOCK_ASSERT(ic); 5761 5762 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5763 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 5764 return 1; 5765 } 5766 return 0; 5767 } 5768 5769 static int 5770 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5771 { 5772 struct ieee80211com *ic = vap->iv_ic; 5773 struct ath_softc *sc = ic->ic_softc; 5774 struct ath_vap *avp = ATH_VAP(vap); 5775 struct ath_hal *ah = sc->sc_ah; 5776 struct ieee80211_node *ni = NULL; 5777 int i, error, stamode; 5778 u_int32_t rfilt; 5779 int csa_run_transition = 0; 5780 enum ieee80211_state ostate = vap->iv_state; 5781 5782 static const HAL_LED_STATE leds[] = { 5783 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5784 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5785 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5786 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5787 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5788 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5789 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5790 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5791 }; 5792 5793 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5794 ieee80211_state_name[ostate], 5795 ieee80211_state_name[nstate]); 5796 5797 /* 5798 * net80211 _should_ have the comlock asserted at this point. 5799 * There are some comments around the calls to vap->iv_newstate 5800 * which indicate that it (newstate) may end up dropping the 5801 * lock. This and the subsequent lock assert check after newstate 5802 * are an attempt to catch these and figure out how/why. 5803 */ 5804 IEEE80211_LOCK_ASSERT(ic); 5805 5806 /* Before we touch the hardware - wake it up */ 5807 ATH_LOCK(sc); 5808 /* 5809 * If the NIC is in anything other than SLEEP state, 5810 * we need to ensure that self-generated frames are 5811 * set for PWRMGT=0. Otherwise we may end up with 5812 * strange situations. 5813 * 5814 * XXX TODO: is this actually the case? :-) 5815 */ 5816 if (nstate != IEEE80211_S_SLEEP) 5817 ath_power_setselfgen(sc, HAL_PM_AWAKE); 5818 5819 /* 5820 * Now, wake the thing up. 5821 */ 5822 ath_power_set_power_state(sc, HAL_PM_AWAKE); 5823 5824 /* 5825 * And stop the calibration callout whilst we have 5826 * ATH_LOCK held. 5827 */ 5828 callout_stop(&sc->sc_cal_ch); 5829 ATH_UNLOCK(sc); 5830 5831 if (ostate == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN) 5832 csa_run_transition = 1; 5833 5834 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5835 5836 if (nstate == IEEE80211_S_SCAN) { 5837 /* 5838 * Scanning: turn off beacon miss and don't beacon. 5839 * Mark beacon state so when we reach RUN state we'll 5840 * [re]setup beacons. Unblock the task q thread so 5841 * deferred interrupt processing is done. 5842 */ 5843 5844 /* Ensure we stay awake during scan */ 5845 ATH_LOCK(sc); 5846 ath_power_setselfgen(sc, HAL_PM_AWAKE); 5847 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 5848 ATH_UNLOCK(sc); 5849 5850 ath_hal_intrset(ah, 5851 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5852 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5853 sc->sc_beacons = 0; 5854 taskqueue_unblock(sc->sc_tq); 5855 } 5856 5857 ni = ieee80211_ref_node(vap->iv_bss); 5858 rfilt = ath_calcrxfilter(sc); 5859 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5860 vap->iv_opmode == IEEE80211_M_AHDEMO || 5861 vap->iv_opmode == IEEE80211_M_IBSS); 5862 5863 /* 5864 * XXX Dont need to do this (and others) if we've transitioned 5865 * from SLEEP->RUN. 5866 */ 5867 if (stamode && nstate == IEEE80211_S_RUN) { 5868 sc->sc_curaid = ni->ni_associd; 5869 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5870 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5871 } 5872 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5873 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5874 ath_hal_setrxfilter(ah, rfilt); 5875 5876 /* XXX is this to restore keycache on resume? */ 5877 if (vap->iv_opmode != IEEE80211_M_STA && 5878 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5879 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5880 if (ath_hal_keyisvalid(ah, i)) 5881 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5882 } 5883 5884 /* 5885 * Invoke the parent method to do net80211 work. 5886 */ 5887 error = avp->av_newstate(vap, nstate, arg); 5888 if (error != 0) 5889 goto bad; 5890 5891 /* 5892 * See above: ensure av_newstate() doesn't drop the lock 5893 * on us. 5894 */ 5895 IEEE80211_LOCK_ASSERT(ic); 5896 5897 /* 5898 * XXX TODO: if nstate is _S_CAC, then we should disable 5899 * ACK processing until CAC is completed. 5900 */ 5901 5902 /* 5903 * XXX TODO: if we're on a passive channel, then we should 5904 * not allow any ACKs or self-generated frames until we hear 5905 * a beacon. Unfortunately there isn't a notification from 5906 * net80211 so perhaps we could slot that particular check 5907 * into the mgmt receive path and just ensure that we clear 5908 * it on RX of beacons in passive mode (and only clear it 5909 * once, obviously.) 5910 */ 5911 5912 /* 5913 * XXX TODO: net80211 should be tracking whether channels 5914 * have heard beacons and are thus considered "OK" for 5915 * transmitting - and then inform the driver about this 5916 * state change. That way if we hear an AP go quiet 5917 * (and nothing else is beaconing on a channel) the 5918 * channel can go back to being passive until another 5919 * beacon is heard. 5920 */ 5921 5922 /* 5923 * XXX TODO: if nstate is _S_CAC, then we should disable 5924 * ACK processing until CAC is completed. 5925 */ 5926 5927 /* 5928 * XXX TODO: if we're on a passive channel, then we should 5929 * not allow any ACKs or self-generated frames until we hear 5930 * a beacon. Unfortunately there isn't a notification from 5931 * net80211 so perhaps we could slot that particular check 5932 * into the mgmt receive path and just ensure that we clear 5933 * it on RX of beacons in passive mode (and only clear it 5934 * once, obviously.) 5935 */ 5936 5937 /* 5938 * XXX TODO: net80211 should be tracking whether channels 5939 * have heard beacons and are thus considered "OK" for 5940 * transmitting - and then inform the driver about this 5941 * state change. That way if we hear an AP go quiet 5942 * (and nothing else is beaconing on a channel) the 5943 * channel can go back to being passive until another 5944 * beacon is heard. 5945 */ 5946 5947 if (nstate == IEEE80211_S_RUN) { 5948 /* NB: collect bss node again, it may have changed */ 5949 ieee80211_free_node(ni); 5950 ni = ieee80211_ref_node(vap->iv_bss); 5951 5952 DPRINTF(sc, ATH_DEBUG_STATE, 5953 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5954 "capinfo 0x%04x chan %d\n", __func__, 5955 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5956 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5957 5958 switch (vap->iv_opmode) { 5959 #ifdef IEEE80211_SUPPORT_TDMA 5960 case IEEE80211_M_AHDEMO: 5961 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5962 break; 5963 /* fall thru... */ 5964 #endif 5965 case IEEE80211_M_HOSTAP: 5966 case IEEE80211_M_IBSS: 5967 case IEEE80211_M_MBSS: 5968 5969 /* 5970 * TODO: Enable ACK processing (ie, clear AR_DIAG_ACK_DIS.) 5971 * For channels that are in CAC, we may have disabled 5972 * this during CAC to ensure we don't ACK frames 5973 * sent to us. 5974 */ 5975 5976 /* 5977 * Allocate and setup the beacon frame. 5978 * 5979 * Stop any previous beacon DMA. This may be 5980 * necessary, for example, when an ibss merge 5981 * causes reconfiguration; there will be a state 5982 * transition from RUN->RUN that means we may 5983 * be called with beacon transmission active. 5984 */ 5985 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5986 5987 error = ath_beacon_alloc(sc, ni); 5988 if (error != 0) 5989 goto bad; 5990 /* 5991 * If joining an adhoc network defer beacon timer 5992 * configuration to the next beacon frame so we 5993 * have a current TSF to use. Otherwise we're 5994 * starting an ibss/bss so there's no need to delay; 5995 * if this is the first vap moving to RUN state, then 5996 * beacon state needs to be [re]configured. 5997 */ 5998 if (vap->iv_opmode == IEEE80211_M_IBSS && 5999 ni->ni_tstamp.tsf != 0) { 6000 sc->sc_syncbeacon = 1; 6001 } else if (!sc->sc_beacons) { 6002 #ifdef IEEE80211_SUPPORT_TDMA 6003 if (vap->iv_caps & IEEE80211_C_TDMA) 6004 ath_tdma_config(sc, vap); 6005 else 6006 #endif 6007 ath_beacon_config(sc, vap); 6008 sc->sc_beacons = 1; 6009 } 6010 break; 6011 case IEEE80211_M_STA: 6012 /* 6013 * Defer beacon timer configuration to the next 6014 * beacon frame so we have a current TSF to use 6015 * (any TSF collected when scanning is likely old). 6016 * However if it's due to a CSA -> RUN transition, 6017 * force a beacon update so we pick up a lack of 6018 * beacons from an AP in CAC and thus force a 6019 * scan. 6020 * 6021 * And, there's also corner cases here where 6022 * after a scan, the AP may have disappeared. 6023 * In that case, we may not receive an actual 6024 * beacon to update the beacon timer and thus we 6025 * won't get notified of the missing beacons. 6026 */ 6027 if (ostate != IEEE80211_S_RUN && 6028 ostate != IEEE80211_S_SLEEP) { 6029 DPRINTF(sc, ATH_DEBUG_BEACON, 6030 "%s: STA; syncbeacon=1\n", __func__); 6031 sc->sc_syncbeacon = 1; 6032 6033 /* Quiet time handling - ensure we resync */ 6034 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 6035 6036 if (csa_run_transition) 6037 ath_beacon_config(sc, vap); 6038 6039 /* 6040 * PR: kern/175227 6041 * 6042 * Reconfigure beacons during reset; as otherwise 6043 * we won't get the beacon timers reprogrammed 6044 * after a reset and thus we won't pick up a 6045 * beacon miss interrupt. 6046 * 6047 * Hopefully we'll see a beacon before the BMISS 6048 * timer fires (too often), leading to a STA 6049 * disassociation. 6050 */ 6051 sc->sc_beacons = 1; 6052 } 6053 break; 6054 case IEEE80211_M_MONITOR: 6055 /* 6056 * Monitor mode vaps have only INIT->RUN and RUN->RUN 6057 * transitions so we must re-enable interrupts here to 6058 * handle the case of a single monitor mode vap. 6059 */ 6060 ath_hal_intrset(ah, sc->sc_imask); 6061 break; 6062 case IEEE80211_M_WDS: 6063 break; 6064 default: 6065 break; 6066 } 6067 /* 6068 * Let the hal process statistics collected during a 6069 * scan so it can provide calibrated noise floor data. 6070 */ 6071 ath_hal_process_noisefloor(ah); 6072 /* 6073 * Reset rssi stats; maybe not the best place... 6074 */ 6075 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 6076 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 6077 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 6078 6079 /* 6080 * Force awake for RUN mode. 6081 */ 6082 ATH_LOCK(sc); 6083 ath_power_setselfgen(sc, HAL_PM_AWAKE); 6084 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 6085 6086 /* 6087 * Finally, start any timers and the task q thread 6088 * (in case we didn't go through SCAN state). 6089 */ 6090 if (ath_longcalinterval != 0) { 6091 /* start periodic recalibration timer */ 6092 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 6093 } else { 6094 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 6095 "%s: calibration disabled\n", __func__); 6096 } 6097 ATH_UNLOCK(sc); 6098 6099 taskqueue_unblock(sc->sc_tq); 6100 } else if (nstate == IEEE80211_S_INIT) { 6101 6102 /* Quiet time handling - ensure we resync */ 6103 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 6104 6105 /* 6106 * If there are no vaps left in RUN state then 6107 * shutdown host/driver operation: 6108 * o disable interrupts 6109 * o disable the task queue thread 6110 * o mark beacon processing as stopped 6111 */ 6112 if (!ath_isanyrunningvaps(vap)) { 6113 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 6114 /* disable interrupts */ 6115 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 6116 taskqueue_block(sc->sc_tq); 6117 sc->sc_beacons = 0; 6118 } 6119 6120 /* 6121 * For at least STA mode we likely should clear the ANI 6122 * and NF calibration state and allow the NIC/HAL to figure 6123 * out optimal parameters at runtime. Otherwise if we 6124 * disassociate due to interference / deafness it may persist 6125 * when we reconnect. 6126 * 6127 * Note: may need to do this for other states too, not just 6128 * _S_INIT. 6129 */ 6130 #ifdef IEEE80211_SUPPORT_TDMA 6131 ath_hal_setcca(ah, AH_TRUE); 6132 #endif 6133 } else if (nstate == IEEE80211_S_SLEEP) { 6134 /* We're going to sleep, so transition appropriately */ 6135 /* For now, only do this if we're a single STA vap */ 6136 if (sc->sc_nvaps == 1 && 6137 vap->iv_opmode == IEEE80211_M_STA) { 6138 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: syncbeacon=%d\n", __func__, sc->sc_syncbeacon); 6139 ATH_LOCK(sc); 6140 /* 6141 * Always at least set the self-generated 6142 * frame config to set PWRMGT=1. 6143 */ 6144 ath_power_setselfgen(sc, HAL_PM_NETWORK_SLEEP); 6145 6146 /* 6147 * If we're not syncing beacons, transition 6148 * to NETWORK_SLEEP. 6149 * 6150 * We stay awake if syncbeacon > 0 in case 6151 * we need to listen for some beacons otherwise 6152 * our beacon timer config may be wrong. 6153 */ 6154 if (sc->sc_syncbeacon == 0) { 6155 ath_power_setpower(sc, HAL_PM_NETWORK_SLEEP, 1); 6156 } 6157 ATH_UNLOCK(sc); 6158 } 6159 6160 /* 6161 * Note - the ANI/calibration timer isn't re-enabled during 6162 * network sleep for now. One unfortunate side-effect is that 6163 * the PHY/airtime statistics aren't gathered on the channel 6164 * but I haven't yet tested to see if reading those registers 6165 * CAN occur during network sleep. 6166 * 6167 * This should be revisited in a future commit, even if it's 6168 * just to split out the airtime polling from ANI/calibration. 6169 */ 6170 } else if (nstate == IEEE80211_S_SCAN) { 6171 /* Quiet time handling - ensure we resync */ 6172 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 6173 6174 /* 6175 * If we're in scan mode then startpcureceive() is 6176 * hopefully being called with "reset ANI" for this channel; 6177 * but once we attempt to reassociate we program in the previous 6178 * ANI values and.. not do any calibration until we're running. 6179 * This may mean we stay deaf unless we can associate successfully. 6180 * 6181 * So do kick off the cal timer to get NF/ANI going. 6182 */ 6183 ATH_LOCK(sc); 6184 if (ath_longcalinterval != 0) { 6185 /* start periodic recalibration timer */ 6186 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 6187 } else { 6188 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 6189 "%s: calibration disabled\n", __func__); 6190 } 6191 ATH_UNLOCK(sc); 6192 } 6193 bad: 6194 ieee80211_free_node(ni); 6195 6196 /* 6197 * Restore the power state - either to what it was, or 6198 * to network_sleep if it's alright. 6199 */ 6200 ATH_LOCK(sc); 6201 ath_power_restore_power_state(sc); 6202 ATH_UNLOCK(sc); 6203 return error; 6204 } 6205 6206 /* 6207 * Allocate a key cache slot to the station so we can 6208 * setup a mapping from key index to node. The key cache 6209 * slot is needed for managing antenna state and for 6210 * compression when stations do not use crypto. We do 6211 * it uniliaterally here; if crypto is employed this slot 6212 * will be reassigned. 6213 */ 6214 static void 6215 ath_setup_stationkey(struct ieee80211_node *ni) 6216 { 6217 struct ieee80211vap *vap = ni->ni_vap; 6218 struct ath_softc *sc = vap->iv_ic->ic_softc; 6219 ieee80211_keyix keyix, rxkeyix; 6220 6221 /* XXX should take a locked ref to vap->iv_bss */ 6222 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 6223 /* 6224 * Key cache is full; we'll fall back to doing 6225 * the more expensive lookup in software. Note 6226 * this also means no h/w compression. 6227 */ 6228 /* XXX msg+statistic */ 6229 } else { 6230 /* XXX locking? */ 6231 ni->ni_ucastkey.wk_keyix = keyix; 6232 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 6233 /* NB: must mark device key to get called back on delete */ 6234 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 6235 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 6236 /* NB: this will create a pass-thru key entry */ 6237 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss); 6238 } 6239 } 6240 6241 /* 6242 * Setup driver-specific state for a newly associated node. 6243 * Note that we're called also on a re-associate, the isnew 6244 * param tells us if this is the first time or not. 6245 */ 6246 static void 6247 ath_newassoc(struct ieee80211_node *ni, int isnew) 6248 { 6249 struct ath_node *an = ATH_NODE(ni); 6250 struct ieee80211vap *vap = ni->ni_vap; 6251 struct ath_softc *sc = vap->iv_ic->ic_softc; 6252 const struct ieee80211_txparam *tp = ni->ni_txparms; 6253 6254 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 6255 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 6256 6257 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: reassoc; isnew=%d, is_powersave=%d\n", 6258 __func__, 6259 ni->ni_macaddr, 6260 ":", 6261 isnew, 6262 an->an_is_powersave); 6263 6264 ATH_NODE_LOCK(an); 6265 ath_rate_newassoc(sc, an, isnew); 6266 ATH_NODE_UNLOCK(an); 6267 6268 if (isnew && 6269 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 6270 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 6271 ath_setup_stationkey(ni); 6272 6273 /* 6274 * If we're reassociating, make sure that any paused queues 6275 * get unpaused. 6276 * 6277 * Now, we may have frames in the hardware queue for this node. 6278 * So if we are reassociating and there are frames in the queue, 6279 * we need to go through the cleanup path to ensure that they're 6280 * marked as non-aggregate. 6281 */ 6282 if (! isnew) { 6283 DPRINTF(sc, ATH_DEBUG_NODE, 6284 "%s: %6D: reassoc; is_powersave=%d\n", 6285 __func__, 6286 ni->ni_macaddr, 6287 ":", 6288 an->an_is_powersave); 6289 6290 /* XXX for now, we can't hold the lock across assoc */ 6291 ath_tx_node_reassoc(sc, an); 6292 6293 /* XXX for now, we can't hold the lock across wakeup */ 6294 if (an->an_is_powersave) 6295 ath_tx_node_wakeup(sc, an); 6296 } 6297 } 6298 6299 static int 6300 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 6301 int nchans, struct ieee80211_channel chans[]) 6302 { 6303 struct ath_softc *sc = ic->ic_softc; 6304 struct ath_hal *ah = sc->sc_ah; 6305 HAL_STATUS status; 6306 6307 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 6308 "%s: rd %u cc %u location %c%s\n", 6309 __func__, reg->regdomain, reg->country, reg->location, 6310 reg->ecm ? " ecm" : ""); 6311 6312 status = ath_hal_set_channels(ah, chans, nchans, 6313 reg->country, reg->regdomain); 6314 if (status != HAL_OK) { 6315 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 6316 __func__, status); 6317 return EINVAL; /* XXX */ 6318 } 6319 6320 return 0; 6321 } 6322 6323 static void 6324 ath_getradiocaps(struct ieee80211com *ic, 6325 int maxchans, int *nchans, struct ieee80211_channel chans[]) 6326 { 6327 struct ath_softc *sc = ic->ic_softc; 6328 struct ath_hal *ah = sc->sc_ah; 6329 6330 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 6331 __func__, SKU_DEBUG, CTRY_DEFAULT); 6332 6333 /* XXX check return */ 6334 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 6335 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 6336 6337 } 6338 6339 static int 6340 ath_getchannels(struct ath_softc *sc) 6341 { 6342 struct ieee80211com *ic = &sc->sc_ic; 6343 struct ath_hal *ah = sc->sc_ah; 6344 HAL_STATUS status; 6345 6346 /* 6347 * Collect channel set based on EEPROM contents. 6348 */ 6349 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 6350 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 6351 if (status != HAL_OK) { 6352 device_printf(sc->sc_dev, 6353 "%s: unable to collect channel list from hal, status %d\n", 6354 __func__, status); 6355 return EINVAL; 6356 } 6357 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 6358 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 6359 /* XXX map Atheros sku's to net80211 SKU's */ 6360 /* XXX net80211 types too small */ 6361 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 6362 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 6363 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 6364 ic->ic_regdomain.isocc[1] = ' '; 6365 6366 ic->ic_regdomain.ecm = 1; 6367 ic->ic_regdomain.location = 'I'; 6368 6369 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 6370 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 6371 __func__, sc->sc_eerd, sc->sc_eecc, 6372 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 6373 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 6374 return 0; 6375 } 6376 6377 static int 6378 ath_rate_setup(struct ath_softc *sc, u_int mode) 6379 { 6380 struct ath_hal *ah = sc->sc_ah; 6381 const HAL_RATE_TABLE *rt; 6382 6383 switch (mode) { 6384 case IEEE80211_MODE_11A: 6385 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 6386 break; 6387 case IEEE80211_MODE_HALF: 6388 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 6389 break; 6390 case IEEE80211_MODE_QUARTER: 6391 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 6392 break; 6393 case IEEE80211_MODE_11B: 6394 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 6395 break; 6396 case IEEE80211_MODE_11G: 6397 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 6398 break; 6399 case IEEE80211_MODE_TURBO_A: 6400 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 6401 break; 6402 case IEEE80211_MODE_TURBO_G: 6403 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 6404 break; 6405 case IEEE80211_MODE_STURBO_A: 6406 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 6407 break; 6408 case IEEE80211_MODE_11NA: 6409 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 6410 break; 6411 case IEEE80211_MODE_11NG: 6412 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 6413 break; 6414 default: 6415 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 6416 __func__, mode); 6417 return 0; 6418 } 6419 sc->sc_rates[mode] = rt; 6420 return (rt != NULL); 6421 } 6422 6423 static void 6424 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 6425 { 6426 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 6427 static const struct { 6428 u_int rate; /* tx/rx 802.11 rate */ 6429 u_int16_t timeOn; /* LED on time (ms) */ 6430 u_int16_t timeOff; /* LED off time (ms) */ 6431 } blinkrates[] = { 6432 { 108, 40, 10 }, 6433 { 96, 44, 11 }, 6434 { 72, 50, 13 }, 6435 { 48, 57, 14 }, 6436 { 36, 67, 16 }, 6437 { 24, 80, 20 }, 6438 { 22, 100, 25 }, 6439 { 18, 133, 34 }, 6440 { 12, 160, 40 }, 6441 { 10, 200, 50 }, 6442 { 6, 240, 58 }, 6443 { 4, 267, 66 }, 6444 { 2, 400, 100 }, 6445 { 0, 500, 130 }, 6446 /* XXX half/quarter rates */ 6447 }; 6448 const HAL_RATE_TABLE *rt; 6449 int i, j; 6450 6451 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 6452 rt = sc->sc_rates[mode]; 6453 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 6454 for (i = 0; i < rt->rateCount; i++) { 6455 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6456 if (rt->info[i].phy != IEEE80211_T_HT) 6457 sc->sc_rixmap[ieeerate] = i; 6458 else 6459 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 6460 } 6461 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6462 for (i = 0; i < nitems(sc->sc_hwmap); i++) { 6463 if (i >= rt->rateCount) { 6464 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6465 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6466 continue; 6467 } 6468 sc->sc_hwmap[i].ieeerate = 6469 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6470 if (rt->info[i].phy == IEEE80211_T_HT) 6471 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 6472 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6473 if (rt->info[i].shortPreamble || 6474 rt->info[i].phy == IEEE80211_T_OFDM) 6475 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6476 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 6477 for (j = 0; j < nitems(blinkrates)-1; j++) 6478 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6479 break; 6480 /* NB: this uses the last entry if the rate isn't found */ 6481 /* XXX beware of overlow */ 6482 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6483 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6484 } 6485 sc->sc_currates = rt; 6486 sc->sc_curmode = mode; 6487 /* 6488 * All protection frames are transmitted at 2Mb/s for 6489 * 11g, otherwise at 1Mb/s. 6490 */ 6491 if (mode == IEEE80211_MODE_11G) 6492 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 6493 else 6494 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 6495 /* NB: caller is responsible for resetting rate control state */ 6496 } 6497 6498 static void 6499 ath_watchdog(void *arg) 6500 { 6501 struct ath_softc *sc = arg; 6502 struct ieee80211com *ic = &sc->sc_ic; 6503 int do_reset = 0; 6504 6505 ATH_LOCK_ASSERT(sc); 6506 6507 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 6508 uint32_t hangs; 6509 6510 ath_power_set_power_state(sc, HAL_PM_AWAKE); 6511 6512 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 6513 hangs != 0) { 6514 device_printf(sc->sc_dev, "%s hang detected (0x%x)\n", 6515 hangs & 0xff ? "bb" : "mac", hangs); 6516 } else 6517 device_printf(sc->sc_dev, "device timeout\n"); 6518 do_reset = 1; 6519 counter_u64_add(ic->ic_oerrors, 1); 6520 sc->sc_stats.ast_watchdog++; 6521 6522 ath_power_restore_power_state(sc); 6523 } 6524 6525 /* 6526 * We can't hold the lock across the ath_reset() call. 6527 * 6528 * And since this routine can't hold a lock and sleep, 6529 * do the reset deferred. 6530 */ 6531 if (do_reset) { 6532 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 6533 } 6534 6535 callout_schedule(&sc->sc_wd_ch, hz); 6536 } 6537 6538 static void 6539 ath_parent(struct ieee80211com *ic) 6540 { 6541 struct ath_softc *sc = ic->ic_softc; 6542 int error = EDOOFUS; 6543 6544 ATH_LOCK(sc); 6545 if (ic->ic_nrunning > 0) { 6546 /* 6547 * To avoid rescanning another access point, 6548 * do not call ath_init() here. Instead, 6549 * only reflect promisc mode settings. 6550 */ 6551 if (sc->sc_running) { 6552 ath_power_set_power_state(sc, HAL_PM_AWAKE); 6553 ath_mode_init(sc); 6554 ath_power_restore_power_state(sc); 6555 } else if (!sc->sc_invalid) { 6556 /* 6557 * Beware of being called during attach/detach 6558 * to reset promiscuous mode. In that case we 6559 * will still be marked UP but not RUNNING. 6560 * However trying to re-init the interface 6561 * is the wrong thing to do as we've already 6562 * torn down much of our state. There's 6563 * probably a better way to deal with this. 6564 */ 6565 error = ath_init(sc); 6566 } 6567 } else { 6568 ath_stop(sc); 6569 if (!sc->sc_invalid) 6570 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1); 6571 } 6572 ATH_UNLOCK(sc); 6573 6574 if (error == 0) { 6575 #ifdef ATH_TX99_DIAG 6576 if (sc->sc_tx99 != NULL) 6577 sc->sc_tx99->start(sc->sc_tx99); 6578 else 6579 #endif 6580 ieee80211_start_all(ic); 6581 } 6582 } 6583 6584 /* 6585 * Announce various information on device/driver attach. 6586 */ 6587 static void 6588 ath_announce(struct ath_softc *sc) 6589 { 6590 struct ath_hal *ah = sc->sc_ah; 6591 6592 device_printf(sc->sc_dev, "%s mac %d.%d RF%s phy %d.%d\n", 6593 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 6594 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 6595 device_printf(sc->sc_dev, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n", 6596 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev); 6597 if (bootverbose) { 6598 int i; 6599 for (i = 0; i <= WME_AC_VO; i++) { 6600 struct ath_txq *txq = sc->sc_ac2q[i]; 6601 device_printf(sc->sc_dev, 6602 "Use hw queue %u for %s traffic\n", 6603 txq->axq_qnum, ieee80211_wme_acnames[i]); 6604 } 6605 device_printf(sc->sc_dev, "Use hw queue %u for CAB traffic\n", 6606 sc->sc_cabq->axq_qnum); 6607 device_printf(sc->sc_dev, "Use hw queue %u for beacons\n", 6608 sc->sc_bhalq); 6609 } 6610 if (ath_rxbuf != ATH_RXBUF) 6611 device_printf(sc->sc_dev, "using %u rx buffers\n", ath_rxbuf); 6612 if (ath_txbuf != ATH_TXBUF) 6613 device_printf(sc->sc_dev, "using %u tx buffers\n", ath_txbuf); 6614 if (sc->sc_mcastkey && bootverbose) 6615 device_printf(sc->sc_dev, "using multicast key search\n"); 6616 } 6617 6618 static void 6619 ath_dfs_tasklet(void *p, int npending) 6620 { 6621 struct ath_softc *sc = (struct ath_softc *) p; 6622 struct ieee80211com *ic = &sc->sc_ic; 6623 6624 /* 6625 * If previous processing has found a radar event, 6626 * signal this to the net80211 layer to begin DFS 6627 * processing. 6628 */ 6629 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) { 6630 /* DFS event found, initiate channel change */ 6631 6632 /* 6633 * XXX TODO: immediately disable ACK processing 6634 * on the current channel. This would be done 6635 * by setting AR_DIAG_ACK_DIS (AR5212; may be 6636 * different for others) until we are out of 6637 * CAC. 6638 */ 6639 6640 /* 6641 * XXX doesn't currently tell us whether the event 6642 * XXX was found in the primary or extension 6643 * XXX channel! 6644 */ 6645 IEEE80211_LOCK(ic); 6646 ieee80211_dfs_notify_radar(ic, sc->sc_curchan); 6647 IEEE80211_UNLOCK(ic); 6648 } 6649 } 6650 6651 /* 6652 * Enable/disable power save. This must be called with 6653 * no TX driver locks currently held, so it should only 6654 * be called from the RX path (which doesn't hold any 6655 * TX driver locks.) 6656 */ 6657 static void 6658 ath_node_powersave(struct ieee80211_node *ni, int enable) 6659 { 6660 #ifdef ATH_SW_PSQ 6661 struct ath_node *an = ATH_NODE(ni); 6662 struct ieee80211com *ic = ni->ni_ic; 6663 struct ath_softc *sc = ic->ic_softc; 6664 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6665 6666 /* XXX and no TXQ locks should be held here */ 6667 6668 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n", 6669 __func__, 6670 ni->ni_macaddr, 6671 ":", 6672 !! enable); 6673 6674 /* Suspend or resume software queue handling */ 6675 if (enable) 6676 ath_tx_node_sleep(sc, an); 6677 else 6678 ath_tx_node_wakeup(sc, an); 6679 6680 /* Update net80211 state */ 6681 avp->av_node_ps(ni, enable); 6682 #else 6683 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6684 6685 /* Update net80211 state */ 6686 avp->av_node_ps(ni, enable); 6687 #endif/* ATH_SW_PSQ */ 6688 } 6689 6690 /* 6691 * Notification from net80211 that the powersave queue state has 6692 * changed. 6693 * 6694 * Since the software queue also may have some frames: 6695 * 6696 * + if the node software queue has frames and the TID state 6697 * is 0, we set the TIM; 6698 * + if the node and the stack are both empty, we clear the TIM bit. 6699 * + If the stack tries to set the bit, always set it. 6700 * + If the stack tries to clear the bit, only clear it if the 6701 * software queue in question is also cleared. 6702 * 6703 * TODO: this is called during node teardown; so let's ensure this 6704 * is all correctly handled and that the TIM bit is cleared. 6705 * It may be that the node flush is called _AFTER_ the net80211 6706 * stack clears the TIM. 6707 * 6708 * Here is the racy part. Since it's possible >1 concurrent, 6709 * overlapping TXes will appear complete with a TX completion in 6710 * another thread, it's possible that the concurrent TIM calls will 6711 * clash. We can't hold the node lock here because setting the 6712 * TIM grabs the net80211 comlock and this may cause a LOR. 6713 * The solution is either to totally serialise _everything_ at 6714 * this point (ie, all TX, completion and any reset/flush go into 6715 * one taskqueue) or a new "ath TIM lock" needs to be created that 6716 * just wraps the driver state change and this call to avp->av_set_tim(). 6717 * 6718 * The same race exists in the net80211 power save queue handling 6719 * as well. Since multiple transmitting threads may queue frames 6720 * into the driver, as well as ps-poll and the driver transmitting 6721 * frames (and thus clearing the psq), it's quite possible that 6722 * a packet entering the PSQ and a ps-poll being handled will 6723 * race, causing the TIM to be cleared and not re-set. 6724 */ 6725 static int 6726 ath_node_set_tim(struct ieee80211_node *ni, int enable) 6727 { 6728 #ifdef ATH_SW_PSQ 6729 struct ieee80211com *ic = ni->ni_ic; 6730 struct ath_softc *sc = ic->ic_softc; 6731 struct ath_node *an = ATH_NODE(ni); 6732 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6733 int changed = 0; 6734 6735 ATH_TX_LOCK(sc); 6736 an->an_stack_psq = enable; 6737 6738 /* 6739 * This will get called for all operating modes, 6740 * even if avp->av_set_tim is unset. 6741 * It's currently set for hostap/ibss modes; but 6742 * the same infrastructure is used for both STA 6743 * and AP/IBSS node power save. 6744 */ 6745 if (avp->av_set_tim == NULL) { 6746 ATH_TX_UNLOCK(sc); 6747 return (0); 6748 } 6749 6750 /* 6751 * If setting the bit, always set it here. 6752 * If clearing the bit, only clear it if the 6753 * software queue is also empty. 6754 * 6755 * If the node has left power save, just clear the TIM 6756 * bit regardless of the state of the power save queue. 6757 * 6758 * XXX TODO: although atomics are used, it's quite possible 6759 * that a race will occur between this and setting/clearing 6760 * in another thread. TX completion will occur always in 6761 * one thread, however setting/clearing the TIM bit can come 6762 * from a variety of different process contexts! 6763 */ 6764 if (enable && an->an_tim_set == 1) { 6765 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6766 "%s: %6D: enable=%d, tim_set=1, ignoring\n", 6767 __func__, 6768 ni->ni_macaddr, 6769 ":", 6770 enable); 6771 ATH_TX_UNLOCK(sc); 6772 } else if (enable) { 6773 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6774 "%s: %6D: enable=%d, enabling TIM\n", 6775 __func__, 6776 ni->ni_macaddr, 6777 ":", 6778 enable); 6779 an->an_tim_set = 1; 6780 ATH_TX_UNLOCK(sc); 6781 changed = avp->av_set_tim(ni, enable); 6782 } else if (an->an_swq_depth == 0) { 6783 /* disable */ 6784 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6785 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n", 6786 __func__, 6787 ni->ni_macaddr, 6788 ":", 6789 enable); 6790 an->an_tim_set = 0; 6791 ATH_TX_UNLOCK(sc); 6792 changed = avp->av_set_tim(ni, enable); 6793 } else if (! an->an_is_powersave) { 6794 /* 6795 * disable regardless; the node isn't in powersave now 6796 */ 6797 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6798 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n", 6799 __func__, 6800 ni->ni_macaddr, 6801 ":", 6802 enable); 6803 an->an_tim_set = 0; 6804 ATH_TX_UNLOCK(sc); 6805 changed = avp->av_set_tim(ni, enable); 6806 } else { 6807 /* 6808 * psq disable, node is currently in powersave, node 6809 * software queue isn't empty, so don't clear the TIM bit 6810 * for now. 6811 */ 6812 ATH_TX_UNLOCK(sc); 6813 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6814 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n", 6815 __func__, 6816 ni->ni_macaddr, 6817 ":", 6818 enable); 6819 changed = 0; 6820 } 6821 6822 return (changed); 6823 #else 6824 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6825 6826 /* 6827 * Some operating modes don't set av_set_tim(), so don't 6828 * update it here. 6829 */ 6830 if (avp->av_set_tim == NULL) 6831 return (0); 6832 6833 return (avp->av_set_tim(ni, enable)); 6834 #endif /* ATH_SW_PSQ */ 6835 } 6836 6837 /* 6838 * Set or update the TIM from the software queue. 6839 * 6840 * Check the software queue depth before attempting to do lock 6841 * anything; that avoids trying to obtain the lock. Then, 6842 * re-check afterwards to ensure nothing has changed in the 6843 * meantime. 6844 * 6845 * set: This is designed to be called from the TX path, after 6846 * a frame has been queued; to see if the swq > 0. 6847 * 6848 * clear: This is designed to be called from the buffer completion point 6849 * (right now it's ath_tx_default_comp()) where the state of 6850 * a software queue has changed. 6851 * 6852 * It makes sense to place it at buffer free / completion rather 6853 * than after each software queue operation, as there's no real 6854 * point in churning the TIM bit as the last frames in the software 6855 * queue are transmitted. If they fail and we retry them, we'd 6856 * just be setting the TIM bit again anyway. 6857 */ 6858 void 6859 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni, 6860 int enable) 6861 { 6862 #ifdef ATH_SW_PSQ 6863 struct ath_node *an; 6864 struct ath_vap *avp; 6865 6866 /* Don't do this for broadcast/etc frames */ 6867 if (ni == NULL) 6868 return; 6869 6870 an = ATH_NODE(ni); 6871 avp = ATH_VAP(ni->ni_vap); 6872 6873 /* 6874 * And for operating modes without the TIM handler set, let's 6875 * just skip those. 6876 */ 6877 if (avp->av_set_tim == NULL) 6878 return; 6879 6880 ATH_TX_LOCK_ASSERT(sc); 6881 6882 if (enable) { 6883 if (an->an_is_powersave && 6884 an->an_tim_set == 0 && 6885 an->an_swq_depth != 0) { 6886 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6887 "%s: %6D: swq_depth>0, tim_set=0, set!\n", 6888 __func__, 6889 ni->ni_macaddr, 6890 ":"); 6891 an->an_tim_set = 1; 6892 (void) avp->av_set_tim(ni, 1); 6893 } 6894 } else { 6895 /* 6896 * Don't bother grabbing the lock unless the queue is empty. 6897 */ 6898 if (an->an_swq_depth != 0) 6899 return; 6900 6901 if (an->an_is_powersave && 6902 an->an_stack_psq == 0 && 6903 an->an_tim_set == 1 && 6904 an->an_swq_depth == 0) { 6905 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6906 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0," 6907 " clear!\n", 6908 __func__, 6909 ni->ni_macaddr, 6910 ":"); 6911 an->an_tim_set = 0; 6912 (void) avp->av_set_tim(ni, 0); 6913 } 6914 } 6915 #else 6916 return; 6917 #endif /* ATH_SW_PSQ */ 6918 } 6919 6920 /* 6921 * Received a ps-poll frame from net80211. 6922 * 6923 * Here we get a chance to serve out a software-queued frame ourselves 6924 * before we punt it to net80211 to transmit us one itself - either 6925 * because there's traffic in the net80211 psq, or a NULL frame to 6926 * indicate there's nothing else. 6927 */ 6928 static void 6929 ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m) 6930 { 6931 #ifdef ATH_SW_PSQ 6932 struct ath_node *an; 6933 struct ath_vap *avp; 6934 struct ieee80211com *ic = ni->ni_ic; 6935 struct ath_softc *sc = ic->ic_softc; 6936 int tid; 6937 6938 /* Just paranoia */ 6939 if (ni == NULL) 6940 return; 6941 6942 /* 6943 * Unassociated (temporary node) station. 6944 */ 6945 if (ni->ni_associd == 0) 6946 return; 6947 6948 /* 6949 * We do have an active node, so let's begin looking into it. 6950 */ 6951 an = ATH_NODE(ni); 6952 avp = ATH_VAP(ni->ni_vap); 6953 6954 /* 6955 * For now, we just call the original ps-poll method. 6956 * Once we're ready to flip this on: 6957 * 6958 * + Set leak to 1, as no matter what we're going to have 6959 * to send a frame; 6960 * + Check the software queue and if there's something in it, 6961 * schedule the highest TID thas has traffic from this node. 6962 * Then make sure we schedule the software scheduler to 6963 * run so it picks up said frame. 6964 * 6965 * That way whatever happens, we'll at least send _a_ frame 6966 * to the given node. 6967 * 6968 * Again, yes, it's crappy QoS if the node has multiple 6969 * TIDs worth of traffic - but let's get it working first 6970 * before we optimise it. 6971 * 6972 * Also yes, there's definitely latency here - we're not 6973 * direct dispatching to the hardware in this path (and 6974 * we're likely being called from the packet receive path, 6975 * so going back into TX may be a little hairy!) but again 6976 * I'd like to get this working first before optimising 6977 * turn-around time. 6978 */ 6979 6980 ATH_TX_LOCK(sc); 6981 6982 /* 6983 * Legacy - we're called and the node isn't asleep. 6984 * Immediately punt. 6985 */ 6986 if (! an->an_is_powersave) { 6987 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6988 "%s: %6D: not in powersave?\n", 6989 __func__, 6990 ni->ni_macaddr, 6991 ":"); 6992 ATH_TX_UNLOCK(sc); 6993 avp->av_recv_pspoll(ni, m); 6994 return; 6995 } 6996 6997 /* 6998 * We're in powersave. 6999 * 7000 * Leak a frame. 7001 */ 7002 an->an_leak_count = 1; 7003 7004 /* 7005 * Now, if there's no frames in the node, just punt to 7006 * recv_pspoll. 7007 * 7008 * Don't bother checking if the TIM bit is set, we really 7009 * only care if there are any frames here! 7010 */ 7011 if (an->an_swq_depth == 0) { 7012 ATH_TX_UNLOCK(sc); 7013 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 7014 "%s: %6D: SWQ empty; punting to net80211\n", 7015 __func__, 7016 ni->ni_macaddr, 7017 ":"); 7018 avp->av_recv_pspoll(ni, m); 7019 return; 7020 } 7021 7022 /* 7023 * Ok, let's schedule the highest TID that has traffic 7024 * and then schedule something. 7025 */ 7026 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) { 7027 struct ath_tid *atid = &an->an_tid[tid]; 7028 /* 7029 * No frames? Skip. 7030 */ 7031 if (atid->axq_depth == 0) 7032 continue; 7033 ath_tx_tid_sched(sc, atid); 7034 /* 7035 * XXX we could do a direct call to the TXQ 7036 * scheduler code here to optimise latency 7037 * at the expense of a REALLY deep callstack. 7038 */ 7039 ATH_TX_UNLOCK(sc); 7040 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 7041 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 7042 "%s: %6D: leaking frame to TID %d\n", 7043 __func__, 7044 ni->ni_macaddr, 7045 ":", 7046 tid); 7047 return; 7048 } 7049 7050 ATH_TX_UNLOCK(sc); 7051 7052 /* 7053 * XXX nothing in the TIDs at this point? Eek. 7054 */ 7055 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 7056 "%s: %6D: TIDs empty, but ath_node showed traffic?!\n", 7057 __func__, 7058 ni->ni_macaddr, 7059 ":"); 7060 avp->av_recv_pspoll(ni, m); 7061 #else 7062 avp->av_recv_pspoll(ni, m); 7063 #endif /* ATH_SW_PSQ */ 7064 } 7065 7066 MODULE_VERSION(ath_main, 1); 7067 MODULE_DEPEND(ath_main, wlan, 1, 1, 1); /* 802.11 media layer */ 7068 MODULE_DEPEND(ath_main, ath_rate, 1, 1, 1); 7069 MODULE_DEPEND(ath_main, ath_dfs, 1, 1, 1); 7070 MODULE_DEPEND(ath_main, ath_hal, 1, 1, 1); 7071 #if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) || defined(ATH_DEBUG_ALQ) 7072 MODULE_DEPEND(ath_main, alq, 1, 1, 1); 7073 #endif 7074