1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_regdomain.h> 85 #ifdef IEEE80211_SUPPORT_SUPERG 86 #include <net80211/ieee80211_superg.h> 87 #endif 88 #ifdef IEEE80211_SUPPORT_TDMA 89 #include <net80211/ieee80211_tdma.h> 90 #endif 91 92 #include <net/bpf.h> 93 94 #ifdef INET 95 #include <netinet/in.h> 96 #include <netinet/if_ether.h> 97 #endif 98 99 #include <dev/ath/if_athvar.h> 100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101 #include <dev/ath/ath_hal/ah_diagcodes.h> 102 103 #include <dev/ath/if_ath_debug.h> 104 #include <dev/ath/if_ath_misc.h> 105 #include <dev/ath/if_ath_tsf.h> 106 #include <dev/ath/if_ath_tx.h> 107 #include <dev/ath/if_ath_sysctl.h> 108 #include <dev/ath/if_ath_led.h> 109 #include <dev/ath/if_ath_keycache.h> 110 #include <dev/ath/if_ath_rx.h> 111 #include <dev/ath/if_ath_rx_edma.h> 112 #include <dev/ath/if_ath_tx_edma.h> 113 #include <dev/ath/if_ath_beacon.h> 114 #include <dev/ath/if_athdfs.h> 115 116 #ifdef ATH_TX99_DIAG 117 #include <dev/ath/ath_tx99/ath_tx99.h> 118 #endif 119 120 #ifdef ATH_DEBUG_ALQ 121 #include <dev/ath/if_ath_alq.h> 122 #endif 123 124 /* 125 * Only enable this if you're working on PS-POLL support. 126 */ 127 #undef ATH_SW_PSQ 128 129 /* 130 * ATH_BCBUF determines the number of vap's that can transmit 131 * beacons and also (currently) the number of vap's that can 132 * have unique mac addresses/bssid. When staggering beacons 133 * 4 is probably a good max as otherwise the beacons become 134 * very closely spaced and there is limited time for cab q traffic 135 * to go out. You can burst beacons instead but that is not good 136 * for stations in power save and at some point you really want 137 * another radio (and channel). 138 * 139 * The limit on the number of mac addresses is tied to our use of 140 * the U/L bit and tracking addresses in a byte; it would be 141 * worthwhile to allow more for applications like proxy sta. 142 */ 143 CTASSERT(ATH_BCBUF <= 8); 144 145 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 146 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 147 const uint8_t [IEEE80211_ADDR_LEN], 148 const uint8_t [IEEE80211_ADDR_LEN]); 149 static void ath_vap_delete(struct ieee80211vap *); 150 static void ath_init(void *); 151 static void ath_stop_locked(struct ifnet *); 152 static void ath_stop(struct ifnet *); 153 static int ath_reset_vap(struct ieee80211vap *, u_long); 154 static void ath_start_queue(struct ifnet *ifp); 155 static int ath_media_change(struct ifnet *); 156 static void ath_watchdog(void *); 157 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 158 static void ath_fatal_proc(void *, int); 159 static void ath_bmiss_vap(struct ieee80211vap *); 160 static void ath_bmiss_proc(void *, int); 161 static void ath_key_update_begin(struct ieee80211vap *); 162 static void ath_key_update_end(struct ieee80211vap *); 163 static void ath_update_mcast(struct ifnet *); 164 static void ath_update_promisc(struct ifnet *); 165 static void ath_updateslot(struct ifnet *); 166 static void ath_bstuck_proc(void *, int); 167 static void ath_reset_proc(void *, int); 168 static int ath_desc_alloc(struct ath_softc *); 169 static void ath_desc_free(struct ath_softc *); 170 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 171 const uint8_t [IEEE80211_ADDR_LEN]); 172 static void ath_node_cleanup(struct ieee80211_node *); 173 static void ath_node_free(struct ieee80211_node *); 174 static void ath_node_getsignal(const struct ieee80211_node *, 175 int8_t *, int8_t *); 176 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 177 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 178 static int ath_tx_setup(struct ath_softc *, int, int); 179 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 180 static void ath_tx_cleanup(struct ath_softc *); 181 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, 182 int dosched); 183 static void ath_tx_proc_q0(void *, int); 184 static void ath_tx_proc_q0123(void *, int); 185 static void ath_tx_proc(void *, int); 186 static void ath_txq_sched_tasklet(void *, int); 187 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 188 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 189 static void ath_scan_start(struct ieee80211com *); 190 static void ath_scan_end(struct ieee80211com *); 191 static void ath_set_channel(struct ieee80211com *); 192 #ifdef ATH_ENABLE_11N 193 static void ath_update_chw(struct ieee80211com *); 194 #endif /* ATH_ENABLE_11N */ 195 static void ath_calibrate(void *); 196 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 197 static void ath_setup_stationkey(struct ieee80211_node *); 198 static void ath_newassoc(struct ieee80211_node *, int); 199 static int ath_setregdomain(struct ieee80211com *, 200 struct ieee80211_regdomain *, int, 201 struct ieee80211_channel []); 202 static void ath_getradiocaps(struct ieee80211com *, int, int *, 203 struct ieee80211_channel []); 204 static int ath_getchannels(struct ath_softc *); 205 206 static int ath_rate_setup(struct ath_softc *, u_int mode); 207 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 208 209 static void ath_announce(struct ath_softc *); 210 211 static void ath_dfs_tasklet(void *, int); 212 static void ath_node_powersave(struct ieee80211_node *, int); 213 static int ath_node_set_tim(struct ieee80211_node *, int); 214 215 #ifdef IEEE80211_SUPPORT_TDMA 216 #include <dev/ath/if_ath_tdma.h> 217 #endif 218 219 SYSCTL_DECL(_hw_ath); 220 221 /* XXX validate sysctl values */ 222 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 223 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 224 0, "long chip calibration interval (secs)"); 225 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 226 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 227 0, "short chip calibration interval (msecs)"); 228 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 229 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 230 0, "reset chip calibration results (secs)"); 231 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */ 232 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval, 233 0, "ANI calibration (msecs)"); 234 235 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 236 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 237 0, "rx buffers allocated"); 238 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 239 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 240 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 241 0, "tx buffers allocated"); 242 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 243 int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */ 244 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RW, &ath_txbuf_mgmt, 245 0, "tx (mgmt) buffers allocated"); 246 TUNABLE_INT("hw.ath.txbuf_mgmt", &ath_txbuf_mgmt); 247 248 int ath_bstuck_threshold = 4; /* max missed beacons */ 249 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 250 0, "max missed beacon xmits before chip reset"); 251 252 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 253 254 void 255 ath_legacy_attach_comp_func(struct ath_softc *sc) 256 { 257 258 /* 259 * Special case certain configurations. Note the 260 * CAB queue is handled by these specially so don't 261 * include them when checking the txq setup mask. 262 */ 263 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 264 case 0x01: 265 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 266 break; 267 case 0x0f: 268 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 269 break; 270 default: 271 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 272 break; 273 } 274 } 275 276 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20) 277 #define HAL_MODE_HT40 \ 278 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \ 279 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS) 280 int 281 ath_attach(u_int16_t devid, struct ath_softc *sc) 282 { 283 struct ifnet *ifp; 284 struct ieee80211com *ic; 285 struct ath_hal *ah = NULL; 286 HAL_STATUS status; 287 int error = 0, i; 288 u_int wmodes; 289 uint8_t macaddr[IEEE80211_ADDR_LEN]; 290 int rx_chainmask, tx_chainmask; 291 292 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 293 294 CURVNET_SET(vnet0); 295 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 296 if (ifp == NULL) { 297 device_printf(sc->sc_dev, "can not if_alloc()\n"); 298 error = ENOSPC; 299 CURVNET_RESTORE(); 300 goto bad; 301 } 302 ic = ifp->if_l2com; 303 304 /* set these up early for if_printf use */ 305 if_initname(ifp, device_get_name(sc->sc_dev), 306 device_get_unit(sc->sc_dev)); 307 CURVNET_RESTORE(); 308 309 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, 310 sc->sc_eepromdata, &status); 311 if (ah == NULL) { 312 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 313 status); 314 error = ENXIO; 315 goto bad; 316 } 317 sc->sc_ah = ah; 318 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 319 #ifdef ATH_DEBUG 320 sc->sc_debug = ath_debug; 321 #endif 322 323 /* 324 * Setup the DMA/EDMA functions based on the current 325 * hardware support. 326 * 327 * This is required before the descriptors are allocated. 328 */ 329 if (ath_hal_hasedma(sc->sc_ah)) { 330 sc->sc_isedma = 1; 331 ath_recv_setup_edma(sc); 332 ath_xmit_setup_edma(sc); 333 } else { 334 ath_recv_setup_legacy(sc); 335 ath_xmit_setup_legacy(sc); 336 } 337 338 /* 339 * Check if the MAC has multi-rate retry support. 340 * We do this by trying to setup a fake extended 341 * descriptor. MAC's that don't have support will 342 * return false w/o doing anything. MAC's that do 343 * support it will return true w/o doing anything. 344 */ 345 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 346 347 /* 348 * Check if the device has hardware counters for PHY 349 * errors. If so we need to enable the MIB interrupt 350 * so we can act on stat triggers. 351 */ 352 if (ath_hal_hwphycounters(ah)) 353 sc->sc_needmib = 1; 354 355 /* 356 * Get the hardware key cache size. 357 */ 358 sc->sc_keymax = ath_hal_keycachesize(ah); 359 if (sc->sc_keymax > ATH_KEYMAX) { 360 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 361 ATH_KEYMAX, sc->sc_keymax); 362 sc->sc_keymax = ATH_KEYMAX; 363 } 364 /* 365 * Reset the key cache since some parts do not 366 * reset the contents on initial power up. 367 */ 368 for (i = 0; i < sc->sc_keymax; i++) 369 ath_hal_keyreset(ah, i); 370 371 /* 372 * Collect the default channel list. 373 */ 374 error = ath_getchannels(sc); 375 if (error != 0) 376 goto bad; 377 378 /* 379 * Setup rate tables for all potential media types. 380 */ 381 ath_rate_setup(sc, IEEE80211_MODE_11A); 382 ath_rate_setup(sc, IEEE80211_MODE_11B); 383 ath_rate_setup(sc, IEEE80211_MODE_11G); 384 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 385 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 386 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 387 ath_rate_setup(sc, IEEE80211_MODE_11NA); 388 ath_rate_setup(sc, IEEE80211_MODE_11NG); 389 ath_rate_setup(sc, IEEE80211_MODE_HALF); 390 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 391 392 /* NB: setup here so ath_rate_update is happy */ 393 ath_setcurmode(sc, IEEE80211_MODE_11A); 394 395 /* 396 * Allocate TX descriptors and populate the lists. 397 */ 398 error = ath_desc_alloc(sc); 399 if (error != 0) { 400 if_printf(ifp, "failed to allocate TX descriptors: %d\n", 401 error); 402 goto bad; 403 } 404 error = ath_txdma_setup(sc); 405 if (error != 0) { 406 if_printf(ifp, "failed to allocate TX descriptors: %d\n", 407 error); 408 goto bad; 409 } 410 411 /* 412 * Allocate RX descriptors and populate the lists. 413 */ 414 error = ath_rxdma_setup(sc); 415 if (error != 0) { 416 if_printf(ifp, "failed to allocate RX descriptors: %d\n", 417 error); 418 goto bad; 419 } 420 421 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 422 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 423 424 ATH_TXBUF_LOCK_INIT(sc); 425 426 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 427 taskqueue_thread_enqueue, &sc->sc_tq); 428 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 429 "%s taskq", ifp->if_xname); 430 431 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc); 432 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 433 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 434 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc); 435 TASK_INIT(&sc->sc_txqtask,0, ath_txq_sched_tasklet, sc); 436 TASK_INIT(&sc->sc_fataltask,0, ath_fatal_proc, sc); 437 438 /* 439 * Allocate hardware transmit queues: one queue for 440 * beacon frames and one data queue for each QoS 441 * priority. Note that the hal handles resetting 442 * these queues at the needed time. 443 * 444 * XXX PS-Poll 445 */ 446 sc->sc_bhalq = ath_beaconq_setup(sc); 447 if (sc->sc_bhalq == (u_int) -1) { 448 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 449 error = EIO; 450 goto bad2; 451 } 452 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 453 if (sc->sc_cabq == NULL) { 454 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 455 error = EIO; 456 goto bad2; 457 } 458 /* NB: insure BK queue is the lowest priority h/w queue */ 459 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 460 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 461 ieee80211_wme_acnames[WME_AC_BK]); 462 error = EIO; 463 goto bad2; 464 } 465 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 466 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 467 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 468 /* 469 * Not enough hardware tx queues to properly do WME; 470 * just punt and assign them all to the same h/w queue. 471 * We could do a better job of this if, for example, 472 * we allocate queues when we switch from station to 473 * AP mode. 474 */ 475 if (sc->sc_ac2q[WME_AC_VI] != NULL) 476 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 477 if (sc->sc_ac2q[WME_AC_BE] != NULL) 478 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 479 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 480 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 481 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 482 } 483 484 /* 485 * Attach the TX completion function. 486 * 487 * The non-EDMA chips may have some special case optimisations; 488 * this method gives everyone a chance to attach cleanly. 489 */ 490 sc->sc_tx.xmit_attach_comp_func(sc); 491 492 /* 493 * Setup rate control. Some rate control modules 494 * call back to change the anntena state so expose 495 * the necessary entry points. 496 * XXX maybe belongs in struct ath_ratectrl? 497 */ 498 sc->sc_setdefantenna = ath_setdefantenna; 499 sc->sc_rc = ath_rate_attach(sc); 500 if (sc->sc_rc == NULL) { 501 error = EIO; 502 goto bad2; 503 } 504 505 /* Attach DFS module */ 506 if (! ath_dfs_attach(sc)) { 507 device_printf(sc->sc_dev, 508 "%s: unable to attach DFS\n", __func__); 509 error = EIO; 510 goto bad2; 511 } 512 513 /* Start DFS processing tasklet */ 514 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc); 515 516 /* Configure LED state */ 517 sc->sc_blinking = 0; 518 sc->sc_ledstate = 1; 519 sc->sc_ledon = 0; /* low true */ 520 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 521 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 522 523 /* 524 * Don't setup hardware-based blinking. 525 * 526 * Although some NICs may have this configured in the 527 * default reset register values, the user may wish 528 * to alter which pins have which function. 529 * 530 * The reference driver attaches the MAC network LED to GPIO1 and 531 * the MAC power LED to GPIO2. However, the DWA-552 cardbus 532 * NIC has these reversed. 533 */ 534 sc->sc_hardled = (1 == 0); 535 sc->sc_led_net_pin = -1; 536 sc->sc_led_pwr_pin = -1; 537 /* 538 * Auto-enable soft led processing for IBM cards and for 539 * 5211 minipci cards. Users can also manually enable/disable 540 * support with a sysctl. 541 */ 542 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 543 ath_led_config(sc); 544 ath_hal_setledstate(ah, HAL_LED_INIT); 545 546 ifp->if_softc = sc; 547 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 548 ifp->if_start = ath_start_queue; 549 ifp->if_ioctl = ath_ioctl; 550 ifp->if_init = ath_init; 551 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 552 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 553 IFQ_SET_READY(&ifp->if_snd); 554 555 ic->ic_ifp = ifp; 556 /* XXX not right but it's not used anywhere important */ 557 ic->ic_phytype = IEEE80211_T_OFDM; 558 ic->ic_opmode = IEEE80211_M_STA; 559 ic->ic_caps = 560 IEEE80211_C_STA /* station mode */ 561 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 562 | IEEE80211_C_HOSTAP /* hostap mode */ 563 | IEEE80211_C_MONITOR /* monitor mode */ 564 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 565 | IEEE80211_C_WDS /* 4-address traffic works */ 566 | IEEE80211_C_MBSS /* mesh point link mode */ 567 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 568 | IEEE80211_C_SHSLOT /* short slot time supported */ 569 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 570 #ifndef ATH_ENABLE_11N 571 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 572 #endif 573 | IEEE80211_C_TXFRAG /* handle tx frags */ 574 #ifdef ATH_ENABLE_DFS 575 | IEEE80211_C_DFS /* Enable radar detection */ 576 #endif 577 ; 578 /* 579 * Query the hal to figure out h/w crypto support. 580 */ 581 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 582 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 583 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 584 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 585 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 586 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 587 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 588 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 589 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 590 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 591 /* 592 * Check if h/w does the MIC and/or whether the 593 * separate key cache entries are required to 594 * handle both tx+rx MIC keys. 595 */ 596 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 597 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 598 /* 599 * If the h/w supports storing tx+rx MIC keys 600 * in one cache slot automatically enable use. 601 */ 602 if (ath_hal_hastkipsplit(ah) || 603 !ath_hal_settkipsplit(ah, AH_FALSE)) 604 sc->sc_splitmic = 1; 605 /* 606 * If the h/w can do TKIP MIC together with WME then 607 * we use it; otherwise we force the MIC to be done 608 * in software by the net80211 layer. 609 */ 610 if (ath_hal_haswmetkipmic(ah)) 611 sc->sc_wmetkipmic = 1; 612 } 613 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 614 /* 615 * Check for multicast key search support. 616 */ 617 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 618 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 619 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 620 } 621 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 622 /* 623 * Mark key cache slots associated with global keys 624 * as in use. If we knew TKIP was not to be used we 625 * could leave the +32, +64, and +32+64 slots free. 626 */ 627 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 628 setbit(sc->sc_keymap, i); 629 setbit(sc->sc_keymap, i+64); 630 if (sc->sc_splitmic) { 631 setbit(sc->sc_keymap, i+32); 632 setbit(sc->sc_keymap, i+32+64); 633 } 634 } 635 /* 636 * TPC support can be done either with a global cap or 637 * per-packet support. The latter is not available on 638 * all parts. We're a bit pedantic here as all parts 639 * support a global cap. 640 */ 641 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 642 ic->ic_caps |= IEEE80211_C_TXPMGT; 643 644 /* 645 * Mark WME capability only if we have sufficient 646 * hardware queues to do proper priority scheduling. 647 */ 648 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 649 ic->ic_caps |= IEEE80211_C_WME; 650 /* 651 * Check for misc other capabilities. 652 */ 653 if (ath_hal_hasbursting(ah)) 654 ic->ic_caps |= IEEE80211_C_BURST; 655 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 656 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 657 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 658 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah); 659 sc->sc_rxtsf32 = ath_hal_has_long_rxdesc_tsf(ah); 660 if (ath_hal_hasfastframes(ah)) 661 ic->ic_caps |= IEEE80211_C_FF; 662 wmodes = ath_hal_getwirelessmodes(ah); 663 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 664 ic->ic_caps |= IEEE80211_C_TURBOP; 665 #ifdef IEEE80211_SUPPORT_TDMA 666 if (ath_hal_macversion(ah) > 0x78) { 667 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 668 ic->ic_tdma_update = ath_tdma_update; 669 } 670 #endif 671 672 /* 673 * TODO: enforce that at least this many frames are available 674 * in the txbuf list before allowing data frames (raw or 675 * otherwise) to be transmitted. 676 */ 677 sc->sc_txq_data_minfree = 10; 678 /* 679 * Leave this as default to maintain legacy behaviour. 680 * Shortening the cabq/mcastq may end up causing some 681 * undesirable behaviour. 682 */ 683 sc->sc_txq_mcastq_maxdepth = ath_txbuf; 684 685 /* 686 * Allow the TX and RX chainmasks to be overridden by 687 * environment variables and/or device.hints. 688 * 689 * This must be done early - before the hardware is 690 * calibrated or before the 802.11n stream calculation 691 * is done. 692 */ 693 if (resource_int_value(device_get_name(sc->sc_dev), 694 device_get_unit(sc->sc_dev), "rx_chainmask", 695 &rx_chainmask) == 0) { 696 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n", 697 rx_chainmask); 698 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask); 699 } 700 if (resource_int_value(device_get_name(sc->sc_dev), 701 device_get_unit(sc->sc_dev), "tx_chainmask", 702 &tx_chainmask) == 0) { 703 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n", 704 tx_chainmask); 705 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask); 706 } 707 708 /* 709 * Disable MRR with protected frames by default. 710 * Only 802.11n series NICs can handle this. 711 */ 712 sc->sc_mrrprot = 0; /* XXX should be a capability */ 713 714 /* 715 * Query the enterprise mode information the HAL. 716 */ 717 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0, 718 &sc->sc_ent_cfg) == HAL_OK) 719 sc->sc_use_ent = 1; 720 721 #ifdef ATH_ENABLE_11N 722 /* 723 * Query HT capabilities 724 */ 725 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK && 726 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) { 727 int rxs, txs; 728 729 device_printf(sc->sc_dev, "[HT] enabling HT modes\n"); 730 731 sc->sc_mrrprot = 1; /* XXX should be a capability */ 732 733 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */ 734 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */ 735 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */ 736 | IEEE80211_HTCAP_MAXAMSDU_3839 737 /* max A-MSDU length */ 738 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */ 739 ; 740 741 /* 742 * Enable short-GI for HT20 only if the hardware 743 * advertises support. 744 * Notably, anything earlier than the AR9287 doesn't. 745 */ 746 if ((ath_hal_getcapability(ah, 747 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) && 748 (wmodes & HAL_MODE_HT20)) { 749 device_printf(sc->sc_dev, 750 "[HT] enabling short-GI in 20MHz mode\n"); 751 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20; 752 } 753 754 if (wmodes & HAL_MODE_HT40) 755 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40 756 | IEEE80211_HTCAP_SHORTGI40; 757 758 /* 759 * TX/RX streams need to be taken into account when 760 * negotiating which MCS rates it'll receive and 761 * what MCS rates are available for TX. 762 */ 763 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs); 764 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs); 765 766 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask); 767 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask); 768 769 ic->ic_txstream = txs; 770 ic->ic_rxstream = rxs; 771 772 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1, 773 &sc->sc_rts_aggr_limit); 774 if (sc->sc_rts_aggr_limit != (64 * 1024)) 775 device_printf(sc->sc_dev, 776 "[HT] RTS aggregates limited to %d KiB\n", 777 sc->sc_rts_aggr_limit / 1024); 778 779 device_printf(sc->sc_dev, 780 "[HT] %d RX streams; %d TX streams\n", rxs, txs); 781 } 782 #endif 783 784 /* 785 * Initial aggregation settings. 786 */ 787 sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH; 788 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW; 789 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH; 790 791 /* 792 * Check if the hardware requires PCI register serialisation. 793 * Some of the Owl based MACs require this. 794 */ 795 if (mp_ncpus > 1 && 796 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR, 797 0, NULL) == HAL_OK) { 798 sc->sc_ah->ah_config.ah_serialise_reg_war = 1; 799 device_printf(sc->sc_dev, 800 "Enabling register serialisation\n"); 801 } 802 803 /* 804 * Indicate we need the 802.11 header padded to a 805 * 32-bit boundary for 4-address and QoS frames. 806 */ 807 ic->ic_flags |= IEEE80211_F_DATAPAD; 808 809 /* 810 * Query the hal about antenna support. 811 */ 812 sc->sc_defant = ath_hal_getdefantenna(ah); 813 814 /* 815 * Not all chips have the VEOL support we want to 816 * use with IBSS beacons; check here for it. 817 */ 818 sc->sc_hasveol = ath_hal_hasveol(ah); 819 820 /* get mac address from hardware */ 821 ath_hal_getmac(ah, macaddr); 822 if (sc->sc_hasbmask) 823 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 824 825 /* NB: used to size node table key mapping array */ 826 ic->ic_max_keyix = sc->sc_keymax; 827 /* call MI attach routine. */ 828 ieee80211_ifattach(ic, macaddr); 829 ic->ic_setregdomain = ath_setregdomain; 830 ic->ic_getradiocaps = ath_getradiocaps; 831 sc->sc_opmode = HAL_M_STA; 832 833 /* override default methods */ 834 ic->ic_newassoc = ath_newassoc; 835 ic->ic_updateslot = ath_updateslot; 836 ic->ic_wme.wme_update = ath_wme_update; 837 ic->ic_vap_create = ath_vap_create; 838 ic->ic_vap_delete = ath_vap_delete; 839 ic->ic_raw_xmit = ath_raw_xmit; 840 ic->ic_update_mcast = ath_update_mcast; 841 ic->ic_update_promisc = ath_update_promisc; 842 ic->ic_node_alloc = ath_node_alloc; 843 sc->sc_node_free = ic->ic_node_free; 844 ic->ic_node_free = ath_node_free; 845 sc->sc_node_cleanup = ic->ic_node_cleanup; 846 ic->ic_node_cleanup = ath_node_cleanup; 847 ic->ic_node_getsignal = ath_node_getsignal; 848 ic->ic_scan_start = ath_scan_start; 849 ic->ic_scan_end = ath_scan_end; 850 ic->ic_set_channel = ath_set_channel; 851 #ifdef ATH_ENABLE_11N 852 /* 802.11n specific - but just override anyway */ 853 sc->sc_addba_request = ic->ic_addba_request; 854 sc->sc_addba_response = ic->ic_addba_response; 855 sc->sc_addba_stop = ic->ic_addba_stop; 856 sc->sc_bar_response = ic->ic_bar_response; 857 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout; 858 859 ic->ic_addba_request = ath_addba_request; 860 ic->ic_addba_response = ath_addba_response; 861 ic->ic_addba_response_timeout = ath_addba_response_timeout; 862 ic->ic_addba_stop = ath_addba_stop; 863 ic->ic_bar_response = ath_bar_response; 864 865 ic->ic_update_chw = ath_update_chw; 866 #endif /* ATH_ENABLE_11N */ 867 868 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 869 /* 870 * There's one vendor bitmap entry in the RX radiotap 871 * header; make sure that's taken into account. 872 */ 873 ieee80211_radiotap_attachv(ic, 874 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0, 875 ATH_TX_RADIOTAP_PRESENT, 876 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1, 877 ATH_RX_RADIOTAP_PRESENT); 878 #else 879 /* 880 * No vendor bitmap/extensions are present. 881 */ 882 ieee80211_radiotap_attach(ic, 883 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 884 ATH_TX_RADIOTAP_PRESENT, 885 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 886 ATH_RX_RADIOTAP_PRESENT); 887 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 888 889 /* 890 * Setup the ALQ logging if required 891 */ 892 #ifdef ATH_DEBUG_ALQ 893 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev)); 894 if_ath_alq_setcfg(&sc->sc_alq, 895 sc->sc_ah->ah_macVersion, 896 sc->sc_ah->ah_macRev, 897 sc->sc_ah->ah_phyRev, 898 sc->sc_ah->ah_magic); 899 #endif 900 901 /* 902 * Setup dynamic sysctl's now that country code and 903 * regdomain are available from the hal. 904 */ 905 ath_sysctlattach(sc); 906 ath_sysctl_stats_attach(sc); 907 ath_sysctl_hal_attach(sc); 908 909 if (bootverbose) 910 ieee80211_announce(ic); 911 ath_announce(sc); 912 return 0; 913 bad2: 914 ath_tx_cleanup(sc); 915 ath_desc_free(sc); 916 ath_txdma_teardown(sc); 917 ath_rxdma_teardown(sc); 918 bad: 919 if (ah) 920 ath_hal_detach(ah); 921 if (ifp != NULL) { 922 CURVNET_SET(ifp->if_vnet); 923 if_free(ifp); 924 CURVNET_RESTORE(); 925 } 926 sc->sc_invalid = 1; 927 return error; 928 } 929 930 int 931 ath_detach(struct ath_softc *sc) 932 { 933 struct ifnet *ifp = sc->sc_ifp; 934 935 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 936 __func__, ifp->if_flags); 937 938 /* 939 * NB: the order of these is important: 940 * o stop the chip so no more interrupts will fire 941 * o call the 802.11 layer before detaching the hal to 942 * insure callbacks into the driver to delete global 943 * key cache entries can be handled 944 * o free the taskqueue which drains any pending tasks 945 * o reclaim the tx queue data structures after calling 946 * the 802.11 layer as we'll get called back to reclaim 947 * node state and potentially want to use them 948 * o to cleanup the tx queues the hal is called, so detach 949 * it last 950 * Other than that, it's straightforward... 951 */ 952 ath_stop(ifp); 953 ieee80211_ifdetach(ifp->if_l2com); 954 taskqueue_free(sc->sc_tq); 955 #ifdef ATH_TX99_DIAG 956 if (sc->sc_tx99 != NULL) 957 sc->sc_tx99->detach(sc->sc_tx99); 958 #endif 959 ath_rate_detach(sc->sc_rc); 960 961 #ifdef ATH_DEBUG_ALQ 962 if_ath_alq_tidyup(&sc->sc_alq); 963 #endif 964 965 ath_dfs_detach(sc); 966 ath_desc_free(sc); 967 ath_txdma_teardown(sc); 968 ath_rxdma_teardown(sc); 969 ath_tx_cleanup(sc); 970 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 971 972 CURVNET_SET(ifp->if_vnet); 973 if_free(ifp); 974 CURVNET_RESTORE(); 975 976 return 0; 977 } 978 979 /* 980 * MAC address handling for multiple BSS on the same radio. 981 * The first vap uses the MAC address from the EEPROM. For 982 * subsequent vap's we set the U/L bit (bit 1) in the MAC 983 * address and use the next six bits as an index. 984 */ 985 static void 986 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 987 { 988 int i; 989 990 if (clone && sc->sc_hasbmask) { 991 /* NB: we only do this if h/w supports multiple bssid */ 992 for (i = 0; i < 8; i++) 993 if ((sc->sc_bssidmask & (1<<i)) == 0) 994 break; 995 if (i != 0) 996 mac[0] |= (i << 2)|0x2; 997 } else 998 i = 0; 999 sc->sc_bssidmask |= 1<<i; 1000 sc->sc_hwbssidmask[0] &= ~mac[0]; 1001 if (i == 0) 1002 sc->sc_nbssid0++; 1003 } 1004 1005 static void 1006 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 1007 { 1008 int i = mac[0] >> 2; 1009 uint8_t mask; 1010 1011 if (i != 0 || --sc->sc_nbssid0 == 0) { 1012 sc->sc_bssidmask &= ~(1<<i); 1013 /* recalculate bssid mask from remaining addresses */ 1014 mask = 0xff; 1015 for (i = 1; i < 8; i++) 1016 if (sc->sc_bssidmask & (1<<i)) 1017 mask &= ~((i<<2)|0x2); 1018 sc->sc_hwbssidmask[0] |= mask; 1019 } 1020 } 1021 1022 /* 1023 * Assign a beacon xmit slot. We try to space out 1024 * assignments so when beacons are staggered the 1025 * traffic coming out of the cab q has maximal time 1026 * to go out before the next beacon is scheduled. 1027 */ 1028 static int 1029 assign_bslot(struct ath_softc *sc) 1030 { 1031 u_int slot, free; 1032 1033 free = 0; 1034 for (slot = 0; slot < ATH_BCBUF; slot++) 1035 if (sc->sc_bslot[slot] == NULL) { 1036 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 1037 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 1038 return slot; 1039 free = slot; 1040 /* NB: keep looking for a double slot */ 1041 } 1042 return free; 1043 } 1044 1045 static struct ieee80211vap * 1046 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1047 enum ieee80211_opmode opmode, int flags, 1048 const uint8_t bssid[IEEE80211_ADDR_LEN], 1049 const uint8_t mac0[IEEE80211_ADDR_LEN]) 1050 { 1051 struct ath_softc *sc = ic->ic_ifp->if_softc; 1052 struct ath_vap *avp; 1053 struct ieee80211vap *vap; 1054 uint8_t mac[IEEE80211_ADDR_LEN]; 1055 int needbeacon, error; 1056 enum ieee80211_opmode ic_opmode; 1057 1058 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap), 1059 M_80211_VAP, M_WAITOK | M_ZERO); 1060 needbeacon = 0; 1061 IEEE80211_ADDR_COPY(mac, mac0); 1062 1063 ATH_LOCK(sc); 1064 ic_opmode = opmode; /* default to opmode of new vap */ 1065 switch (opmode) { 1066 case IEEE80211_M_STA: 1067 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 1068 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 1069 goto bad; 1070 } 1071 if (sc->sc_nvaps) { 1072 /* 1073 * With multiple vaps we must fall back 1074 * to s/w beacon miss handling. 1075 */ 1076 flags |= IEEE80211_CLONE_NOBEACONS; 1077 } 1078 if (flags & IEEE80211_CLONE_NOBEACONS) { 1079 /* 1080 * Station mode w/o beacons are implemented w/ AP mode. 1081 */ 1082 ic_opmode = IEEE80211_M_HOSTAP; 1083 } 1084 break; 1085 case IEEE80211_M_IBSS: 1086 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 1087 device_printf(sc->sc_dev, 1088 "only 1 ibss vap supported\n"); 1089 goto bad; 1090 } 1091 needbeacon = 1; 1092 break; 1093 case IEEE80211_M_AHDEMO: 1094 #ifdef IEEE80211_SUPPORT_TDMA 1095 if (flags & IEEE80211_CLONE_TDMA) { 1096 if (sc->sc_nvaps != 0) { 1097 device_printf(sc->sc_dev, 1098 "only 1 tdma vap supported\n"); 1099 goto bad; 1100 } 1101 needbeacon = 1; 1102 flags |= IEEE80211_CLONE_NOBEACONS; 1103 } 1104 /* fall thru... */ 1105 #endif 1106 case IEEE80211_M_MONITOR: 1107 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 1108 /* 1109 * Adopt existing mode. Adding a monitor or ahdemo 1110 * vap to an existing configuration is of dubious 1111 * value but should be ok. 1112 */ 1113 /* XXX not right for monitor mode */ 1114 ic_opmode = ic->ic_opmode; 1115 } 1116 break; 1117 case IEEE80211_M_HOSTAP: 1118 case IEEE80211_M_MBSS: 1119 needbeacon = 1; 1120 break; 1121 case IEEE80211_M_WDS: 1122 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 1123 device_printf(sc->sc_dev, 1124 "wds not supported in sta mode\n"); 1125 goto bad; 1126 } 1127 /* 1128 * Silently remove any request for a unique 1129 * bssid; WDS vap's always share the local 1130 * mac address. 1131 */ 1132 flags &= ~IEEE80211_CLONE_BSSID; 1133 if (sc->sc_nvaps == 0) 1134 ic_opmode = IEEE80211_M_HOSTAP; 1135 else 1136 ic_opmode = ic->ic_opmode; 1137 break; 1138 default: 1139 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 1140 goto bad; 1141 } 1142 /* 1143 * Check that a beacon buffer is available; the code below assumes it. 1144 */ 1145 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) { 1146 device_printf(sc->sc_dev, "no beacon buffer available\n"); 1147 goto bad; 1148 } 1149 1150 /* STA, AHDEMO? */ 1151 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 1152 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 1153 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1154 } 1155 1156 vap = &avp->av_vap; 1157 /* XXX can't hold mutex across if_alloc */ 1158 ATH_UNLOCK(sc); 1159 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 1160 bssid, mac); 1161 ATH_LOCK(sc); 1162 if (error != 0) { 1163 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 1164 __func__, error); 1165 goto bad2; 1166 } 1167 1168 /* h/w crypto support */ 1169 vap->iv_key_alloc = ath_key_alloc; 1170 vap->iv_key_delete = ath_key_delete; 1171 vap->iv_key_set = ath_key_set; 1172 vap->iv_key_update_begin = ath_key_update_begin; 1173 vap->iv_key_update_end = ath_key_update_end; 1174 1175 /* override various methods */ 1176 avp->av_recv_mgmt = vap->iv_recv_mgmt; 1177 vap->iv_recv_mgmt = ath_recv_mgmt; 1178 vap->iv_reset = ath_reset_vap; 1179 vap->iv_update_beacon = ath_beacon_update; 1180 avp->av_newstate = vap->iv_newstate; 1181 vap->iv_newstate = ath_newstate; 1182 avp->av_bmiss = vap->iv_bmiss; 1183 vap->iv_bmiss = ath_bmiss_vap; 1184 1185 avp->av_node_ps = vap->iv_node_ps; 1186 vap->iv_node_ps = ath_node_powersave; 1187 1188 avp->av_set_tim = vap->iv_set_tim; 1189 vap->iv_set_tim = ath_node_set_tim; 1190 1191 /* Set default parameters */ 1192 1193 /* 1194 * Anything earlier than some AR9300 series MACs don't 1195 * support a smaller MPDU density. 1196 */ 1197 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8; 1198 /* 1199 * All NICs can handle the maximum size, however 1200 * AR5416 based MACs can only TX aggregates w/ RTS 1201 * protection when the total aggregate size is <= 8k. 1202 * However, for now that's enforced by the TX path. 1203 */ 1204 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1205 1206 avp->av_bslot = -1; 1207 if (needbeacon) { 1208 /* 1209 * Allocate beacon state and setup the q for buffered 1210 * multicast frames. We know a beacon buffer is 1211 * available because we checked above. 1212 */ 1213 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf); 1214 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list); 1215 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1216 /* 1217 * Assign the vap to a beacon xmit slot. As above 1218 * this cannot fail to find a free one. 1219 */ 1220 avp->av_bslot = assign_bslot(sc); 1221 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1222 ("beacon slot %u not empty", avp->av_bslot)); 1223 sc->sc_bslot[avp->av_bslot] = vap; 1224 sc->sc_nbcnvaps++; 1225 } 1226 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1227 /* 1228 * Multple vaps are to transmit beacons and we 1229 * have h/w support for TSF adjusting; enable 1230 * use of staggered beacons. 1231 */ 1232 sc->sc_stagbeacons = 1; 1233 } 1234 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1235 } 1236 1237 ic->ic_opmode = ic_opmode; 1238 if (opmode != IEEE80211_M_WDS) { 1239 sc->sc_nvaps++; 1240 if (opmode == IEEE80211_M_STA) 1241 sc->sc_nstavaps++; 1242 if (opmode == IEEE80211_M_MBSS) 1243 sc->sc_nmeshvaps++; 1244 } 1245 switch (ic_opmode) { 1246 case IEEE80211_M_IBSS: 1247 sc->sc_opmode = HAL_M_IBSS; 1248 break; 1249 case IEEE80211_M_STA: 1250 sc->sc_opmode = HAL_M_STA; 1251 break; 1252 case IEEE80211_M_AHDEMO: 1253 #ifdef IEEE80211_SUPPORT_TDMA 1254 if (vap->iv_caps & IEEE80211_C_TDMA) { 1255 sc->sc_tdma = 1; 1256 /* NB: disable tsf adjust */ 1257 sc->sc_stagbeacons = 0; 1258 } 1259 /* 1260 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1261 * just ap mode. 1262 */ 1263 /* fall thru... */ 1264 #endif 1265 case IEEE80211_M_HOSTAP: 1266 case IEEE80211_M_MBSS: 1267 sc->sc_opmode = HAL_M_HOSTAP; 1268 break; 1269 case IEEE80211_M_MONITOR: 1270 sc->sc_opmode = HAL_M_MONITOR; 1271 break; 1272 default: 1273 /* XXX should not happen */ 1274 break; 1275 } 1276 if (sc->sc_hastsfadd) { 1277 /* 1278 * Configure whether or not TSF adjust should be done. 1279 */ 1280 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1281 } 1282 if (flags & IEEE80211_CLONE_NOBEACONS) { 1283 /* 1284 * Enable s/w beacon miss handling. 1285 */ 1286 sc->sc_swbmiss = 1; 1287 } 1288 ATH_UNLOCK(sc); 1289 1290 /* complete setup */ 1291 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1292 return vap; 1293 bad2: 1294 reclaim_address(sc, mac); 1295 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1296 bad: 1297 free(avp, M_80211_VAP); 1298 ATH_UNLOCK(sc); 1299 return NULL; 1300 } 1301 1302 static void 1303 ath_vap_delete(struct ieee80211vap *vap) 1304 { 1305 struct ieee80211com *ic = vap->iv_ic; 1306 struct ifnet *ifp = ic->ic_ifp; 1307 struct ath_softc *sc = ifp->if_softc; 1308 struct ath_hal *ah = sc->sc_ah; 1309 struct ath_vap *avp = ATH_VAP(vap); 1310 1311 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 1312 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1313 /* 1314 * Quiesce the hardware while we remove the vap. In 1315 * particular we need to reclaim all references to 1316 * the vap state by any frames pending on the tx queues. 1317 */ 1318 ath_hal_intrset(ah, 0); /* disable interrupts */ 1319 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */ 1320 /* XXX Do all frames from all vaps/nodes need draining here? */ 1321 ath_stoprecv(sc, 1); /* stop recv side */ 1322 } 1323 1324 ieee80211_vap_detach(vap); 1325 1326 /* 1327 * XXX Danger Will Robinson! Danger! 1328 * 1329 * Because ieee80211_vap_detach() can queue a frame (the station 1330 * diassociate message?) after we've drained the TXQ and 1331 * flushed the software TXQ, we will end up with a frame queued 1332 * to a node whose vap is about to be freed. 1333 * 1334 * To work around this, flush the hardware/software again. 1335 * This may be racy - the ath task may be running and the packet 1336 * may be being scheduled between sw->hw txq. Tsk. 1337 * 1338 * TODO: figure out why a new node gets allocated somewhere around 1339 * here (after the ath_tx_swq() call; and after an ath_stop_locked() 1340 * call!) 1341 */ 1342 1343 ath_draintxq(sc, ATH_RESET_DEFAULT); 1344 1345 ATH_LOCK(sc); 1346 /* 1347 * Reclaim beacon state. Note this must be done before 1348 * the vap instance is reclaimed as we may have a reference 1349 * to it in the buffer for the beacon frame. 1350 */ 1351 if (avp->av_bcbuf != NULL) { 1352 if (avp->av_bslot != -1) { 1353 sc->sc_bslot[avp->av_bslot] = NULL; 1354 sc->sc_nbcnvaps--; 1355 } 1356 ath_beacon_return(sc, avp->av_bcbuf); 1357 avp->av_bcbuf = NULL; 1358 if (sc->sc_nbcnvaps == 0) { 1359 sc->sc_stagbeacons = 0; 1360 if (sc->sc_hastsfadd) 1361 ath_hal_settsfadjust(sc->sc_ah, 0); 1362 } 1363 /* 1364 * Reclaim any pending mcast frames for the vap. 1365 */ 1366 ath_tx_draintxq(sc, &avp->av_mcastq); 1367 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq); 1368 } 1369 /* 1370 * Update bookkeeping. 1371 */ 1372 if (vap->iv_opmode == IEEE80211_M_STA) { 1373 sc->sc_nstavaps--; 1374 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1375 sc->sc_swbmiss = 0; 1376 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1377 vap->iv_opmode == IEEE80211_M_MBSS) { 1378 reclaim_address(sc, vap->iv_myaddr); 1379 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1380 if (vap->iv_opmode == IEEE80211_M_MBSS) 1381 sc->sc_nmeshvaps--; 1382 } 1383 if (vap->iv_opmode != IEEE80211_M_WDS) 1384 sc->sc_nvaps--; 1385 #ifdef IEEE80211_SUPPORT_TDMA 1386 /* TDMA operation ceases when the last vap is destroyed */ 1387 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1388 sc->sc_tdma = 0; 1389 sc->sc_swbmiss = 0; 1390 } 1391 #endif 1392 free(avp, M_80211_VAP); 1393 1394 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1395 /* 1396 * Restart rx+tx machines if still running (RUNNING will 1397 * be reset if we just destroyed the last vap). 1398 */ 1399 if (ath_startrecv(sc) != 0) 1400 if_printf(ifp, "%s: unable to restart recv logic\n", 1401 __func__); 1402 if (sc->sc_beacons) { /* restart beacons */ 1403 #ifdef IEEE80211_SUPPORT_TDMA 1404 if (sc->sc_tdma) 1405 ath_tdma_config(sc, NULL); 1406 else 1407 #endif 1408 ath_beacon_config(sc, NULL); 1409 } 1410 ath_hal_intrset(ah, sc->sc_imask); 1411 } 1412 ATH_UNLOCK(sc); 1413 } 1414 1415 void 1416 ath_suspend(struct ath_softc *sc) 1417 { 1418 struct ifnet *ifp = sc->sc_ifp; 1419 struct ieee80211com *ic = ifp->if_l2com; 1420 1421 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1422 __func__, ifp->if_flags); 1423 1424 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1425 1426 ieee80211_suspend_all(ic); 1427 /* 1428 * NB: don't worry about putting the chip in low power 1429 * mode; pci will power off our socket on suspend and 1430 * CardBus detaches the device. 1431 */ 1432 1433 /* 1434 * XXX ensure none of the taskqueues are running 1435 * XXX ensure sc_invalid is 1 1436 * XXX ensure the calibration callout is disabled 1437 */ 1438 1439 /* Disable the PCIe PHY, complete with workarounds */ 1440 ath_hal_enablepcie(sc->sc_ah, 1, 1); 1441 } 1442 1443 /* 1444 * Reset the key cache since some parts do not reset the 1445 * contents on resume. First we clear all entries, then 1446 * re-load keys that the 802.11 layer assumes are setup 1447 * in h/w. 1448 */ 1449 static void 1450 ath_reset_keycache(struct ath_softc *sc) 1451 { 1452 struct ifnet *ifp = sc->sc_ifp; 1453 struct ieee80211com *ic = ifp->if_l2com; 1454 struct ath_hal *ah = sc->sc_ah; 1455 int i; 1456 1457 for (i = 0; i < sc->sc_keymax; i++) 1458 ath_hal_keyreset(ah, i); 1459 ieee80211_crypto_reload_keys(ic); 1460 } 1461 1462 void 1463 ath_resume(struct ath_softc *sc) 1464 { 1465 struct ifnet *ifp = sc->sc_ifp; 1466 struct ieee80211com *ic = ifp->if_l2com; 1467 struct ath_hal *ah = sc->sc_ah; 1468 HAL_STATUS status; 1469 1470 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1471 __func__, ifp->if_flags); 1472 1473 /* Re-enable PCIe, re-enable the PCIe bus */ 1474 ath_hal_enablepcie(ah, 0, 0); 1475 1476 /* 1477 * Must reset the chip before we reload the 1478 * keycache as we were powered down on suspend. 1479 */ 1480 ath_hal_reset(ah, sc->sc_opmode, 1481 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1482 AH_FALSE, &status); 1483 ath_reset_keycache(sc); 1484 1485 /* Let DFS at it in case it's a DFS channel */ 1486 ath_dfs_radar_enable(sc, ic->ic_curchan); 1487 1488 /* Restore the LED configuration */ 1489 ath_led_config(sc); 1490 ath_hal_setledstate(ah, HAL_LED_INIT); 1491 1492 if (sc->sc_resume_up) 1493 ieee80211_resume_all(ic); 1494 1495 /* XXX beacons ? */ 1496 } 1497 1498 void 1499 ath_shutdown(struct ath_softc *sc) 1500 { 1501 struct ifnet *ifp = sc->sc_ifp; 1502 1503 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1504 __func__, ifp->if_flags); 1505 1506 ath_stop(ifp); 1507 /* NB: no point powering down chip as we're about to reboot */ 1508 } 1509 1510 /* 1511 * Interrupt handler. Most of the actual processing is deferred. 1512 */ 1513 void 1514 ath_intr(void *arg) 1515 { 1516 struct ath_softc *sc = arg; 1517 struct ifnet *ifp = sc->sc_ifp; 1518 struct ath_hal *ah = sc->sc_ah; 1519 HAL_INT status = 0; 1520 uint32_t txqs; 1521 1522 /* 1523 * If we're inside a reset path, just print a warning and 1524 * clear the ISR. The reset routine will finish it for us. 1525 */ 1526 ATH_PCU_LOCK(sc); 1527 if (sc->sc_inreset_cnt) { 1528 HAL_INT status; 1529 ath_hal_getisr(ah, &status); /* clear ISR */ 1530 ath_hal_intrset(ah, 0); /* disable further intr's */ 1531 DPRINTF(sc, ATH_DEBUG_ANY, 1532 "%s: in reset, ignoring: status=0x%x\n", 1533 __func__, status); 1534 ATH_PCU_UNLOCK(sc); 1535 return; 1536 } 1537 1538 if (sc->sc_invalid) { 1539 /* 1540 * The hardware is not ready/present, don't touch anything. 1541 * Note this can happen early on if the IRQ is shared. 1542 */ 1543 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1544 ATH_PCU_UNLOCK(sc); 1545 return; 1546 } 1547 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */ 1548 ATH_PCU_UNLOCK(sc); 1549 return; 1550 } 1551 1552 if ((ifp->if_flags & IFF_UP) == 0 || 1553 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1554 HAL_INT status; 1555 1556 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1557 __func__, ifp->if_flags); 1558 ath_hal_getisr(ah, &status); /* clear ISR */ 1559 ath_hal_intrset(ah, 0); /* disable further intr's */ 1560 ATH_PCU_UNLOCK(sc); 1561 return; 1562 } 1563 1564 /* 1565 * Figure out the reason(s) for the interrupt. Note 1566 * that the hal returns a pseudo-ISR that may include 1567 * bits we haven't explicitly enabled so we mask the 1568 * value to insure we only process bits we requested. 1569 */ 1570 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 1571 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 1572 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status); 1573 #ifdef ATH_KTR_INTR_DEBUG 1574 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5, 1575 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x", 1576 ah->ah_intrstate[0], 1577 ah->ah_intrstate[1], 1578 ah->ah_intrstate[2], 1579 ah->ah_intrstate[3], 1580 ah->ah_intrstate[6]); 1581 #endif 1582 1583 /* Squirrel away SYNC interrupt debugging */ 1584 if (ah->ah_syncstate != 0) { 1585 int i; 1586 for (i = 0; i < 32; i++) 1587 if (ah->ah_syncstate & (i << i)) 1588 sc->sc_intr_stats.sync_intr[i]++; 1589 } 1590 1591 status &= sc->sc_imask; /* discard unasked for bits */ 1592 1593 /* Short-circuit un-handled interrupts */ 1594 if (status == 0x0) { 1595 ATH_PCU_UNLOCK(sc); 1596 return; 1597 } 1598 1599 /* 1600 * Take a note that we're inside the interrupt handler, so 1601 * the reset routines know to wait. 1602 */ 1603 sc->sc_intr_cnt++; 1604 ATH_PCU_UNLOCK(sc); 1605 1606 /* 1607 * Handle the interrupt. We won't run concurrent with the reset 1608 * or channel change routines as they'll wait for sc_intr_cnt 1609 * to be 0 before continuing. 1610 */ 1611 if (status & HAL_INT_FATAL) { 1612 sc->sc_stats.ast_hardware++; 1613 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1614 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask); 1615 } else { 1616 if (status & HAL_INT_SWBA) { 1617 /* 1618 * Software beacon alert--time to send a beacon. 1619 * Handle beacon transmission directly; deferring 1620 * this is too slow to meet timing constraints 1621 * under load. 1622 */ 1623 #ifdef IEEE80211_SUPPORT_TDMA 1624 if (sc->sc_tdma) { 1625 if (sc->sc_tdmaswba == 0) { 1626 struct ieee80211com *ic = ifp->if_l2com; 1627 struct ieee80211vap *vap = 1628 TAILQ_FIRST(&ic->ic_vaps); 1629 ath_tdma_beacon_send(sc, vap); 1630 sc->sc_tdmaswba = 1631 vap->iv_tdma->tdma_bintval; 1632 } else 1633 sc->sc_tdmaswba--; 1634 } else 1635 #endif 1636 { 1637 ath_beacon_proc(sc, 0); 1638 #ifdef IEEE80211_SUPPORT_SUPERG 1639 /* 1640 * Schedule the rx taskq in case there's no 1641 * traffic so any frames held on the staging 1642 * queue are aged and potentially flushed. 1643 */ 1644 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1645 #endif 1646 } 1647 } 1648 if (status & HAL_INT_RXEOL) { 1649 int imask; 1650 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL"); 1651 ATH_PCU_LOCK(sc); 1652 /* 1653 * NB: the hardware should re-read the link when 1654 * RXE bit is written, but it doesn't work at 1655 * least on older hardware revs. 1656 */ 1657 sc->sc_stats.ast_rxeol++; 1658 /* 1659 * Disable RXEOL/RXORN - prevent an interrupt 1660 * storm until the PCU logic can be reset. 1661 * In case the interface is reset some other 1662 * way before "sc_kickpcu" is called, don't 1663 * modify sc_imask - that way if it is reset 1664 * by a call to ath_reset() somehow, the 1665 * interrupt mask will be correctly reprogrammed. 1666 */ 1667 imask = sc->sc_imask; 1668 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN); 1669 ath_hal_intrset(ah, imask); 1670 /* 1671 * Only blank sc_rxlink if we've not yet kicked 1672 * the PCU. 1673 * 1674 * This isn't entirely correct - the correct solution 1675 * would be to have a PCU lock and engage that for 1676 * the duration of the PCU fiddling; which would include 1677 * running the RX process. Otherwise we could end up 1678 * messing up the RX descriptor chain and making the 1679 * RX desc list much shorter. 1680 */ 1681 if (! sc->sc_kickpcu) 1682 sc->sc_rxlink = NULL; 1683 sc->sc_kickpcu = 1; 1684 /* 1685 * Enqueue an RX proc, to handled whatever 1686 * is in the RX queue. 1687 * This will then kick the PCU. 1688 */ 1689 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1690 ATH_PCU_UNLOCK(sc); 1691 } 1692 if (status & HAL_INT_TXURN) { 1693 sc->sc_stats.ast_txurn++; 1694 /* bump tx trigger level */ 1695 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1696 } 1697 /* 1698 * Handle both the legacy and RX EDMA interrupt bits. 1699 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC. 1700 */ 1701 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) { 1702 sc->sc_stats.ast_rx_intr++; 1703 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1704 } 1705 if (status & HAL_INT_TX) { 1706 sc->sc_stats.ast_tx_intr++; 1707 /* 1708 * Grab all the currently set bits in the HAL txq bitmap 1709 * and blank them. This is the only place we should be 1710 * doing this. 1711 */ 1712 if (! sc->sc_isedma) { 1713 ATH_PCU_LOCK(sc); 1714 txqs = 0xffffffff; 1715 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs); 1716 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3, 1717 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x", 1718 txqs, 1719 sc->sc_txq_active, 1720 sc->sc_txq_active | txqs); 1721 sc->sc_txq_active |= txqs; 1722 ATH_PCU_UNLOCK(sc); 1723 } 1724 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1725 } 1726 if (status & HAL_INT_BMISS) { 1727 sc->sc_stats.ast_bmiss++; 1728 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1729 } 1730 if (status & HAL_INT_GTT) 1731 sc->sc_stats.ast_tx_timeout++; 1732 if (status & HAL_INT_CST) 1733 sc->sc_stats.ast_tx_cst++; 1734 if (status & HAL_INT_MIB) { 1735 sc->sc_stats.ast_mib++; 1736 ATH_PCU_LOCK(sc); 1737 /* 1738 * Disable interrupts until we service the MIB 1739 * interrupt; otherwise it will continue to fire. 1740 */ 1741 ath_hal_intrset(ah, 0); 1742 /* 1743 * Let the hal handle the event. We assume it will 1744 * clear whatever condition caused the interrupt. 1745 */ 1746 ath_hal_mibevent(ah, &sc->sc_halstats); 1747 /* 1748 * Don't reset the interrupt if we've just 1749 * kicked the PCU, or we may get a nested 1750 * RXEOL before the rxproc has had a chance 1751 * to run. 1752 */ 1753 if (sc->sc_kickpcu == 0) 1754 ath_hal_intrset(ah, sc->sc_imask); 1755 ATH_PCU_UNLOCK(sc); 1756 } 1757 if (status & HAL_INT_RXORN) { 1758 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1759 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN"); 1760 sc->sc_stats.ast_rxorn++; 1761 } 1762 } 1763 ATH_PCU_LOCK(sc); 1764 sc->sc_intr_cnt--; 1765 ATH_PCU_UNLOCK(sc); 1766 } 1767 1768 static void 1769 ath_fatal_proc(void *arg, int pending) 1770 { 1771 struct ath_softc *sc = arg; 1772 struct ifnet *ifp = sc->sc_ifp; 1773 u_int32_t *state; 1774 u_int32_t len; 1775 void *sp; 1776 1777 if_printf(ifp, "hardware error; resetting\n"); 1778 /* 1779 * Fatal errors are unrecoverable. Typically these 1780 * are caused by DMA errors. Collect h/w state from 1781 * the hal so we can diagnose what's going on. 1782 */ 1783 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1784 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1785 state = sp; 1786 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1787 state[0], state[1] , state[2], state[3], 1788 state[4], state[5]); 1789 } 1790 ath_reset(ifp, ATH_RESET_NOLOSS); 1791 } 1792 1793 static void 1794 ath_bmiss_vap(struct ieee80211vap *vap) 1795 { 1796 /* 1797 * Workaround phantom bmiss interrupts by sanity-checking 1798 * the time of our last rx'd frame. If it is within the 1799 * beacon miss interval then ignore the interrupt. If it's 1800 * truly a bmiss we'll get another interrupt soon and that'll 1801 * be dispatched up for processing. Note this applies only 1802 * for h/w beacon miss events. 1803 */ 1804 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1805 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1806 struct ath_softc *sc = ifp->if_softc; 1807 u_int64_t lastrx = sc->sc_lastrx; 1808 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1809 /* XXX should take a locked ref to iv_bss */ 1810 u_int bmisstimeout = 1811 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1812 1813 DPRINTF(sc, ATH_DEBUG_BEACON, 1814 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1815 __func__, (unsigned long long) tsf, 1816 (unsigned long long)(tsf - lastrx), 1817 (unsigned long long) lastrx, bmisstimeout); 1818 1819 if (tsf - lastrx <= bmisstimeout) { 1820 sc->sc_stats.ast_bmiss_phantom++; 1821 return; 1822 } 1823 } 1824 ATH_VAP(vap)->av_bmiss(vap); 1825 } 1826 1827 static int 1828 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1829 { 1830 uint32_t rsize; 1831 void *sp; 1832 1833 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize)) 1834 return 0; 1835 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1836 *hangs = *(uint32_t *)sp; 1837 return 1; 1838 } 1839 1840 static void 1841 ath_bmiss_proc(void *arg, int pending) 1842 { 1843 struct ath_softc *sc = arg; 1844 struct ifnet *ifp = sc->sc_ifp; 1845 uint32_t hangs; 1846 1847 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1848 1849 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1850 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs); 1851 ath_reset(ifp, ATH_RESET_NOLOSS); 1852 } else 1853 ieee80211_beacon_miss(ifp->if_l2com); 1854 } 1855 1856 /* 1857 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1858 * calcs together with WME. If necessary disable the crypto 1859 * hardware and mark the 802.11 state so keys will be setup 1860 * with the MIC work done in software. 1861 */ 1862 static void 1863 ath_settkipmic(struct ath_softc *sc) 1864 { 1865 struct ifnet *ifp = sc->sc_ifp; 1866 struct ieee80211com *ic = ifp->if_l2com; 1867 1868 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1869 if (ic->ic_flags & IEEE80211_F_WME) { 1870 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1871 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1872 } else { 1873 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1874 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1875 } 1876 } 1877 } 1878 1879 static void 1880 ath_init(void *arg) 1881 { 1882 struct ath_softc *sc = (struct ath_softc *) arg; 1883 struct ifnet *ifp = sc->sc_ifp; 1884 struct ieee80211com *ic = ifp->if_l2com; 1885 struct ath_hal *ah = sc->sc_ah; 1886 HAL_STATUS status; 1887 1888 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1889 __func__, ifp->if_flags); 1890 1891 ATH_LOCK(sc); 1892 /* 1893 * Stop anything previously setup. This is safe 1894 * whether this is the first time through or not. 1895 */ 1896 ath_stop_locked(ifp); 1897 1898 /* 1899 * The basic interface to setting the hardware in a good 1900 * state is ``reset''. On return the hardware is known to 1901 * be powered up and with interrupts disabled. This must 1902 * be followed by initialization of the appropriate bits 1903 * and then setup of the interrupt mask. 1904 */ 1905 ath_settkipmic(sc); 1906 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 1907 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1908 status); 1909 ATH_UNLOCK(sc); 1910 return; 1911 } 1912 ath_chan_change(sc, ic->ic_curchan); 1913 1914 /* Let DFS at it in case it's a DFS channel */ 1915 ath_dfs_radar_enable(sc, ic->ic_curchan); 1916 1917 /* 1918 * Likewise this is set during reset so update 1919 * state cached in the driver. 1920 */ 1921 sc->sc_diversity = ath_hal_getdiversity(ah); 1922 sc->sc_lastlongcal = 0; 1923 sc->sc_resetcal = 1; 1924 sc->sc_lastcalreset = 0; 1925 sc->sc_lastani = 0; 1926 sc->sc_lastshortcal = 0; 1927 sc->sc_doresetcal = AH_FALSE; 1928 /* 1929 * Beacon timers were cleared here; give ath_newstate() 1930 * a hint that the beacon timers should be poked when 1931 * things transition to the RUN state. 1932 */ 1933 sc->sc_beacons = 0; 1934 1935 /* 1936 * Setup the hardware after reset: the key cache 1937 * is filled as needed and the receive engine is 1938 * set going. Frame transmit is handled entirely 1939 * in the frame output path; there's nothing to do 1940 * here except setup the interrupt mask. 1941 */ 1942 if (ath_startrecv(sc) != 0) { 1943 if_printf(ifp, "unable to start recv logic\n"); 1944 ATH_UNLOCK(sc); 1945 return; 1946 } 1947 1948 /* 1949 * Enable interrupts. 1950 */ 1951 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1952 | HAL_INT_RXEOL | HAL_INT_RXORN 1953 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1954 1955 /* 1956 * Enable RX EDMA bits. Note these overlap with 1957 * HAL_INT_RX and HAL_INT_RXDESC respectively. 1958 */ 1959 if (sc->sc_isedma) 1960 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP); 1961 1962 /* 1963 * Enable MIB interrupts when there are hardware phy counters. 1964 * Note we only do this (at the moment) for station mode. 1965 */ 1966 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1967 sc->sc_imask |= HAL_INT_MIB; 1968 1969 /* Enable global TX timeout and carrier sense timeout if available */ 1970 if (ath_hal_gtxto_supported(ah)) 1971 sc->sc_imask |= HAL_INT_GTT; 1972 1973 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n", 1974 __func__, sc->sc_imask); 1975 1976 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1977 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 1978 ath_hal_intrset(ah, sc->sc_imask); 1979 1980 ATH_UNLOCK(sc); 1981 1982 #ifdef ATH_TX99_DIAG 1983 if (sc->sc_tx99 != NULL) 1984 sc->sc_tx99->start(sc->sc_tx99); 1985 else 1986 #endif 1987 ieee80211_start_all(ic); /* start all vap's */ 1988 } 1989 1990 static void 1991 ath_stop_locked(struct ifnet *ifp) 1992 { 1993 struct ath_softc *sc = ifp->if_softc; 1994 struct ath_hal *ah = sc->sc_ah; 1995 1996 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1997 __func__, sc->sc_invalid, ifp->if_flags); 1998 1999 ATH_LOCK_ASSERT(sc); 2000 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2001 /* 2002 * Shutdown the hardware and driver: 2003 * reset 802.11 state machine 2004 * turn off timers 2005 * disable interrupts 2006 * turn off the radio 2007 * clear transmit machinery 2008 * clear receive machinery 2009 * drain and release tx queues 2010 * reclaim beacon resources 2011 * power down hardware 2012 * 2013 * Note that some of this work is not possible if the 2014 * hardware is gone (invalid). 2015 */ 2016 #ifdef ATH_TX99_DIAG 2017 if (sc->sc_tx99 != NULL) 2018 sc->sc_tx99->stop(sc->sc_tx99); 2019 #endif 2020 callout_stop(&sc->sc_wd_ch); 2021 sc->sc_wd_timer = 0; 2022 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2023 if (!sc->sc_invalid) { 2024 if (sc->sc_softled) { 2025 callout_stop(&sc->sc_ledtimer); 2026 ath_hal_gpioset(ah, sc->sc_ledpin, 2027 !sc->sc_ledon); 2028 sc->sc_blinking = 0; 2029 } 2030 ath_hal_intrset(ah, 0); 2031 } 2032 ath_draintxq(sc, ATH_RESET_DEFAULT); 2033 if (!sc->sc_invalid) { 2034 ath_stoprecv(sc, 1); 2035 ath_hal_phydisable(ah); 2036 } else 2037 sc->sc_rxlink = NULL; 2038 ath_beacon_free(sc); /* XXX not needed */ 2039 } 2040 } 2041 2042 #define MAX_TXRX_ITERATIONS 1000 2043 static void 2044 ath_txrx_stop_locked(struct ath_softc *sc) 2045 { 2046 int i = MAX_TXRX_ITERATIONS; 2047 2048 ATH_UNLOCK_ASSERT(sc); 2049 ATH_PCU_LOCK_ASSERT(sc); 2050 2051 /* 2052 * Sleep until all the pending operations have completed. 2053 * 2054 * The caller must ensure that reset has been incremented 2055 * or the pending operations may continue being queued. 2056 */ 2057 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt || 2058 sc->sc_txstart_cnt || sc->sc_intr_cnt) { 2059 if (i <= 0) 2060 break; 2061 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1); 2062 i--; 2063 } 2064 2065 if (i <= 0) 2066 device_printf(sc->sc_dev, 2067 "%s: didn't finish after %d iterations\n", 2068 __func__, MAX_TXRX_ITERATIONS); 2069 } 2070 #undef MAX_TXRX_ITERATIONS 2071 2072 #if 0 2073 static void 2074 ath_txrx_stop(struct ath_softc *sc) 2075 { 2076 ATH_UNLOCK_ASSERT(sc); 2077 ATH_PCU_UNLOCK_ASSERT(sc); 2078 2079 ATH_PCU_LOCK(sc); 2080 ath_txrx_stop_locked(sc); 2081 ATH_PCU_UNLOCK(sc); 2082 } 2083 #endif 2084 2085 static void 2086 ath_txrx_start(struct ath_softc *sc) 2087 { 2088 2089 taskqueue_unblock(sc->sc_tq); 2090 } 2091 2092 /* 2093 * Grab the reset lock, and wait around until noone else 2094 * is trying to do anything with it. 2095 * 2096 * This is totally horrible but we can't hold this lock for 2097 * long enough to do TX/RX or we end up with net80211/ip stack 2098 * LORs and eventual deadlock. 2099 * 2100 * "dowait" signals whether to spin, waiting for the reset 2101 * lock count to reach 0. This should (for now) only be used 2102 * during the reset path, as the rest of the code may not 2103 * be locking-reentrant enough to behave correctly. 2104 * 2105 * Another, cleaner way should be found to serialise all of 2106 * these operations. 2107 */ 2108 #define MAX_RESET_ITERATIONS 10 2109 static int 2110 ath_reset_grablock(struct ath_softc *sc, int dowait) 2111 { 2112 int w = 0; 2113 int i = MAX_RESET_ITERATIONS; 2114 2115 ATH_PCU_LOCK_ASSERT(sc); 2116 do { 2117 if (sc->sc_inreset_cnt == 0) { 2118 w = 1; 2119 break; 2120 } 2121 if (dowait == 0) { 2122 w = 0; 2123 break; 2124 } 2125 ATH_PCU_UNLOCK(sc); 2126 pause("ath_reset_grablock", 1); 2127 i--; 2128 ATH_PCU_LOCK(sc); 2129 } while (i > 0); 2130 2131 /* 2132 * We always increment the refcounter, regardless 2133 * of whether we succeeded to get it in an exclusive 2134 * way. 2135 */ 2136 sc->sc_inreset_cnt++; 2137 2138 if (i <= 0) 2139 device_printf(sc->sc_dev, 2140 "%s: didn't finish after %d iterations\n", 2141 __func__, MAX_RESET_ITERATIONS); 2142 2143 if (w == 0) 2144 device_printf(sc->sc_dev, 2145 "%s: warning, recursive reset path!\n", 2146 __func__); 2147 2148 return w; 2149 } 2150 #undef MAX_RESET_ITERATIONS 2151 2152 /* 2153 * XXX TODO: write ath_reset_releaselock 2154 */ 2155 2156 static void 2157 ath_stop(struct ifnet *ifp) 2158 { 2159 struct ath_softc *sc = ifp->if_softc; 2160 2161 ATH_LOCK(sc); 2162 ath_stop_locked(ifp); 2163 ATH_UNLOCK(sc); 2164 } 2165 2166 /* 2167 * Reset the hardware w/o losing operational state. This is 2168 * basically a more efficient way of doing ath_stop, ath_init, 2169 * followed by state transitions to the current 802.11 2170 * operational state. Used to recover from various errors and 2171 * to reset or reload hardware state. 2172 */ 2173 int 2174 ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type) 2175 { 2176 struct ath_softc *sc = ifp->if_softc; 2177 struct ieee80211com *ic = ifp->if_l2com; 2178 struct ath_hal *ah = sc->sc_ah; 2179 HAL_STATUS status; 2180 int i; 2181 2182 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 2183 2184 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */ 2185 ATH_PCU_UNLOCK_ASSERT(sc); 2186 ATH_UNLOCK_ASSERT(sc); 2187 2188 /* Try to (stop any further TX/RX from occuring */ 2189 taskqueue_block(sc->sc_tq); 2190 2191 ATH_PCU_LOCK(sc); 2192 ath_hal_intrset(ah, 0); /* disable interrupts */ 2193 ath_txrx_stop_locked(sc); /* Ensure TX/RX is stopped */ 2194 if (ath_reset_grablock(sc, 1) == 0) { 2195 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 2196 __func__); 2197 } 2198 ATH_PCU_UNLOCK(sc); 2199 2200 /* 2201 * Should now wait for pending TX/RX to complete 2202 * and block future ones from occuring. This needs to be 2203 * done before the TX queue is drained. 2204 */ 2205 ath_draintxq(sc, reset_type); /* stop xmit side */ 2206 2207 /* 2208 * Regardless of whether we're doing a no-loss flush or 2209 * not, stop the PCU and handle what's in the RX queue. 2210 * That way frames aren't dropped which shouldn't be. 2211 */ 2212 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS)); 2213 ath_rx_flush(sc); 2214 2215 ath_settkipmic(sc); /* configure TKIP MIC handling */ 2216 /* NB: indicate channel change so we do a full reset */ 2217 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 2218 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 2219 __func__, status); 2220 sc->sc_diversity = ath_hal_getdiversity(ah); 2221 2222 /* Let DFS at it in case it's a DFS channel */ 2223 ath_dfs_radar_enable(sc, ic->ic_curchan); 2224 2225 if (ath_startrecv(sc) != 0) /* restart recv */ 2226 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 2227 /* 2228 * We may be doing a reset in response to an ioctl 2229 * that changes the channel so update any state that 2230 * might change as a result. 2231 */ 2232 ath_chan_change(sc, ic->ic_curchan); 2233 if (sc->sc_beacons) { /* restart beacons */ 2234 #ifdef IEEE80211_SUPPORT_TDMA 2235 if (sc->sc_tdma) 2236 ath_tdma_config(sc, NULL); 2237 else 2238 #endif 2239 ath_beacon_config(sc, NULL); 2240 } 2241 2242 /* 2243 * Release the reset lock and re-enable interrupts here. 2244 * If an interrupt was being processed in ath_intr(), 2245 * it would disable interrupts at this point. So we have 2246 * to atomically enable interrupts and decrement the 2247 * reset counter - this way ath_intr() doesn't end up 2248 * disabling interrupts without a corresponding enable 2249 * in the rest or channel change path. 2250 */ 2251 ATH_PCU_LOCK(sc); 2252 sc->sc_inreset_cnt--; 2253 /* XXX only do this if sc_inreset_cnt == 0? */ 2254 ath_hal_intrset(ah, sc->sc_imask); 2255 ATH_PCU_UNLOCK(sc); 2256 2257 /* 2258 * TX and RX can be started here. If it were started with 2259 * sc_inreset_cnt > 0, the TX and RX path would abort. 2260 * Thus if this is a nested call through the reset or 2261 * channel change code, TX completion will occur but 2262 * RX completion and ath_start / ath_tx_start will not 2263 * run. 2264 */ 2265 2266 /* Restart TX/RX as needed */ 2267 ath_txrx_start(sc); 2268 2269 /* XXX Restart TX completion and pending TX */ 2270 if (reset_type == ATH_RESET_NOLOSS) { 2271 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 2272 if (ATH_TXQ_SETUP(sc, i)) { 2273 ATH_TXQ_LOCK(&sc->sc_txq[i]); 2274 ath_txq_restart_dma(sc, &sc->sc_txq[i]); 2275 ath_txq_sched(sc, &sc->sc_txq[i]); 2276 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 2277 } 2278 } 2279 } 2280 2281 /* 2282 * This may have been set during an ath_start() call which 2283 * set this once it detected a concurrent TX was going on. 2284 * So, clear it. 2285 */ 2286 IF_LOCK(&ifp->if_snd); 2287 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2288 IF_UNLOCK(&ifp->if_snd); 2289 2290 /* Handle any frames in the TX queue */ 2291 /* 2292 * XXX should this be done by the caller, rather than 2293 * ath_reset() ? 2294 */ 2295 ath_tx_kick(sc); /* restart xmit */ 2296 return 0; 2297 } 2298 2299 static int 2300 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 2301 { 2302 struct ieee80211com *ic = vap->iv_ic; 2303 struct ifnet *ifp = ic->ic_ifp; 2304 struct ath_softc *sc = ifp->if_softc; 2305 struct ath_hal *ah = sc->sc_ah; 2306 2307 switch (cmd) { 2308 case IEEE80211_IOC_TXPOWER: 2309 /* 2310 * If per-packet TPC is enabled, then we have nothing 2311 * to do; otherwise we need to force the global limit. 2312 * All this can happen directly; no need to reset. 2313 */ 2314 if (!ath_hal_gettpc(ah)) 2315 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 2316 return 0; 2317 } 2318 /* XXX? Full or NOLOSS? */ 2319 return ath_reset(ifp, ATH_RESET_FULL); 2320 } 2321 2322 struct ath_buf * 2323 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype) 2324 { 2325 struct ath_buf *bf; 2326 2327 ATH_TXBUF_LOCK_ASSERT(sc); 2328 2329 if (btype == ATH_BUFTYPE_MGMT) 2330 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt); 2331 else 2332 bf = TAILQ_FIRST(&sc->sc_txbuf); 2333 2334 if (bf == NULL) { 2335 sc->sc_stats.ast_tx_getnobuf++; 2336 } else { 2337 if (bf->bf_flags & ATH_BUF_BUSY) { 2338 sc->sc_stats.ast_tx_getbusybuf++; 2339 bf = NULL; 2340 } 2341 } 2342 2343 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) { 2344 if (btype == ATH_BUFTYPE_MGMT) 2345 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list); 2346 else { 2347 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 2348 sc->sc_txbuf_cnt--; 2349 2350 /* 2351 * This shuldn't happen; however just to be 2352 * safe print a warning and fudge the txbuf 2353 * count. 2354 */ 2355 if (sc->sc_txbuf_cnt < 0) { 2356 device_printf(sc->sc_dev, 2357 "%s: sc_txbuf_cnt < 0?\n", 2358 __func__); 2359 sc->sc_txbuf_cnt = 0; 2360 } 2361 } 2362 } else 2363 bf = NULL; 2364 2365 if (bf == NULL) { 2366 /* XXX should check which list, mgmt or otherwise */ 2367 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 2368 TAILQ_FIRST(&sc->sc_txbuf) == NULL ? 2369 "out of xmit buffers" : "xmit buffer busy"); 2370 return NULL; 2371 } 2372 2373 /* XXX TODO: should do this at buffer list initialisation */ 2374 /* XXX (then, ensure the buffer has the right flag set) */ 2375 if (btype == ATH_BUFTYPE_MGMT) 2376 bf->bf_flags |= ATH_BUF_MGMT; 2377 else 2378 bf->bf_flags &= (~ATH_BUF_MGMT); 2379 2380 /* Valid bf here; clear some basic fields */ 2381 bf->bf_next = NULL; /* XXX just to be sure */ 2382 bf->bf_last = NULL; /* XXX again, just to be sure */ 2383 bf->bf_comp = NULL; /* XXX again, just to be sure */ 2384 bzero(&bf->bf_state, sizeof(bf->bf_state)); 2385 2386 /* 2387 * Track the descriptor ID only if doing EDMA 2388 */ 2389 if (sc->sc_isedma) { 2390 bf->bf_descid = sc->sc_txbuf_descid; 2391 sc->sc_txbuf_descid++; 2392 } 2393 2394 return bf; 2395 } 2396 2397 /* 2398 * When retrying a software frame, buffers marked ATH_BUF_BUSY 2399 * can't be thrown back on the queue as they could still be 2400 * in use by the hardware. 2401 * 2402 * This duplicates the buffer, or returns NULL. 2403 * 2404 * The descriptor is also copied but the link pointers and 2405 * the DMA segments aren't copied; this frame should thus 2406 * be again passed through the descriptor setup/chain routines 2407 * so the link is correct. 2408 * 2409 * The caller must free the buffer using ath_freebuf(). 2410 * 2411 * XXX TODO: this call shouldn't fail as it'll cause packet loss 2412 * XXX in the TX pathway when retries are needed. 2413 * XXX Figure out how to keep some buffers free, or factor the 2414 * XXX number of busy buffers into the xmit path (ath_start()) 2415 * XXX so we don't over-commit. 2416 */ 2417 struct ath_buf * 2418 ath_buf_clone(struct ath_softc *sc, const struct ath_buf *bf) 2419 { 2420 struct ath_buf *tbf; 2421 2422 tbf = ath_getbuf(sc, 2423 (bf->bf_flags & ATH_BUF_MGMT) ? 2424 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL); 2425 if (tbf == NULL) 2426 return NULL; /* XXX failure? Why? */ 2427 2428 /* Copy basics */ 2429 tbf->bf_next = NULL; 2430 tbf->bf_nseg = bf->bf_nseg; 2431 tbf->bf_flags = bf->bf_flags & ~ATH_BUF_BUSY; 2432 tbf->bf_status = bf->bf_status; 2433 tbf->bf_m = bf->bf_m; 2434 tbf->bf_node = bf->bf_node; 2435 /* will be setup by the chain/setup function */ 2436 tbf->bf_lastds = NULL; 2437 /* for now, last == self */ 2438 tbf->bf_last = tbf; 2439 tbf->bf_comp = bf->bf_comp; 2440 2441 /* NOTE: DMA segments will be setup by the setup/chain functions */ 2442 2443 /* The caller has to re-init the descriptor + links */ 2444 2445 /* Copy state */ 2446 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state)); 2447 2448 return tbf; 2449 } 2450 2451 struct ath_buf * 2452 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype) 2453 { 2454 struct ath_buf *bf; 2455 2456 ATH_TXBUF_LOCK(sc); 2457 bf = _ath_getbuf_locked(sc, btype); 2458 /* 2459 * If a mgmt buffer was requested but we're out of those, 2460 * try requesting a normal one. 2461 */ 2462 if (bf == NULL && btype == ATH_BUFTYPE_MGMT) 2463 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 2464 ATH_TXBUF_UNLOCK(sc); 2465 if (bf == NULL) { 2466 struct ifnet *ifp = sc->sc_ifp; 2467 2468 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 2469 sc->sc_stats.ast_tx_qstop++; 2470 IF_LOCK(&ifp->if_snd); 2471 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2472 IF_UNLOCK(&ifp->if_snd); 2473 } 2474 return bf; 2475 } 2476 2477 static void 2478 ath_start_queue(struct ifnet *ifp) 2479 { 2480 struct ath_softc *sc = ifp->if_softc; 2481 2482 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_queue: start"); 2483 ath_tx_kick(sc); 2484 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_queue: finished"); 2485 } 2486 2487 void 2488 ath_start_task(void *arg, int npending) 2489 { 2490 struct ath_softc *sc = (struct ath_softc *) arg; 2491 struct ifnet *ifp = sc->sc_ifp; 2492 2493 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: start"); 2494 2495 /* XXX is it ok to hold the ATH_LOCK here? */ 2496 ATH_PCU_LOCK(sc); 2497 if (sc->sc_inreset_cnt > 0) { 2498 device_printf(sc->sc_dev, 2499 "%s: sc_inreset_cnt > 0; bailing\n", __func__); 2500 ATH_PCU_UNLOCK(sc); 2501 IF_LOCK(&ifp->if_snd); 2502 sc->sc_stats.ast_tx_qstop++; 2503 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2504 IF_UNLOCK(&ifp->if_snd); 2505 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish"); 2506 return; 2507 } 2508 sc->sc_txstart_cnt++; 2509 ATH_PCU_UNLOCK(sc); 2510 2511 ath_start(sc->sc_ifp); 2512 2513 ATH_PCU_LOCK(sc); 2514 sc->sc_txstart_cnt--; 2515 ATH_PCU_UNLOCK(sc); 2516 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: finished"); 2517 } 2518 2519 void 2520 ath_start(struct ifnet *ifp) 2521 { 2522 struct ath_softc *sc = ifp->if_softc; 2523 struct ieee80211_node *ni; 2524 struct ath_buf *bf; 2525 struct mbuf *m, *next; 2526 ath_bufhead frags; 2527 int npkts = 0; 2528 2529 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 2530 return; 2531 2532 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start: called"); 2533 2534 for (;;) { 2535 ATH_TXBUF_LOCK(sc); 2536 if (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree) { 2537 /* XXX increment counter? */ 2538 ATH_TXBUF_UNLOCK(sc); 2539 IF_LOCK(&ifp->if_snd); 2540 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2541 IF_UNLOCK(&ifp->if_snd); 2542 break; 2543 } 2544 ATH_TXBUF_UNLOCK(sc); 2545 2546 /* 2547 * Grab a TX buffer and associated resources. 2548 */ 2549 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL); 2550 if (bf == NULL) 2551 break; 2552 2553 IFQ_DEQUEUE(&ifp->if_snd, m); 2554 if (m == NULL) { 2555 ATH_TXBUF_LOCK(sc); 2556 ath_returnbuf_head(sc, bf); 2557 ATH_TXBUF_UNLOCK(sc); 2558 break; 2559 } 2560 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 2561 npkts ++; 2562 /* 2563 * Check for fragmentation. If this frame 2564 * has been broken up verify we have enough 2565 * buffers to send all the fragments so all 2566 * go out or none... 2567 */ 2568 TAILQ_INIT(&frags); 2569 if ((m->m_flags & M_FRAG) && 2570 !ath_txfrag_setup(sc, &frags, m, ni)) { 2571 DPRINTF(sc, ATH_DEBUG_XMIT, 2572 "%s: out of txfrag buffers\n", __func__); 2573 sc->sc_stats.ast_tx_nofrag++; 2574 ifp->if_oerrors++; 2575 ath_freetx(m); 2576 goto bad; 2577 } 2578 ifp->if_opackets++; 2579 nextfrag: 2580 /* 2581 * Pass the frame to the h/w for transmission. 2582 * Fragmented frames have each frag chained together 2583 * with m_nextpkt. We know there are sufficient ath_buf's 2584 * to send all the frags because of work done by 2585 * ath_txfrag_setup. We leave m_nextpkt set while 2586 * calling ath_tx_start so it can use it to extend the 2587 * the tx duration to cover the subsequent frag and 2588 * so it can reclaim all the mbufs in case of an error; 2589 * ath_tx_start clears m_nextpkt once it commits to 2590 * handing the frame to the hardware. 2591 */ 2592 next = m->m_nextpkt; 2593 if (ath_tx_start(sc, ni, bf, m)) { 2594 bad: 2595 ifp->if_oerrors++; 2596 reclaim: 2597 bf->bf_m = NULL; 2598 bf->bf_node = NULL; 2599 ATH_TXBUF_LOCK(sc); 2600 ath_returnbuf_head(sc, bf); 2601 ath_txfrag_cleanup(sc, &frags, ni); 2602 ATH_TXBUF_UNLOCK(sc); 2603 if (ni != NULL) 2604 ieee80211_free_node(ni); 2605 continue; 2606 } 2607 2608 /* 2609 * Check here if the node is in power save state. 2610 */ 2611 ath_tx_update_tim(sc, ni, 1); 2612 2613 if (next != NULL) { 2614 /* 2615 * Beware of state changing between frags. 2616 * XXX check sta power-save state? 2617 */ 2618 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 2619 DPRINTF(sc, ATH_DEBUG_XMIT, 2620 "%s: flush fragmented packet, state %s\n", 2621 __func__, 2622 ieee80211_state_name[ni->ni_vap->iv_state]); 2623 ath_freetx(next); 2624 goto reclaim; 2625 } 2626 m = next; 2627 bf = TAILQ_FIRST(&frags); 2628 KASSERT(bf != NULL, ("no buf for txfrag")); 2629 TAILQ_REMOVE(&frags, bf, bf_list); 2630 goto nextfrag; 2631 } 2632 2633 sc->sc_wd_timer = 5; 2634 } 2635 ATH_KTR(sc, ATH_KTR_TX, 1, "ath_start: finished; npkts=%d", npkts); 2636 } 2637 2638 static int 2639 ath_media_change(struct ifnet *ifp) 2640 { 2641 int error = ieee80211_media_change(ifp); 2642 /* NB: only the fixed rate can change and that doesn't need a reset */ 2643 return (error == ENETRESET ? 0 : error); 2644 } 2645 2646 /* 2647 * Block/unblock tx+rx processing while a key change is done. 2648 * We assume the caller serializes key management operations 2649 * so we only need to worry about synchronization with other 2650 * uses that originate in the driver. 2651 */ 2652 static void 2653 ath_key_update_begin(struct ieee80211vap *vap) 2654 { 2655 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2656 struct ath_softc *sc = ifp->if_softc; 2657 2658 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2659 taskqueue_block(sc->sc_tq); 2660 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2661 } 2662 2663 static void 2664 ath_key_update_end(struct ieee80211vap *vap) 2665 { 2666 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2667 struct ath_softc *sc = ifp->if_softc; 2668 2669 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2670 IF_UNLOCK(&ifp->if_snd); 2671 taskqueue_unblock(sc->sc_tq); 2672 } 2673 2674 static void 2675 ath_update_promisc(struct ifnet *ifp) 2676 { 2677 struct ath_softc *sc = ifp->if_softc; 2678 u_int32_t rfilt; 2679 2680 /* configure rx filter */ 2681 rfilt = ath_calcrxfilter(sc); 2682 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2683 2684 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2685 } 2686 2687 static void 2688 ath_update_mcast(struct ifnet *ifp) 2689 { 2690 struct ath_softc *sc = ifp->if_softc; 2691 u_int32_t mfilt[2]; 2692 2693 /* calculate and install multicast filter */ 2694 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2695 struct ifmultiaddr *ifma; 2696 /* 2697 * Merge multicast addresses to form the hardware filter. 2698 */ 2699 mfilt[0] = mfilt[1] = 0; 2700 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */ 2701 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2702 caddr_t dl; 2703 u_int32_t val; 2704 u_int8_t pos; 2705 2706 /* calculate XOR of eight 6bit values */ 2707 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2708 val = LE_READ_4(dl + 0); 2709 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2710 val = LE_READ_4(dl + 3); 2711 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2712 pos &= 0x3f; 2713 mfilt[pos / 32] |= (1 << (pos % 32)); 2714 } 2715 if_maddr_runlock(ifp); 2716 } else 2717 mfilt[0] = mfilt[1] = ~0; 2718 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2719 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2720 __func__, mfilt[0], mfilt[1]); 2721 } 2722 2723 void 2724 ath_mode_init(struct ath_softc *sc) 2725 { 2726 struct ifnet *ifp = sc->sc_ifp; 2727 struct ath_hal *ah = sc->sc_ah; 2728 u_int32_t rfilt; 2729 2730 /* configure rx filter */ 2731 rfilt = ath_calcrxfilter(sc); 2732 ath_hal_setrxfilter(ah, rfilt); 2733 2734 /* configure operational mode */ 2735 ath_hal_setopmode(ah); 2736 2737 DPRINTF(sc, ATH_DEBUG_STATE | ATH_DEBUG_MODE, 2738 "%s: ah=%p, ifp=%p, if_addr=%p\n", 2739 __func__, 2740 ah, 2741 ifp, 2742 (ifp == NULL) ? NULL : ifp->if_addr); 2743 2744 /* handle any link-level address change */ 2745 ath_hal_setmac(ah, IF_LLADDR(ifp)); 2746 2747 /* calculate and install multicast filter */ 2748 ath_update_mcast(ifp); 2749 } 2750 2751 /* 2752 * Set the slot time based on the current setting. 2753 */ 2754 void 2755 ath_setslottime(struct ath_softc *sc) 2756 { 2757 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2758 struct ath_hal *ah = sc->sc_ah; 2759 u_int usec; 2760 2761 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2762 usec = 13; 2763 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2764 usec = 21; 2765 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2766 /* honor short/long slot time only in 11g */ 2767 /* XXX shouldn't honor on pure g or turbo g channel */ 2768 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2769 usec = HAL_SLOT_TIME_9; 2770 else 2771 usec = HAL_SLOT_TIME_20; 2772 } else 2773 usec = HAL_SLOT_TIME_9; 2774 2775 DPRINTF(sc, ATH_DEBUG_RESET, 2776 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2777 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2778 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2779 2780 ath_hal_setslottime(ah, usec); 2781 sc->sc_updateslot = OK; 2782 } 2783 2784 /* 2785 * Callback from the 802.11 layer to update the 2786 * slot time based on the current setting. 2787 */ 2788 static void 2789 ath_updateslot(struct ifnet *ifp) 2790 { 2791 struct ath_softc *sc = ifp->if_softc; 2792 struct ieee80211com *ic = ifp->if_l2com; 2793 2794 /* 2795 * When not coordinating the BSS, change the hardware 2796 * immediately. For other operation we defer the change 2797 * until beacon updates have propagated to the stations. 2798 */ 2799 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2800 ic->ic_opmode == IEEE80211_M_MBSS) 2801 sc->sc_updateslot = UPDATE; 2802 else 2803 ath_setslottime(sc); 2804 } 2805 2806 /* 2807 * Append the contents of src to dst; both queues 2808 * are assumed to be locked. 2809 */ 2810 void 2811 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2812 { 2813 2814 ATH_TXQ_LOCK_ASSERT(dst); 2815 ATH_TXQ_LOCK_ASSERT(src); 2816 2817 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list); 2818 dst->axq_link = src->axq_link; 2819 src->axq_link = NULL; 2820 dst->axq_depth += src->axq_depth; 2821 dst->axq_aggr_depth += src->axq_aggr_depth; 2822 src->axq_depth = 0; 2823 src->axq_aggr_depth = 0; 2824 } 2825 2826 /* 2827 * Reset the hardware, with no loss. 2828 * 2829 * This can't be used for a general case reset. 2830 */ 2831 static void 2832 ath_reset_proc(void *arg, int pending) 2833 { 2834 struct ath_softc *sc = arg; 2835 struct ifnet *ifp = sc->sc_ifp; 2836 2837 #if 0 2838 if_printf(ifp, "%s: resetting\n", __func__); 2839 #endif 2840 ath_reset(ifp, ATH_RESET_NOLOSS); 2841 } 2842 2843 /* 2844 * Reset the hardware after detecting beacons have stopped. 2845 */ 2846 static void 2847 ath_bstuck_proc(void *arg, int pending) 2848 { 2849 struct ath_softc *sc = arg; 2850 struct ifnet *ifp = sc->sc_ifp; 2851 uint32_t hangs = 0; 2852 2853 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) 2854 if_printf(ifp, "bb hang detected (0x%x)\n", hangs); 2855 2856 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2857 sc->sc_bmisscount); 2858 sc->sc_stats.ast_bstuck++; 2859 /* 2860 * This assumes that there's no simultaneous channel mode change 2861 * occuring. 2862 */ 2863 ath_reset(ifp, ATH_RESET_NOLOSS); 2864 } 2865 2866 static void 2867 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2868 { 2869 bus_addr_t *paddr = (bus_addr_t*) arg; 2870 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 2871 *paddr = segs->ds_addr; 2872 } 2873 2874 /* 2875 * Allocate the descriptors and appropriate DMA tag/setup. 2876 * 2877 * For some situations (eg EDMA TX completion), there isn't a requirement 2878 * for the ath_buf entries to be allocated. 2879 */ 2880 int 2881 ath_descdma_alloc_desc(struct ath_softc *sc, 2882 struct ath_descdma *dd, ath_bufhead *head, 2883 const char *name, int ds_size, int ndesc) 2884 { 2885 #define DS2PHYS(_dd, _ds) \ 2886 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2887 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 2888 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 2889 struct ifnet *ifp = sc->sc_ifp; 2890 int error; 2891 2892 dd->dd_descsize = ds_size; 2893 2894 DPRINTF(sc, ATH_DEBUG_RESET, 2895 "%s: %s DMA: %u desc, %d bytes per descriptor\n", 2896 __func__, name, ndesc, dd->dd_descsize); 2897 2898 dd->dd_name = name; 2899 dd->dd_desc_len = dd->dd_descsize * ndesc; 2900 2901 /* 2902 * Merlin work-around: 2903 * Descriptors that cross the 4KB boundary can't be used. 2904 * Assume one skipped descriptor per 4KB page. 2905 */ 2906 if (! ath_hal_split4ktrans(sc->sc_ah)) { 2907 int numpages = dd->dd_desc_len / 4096; 2908 dd->dd_desc_len += ds_size * numpages; 2909 } 2910 2911 /* 2912 * Setup DMA descriptor area. 2913 */ 2914 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 2915 PAGE_SIZE, 0, /* alignment, bounds */ 2916 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2917 BUS_SPACE_MAXADDR, /* highaddr */ 2918 NULL, NULL, /* filter, filterarg */ 2919 dd->dd_desc_len, /* maxsize */ 2920 1, /* nsegments */ 2921 dd->dd_desc_len, /* maxsegsize */ 2922 BUS_DMA_ALLOCNOW, /* flags */ 2923 NULL, /* lockfunc */ 2924 NULL, /* lockarg */ 2925 &dd->dd_dmat); 2926 if (error != 0) { 2927 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 2928 return error; 2929 } 2930 2931 /* allocate descriptors */ 2932 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 2933 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 2934 &dd->dd_dmamap); 2935 if (error != 0) { 2936 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2937 "error %u\n", ndesc, dd->dd_name, error); 2938 goto fail1; 2939 } 2940 2941 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 2942 dd->dd_desc, dd->dd_desc_len, 2943 ath_load_cb, &dd->dd_desc_paddr, 2944 BUS_DMA_NOWAIT); 2945 if (error != 0) { 2946 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2947 dd->dd_name, error); 2948 goto fail2; 2949 } 2950 2951 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2952 __func__, dd->dd_name, (uint8_t *) dd->dd_desc, 2953 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr, 2954 /*XXX*/ (u_long) dd->dd_desc_len); 2955 2956 return (0); 2957 2958 fail2: 2959 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2960 fail1: 2961 bus_dma_tag_destroy(dd->dd_dmat); 2962 memset(dd, 0, sizeof(*dd)); 2963 return error; 2964 #undef DS2PHYS 2965 #undef ATH_DESC_4KB_BOUND_CHECK 2966 } 2967 2968 int 2969 ath_descdma_setup(struct ath_softc *sc, 2970 struct ath_descdma *dd, ath_bufhead *head, 2971 const char *name, int ds_size, int nbuf, int ndesc) 2972 { 2973 #define DS2PHYS(_dd, _ds) \ 2974 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2975 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 2976 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 2977 struct ifnet *ifp = sc->sc_ifp; 2978 uint8_t *ds; 2979 struct ath_buf *bf; 2980 int i, bsize, error; 2981 2982 /* Allocate descriptors */ 2983 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size, 2984 nbuf * ndesc); 2985 2986 /* Assume any errors during allocation were dealt with */ 2987 if (error != 0) { 2988 return (error); 2989 } 2990 2991 ds = (uint8_t *) dd->dd_desc; 2992 2993 /* allocate rx buffers */ 2994 bsize = sizeof(struct ath_buf) * nbuf; 2995 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2996 if (bf == NULL) { 2997 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2998 dd->dd_name, bsize); 2999 goto fail3; 3000 } 3001 dd->dd_bufptr = bf; 3002 3003 TAILQ_INIT(head); 3004 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) { 3005 bf->bf_desc = (struct ath_desc *) ds; 3006 bf->bf_daddr = DS2PHYS(dd, ds); 3007 if (! ath_hal_split4ktrans(sc->sc_ah)) { 3008 /* 3009 * Merlin WAR: Skip descriptor addresses which 3010 * cause 4KB boundary crossing along any point 3011 * in the descriptor. 3012 */ 3013 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr, 3014 dd->dd_descsize)) { 3015 /* Start at the next page */ 3016 ds += 0x1000 - (bf->bf_daddr & 0xFFF); 3017 bf->bf_desc = (struct ath_desc *) ds; 3018 bf->bf_daddr = DS2PHYS(dd, ds); 3019 } 3020 } 3021 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3022 &bf->bf_dmamap); 3023 if (error != 0) { 3024 if_printf(ifp, "unable to create dmamap for %s " 3025 "buffer %u, error %u\n", dd->dd_name, i, error); 3026 ath_descdma_cleanup(sc, dd, head); 3027 return error; 3028 } 3029 bf->bf_lastds = bf->bf_desc; /* Just an initial value */ 3030 TAILQ_INSERT_TAIL(head, bf, bf_list); 3031 } 3032 3033 /* 3034 * XXX TODO: ensure that ds doesn't overflow the descriptor 3035 * allocation otherwise weird stuff will occur and crash your 3036 * machine. 3037 */ 3038 return 0; 3039 /* XXX this should likely just call ath_descdma_cleanup() */ 3040 fail3: 3041 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3042 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3043 bus_dma_tag_destroy(dd->dd_dmat); 3044 memset(dd, 0, sizeof(*dd)); 3045 return error; 3046 #undef DS2PHYS 3047 #undef ATH_DESC_4KB_BOUND_CHECK 3048 } 3049 3050 /* 3051 * Allocate ath_buf entries but no descriptor contents. 3052 * 3053 * This is for RX EDMA where the descriptors are the header part of 3054 * the RX buffer. 3055 */ 3056 int 3057 ath_descdma_setup_rx_edma(struct ath_softc *sc, 3058 struct ath_descdma *dd, ath_bufhead *head, 3059 const char *name, int nbuf, int rx_status_len) 3060 { 3061 struct ifnet *ifp = sc->sc_ifp; 3062 struct ath_buf *bf; 3063 int i, bsize, error; 3064 3065 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n", 3066 __func__, name, nbuf); 3067 3068 dd->dd_name = name; 3069 /* 3070 * This is (mostly) purely for show. We're not allocating any actual 3071 * descriptors here as EDMA RX has the descriptor be part 3072 * of the RX buffer. 3073 * 3074 * However, dd_desc_len is used by ath_descdma_free() to determine 3075 * whether we have already freed this DMA mapping. 3076 */ 3077 dd->dd_desc_len = rx_status_len * nbuf; 3078 dd->dd_descsize = rx_status_len; 3079 3080 /* allocate rx buffers */ 3081 bsize = sizeof(struct ath_buf) * nbuf; 3082 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3083 if (bf == NULL) { 3084 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3085 dd->dd_name, bsize); 3086 error = ENOMEM; 3087 goto fail3; 3088 } 3089 dd->dd_bufptr = bf; 3090 3091 TAILQ_INIT(head); 3092 for (i = 0; i < nbuf; i++, bf++) { 3093 bf->bf_desc = NULL; 3094 bf->bf_daddr = 0; 3095 bf->bf_lastds = NULL; /* Just an initial value */ 3096 3097 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3098 &bf->bf_dmamap); 3099 if (error != 0) { 3100 if_printf(ifp, "unable to create dmamap for %s " 3101 "buffer %u, error %u\n", dd->dd_name, i, error); 3102 ath_descdma_cleanup(sc, dd, head); 3103 return error; 3104 } 3105 TAILQ_INSERT_TAIL(head, bf, bf_list); 3106 } 3107 return 0; 3108 fail3: 3109 memset(dd, 0, sizeof(*dd)); 3110 return error; 3111 } 3112 3113 void 3114 ath_descdma_cleanup(struct ath_softc *sc, 3115 struct ath_descdma *dd, ath_bufhead *head) 3116 { 3117 struct ath_buf *bf; 3118 struct ieee80211_node *ni; 3119 3120 if (dd->dd_dmamap != 0) { 3121 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3122 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3123 bus_dma_tag_destroy(dd->dd_dmat); 3124 } 3125 3126 if (head != NULL) { 3127 TAILQ_FOREACH(bf, head, bf_list) { 3128 if (bf->bf_m) { 3129 m_freem(bf->bf_m); 3130 bf->bf_m = NULL; 3131 } 3132 if (bf->bf_dmamap != NULL) { 3133 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3134 bf->bf_dmamap = NULL; 3135 } 3136 ni = bf->bf_node; 3137 bf->bf_node = NULL; 3138 if (ni != NULL) { 3139 /* 3140 * Reclaim node reference. 3141 */ 3142 ieee80211_free_node(ni); 3143 } 3144 } 3145 } 3146 3147 if (head != NULL) 3148 TAILQ_INIT(head); 3149 3150 if (dd->dd_bufptr != NULL) 3151 free(dd->dd_bufptr, M_ATHDEV); 3152 memset(dd, 0, sizeof(*dd)); 3153 } 3154 3155 static int 3156 ath_desc_alloc(struct ath_softc *sc) 3157 { 3158 int error; 3159 3160 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3161 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_TXDESC); 3162 if (error != 0) { 3163 return error; 3164 } 3165 sc->sc_txbuf_cnt = ath_txbuf; 3166 3167 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt, 3168 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt, 3169 ATH_TXDESC); 3170 if (error != 0) { 3171 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3172 return error; 3173 } 3174 3175 /* 3176 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the 3177 * flag doesn't have to be set in ath_getbuf_locked(). 3178 */ 3179 3180 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3181 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1); 3182 if (error != 0) { 3183 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3184 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3185 &sc->sc_txbuf_mgmt); 3186 return error; 3187 } 3188 return 0; 3189 } 3190 3191 static void 3192 ath_desc_free(struct ath_softc *sc) 3193 { 3194 3195 if (sc->sc_bdma.dd_desc_len != 0) 3196 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3197 if (sc->sc_txdma.dd_desc_len != 0) 3198 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3199 if (sc->sc_txdma_mgmt.dd_desc_len != 0) 3200 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3201 &sc->sc_txbuf_mgmt); 3202 } 3203 3204 static struct ieee80211_node * 3205 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3206 { 3207 struct ieee80211com *ic = vap->iv_ic; 3208 struct ath_softc *sc = ic->ic_ifp->if_softc; 3209 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3210 struct ath_node *an; 3211 3212 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3213 if (an == NULL) { 3214 /* XXX stat+msg */ 3215 return NULL; 3216 } 3217 ath_rate_node_init(sc, an); 3218 3219 /* Setup the mutex - there's no associd yet so set the name to NULL */ 3220 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p", 3221 device_get_nameunit(sc->sc_dev), an); 3222 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF); 3223 3224 /* XXX setup ath_tid */ 3225 ath_tx_tid_init(sc, an); 3226 3227 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3228 return &an->an_node; 3229 } 3230 3231 static void 3232 ath_node_cleanup(struct ieee80211_node *ni) 3233 { 3234 struct ieee80211com *ic = ni->ni_ic; 3235 struct ath_softc *sc = ic->ic_ifp->if_softc; 3236 3237 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */ 3238 ath_tx_node_flush(sc, ATH_NODE(ni)); 3239 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3240 sc->sc_node_cleanup(ni); 3241 } 3242 3243 static void 3244 ath_node_free(struct ieee80211_node *ni) 3245 { 3246 struct ieee80211com *ic = ni->ni_ic; 3247 struct ath_softc *sc = ic->ic_ifp->if_softc; 3248 3249 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3250 mtx_destroy(&ATH_NODE(ni)->an_mtx); 3251 sc->sc_node_free(ni); 3252 } 3253 3254 static void 3255 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3256 { 3257 struct ieee80211com *ic = ni->ni_ic; 3258 struct ath_softc *sc = ic->ic_ifp->if_softc; 3259 struct ath_hal *ah = sc->sc_ah; 3260 3261 *rssi = ic->ic_node_getrssi(ni); 3262 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3263 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3264 else 3265 *noise = -95; /* nominally correct */ 3266 } 3267 3268 /* 3269 * Set the default antenna. 3270 */ 3271 void 3272 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3273 { 3274 struct ath_hal *ah = sc->sc_ah; 3275 3276 /* XXX block beacon interrupts */ 3277 ath_hal_setdefantenna(ah, antenna); 3278 if (sc->sc_defant != antenna) 3279 sc->sc_stats.ast_ant_defswitch++; 3280 sc->sc_defant = antenna; 3281 sc->sc_rxotherant = 0; 3282 } 3283 3284 static void 3285 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 3286 { 3287 txq->axq_qnum = qnum; 3288 txq->axq_ac = 0; 3289 txq->axq_depth = 0; 3290 txq->axq_aggr_depth = 0; 3291 txq->axq_intrcnt = 0; 3292 txq->axq_link = NULL; 3293 txq->axq_softc = sc; 3294 TAILQ_INIT(&txq->axq_q); 3295 TAILQ_INIT(&txq->axq_tidq); 3296 ATH_TXQ_LOCK_INIT(sc, txq); 3297 } 3298 3299 /* 3300 * Setup a h/w transmit queue. 3301 */ 3302 static struct ath_txq * 3303 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3304 { 3305 #define N(a) (sizeof(a)/sizeof(a[0])) 3306 struct ath_hal *ah = sc->sc_ah; 3307 HAL_TXQ_INFO qi; 3308 int qnum; 3309 3310 memset(&qi, 0, sizeof(qi)); 3311 qi.tqi_subtype = subtype; 3312 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3313 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3314 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3315 /* 3316 * Enable interrupts only for EOL and DESC conditions. 3317 * We mark tx descriptors to receive a DESC interrupt 3318 * when a tx queue gets deep; otherwise waiting for the 3319 * EOL to reap descriptors. Note that this is done to 3320 * reduce interrupt load and this only defers reaping 3321 * descriptors, never transmitting frames. Aside from 3322 * reducing interrupts this also permits more concurrency. 3323 * The only potential downside is if the tx queue backs 3324 * up in which case the top half of the kernel may backup 3325 * due to a lack of tx descriptors. 3326 */ 3327 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3328 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3329 if (qnum == -1) { 3330 /* 3331 * NB: don't print a message, this happens 3332 * normally on parts with too few tx queues 3333 */ 3334 return NULL; 3335 } 3336 if (qnum >= N(sc->sc_txq)) { 3337 device_printf(sc->sc_dev, 3338 "hal qnum %u out of range, max %zu!\n", 3339 qnum, N(sc->sc_txq)); 3340 ath_hal_releasetxqueue(ah, qnum); 3341 return NULL; 3342 } 3343 if (!ATH_TXQ_SETUP(sc, qnum)) { 3344 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 3345 sc->sc_txqsetup |= 1<<qnum; 3346 } 3347 return &sc->sc_txq[qnum]; 3348 #undef N 3349 } 3350 3351 /* 3352 * Setup a hardware data transmit queue for the specified 3353 * access control. The hal may not support all requested 3354 * queues in which case it will return a reference to a 3355 * previously setup queue. We record the mapping from ac's 3356 * to h/w queues for use by ath_tx_start and also track 3357 * the set of h/w queues being used to optimize work in the 3358 * transmit interrupt handler and related routines. 3359 */ 3360 static int 3361 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3362 { 3363 #define N(a) (sizeof(a)/sizeof(a[0])) 3364 struct ath_txq *txq; 3365 3366 if (ac >= N(sc->sc_ac2q)) { 3367 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3368 ac, N(sc->sc_ac2q)); 3369 return 0; 3370 } 3371 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3372 if (txq != NULL) { 3373 txq->axq_ac = ac; 3374 sc->sc_ac2q[ac] = txq; 3375 return 1; 3376 } else 3377 return 0; 3378 #undef N 3379 } 3380 3381 /* 3382 * Update WME parameters for a transmit queue. 3383 */ 3384 static int 3385 ath_txq_update(struct ath_softc *sc, int ac) 3386 { 3387 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3388 #define ATH_TXOP_TO_US(v) (v<<5) 3389 struct ifnet *ifp = sc->sc_ifp; 3390 struct ieee80211com *ic = ifp->if_l2com; 3391 struct ath_txq *txq = sc->sc_ac2q[ac]; 3392 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3393 struct ath_hal *ah = sc->sc_ah; 3394 HAL_TXQ_INFO qi; 3395 3396 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3397 #ifdef IEEE80211_SUPPORT_TDMA 3398 if (sc->sc_tdma) { 3399 /* 3400 * AIFS is zero so there's no pre-transmit wait. The 3401 * burst time defines the slot duration and is configured 3402 * through net80211. The QCU is setup to not do post-xmit 3403 * back off, lockout all lower-priority QCU's, and fire 3404 * off the DMA beacon alert timer which is setup based 3405 * on the slot configuration. 3406 */ 3407 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 3408 | HAL_TXQ_TXERRINT_ENABLE 3409 | HAL_TXQ_TXURNINT_ENABLE 3410 | HAL_TXQ_TXEOLINT_ENABLE 3411 | HAL_TXQ_DBA_GATED 3412 | HAL_TXQ_BACKOFF_DISABLE 3413 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 3414 ; 3415 qi.tqi_aifs = 0; 3416 /* XXX +dbaprep? */ 3417 qi.tqi_readyTime = sc->sc_tdmaslotlen; 3418 qi.tqi_burstTime = qi.tqi_readyTime; 3419 } else { 3420 #endif 3421 /* 3422 * XXX shouldn't this just use the default flags 3423 * used in the previous queue setup? 3424 */ 3425 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 3426 | HAL_TXQ_TXERRINT_ENABLE 3427 | HAL_TXQ_TXDESCINT_ENABLE 3428 | HAL_TXQ_TXURNINT_ENABLE 3429 | HAL_TXQ_TXEOLINT_ENABLE 3430 ; 3431 qi.tqi_aifs = wmep->wmep_aifsn; 3432 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3433 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3434 qi.tqi_readyTime = 0; 3435 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3436 #ifdef IEEE80211_SUPPORT_TDMA 3437 } 3438 #endif 3439 3440 DPRINTF(sc, ATH_DEBUG_RESET, 3441 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 3442 __func__, txq->axq_qnum, qi.tqi_qflags, 3443 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 3444 3445 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3446 if_printf(ifp, "unable to update hardware queue " 3447 "parameters for %s traffic!\n", 3448 ieee80211_wme_acnames[ac]); 3449 return 0; 3450 } else { 3451 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3452 return 1; 3453 } 3454 #undef ATH_TXOP_TO_US 3455 #undef ATH_EXPONENT_TO_VALUE 3456 } 3457 3458 /* 3459 * Callback from the 802.11 layer to update WME parameters. 3460 */ 3461 int 3462 ath_wme_update(struct ieee80211com *ic) 3463 { 3464 struct ath_softc *sc = ic->ic_ifp->if_softc; 3465 3466 return !ath_txq_update(sc, WME_AC_BE) || 3467 !ath_txq_update(sc, WME_AC_BK) || 3468 !ath_txq_update(sc, WME_AC_VI) || 3469 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3470 } 3471 3472 /* 3473 * Reclaim resources for a setup queue. 3474 */ 3475 static void 3476 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3477 { 3478 3479 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3480 ATH_TXQ_LOCK_DESTROY(txq); 3481 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3482 } 3483 3484 /* 3485 * Reclaim all tx queue resources. 3486 */ 3487 static void 3488 ath_tx_cleanup(struct ath_softc *sc) 3489 { 3490 int i; 3491 3492 ATH_TXBUF_LOCK_DESTROY(sc); 3493 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3494 if (ATH_TXQ_SETUP(sc, i)) 3495 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3496 } 3497 3498 /* 3499 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 3500 * using the current rates in sc_rixmap. 3501 */ 3502 int 3503 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 3504 { 3505 int rix = sc->sc_rixmap[rate]; 3506 /* NB: return lowest rix for invalid rate */ 3507 return (rix == 0xff ? 0 : rix); 3508 } 3509 3510 static void 3511 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts, 3512 struct ath_buf *bf) 3513 { 3514 struct ieee80211_node *ni = bf->bf_node; 3515 struct ifnet *ifp = sc->sc_ifp; 3516 struct ieee80211com *ic = ifp->if_l2com; 3517 int sr, lr, pri; 3518 3519 if (ts->ts_status == 0) { 3520 u_int8_t txant = ts->ts_antenna; 3521 sc->sc_stats.ast_ant_tx[txant]++; 3522 sc->sc_ant_tx[txant]++; 3523 if (ts->ts_finaltsi != 0) 3524 sc->sc_stats.ast_tx_altrate++; 3525 pri = M_WME_GETAC(bf->bf_m); 3526 if (pri >= WME_AC_VO) 3527 ic->ic_wme.wme_hipri_traffic++; 3528 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) 3529 ni->ni_inact = ni->ni_inact_reload; 3530 } else { 3531 if (ts->ts_status & HAL_TXERR_XRETRY) 3532 sc->sc_stats.ast_tx_xretries++; 3533 if (ts->ts_status & HAL_TXERR_FIFO) 3534 sc->sc_stats.ast_tx_fifoerr++; 3535 if (ts->ts_status & HAL_TXERR_FILT) 3536 sc->sc_stats.ast_tx_filtered++; 3537 if (ts->ts_status & HAL_TXERR_XTXOP) 3538 sc->sc_stats.ast_tx_xtxop++; 3539 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED) 3540 sc->sc_stats.ast_tx_timerexpired++; 3541 3542 if (ts->ts_status & HAL_TX_DATA_UNDERRUN) 3543 sc->sc_stats.ast_tx_data_underrun++; 3544 if (ts->ts_status & HAL_TX_DELIM_UNDERRUN) 3545 sc->sc_stats.ast_tx_delim_underrun++; 3546 3547 if (bf->bf_m->m_flags & M_FF) 3548 sc->sc_stats.ast_ff_txerr++; 3549 } 3550 /* XXX when is this valid? */ 3551 if (ts->ts_status & HAL_TX_DESC_CFG_ERR) 3552 sc->sc_stats.ast_tx_desccfgerr++; 3553 3554 sr = ts->ts_shortretry; 3555 lr = ts->ts_longretry; 3556 sc->sc_stats.ast_tx_shortretry += sr; 3557 sc->sc_stats.ast_tx_longretry += lr; 3558 3559 } 3560 3561 /* 3562 * The default completion. If fail is 1, this means 3563 * "please don't retry the frame, and just return -1 status 3564 * to the net80211 stack. 3565 */ 3566 void 3567 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3568 { 3569 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3570 int st; 3571 3572 if (fail == 1) 3573 st = -1; 3574 else 3575 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ? 3576 ts->ts_status : HAL_TXERR_XRETRY; 3577 3578 if (bf->bf_state.bfs_dobaw) 3579 device_printf(sc->sc_dev, 3580 "%s: bf %p: seqno %d: dobaw should've been cleared!\n", 3581 __func__, 3582 bf, 3583 SEQNO(bf->bf_state.bfs_seqno)); 3584 if (bf->bf_next != NULL) 3585 device_printf(sc->sc_dev, 3586 "%s: bf %p: seqno %d: bf_next not NULL!\n", 3587 __func__, 3588 bf, 3589 SEQNO(bf->bf_state.bfs_seqno)); 3590 3591 /* 3592 * Check if the node software queue is empty; if so 3593 * then clear the TIM. 3594 * 3595 * This needs to be done before the buffer is freed as 3596 * otherwise the node reference will have been released 3597 * and the node may not actually exist any longer. 3598 * 3599 * XXX I don't like this belonging here, but it's cleaner 3600 * to do it here right now then all the other places 3601 * where ath_tx_default_comp() is called. 3602 * 3603 * XXX TODO: during drain, ensure that the callback is 3604 * being called so we get a chance to update the TIM. 3605 */ 3606 if (bf->bf_node) 3607 ath_tx_update_tim(sc, bf->bf_node, 0); 3608 3609 /* 3610 * Do any tx complete callback. Note this must 3611 * be done before releasing the node reference. 3612 * This will free the mbuf, release the net80211 3613 * node and recycle the ath_buf. 3614 */ 3615 ath_tx_freebuf(sc, bf, st); 3616 } 3617 3618 /* 3619 * Update rate control with the given completion status. 3620 */ 3621 void 3622 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 3623 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen, 3624 int nframes, int nbad) 3625 { 3626 struct ath_node *an; 3627 3628 /* Only for unicast frames */ 3629 if (ni == NULL) 3630 return; 3631 3632 an = ATH_NODE(ni); 3633 ATH_NODE_UNLOCK_ASSERT(an); 3634 3635 if ((ts->ts_status & HAL_TXERR_FILT) == 0) { 3636 ATH_NODE_LOCK(an); 3637 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad); 3638 ATH_NODE_UNLOCK(an); 3639 } 3640 } 3641 3642 /* 3643 * Update the busy status of the last frame on the free list. 3644 * When doing TDMA, the busy flag tracks whether the hardware 3645 * currently points to this buffer or not, and thus gated DMA 3646 * may restart by re-reading the last descriptor in this 3647 * buffer. 3648 * 3649 * This should be called in the completion function once one 3650 * of the buffers has been used. 3651 */ 3652 static void 3653 ath_tx_update_busy(struct ath_softc *sc) 3654 { 3655 struct ath_buf *last; 3656 3657 /* 3658 * Since the last frame may still be marked 3659 * as ATH_BUF_BUSY, unmark it here before 3660 * finishing the frame processing. 3661 * Since we've completed a frame (aggregate 3662 * or otherwise), the hardware has moved on 3663 * and is no longer referencing the previous 3664 * descriptor. 3665 */ 3666 ATH_TXBUF_LOCK_ASSERT(sc); 3667 last = TAILQ_LAST(&sc->sc_txbuf_mgmt, ath_bufhead_s); 3668 if (last != NULL) 3669 last->bf_flags &= ~ATH_BUF_BUSY; 3670 last = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s); 3671 if (last != NULL) 3672 last->bf_flags &= ~ATH_BUF_BUSY; 3673 } 3674 3675 /* 3676 * Process the completion of the given buffer. 3677 * 3678 * This calls the rate control update and then the buffer completion. 3679 * This will either free the buffer or requeue it. In any case, the 3680 * bf pointer should be treated as invalid after this function is called. 3681 */ 3682 void 3683 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq, 3684 struct ath_tx_status *ts, struct ath_buf *bf) 3685 { 3686 struct ieee80211_node *ni = bf->bf_node; 3687 struct ath_node *an = NULL; 3688 3689 ATH_TXQ_UNLOCK_ASSERT(txq); 3690 3691 /* If unicast frame, update general statistics */ 3692 if (ni != NULL) { 3693 an = ATH_NODE(ni); 3694 /* update statistics */ 3695 ath_tx_update_stats(sc, ts, bf); 3696 } 3697 3698 /* 3699 * Call the completion handler. 3700 * The completion handler is responsible for 3701 * calling the rate control code. 3702 * 3703 * Frames with no completion handler get the 3704 * rate control code called here. 3705 */ 3706 if (bf->bf_comp == NULL) { 3707 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 3708 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) { 3709 /* 3710 * XXX assume this isn't an aggregate 3711 * frame. 3712 */ 3713 ath_tx_update_ratectrl(sc, ni, 3714 bf->bf_state.bfs_rc, ts, 3715 bf->bf_state.bfs_pktlen, 1, 3716 (ts->ts_status == 0 ? 0 : 1)); 3717 } 3718 ath_tx_default_comp(sc, bf, 0); 3719 } else 3720 bf->bf_comp(sc, bf, 0); 3721 } 3722 3723 3724 3725 /* 3726 * Process completed xmit descriptors from the specified queue. 3727 * Kick the packet scheduler if needed. This can occur from this 3728 * particular task. 3729 */ 3730 static int 3731 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched) 3732 { 3733 struct ath_hal *ah = sc->sc_ah; 3734 struct ath_buf *bf; 3735 struct ath_desc *ds; 3736 struct ath_tx_status *ts; 3737 struct ieee80211_node *ni; 3738 #ifdef IEEE80211_SUPPORT_SUPERG 3739 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3740 #endif /* IEEE80211_SUPPORT_SUPERG */ 3741 int nacked; 3742 HAL_STATUS status; 3743 3744 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3745 __func__, txq->axq_qnum, 3746 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3747 txq->axq_link); 3748 3749 ATH_KTR(sc, ATH_KTR_TXCOMP, 4, 3750 "ath_tx_processq: txq=%u head %p link %p depth %p", 3751 txq->axq_qnum, 3752 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3753 txq->axq_link, 3754 txq->axq_depth); 3755 3756 nacked = 0; 3757 for (;;) { 3758 ATH_TXQ_LOCK(txq); 3759 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3760 bf = TAILQ_FIRST(&txq->axq_q); 3761 if (bf == NULL) { 3762 ATH_TXQ_UNLOCK(txq); 3763 break; 3764 } 3765 ds = bf->bf_lastds; /* XXX must be setup correctly! */ 3766 ts = &bf->bf_status.ds_txstat; 3767 3768 status = ath_hal_txprocdesc(ah, ds, ts); 3769 #ifdef ATH_DEBUG 3770 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3771 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 3772 status == HAL_OK); 3773 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0)) 3774 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 3775 status == HAL_OK); 3776 #endif 3777 #ifdef ATH_DEBUG_ALQ 3778 if (if_ath_alq_checkdebug(&sc->sc_alq, 3779 ATH_ALQ_EDMA_TXSTATUS)) { 3780 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS, 3781 sc->sc_tx_statuslen, 3782 (char *) ds); 3783 } 3784 #endif 3785 3786 if (status == HAL_EINPROGRESS) { 3787 ATH_KTR(sc, ATH_KTR_TXCOMP, 3, 3788 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS", 3789 txq->axq_qnum, bf, ds); 3790 ATH_TXQ_UNLOCK(txq); 3791 break; 3792 } 3793 ATH_TXQ_REMOVE(txq, bf, bf_list); 3794 #ifdef IEEE80211_SUPPORT_TDMA 3795 if (txq->axq_depth > 0) { 3796 /* 3797 * More frames follow. Mark the buffer busy 3798 * so it's not re-used while the hardware may 3799 * still re-read the link field in the descriptor. 3800 * 3801 * Use the last buffer in an aggregate as that 3802 * is where the hardware may be - intermediate 3803 * descriptors won't be "busy". 3804 */ 3805 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 3806 } else 3807 #else 3808 if (txq->axq_depth == 0) 3809 #endif 3810 txq->axq_link = NULL; 3811 if (bf->bf_state.bfs_aggr) 3812 txq->axq_aggr_depth--; 3813 3814 ni = bf->bf_node; 3815 3816 ATH_KTR(sc, ATH_KTR_TXCOMP, 5, 3817 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x", 3818 txq->axq_qnum, bf, ds, ni, ts->ts_status); 3819 /* 3820 * If unicast frame was ack'd update RSSI, 3821 * including the last rx time used to 3822 * workaround phantom bmiss interrupts. 3823 */ 3824 if (ni != NULL && ts->ts_status == 0 && 3825 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 3826 nacked++; 3827 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 3828 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 3829 ts->ts_rssi); 3830 } 3831 ATH_TXQ_UNLOCK(txq); 3832 3833 /* 3834 * Update statistics and call completion 3835 */ 3836 ath_tx_process_buf_completion(sc, txq, ts, bf); 3837 3838 /* XXX at this point, bf and ni may be totally invalid */ 3839 } 3840 #ifdef IEEE80211_SUPPORT_SUPERG 3841 /* 3842 * Flush fast-frame staging queue when traffic slows. 3843 */ 3844 if (txq->axq_depth <= 1) 3845 ieee80211_ff_flush(ic, txq->axq_ac); 3846 #endif 3847 3848 /* Kick the TXQ scheduler */ 3849 if (dosched) { 3850 ATH_TXQ_LOCK(txq); 3851 ath_txq_sched(sc, txq); 3852 ATH_TXQ_UNLOCK(txq); 3853 } 3854 3855 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 3856 "ath_tx_processq: txq=%u: done", 3857 txq->axq_qnum); 3858 3859 return nacked; 3860 } 3861 3862 #define TXQACTIVE(t, q) ( (t) & (1 << (q))) 3863 3864 /* 3865 * Deferred processing of transmit interrupt; special-cased 3866 * for a single hardware transmit queue (e.g. 5210 and 5211). 3867 */ 3868 static void 3869 ath_tx_proc_q0(void *arg, int npending) 3870 { 3871 struct ath_softc *sc = arg; 3872 struct ifnet *ifp = sc->sc_ifp; 3873 uint32_t txqs; 3874 3875 ATH_PCU_LOCK(sc); 3876 sc->sc_txproc_cnt++; 3877 txqs = sc->sc_txq_active; 3878 sc->sc_txq_active &= ~txqs; 3879 ATH_PCU_UNLOCK(sc); 3880 3881 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 3882 "ath_tx_proc_q0: txqs=0x%08x", txqs); 3883 3884 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1)) 3885 /* XXX why is lastrx updated in tx code? */ 3886 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 3887 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 3888 ath_tx_processq(sc, sc->sc_cabq, 1); 3889 IF_LOCK(&ifp->if_snd); 3890 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3891 IF_UNLOCK(&ifp->if_snd); 3892 sc->sc_wd_timer = 0; 3893 3894 if (sc->sc_softled) 3895 ath_led_event(sc, sc->sc_txrix); 3896 3897 ATH_PCU_LOCK(sc); 3898 sc->sc_txproc_cnt--; 3899 ATH_PCU_UNLOCK(sc); 3900 3901 ath_tx_kick(sc); 3902 } 3903 3904 /* 3905 * Deferred processing of transmit interrupt; special-cased 3906 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3907 */ 3908 static void 3909 ath_tx_proc_q0123(void *arg, int npending) 3910 { 3911 struct ath_softc *sc = arg; 3912 struct ifnet *ifp = sc->sc_ifp; 3913 int nacked; 3914 uint32_t txqs; 3915 3916 ATH_PCU_LOCK(sc); 3917 sc->sc_txproc_cnt++; 3918 txqs = sc->sc_txq_active; 3919 sc->sc_txq_active &= ~txqs; 3920 ATH_PCU_UNLOCK(sc); 3921 3922 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 3923 "ath_tx_proc_q0123: txqs=0x%08x", txqs); 3924 3925 /* 3926 * Process each active queue. 3927 */ 3928 nacked = 0; 3929 if (TXQACTIVE(txqs, 0)) 3930 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1); 3931 if (TXQACTIVE(txqs, 1)) 3932 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1); 3933 if (TXQACTIVE(txqs, 2)) 3934 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1); 3935 if (TXQACTIVE(txqs, 3)) 3936 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1); 3937 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 3938 ath_tx_processq(sc, sc->sc_cabq, 1); 3939 if (nacked) 3940 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 3941 3942 IF_LOCK(&ifp->if_snd); 3943 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3944 IF_UNLOCK(&ifp->if_snd); 3945 sc->sc_wd_timer = 0; 3946 3947 if (sc->sc_softled) 3948 ath_led_event(sc, sc->sc_txrix); 3949 3950 ATH_PCU_LOCK(sc); 3951 sc->sc_txproc_cnt--; 3952 ATH_PCU_UNLOCK(sc); 3953 3954 ath_tx_kick(sc); 3955 } 3956 3957 /* 3958 * Deferred processing of transmit interrupt. 3959 */ 3960 static void 3961 ath_tx_proc(void *arg, int npending) 3962 { 3963 struct ath_softc *sc = arg; 3964 struct ifnet *ifp = sc->sc_ifp; 3965 int i, nacked; 3966 uint32_t txqs; 3967 3968 ATH_PCU_LOCK(sc); 3969 sc->sc_txproc_cnt++; 3970 txqs = sc->sc_txq_active; 3971 sc->sc_txq_active &= ~txqs; 3972 ATH_PCU_UNLOCK(sc); 3973 3974 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs); 3975 3976 /* 3977 * Process each active queue. 3978 */ 3979 nacked = 0; 3980 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3981 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i)) 3982 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1); 3983 if (nacked) 3984 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 3985 3986 /* XXX check this inside of IF_LOCK? */ 3987 IF_LOCK(&ifp->if_snd); 3988 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3989 IF_UNLOCK(&ifp->if_snd); 3990 sc->sc_wd_timer = 0; 3991 3992 if (sc->sc_softled) 3993 ath_led_event(sc, sc->sc_txrix); 3994 3995 ATH_PCU_LOCK(sc); 3996 sc->sc_txproc_cnt--; 3997 ATH_PCU_UNLOCK(sc); 3998 3999 ath_tx_kick(sc); 4000 } 4001 #undef TXQACTIVE 4002 4003 /* 4004 * Deferred processing of TXQ rescheduling. 4005 */ 4006 static void 4007 ath_txq_sched_tasklet(void *arg, int npending) 4008 { 4009 struct ath_softc *sc = arg; 4010 int i; 4011 4012 /* XXX is skipping ok? */ 4013 ATH_PCU_LOCK(sc); 4014 #if 0 4015 if (sc->sc_inreset_cnt > 0) { 4016 device_printf(sc->sc_dev, 4017 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 4018 ATH_PCU_UNLOCK(sc); 4019 return; 4020 } 4021 #endif 4022 sc->sc_txproc_cnt++; 4023 ATH_PCU_UNLOCK(sc); 4024 4025 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 4026 if (ATH_TXQ_SETUP(sc, i)) { 4027 ATH_TXQ_LOCK(&sc->sc_txq[i]); 4028 ath_txq_sched(sc, &sc->sc_txq[i]); 4029 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 4030 } 4031 } 4032 4033 ATH_PCU_LOCK(sc); 4034 sc->sc_txproc_cnt--; 4035 ATH_PCU_UNLOCK(sc); 4036 } 4037 4038 void 4039 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf) 4040 { 4041 4042 ATH_TXBUF_LOCK_ASSERT(sc); 4043 4044 if (bf->bf_flags & ATH_BUF_MGMT) 4045 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list); 4046 else { 4047 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4048 sc->sc_txbuf_cnt++; 4049 if (sc->sc_txbuf_cnt > ath_txbuf) { 4050 device_printf(sc->sc_dev, 4051 "%s: sc_txbuf_cnt > %d?\n", 4052 __func__, 4053 ath_txbuf); 4054 sc->sc_txbuf_cnt = ath_txbuf; 4055 } 4056 } 4057 } 4058 4059 void 4060 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf) 4061 { 4062 4063 ATH_TXBUF_LOCK_ASSERT(sc); 4064 4065 if (bf->bf_flags & ATH_BUF_MGMT) 4066 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list); 4067 else { 4068 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 4069 sc->sc_txbuf_cnt++; 4070 if (sc->sc_txbuf_cnt > ATH_TXBUF) { 4071 device_printf(sc->sc_dev, 4072 "%s: sc_txbuf_cnt > %d?\n", 4073 __func__, 4074 ATH_TXBUF); 4075 sc->sc_txbuf_cnt = ATH_TXBUF; 4076 } 4077 } 4078 } 4079 4080 /* 4081 * Return a buffer to the pool and update the 'busy' flag on the 4082 * previous 'tail' entry. 4083 * 4084 * This _must_ only be called when the buffer is involved in a completed 4085 * TX. The logic is that if it was part of an active TX, the previous 4086 * buffer on the list is now not involved in a halted TX DMA queue, waiting 4087 * for restart (eg for TDMA.) 4088 * 4089 * The caller must free the mbuf and recycle the node reference. 4090 */ 4091 void 4092 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf) 4093 { 4094 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4095 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTWRITE); 4096 4097 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__)); 4098 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__)); 4099 4100 ATH_TXBUF_LOCK(sc); 4101 ath_tx_update_busy(sc); 4102 ath_returnbuf_tail(sc, bf); 4103 ATH_TXBUF_UNLOCK(sc); 4104 } 4105 4106 /* 4107 * This is currently used by ath_tx_draintxq() and 4108 * ath_tx_tid_free_pkts(). 4109 * 4110 * It recycles a single ath_buf. 4111 */ 4112 void 4113 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status) 4114 { 4115 struct ieee80211_node *ni = bf->bf_node; 4116 struct mbuf *m0 = bf->bf_m; 4117 4118 bf->bf_node = NULL; 4119 bf->bf_m = NULL; 4120 4121 /* Free the buffer, it's not needed any longer */ 4122 ath_freebuf(sc, bf); 4123 4124 if (ni != NULL) { 4125 /* 4126 * Do any callback and reclaim the node reference. 4127 */ 4128 if (m0->m_flags & M_TXCB) 4129 ieee80211_process_callback(ni, m0, status); 4130 ieee80211_free_node(ni); 4131 } 4132 m_freem(m0); 4133 4134 /* 4135 * XXX the buffer used to be freed -after-, but the DMA map was 4136 * freed where ath_freebuf() now is. I've no idea what this 4137 * will do. 4138 */ 4139 } 4140 4141 void 4142 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4143 { 4144 #ifdef ATH_DEBUG 4145 struct ath_hal *ah = sc->sc_ah; 4146 #endif 4147 struct ath_buf *bf; 4148 u_int ix; 4149 4150 /* 4151 * NB: this assumes output has been stopped and 4152 * we do not need to block ath_tx_proc 4153 */ 4154 ATH_TXBUF_LOCK(sc); 4155 bf = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s); 4156 if (bf != NULL) 4157 bf->bf_flags &= ~ATH_BUF_BUSY; 4158 bf = TAILQ_LAST(&sc->sc_txbuf_mgmt, ath_bufhead_s); 4159 if (bf != NULL) 4160 bf->bf_flags &= ~ATH_BUF_BUSY; 4161 ATH_TXBUF_UNLOCK(sc); 4162 4163 for (ix = 0;; ix++) { 4164 ATH_TXQ_LOCK(txq); 4165 bf = TAILQ_FIRST(&txq->axq_q); 4166 if (bf == NULL) { 4167 txq->axq_link = NULL; 4168 /* 4169 * There's currently no flag that indicates 4170 * a buffer is on the FIFO. So until that 4171 * occurs, just clear the FIFO counter here. 4172 * 4173 * Yes, this means that if something in parallel 4174 * is pushing things onto this TXQ and pushing 4175 * _that_ into the hardware, things will get 4176 * very fruity very quickly. 4177 */ 4178 txq->axq_fifo_depth = 0; 4179 ATH_TXQ_UNLOCK(txq); 4180 break; 4181 } 4182 ATH_TXQ_REMOVE(txq, bf, bf_list); 4183 if (bf->bf_state.bfs_aggr) 4184 txq->axq_aggr_depth--; 4185 #ifdef ATH_DEBUG 4186 if (sc->sc_debug & ATH_DEBUG_RESET) { 4187 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 4188 int status = 0; 4189 4190 /* 4191 * EDMA operation has a TX completion FIFO 4192 * separate from the TX descriptor, so this 4193 * method of checking the "completion" status 4194 * is wrong. 4195 */ 4196 if (! sc->sc_isedma) { 4197 status = (ath_hal_txprocdesc(ah, 4198 bf->bf_lastds, 4199 &bf->bf_status.ds_txstat) == HAL_OK); 4200 } 4201 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status); 4202 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 4203 bf->bf_m->m_len, 0, -1); 4204 } 4205 #endif /* ATH_DEBUG */ 4206 /* 4207 * Since we're now doing magic in the completion 4208 * functions, we -must- call it for aggregation 4209 * destinations or BAW tracking will get upset. 4210 */ 4211 /* 4212 * Clear ATH_BUF_BUSY; the completion handler 4213 * will free the buffer. 4214 */ 4215 ATH_TXQ_UNLOCK(txq); 4216 bf->bf_flags &= ~ATH_BUF_BUSY; 4217 if (bf->bf_comp) 4218 bf->bf_comp(sc, bf, 1); 4219 else 4220 ath_tx_default_comp(sc, bf, 1); 4221 } 4222 4223 /* 4224 * Drain software queued frames which are on 4225 * active TIDs. 4226 */ 4227 ath_tx_txq_drain(sc, txq); 4228 } 4229 4230 static void 4231 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4232 { 4233 struct ath_hal *ah = sc->sc_ah; 4234 4235 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4236 __func__, txq->axq_qnum, 4237 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4238 txq->axq_link); 4239 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4240 } 4241 4242 int 4243 ath_stoptxdma(struct ath_softc *sc) 4244 { 4245 struct ath_hal *ah = sc->sc_ah; 4246 int i; 4247 4248 /* XXX return value */ 4249 if (sc->sc_invalid) 4250 return 0; 4251 4252 if (!sc->sc_invalid) { 4253 /* don't touch the hardware if marked invalid */ 4254 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4255 __func__, sc->sc_bhalq, 4256 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 4257 NULL); 4258 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4259 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4260 if (ATH_TXQ_SETUP(sc, i)) 4261 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4262 } 4263 4264 return 1; 4265 } 4266 4267 /* 4268 * Drain the transmit queues and reclaim resources. 4269 */ 4270 void 4271 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 4272 { 4273 #ifdef ATH_DEBUG 4274 struct ath_hal *ah = sc->sc_ah; 4275 #endif 4276 struct ifnet *ifp = sc->sc_ifp; 4277 int i; 4278 4279 (void) ath_stoptxdma(sc); 4280 4281 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 4282 /* 4283 * XXX TODO: should we just handle the completed TX frames 4284 * here, whether or not the reset is a full one or not? 4285 */ 4286 if (ATH_TXQ_SETUP(sc, i)) { 4287 if (reset_type == ATH_RESET_NOLOSS) 4288 ath_tx_processq(sc, &sc->sc_txq[i], 0); 4289 else 4290 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4291 } 4292 } 4293 #ifdef ATH_DEBUG 4294 if (sc->sc_debug & ATH_DEBUG_RESET) { 4295 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf); 4296 if (bf != NULL && bf->bf_m != NULL) { 4297 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 4298 ath_hal_txprocdesc(ah, bf->bf_lastds, 4299 &bf->bf_status.ds_txstat) == HAL_OK); 4300 ieee80211_dump_pkt(ifp->if_l2com, 4301 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 4302 0, -1); 4303 } 4304 } 4305 #endif /* ATH_DEBUG */ 4306 IF_LOCK(&ifp->if_snd); 4307 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4308 IF_UNLOCK(&ifp->if_snd); 4309 sc->sc_wd_timer = 0; 4310 } 4311 4312 /* 4313 * Update internal state after a channel change. 4314 */ 4315 static void 4316 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4317 { 4318 enum ieee80211_phymode mode; 4319 4320 /* 4321 * Change channels and update the h/w rate map 4322 * if we're switching; e.g. 11a to 11b/g. 4323 */ 4324 mode = ieee80211_chan2mode(chan); 4325 if (mode != sc->sc_curmode) 4326 ath_setcurmode(sc, mode); 4327 sc->sc_curchan = chan; 4328 } 4329 4330 /* 4331 * Set/change channels. If the channel is really being changed, 4332 * it's done by resetting the chip. To accomplish this we must 4333 * first cleanup any pending DMA, then restart stuff after a la 4334 * ath_init. 4335 */ 4336 static int 4337 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 4338 { 4339 struct ifnet *ifp = sc->sc_ifp; 4340 struct ieee80211com *ic = ifp->if_l2com; 4341 struct ath_hal *ah = sc->sc_ah; 4342 int ret = 0; 4343 4344 /* Treat this as an interface reset */ 4345 ATH_PCU_UNLOCK_ASSERT(sc); 4346 ATH_UNLOCK_ASSERT(sc); 4347 4348 /* (Try to) stop TX/RX from occuring */ 4349 taskqueue_block(sc->sc_tq); 4350 4351 ATH_PCU_LOCK(sc); 4352 ath_hal_intrset(ah, 0); /* Stop new RX/TX completion */ 4353 ath_txrx_stop_locked(sc); /* Stop pending RX/TX completion */ 4354 if (ath_reset_grablock(sc, 1) == 0) { 4355 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 4356 __func__); 4357 } 4358 ATH_PCU_UNLOCK(sc); 4359 4360 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 4361 __func__, ieee80211_chan2ieee(ic, chan), 4362 chan->ic_freq, chan->ic_flags); 4363 if (chan != sc->sc_curchan) { 4364 HAL_STATUS status; 4365 /* 4366 * To switch channels clear any pending DMA operations; 4367 * wait long enough for the RX fifo to drain, reset the 4368 * hardware at the new frequency, and then re-enable 4369 * the relevant bits of the h/w. 4370 */ 4371 #if 0 4372 ath_hal_intrset(ah, 0); /* disable interrupts */ 4373 #endif 4374 ath_stoprecv(sc, 1); /* turn off frame recv */ 4375 /* 4376 * First, handle completed TX/RX frames. 4377 */ 4378 ath_rx_flush(sc); 4379 ath_draintxq(sc, ATH_RESET_NOLOSS); 4380 /* 4381 * Next, flush the non-scheduled frames. 4382 */ 4383 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */ 4384 4385 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 4386 if_printf(ifp, "%s: unable to reset " 4387 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 4388 __func__, ieee80211_chan2ieee(ic, chan), 4389 chan->ic_freq, chan->ic_flags, status); 4390 ret = EIO; 4391 goto finish; 4392 } 4393 sc->sc_diversity = ath_hal_getdiversity(ah); 4394 4395 /* Let DFS at it in case it's a DFS channel */ 4396 ath_dfs_radar_enable(sc, chan); 4397 4398 /* 4399 * Re-enable rx framework. 4400 */ 4401 if (ath_startrecv(sc) != 0) { 4402 if_printf(ifp, "%s: unable to restart recv logic\n", 4403 __func__); 4404 ret = EIO; 4405 goto finish; 4406 } 4407 4408 /* 4409 * Change channels and update the h/w rate map 4410 * if we're switching; e.g. 11a to 11b/g. 4411 */ 4412 ath_chan_change(sc, chan); 4413 4414 /* 4415 * Reset clears the beacon timers; reset them 4416 * here if needed. 4417 */ 4418 if (sc->sc_beacons) { /* restart beacons */ 4419 #ifdef IEEE80211_SUPPORT_TDMA 4420 if (sc->sc_tdma) 4421 ath_tdma_config(sc, NULL); 4422 else 4423 #endif 4424 ath_beacon_config(sc, NULL); 4425 } 4426 4427 /* 4428 * Re-enable interrupts. 4429 */ 4430 #if 0 4431 ath_hal_intrset(ah, sc->sc_imask); 4432 #endif 4433 } 4434 4435 finish: 4436 ATH_PCU_LOCK(sc); 4437 sc->sc_inreset_cnt--; 4438 /* XXX only do this if sc_inreset_cnt == 0? */ 4439 ath_hal_intrset(ah, sc->sc_imask); 4440 ATH_PCU_UNLOCK(sc); 4441 4442 IF_LOCK(&ifp->if_snd); 4443 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4444 IF_UNLOCK(&ifp->if_snd); 4445 ath_txrx_start(sc); 4446 /* XXX ath_start? */ 4447 4448 return ret; 4449 } 4450 4451 /* 4452 * Periodically recalibrate the PHY to account 4453 * for temperature/environment changes. 4454 */ 4455 static void 4456 ath_calibrate(void *arg) 4457 { 4458 struct ath_softc *sc = arg; 4459 struct ath_hal *ah = sc->sc_ah; 4460 struct ifnet *ifp = sc->sc_ifp; 4461 struct ieee80211com *ic = ifp->if_l2com; 4462 HAL_BOOL longCal, isCalDone = AH_TRUE; 4463 HAL_BOOL aniCal, shortCal = AH_FALSE; 4464 int nextcal; 4465 4466 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 4467 goto restart; 4468 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 4469 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000); 4470 if (sc->sc_doresetcal) 4471 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000); 4472 4473 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal); 4474 if (aniCal) { 4475 sc->sc_stats.ast_ani_cal++; 4476 sc->sc_lastani = ticks; 4477 ath_hal_ani_poll(ah, sc->sc_curchan); 4478 } 4479 4480 if (longCal) { 4481 sc->sc_stats.ast_per_cal++; 4482 sc->sc_lastlongcal = ticks; 4483 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4484 /* 4485 * Rfgain is out of bounds, reset the chip 4486 * to load new gain values. 4487 */ 4488 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4489 "%s: rfgain change\n", __func__); 4490 sc->sc_stats.ast_per_rfgain++; 4491 sc->sc_resetcal = 0; 4492 sc->sc_doresetcal = AH_TRUE; 4493 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 4494 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 4495 return; 4496 } 4497 /* 4498 * If this long cal is after an idle period, then 4499 * reset the data collection state so we start fresh. 4500 */ 4501 if (sc->sc_resetcal) { 4502 (void) ath_hal_calreset(ah, sc->sc_curchan); 4503 sc->sc_lastcalreset = ticks; 4504 sc->sc_lastshortcal = ticks; 4505 sc->sc_resetcal = 0; 4506 sc->sc_doresetcal = AH_TRUE; 4507 } 4508 } 4509 4510 /* Only call if we're doing a short/long cal, not for ANI calibration */ 4511 if (shortCal || longCal) { 4512 isCalDone = AH_FALSE; 4513 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 4514 if (longCal) { 4515 /* 4516 * Calibrate noise floor data again in case of change. 4517 */ 4518 ath_hal_process_noisefloor(ah); 4519 } 4520 } else { 4521 DPRINTF(sc, ATH_DEBUG_ANY, 4522 "%s: calibration of channel %u failed\n", 4523 __func__, sc->sc_curchan->ic_freq); 4524 sc->sc_stats.ast_per_calfail++; 4525 } 4526 if (shortCal) 4527 sc->sc_lastshortcal = ticks; 4528 } 4529 if (!isCalDone) { 4530 restart: 4531 /* 4532 * Use a shorter interval to potentially collect multiple 4533 * data samples required to complete calibration. Once 4534 * we're told the work is done we drop back to a longer 4535 * interval between requests. We're more aggressive doing 4536 * work when operating as an AP to improve operation right 4537 * after startup. 4538 */ 4539 sc->sc_lastshortcal = ticks; 4540 nextcal = ath_shortcalinterval*hz/1000; 4541 if (sc->sc_opmode != HAL_M_HOSTAP) 4542 nextcal *= 10; 4543 sc->sc_doresetcal = AH_TRUE; 4544 } else { 4545 /* nextcal should be the shortest time for next event */ 4546 nextcal = ath_longcalinterval*hz; 4547 if (sc->sc_lastcalreset == 0) 4548 sc->sc_lastcalreset = sc->sc_lastlongcal; 4549 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 4550 sc->sc_resetcal = 1; /* setup reset next trip */ 4551 sc->sc_doresetcal = AH_FALSE; 4552 } 4553 /* ANI calibration may occur more often than short/long/resetcal */ 4554 if (ath_anicalinterval > 0) 4555 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000); 4556 4557 if (nextcal != 0) { 4558 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 4559 __func__, nextcal, isCalDone ? "" : "!"); 4560 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 4561 } else { 4562 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 4563 __func__); 4564 /* NB: don't rearm timer */ 4565 } 4566 } 4567 4568 static void 4569 ath_scan_start(struct ieee80211com *ic) 4570 { 4571 struct ifnet *ifp = ic->ic_ifp; 4572 struct ath_softc *sc = ifp->if_softc; 4573 struct ath_hal *ah = sc->sc_ah; 4574 u_int32_t rfilt; 4575 4576 /* XXX calibration timer? */ 4577 4578 ATH_LOCK(sc); 4579 sc->sc_scanning = 1; 4580 sc->sc_syncbeacon = 0; 4581 rfilt = ath_calcrxfilter(sc); 4582 ATH_UNLOCK(sc); 4583 4584 ATH_PCU_LOCK(sc); 4585 ath_hal_setrxfilter(ah, rfilt); 4586 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 4587 ATH_PCU_UNLOCK(sc); 4588 4589 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 4590 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 4591 } 4592 4593 static void 4594 ath_scan_end(struct ieee80211com *ic) 4595 { 4596 struct ifnet *ifp = ic->ic_ifp; 4597 struct ath_softc *sc = ifp->if_softc; 4598 struct ath_hal *ah = sc->sc_ah; 4599 u_int32_t rfilt; 4600 4601 ATH_LOCK(sc); 4602 sc->sc_scanning = 0; 4603 rfilt = ath_calcrxfilter(sc); 4604 ATH_UNLOCK(sc); 4605 4606 ATH_PCU_LOCK(sc); 4607 ath_hal_setrxfilter(ah, rfilt); 4608 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 4609 4610 ath_hal_process_noisefloor(ah); 4611 ATH_PCU_UNLOCK(sc); 4612 4613 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 4614 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 4615 sc->sc_curaid); 4616 } 4617 4618 #ifdef ATH_ENABLE_11N 4619 /* 4620 * For now, just do a channel change. 4621 * 4622 * Later, we'll go through the hard slog of suspending tx/rx, changing rate 4623 * control state and resetting the hardware without dropping frames out 4624 * of the queue. 4625 * 4626 * The unfortunate trouble here is making absolutely sure that the 4627 * channel width change has propagated enough so the hardware 4628 * absolutely isn't handed bogus frames for it's current operating 4629 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and 4630 * does occur in parallel, we need to make certain we've blocked 4631 * any further ongoing TX (and RX, that can cause raw TX) 4632 * before we do this. 4633 */ 4634 static void 4635 ath_update_chw(struct ieee80211com *ic) 4636 { 4637 struct ifnet *ifp = ic->ic_ifp; 4638 struct ath_softc *sc = ifp->if_softc; 4639 4640 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__); 4641 ath_set_channel(ic); 4642 } 4643 #endif /* ATH_ENABLE_11N */ 4644 4645 static void 4646 ath_set_channel(struct ieee80211com *ic) 4647 { 4648 struct ifnet *ifp = ic->ic_ifp; 4649 struct ath_softc *sc = ifp->if_softc; 4650 4651 (void) ath_chan_set(sc, ic->ic_curchan); 4652 /* 4653 * If we are returning to our bss channel then mark state 4654 * so the next recv'd beacon's tsf will be used to sync the 4655 * beacon timers. Note that since we only hear beacons in 4656 * sta/ibss mode this has no effect in other operating modes. 4657 */ 4658 ATH_LOCK(sc); 4659 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 4660 sc->sc_syncbeacon = 1; 4661 ATH_UNLOCK(sc); 4662 } 4663 4664 /* 4665 * Walk the vap list and check if there any vap's in RUN state. 4666 */ 4667 static int 4668 ath_isanyrunningvaps(struct ieee80211vap *this) 4669 { 4670 struct ieee80211com *ic = this->iv_ic; 4671 struct ieee80211vap *vap; 4672 4673 IEEE80211_LOCK_ASSERT(ic); 4674 4675 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 4676 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 4677 return 1; 4678 } 4679 return 0; 4680 } 4681 4682 static int 4683 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4684 { 4685 struct ieee80211com *ic = vap->iv_ic; 4686 struct ath_softc *sc = ic->ic_ifp->if_softc; 4687 struct ath_vap *avp = ATH_VAP(vap); 4688 struct ath_hal *ah = sc->sc_ah; 4689 struct ieee80211_node *ni = NULL; 4690 int i, error, stamode; 4691 u_int32_t rfilt; 4692 int csa_run_transition = 0; 4693 static const HAL_LED_STATE leds[] = { 4694 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4695 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4696 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4697 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4698 HAL_LED_RUN, /* IEEE80211_S_CAC */ 4699 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4700 HAL_LED_RUN, /* IEEE80211_S_CSA */ 4701 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 4702 }; 4703 4704 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4705 ieee80211_state_name[vap->iv_state], 4706 ieee80211_state_name[nstate]); 4707 4708 /* 4709 * net80211 _should_ have the comlock asserted at this point. 4710 * There are some comments around the calls to vap->iv_newstate 4711 * which indicate that it (newstate) may end up dropping the 4712 * lock. This and the subsequent lock assert check after newstate 4713 * are an attempt to catch these and figure out how/why. 4714 */ 4715 IEEE80211_LOCK_ASSERT(ic); 4716 4717 if (vap->iv_state == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN) 4718 csa_run_transition = 1; 4719 4720 callout_drain(&sc->sc_cal_ch); 4721 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4722 4723 if (nstate == IEEE80211_S_SCAN) { 4724 /* 4725 * Scanning: turn off beacon miss and don't beacon. 4726 * Mark beacon state so when we reach RUN state we'll 4727 * [re]setup beacons. Unblock the task q thread so 4728 * deferred interrupt processing is done. 4729 */ 4730 ath_hal_intrset(ah, 4731 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4732 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4733 sc->sc_beacons = 0; 4734 taskqueue_unblock(sc->sc_tq); 4735 } 4736 4737 ni = ieee80211_ref_node(vap->iv_bss); 4738 rfilt = ath_calcrxfilter(sc); 4739 stamode = (vap->iv_opmode == IEEE80211_M_STA || 4740 vap->iv_opmode == IEEE80211_M_AHDEMO || 4741 vap->iv_opmode == IEEE80211_M_IBSS); 4742 if (stamode && nstate == IEEE80211_S_RUN) { 4743 sc->sc_curaid = ni->ni_associd; 4744 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 4745 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 4746 } 4747 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 4748 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 4749 ath_hal_setrxfilter(ah, rfilt); 4750 4751 /* XXX is this to restore keycache on resume? */ 4752 if (vap->iv_opmode != IEEE80211_M_STA && 4753 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 4754 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4755 if (ath_hal_keyisvalid(ah, i)) 4756 ath_hal_keysetmac(ah, i, ni->ni_bssid); 4757 } 4758 4759 /* 4760 * Invoke the parent method to do net80211 work. 4761 */ 4762 error = avp->av_newstate(vap, nstate, arg); 4763 if (error != 0) 4764 goto bad; 4765 4766 /* 4767 * See above: ensure av_newstate() doesn't drop the lock 4768 * on us. 4769 */ 4770 IEEE80211_LOCK_ASSERT(ic); 4771 4772 if (nstate == IEEE80211_S_RUN) { 4773 /* NB: collect bss node again, it may have changed */ 4774 ieee80211_free_node(ni); 4775 ni = ieee80211_ref_node(vap->iv_bss); 4776 4777 DPRINTF(sc, ATH_DEBUG_STATE, 4778 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 4779 "capinfo 0x%04x chan %d\n", __func__, 4780 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 4781 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 4782 4783 switch (vap->iv_opmode) { 4784 #ifdef IEEE80211_SUPPORT_TDMA 4785 case IEEE80211_M_AHDEMO: 4786 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 4787 break; 4788 /* fall thru... */ 4789 #endif 4790 case IEEE80211_M_HOSTAP: 4791 case IEEE80211_M_IBSS: 4792 case IEEE80211_M_MBSS: 4793 /* 4794 * Allocate and setup the beacon frame. 4795 * 4796 * Stop any previous beacon DMA. This may be 4797 * necessary, for example, when an ibss merge 4798 * causes reconfiguration; there will be a state 4799 * transition from RUN->RUN that means we may 4800 * be called with beacon transmission active. 4801 */ 4802 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4803 4804 error = ath_beacon_alloc(sc, ni); 4805 if (error != 0) 4806 goto bad; 4807 /* 4808 * If joining an adhoc network defer beacon timer 4809 * configuration to the next beacon frame so we 4810 * have a current TSF to use. Otherwise we're 4811 * starting an ibss/bss so there's no need to delay; 4812 * if this is the first vap moving to RUN state, then 4813 * beacon state needs to be [re]configured. 4814 */ 4815 if (vap->iv_opmode == IEEE80211_M_IBSS && 4816 ni->ni_tstamp.tsf != 0) { 4817 sc->sc_syncbeacon = 1; 4818 } else if (!sc->sc_beacons) { 4819 #ifdef IEEE80211_SUPPORT_TDMA 4820 if (vap->iv_caps & IEEE80211_C_TDMA) 4821 ath_tdma_config(sc, vap); 4822 else 4823 #endif 4824 ath_beacon_config(sc, vap); 4825 sc->sc_beacons = 1; 4826 } 4827 break; 4828 case IEEE80211_M_STA: 4829 /* 4830 * Defer beacon timer configuration to the next 4831 * beacon frame so we have a current TSF to use 4832 * (any TSF collected when scanning is likely old). 4833 * However if it's due to a CSA -> RUN transition, 4834 * force a beacon update so we pick up a lack of 4835 * beacons from an AP in CAC and thus force a 4836 * scan. 4837 */ 4838 sc->sc_syncbeacon = 1; 4839 if (csa_run_transition) 4840 ath_beacon_config(sc, vap); 4841 break; 4842 case IEEE80211_M_MONITOR: 4843 /* 4844 * Monitor mode vaps have only INIT->RUN and RUN->RUN 4845 * transitions so we must re-enable interrupts here to 4846 * handle the case of a single monitor mode vap. 4847 */ 4848 ath_hal_intrset(ah, sc->sc_imask); 4849 break; 4850 case IEEE80211_M_WDS: 4851 break; 4852 default: 4853 break; 4854 } 4855 /* 4856 * Let the hal process statistics collected during a 4857 * scan so it can provide calibrated noise floor data. 4858 */ 4859 ath_hal_process_noisefloor(ah); 4860 /* 4861 * Reset rssi stats; maybe not the best place... 4862 */ 4863 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 4864 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 4865 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 4866 /* 4867 * Finally, start any timers and the task q thread 4868 * (in case we didn't go through SCAN state). 4869 */ 4870 if (ath_longcalinterval != 0) { 4871 /* start periodic recalibration timer */ 4872 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 4873 } else { 4874 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 4875 "%s: calibration disabled\n", __func__); 4876 } 4877 taskqueue_unblock(sc->sc_tq); 4878 } else if (nstate == IEEE80211_S_INIT) { 4879 /* 4880 * If there are no vaps left in RUN state then 4881 * shutdown host/driver operation: 4882 * o disable interrupts 4883 * o disable the task queue thread 4884 * o mark beacon processing as stopped 4885 */ 4886 if (!ath_isanyrunningvaps(vap)) { 4887 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4888 /* disable interrupts */ 4889 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4890 taskqueue_block(sc->sc_tq); 4891 sc->sc_beacons = 0; 4892 } 4893 #ifdef IEEE80211_SUPPORT_TDMA 4894 ath_hal_setcca(ah, AH_TRUE); 4895 #endif 4896 } 4897 bad: 4898 ieee80211_free_node(ni); 4899 return error; 4900 } 4901 4902 /* 4903 * Allocate a key cache slot to the station so we can 4904 * setup a mapping from key index to node. The key cache 4905 * slot is needed for managing antenna state and for 4906 * compression when stations do not use crypto. We do 4907 * it uniliaterally here; if crypto is employed this slot 4908 * will be reassigned. 4909 */ 4910 static void 4911 ath_setup_stationkey(struct ieee80211_node *ni) 4912 { 4913 struct ieee80211vap *vap = ni->ni_vap; 4914 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 4915 ieee80211_keyix keyix, rxkeyix; 4916 4917 /* XXX should take a locked ref to vap->iv_bss */ 4918 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4919 /* 4920 * Key cache is full; we'll fall back to doing 4921 * the more expensive lookup in software. Note 4922 * this also means no h/w compression. 4923 */ 4924 /* XXX msg+statistic */ 4925 } else { 4926 /* XXX locking? */ 4927 ni->ni_ucastkey.wk_keyix = keyix; 4928 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4929 /* NB: must mark device key to get called back on delete */ 4930 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 4931 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 4932 /* NB: this will create a pass-thru key entry */ 4933 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss); 4934 } 4935 } 4936 4937 /* 4938 * Setup driver-specific state for a newly associated node. 4939 * Note that we're called also on a re-associate, the isnew 4940 * param tells us if this is the first time or not. 4941 */ 4942 static void 4943 ath_newassoc(struct ieee80211_node *ni, int isnew) 4944 { 4945 struct ath_node *an = ATH_NODE(ni); 4946 struct ieee80211vap *vap = ni->ni_vap; 4947 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 4948 const struct ieee80211_txparam *tp = ni->ni_txparms; 4949 4950 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 4951 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 4952 4953 ath_rate_newassoc(sc, an, isnew); 4954 if (isnew && 4955 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 4956 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4957 ath_setup_stationkey(ni); 4958 } 4959 4960 static int 4961 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 4962 int nchans, struct ieee80211_channel chans[]) 4963 { 4964 struct ath_softc *sc = ic->ic_ifp->if_softc; 4965 struct ath_hal *ah = sc->sc_ah; 4966 HAL_STATUS status; 4967 4968 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 4969 "%s: rd %u cc %u location %c%s\n", 4970 __func__, reg->regdomain, reg->country, reg->location, 4971 reg->ecm ? " ecm" : ""); 4972 4973 status = ath_hal_set_channels(ah, chans, nchans, 4974 reg->country, reg->regdomain); 4975 if (status != HAL_OK) { 4976 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 4977 __func__, status); 4978 return EINVAL; /* XXX */ 4979 } 4980 4981 return 0; 4982 } 4983 4984 static void 4985 ath_getradiocaps(struct ieee80211com *ic, 4986 int maxchans, int *nchans, struct ieee80211_channel chans[]) 4987 { 4988 struct ath_softc *sc = ic->ic_ifp->if_softc; 4989 struct ath_hal *ah = sc->sc_ah; 4990 4991 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 4992 __func__, SKU_DEBUG, CTRY_DEFAULT); 4993 4994 /* XXX check return */ 4995 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 4996 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 4997 4998 } 4999 5000 static int 5001 ath_getchannels(struct ath_softc *sc) 5002 { 5003 struct ifnet *ifp = sc->sc_ifp; 5004 struct ieee80211com *ic = ifp->if_l2com; 5005 struct ath_hal *ah = sc->sc_ah; 5006 HAL_STATUS status; 5007 5008 /* 5009 * Collect channel set based on EEPROM contents. 5010 */ 5011 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 5012 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 5013 if (status != HAL_OK) { 5014 if_printf(ifp, "%s: unable to collect channel list from hal, " 5015 "status %d\n", __func__, status); 5016 return EINVAL; 5017 } 5018 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 5019 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 5020 /* XXX map Atheros sku's to net80211 SKU's */ 5021 /* XXX net80211 types too small */ 5022 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 5023 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 5024 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 5025 ic->ic_regdomain.isocc[1] = ' '; 5026 5027 ic->ic_regdomain.ecm = 1; 5028 ic->ic_regdomain.location = 'I'; 5029 5030 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5031 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 5032 __func__, sc->sc_eerd, sc->sc_eecc, 5033 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 5034 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 5035 return 0; 5036 } 5037 5038 static int 5039 ath_rate_setup(struct ath_softc *sc, u_int mode) 5040 { 5041 struct ath_hal *ah = sc->sc_ah; 5042 const HAL_RATE_TABLE *rt; 5043 5044 switch (mode) { 5045 case IEEE80211_MODE_11A: 5046 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5047 break; 5048 case IEEE80211_MODE_HALF: 5049 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 5050 break; 5051 case IEEE80211_MODE_QUARTER: 5052 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 5053 break; 5054 case IEEE80211_MODE_11B: 5055 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5056 break; 5057 case IEEE80211_MODE_11G: 5058 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5059 break; 5060 case IEEE80211_MODE_TURBO_A: 5061 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 5062 break; 5063 case IEEE80211_MODE_TURBO_G: 5064 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5065 break; 5066 case IEEE80211_MODE_STURBO_A: 5067 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5068 break; 5069 case IEEE80211_MODE_11NA: 5070 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 5071 break; 5072 case IEEE80211_MODE_11NG: 5073 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 5074 break; 5075 default: 5076 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5077 __func__, mode); 5078 return 0; 5079 } 5080 sc->sc_rates[mode] = rt; 5081 return (rt != NULL); 5082 } 5083 5084 static void 5085 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5086 { 5087 #define N(a) (sizeof(a)/sizeof(a[0])) 5088 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5089 static const struct { 5090 u_int rate; /* tx/rx 802.11 rate */ 5091 u_int16_t timeOn; /* LED on time (ms) */ 5092 u_int16_t timeOff; /* LED off time (ms) */ 5093 } blinkrates[] = { 5094 { 108, 40, 10 }, 5095 { 96, 44, 11 }, 5096 { 72, 50, 13 }, 5097 { 48, 57, 14 }, 5098 { 36, 67, 16 }, 5099 { 24, 80, 20 }, 5100 { 22, 100, 25 }, 5101 { 18, 133, 34 }, 5102 { 12, 160, 40 }, 5103 { 10, 200, 50 }, 5104 { 6, 240, 58 }, 5105 { 4, 267, 66 }, 5106 { 2, 400, 100 }, 5107 { 0, 500, 130 }, 5108 /* XXX half/quarter rates */ 5109 }; 5110 const HAL_RATE_TABLE *rt; 5111 int i, j; 5112 5113 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5114 rt = sc->sc_rates[mode]; 5115 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5116 for (i = 0; i < rt->rateCount; i++) { 5117 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 5118 if (rt->info[i].phy != IEEE80211_T_HT) 5119 sc->sc_rixmap[ieeerate] = i; 5120 else 5121 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 5122 } 5123 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5124 for (i = 0; i < N(sc->sc_hwmap); i++) { 5125 if (i >= rt->rateCount) { 5126 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5127 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5128 continue; 5129 } 5130 sc->sc_hwmap[i].ieeerate = 5131 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 5132 if (rt->info[i].phy == IEEE80211_T_HT) 5133 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 5134 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5135 if (rt->info[i].shortPreamble || 5136 rt->info[i].phy == IEEE80211_T_OFDM) 5137 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5138 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 5139 for (j = 0; j < N(blinkrates)-1; j++) 5140 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5141 break; 5142 /* NB: this uses the last entry if the rate isn't found */ 5143 /* XXX beware of overlow */ 5144 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5145 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5146 } 5147 sc->sc_currates = rt; 5148 sc->sc_curmode = mode; 5149 /* 5150 * All protection frames are transmited at 2Mb/s for 5151 * 11g, otherwise at 1Mb/s. 5152 */ 5153 if (mode == IEEE80211_MODE_11G) 5154 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 5155 else 5156 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 5157 /* NB: caller is responsible for resetting rate control state */ 5158 #undef N 5159 } 5160 5161 static void 5162 ath_watchdog(void *arg) 5163 { 5164 struct ath_softc *sc = arg; 5165 int do_reset = 0; 5166 5167 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 5168 struct ifnet *ifp = sc->sc_ifp; 5169 uint32_t hangs; 5170 5171 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 5172 hangs != 0) { 5173 if_printf(ifp, "%s hang detected (0x%x)\n", 5174 hangs & 0xff ? "bb" : "mac", hangs); 5175 } else 5176 if_printf(ifp, "device timeout\n"); 5177 do_reset = 1; 5178 ifp->if_oerrors++; 5179 sc->sc_stats.ast_watchdog++; 5180 } 5181 5182 /* 5183 * We can't hold the lock across the ath_reset() call. 5184 * 5185 * And since this routine can't hold a lock and sleep, 5186 * do the reset deferred. 5187 */ 5188 if (do_reset) { 5189 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 5190 } 5191 5192 callout_schedule(&sc->sc_wd_ch, hz); 5193 } 5194 5195 /* 5196 * Fetch the rate control statistics for the given node. 5197 */ 5198 static int 5199 ath_ioctl_ratestats(struct ath_softc *sc, struct ath_rateioctl *rs) 5200 { 5201 struct ath_node *an; 5202 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5203 struct ieee80211_node *ni; 5204 int error = 0; 5205 5206 /* Perform a lookup on the given node */ 5207 ni = ieee80211_find_node(&ic->ic_sta, rs->is_u.macaddr); 5208 if (ni == NULL) { 5209 error = EINVAL; 5210 goto bad; 5211 } 5212 5213 /* Lock the ath_node */ 5214 an = ATH_NODE(ni); 5215 ATH_NODE_LOCK(an); 5216 5217 /* Fetch the rate control stats for this node */ 5218 error = ath_rate_fetch_node_stats(sc, an, rs); 5219 5220 /* No matter what happens here, just drop through */ 5221 5222 /* Unlock the ath_node */ 5223 ATH_NODE_UNLOCK(an); 5224 5225 /* Unref the node */ 5226 ieee80211_node_decref(ni); 5227 5228 bad: 5229 return (error); 5230 } 5231 5232 #ifdef ATH_DIAGAPI 5233 /* 5234 * Diagnostic interface to the HAL. This is used by various 5235 * tools to do things like retrieve register contents for 5236 * debugging. The mechanism is intentionally opaque so that 5237 * it can change frequently w/o concern for compatiblity. 5238 */ 5239 static int 5240 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5241 { 5242 struct ath_hal *ah = sc->sc_ah; 5243 u_int id = ad->ad_id & ATH_DIAG_ID; 5244 void *indata = NULL; 5245 void *outdata = NULL; 5246 u_int32_t insize = ad->ad_in_size; 5247 u_int32_t outsize = ad->ad_out_size; 5248 int error = 0; 5249 5250 if (ad->ad_id & ATH_DIAG_IN) { 5251 /* 5252 * Copy in data. 5253 */ 5254 indata = malloc(insize, M_TEMP, M_NOWAIT); 5255 if (indata == NULL) { 5256 error = ENOMEM; 5257 goto bad; 5258 } 5259 error = copyin(ad->ad_in_data, indata, insize); 5260 if (error) 5261 goto bad; 5262 } 5263 if (ad->ad_id & ATH_DIAG_DYN) { 5264 /* 5265 * Allocate a buffer for the results (otherwise the HAL 5266 * returns a pointer to a buffer where we can read the 5267 * results). Note that we depend on the HAL leaving this 5268 * pointer for us to use below in reclaiming the buffer; 5269 * may want to be more defensive. 5270 */ 5271 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5272 if (outdata == NULL) { 5273 error = ENOMEM; 5274 goto bad; 5275 } 5276 } 5277 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5278 if (outsize < ad->ad_out_size) 5279 ad->ad_out_size = outsize; 5280 if (outdata != NULL) 5281 error = copyout(outdata, ad->ad_out_data, 5282 ad->ad_out_size); 5283 } else { 5284 error = EINVAL; 5285 } 5286 bad: 5287 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5288 free(indata, M_TEMP); 5289 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5290 free(outdata, M_TEMP); 5291 return error; 5292 } 5293 #endif /* ATH_DIAGAPI */ 5294 5295 static int 5296 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 5297 { 5298 #define IS_RUNNING(ifp) \ 5299 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 5300 struct ath_softc *sc = ifp->if_softc; 5301 struct ieee80211com *ic = ifp->if_l2com; 5302 struct ifreq *ifr = (struct ifreq *)data; 5303 const HAL_RATE_TABLE *rt; 5304 int error = 0; 5305 5306 switch (cmd) { 5307 case SIOCSIFFLAGS: 5308 ATH_LOCK(sc); 5309 if (IS_RUNNING(ifp)) { 5310 /* 5311 * To avoid rescanning another access point, 5312 * do not call ath_init() here. Instead, 5313 * only reflect promisc mode settings. 5314 */ 5315 ath_mode_init(sc); 5316 } else if (ifp->if_flags & IFF_UP) { 5317 /* 5318 * Beware of being called during attach/detach 5319 * to reset promiscuous mode. In that case we 5320 * will still be marked UP but not RUNNING. 5321 * However trying to re-init the interface 5322 * is the wrong thing to do as we've already 5323 * torn down much of our state. There's 5324 * probably a better way to deal with this. 5325 */ 5326 if (!sc->sc_invalid) 5327 ath_init(sc); /* XXX lose error */ 5328 } else { 5329 ath_stop_locked(ifp); 5330 #ifdef notyet 5331 /* XXX must wakeup in places like ath_vap_delete */ 5332 if (!sc->sc_invalid) 5333 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 5334 #endif 5335 } 5336 ATH_UNLOCK(sc); 5337 break; 5338 case SIOCGIFMEDIA: 5339 case SIOCSIFMEDIA: 5340 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 5341 break; 5342 case SIOCGATHSTATS: 5343 /* NB: embed these numbers to get a consistent view */ 5344 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5345 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5346 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 5347 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 5348 #ifdef IEEE80211_SUPPORT_TDMA 5349 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 5350 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 5351 #endif 5352 rt = sc->sc_currates; 5353 sc->sc_stats.ast_tx_rate = 5354 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 5355 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT) 5356 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS; 5357 return copyout(&sc->sc_stats, 5358 ifr->ifr_data, sizeof (sc->sc_stats)); 5359 case SIOCGATHAGSTATS: 5360 return copyout(&sc->sc_aggr_stats, 5361 ifr->ifr_data, sizeof (sc->sc_aggr_stats)); 5362 case SIOCZATHSTATS: 5363 error = priv_check(curthread, PRIV_DRIVER); 5364 if (error == 0) { 5365 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 5366 memset(&sc->sc_aggr_stats, 0, 5367 sizeof(sc->sc_aggr_stats)); 5368 memset(&sc->sc_intr_stats, 0, 5369 sizeof(sc->sc_intr_stats)); 5370 } 5371 break; 5372 #ifdef ATH_DIAGAPI 5373 case SIOCGATHDIAG: 5374 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5375 break; 5376 case SIOCGATHPHYERR: 5377 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr); 5378 break; 5379 #endif 5380 case SIOCGATHNODERATESTATS: 5381 error = ath_ioctl_ratestats(sc, (struct ath_rateioctl *) ifr); 5382 break; 5383 case SIOCGIFADDR: 5384 error = ether_ioctl(ifp, cmd, data); 5385 break; 5386 default: 5387 error = EINVAL; 5388 break; 5389 } 5390 return error; 5391 #undef IS_RUNNING 5392 } 5393 5394 /* 5395 * Announce various information on device/driver attach. 5396 */ 5397 static void 5398 ath_announce(struct ath_softc *sc) 5399 { 5400 struct ifnet *ifp = sc->sc_ifp; 5401 struct ath_hal *ah = sc->sc_ah; 5402 5403 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 5404 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 5405 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 5406 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n", 5407 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev); 5408 if (bootverbose) { 5409 int i; 5410 for (i = 0; i <= WME_AC_VO; i++) { 5411 struct ath_txq *txq = sc->sc_ac2q[i]; 5412 if_printf(ifp, "Use hw queue %u for %s traffic\n", 5413 txq->axq_qnum, ieee80211_wme_acnames[i]); 5414 } 5415 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 5416 sc->sc_cabq->axq_qnum); 5417 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 5418 } 5419 if (ath_rxbuf != ATH_RXBUF) 5420 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 5421 if (ath_txbuf != ATH_TXBUF) 5422 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 5423 if (sc->sc_mcastkey && bootverbose) 5424 if_printf(ifp, "using multicast key search\n"); 5425 } 5426 5427 static void 5428 ath_dfs_tasklet(void *p, int npending) 5429 { 5430 struct ath_softc *sc = (struct ath_softc *) p; 5431 struct ifnet *ifp = sc->sc_ifp; 5432 struct ieee80211com *ic = ifp->if_l2com; 5433 5434 /* 5435 * If previous processing has found a radar event, 5436 * signal this to the net80211 layer to begin DFS 5437 * processing. 5438 */ 5439 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) { 5440 /* DFS event found, initiate channel change */ 5441 /* 5442 * XXX doesn't currently tell us whether the event 5443 * XXX was found in the primary or extension 5444 * XXX channel! 5445 */ 5446 IEEE80211_LOCK(ic); 5447 ieee80211_dfs_notify_radar(ic, sc->sc_curchan); 5448 IEEE80211_UNLOCK(ic); 5449 } 5450 } 5451 5452 /* 5453 * Enable/disable power save. This must be called with 5454 * no TX driver locks currently held, so it should only 5455 * be called from the RX path (which doesn't hold any 5456 * TX driver locks.) 5457 */ 5458 static void 5459 ath_node_powersave(struct ieee80211_node *ni, int enable) 5460 { 5461 #ifdef ATH_SW_PSQ 5462 struct ath_node *an = ATH_NODE(ni); 5463 struct ieee80211com *ic = ni->ni_ic; 5464 struct ath_softc *sc = ic->ic_ifp->if_softc; 5465 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 5466 5467 ATH_NODE_UNLOCK_ASSERT(an); 5468 /* XXX and no TXQ locks should be held here */ 5469 5470 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: ni=%p, enable=%d\n", 5471 __func__, ni, enable); 5472 5473 /* Suspend or resume software queue handling */ 5474 if (enable) 5475 ath_tx_node_sleep(sc, an); 5476 else 5477 ath_tx_node_wakeup(sc, an); 5478 5479 /* Update net80211 state */ 5480 avp->av_node_ps(ni, enable); 5481 #else 5482 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 5483 5484 /* Update net80211 state */ 5485 avp->av_node_ps(ni, enable); 5486 #endif/* ATH_SW_PSQ */ 5487 } 5488 5489 /* 5490 * Notification from net80211 that the powersave queue state has 5491 * changed. 5492 * 5493 * Since the software queue also may have some frames: 5494 * 5495 * + if the node software queue has frames and the TID state 5496 * is 0, we set the TIM; 5497 * + if the node and the stack are both empty, we clear the TIM bit. 5498 * + If the stack tries to set the bit, always set it. 5499 * + If the stack tries to clear the bit, only clear it if the 5500 * software queue in question is also cleared. 5501 * 5502 * TODO: this is called during node teardown; so let's ensure this 5503 * is all correctly handled and that the TIM bit is cleared. 5504 * It may be that the node flush is called _AFTER_ the net80211 5505 * stack clears the TIM. 5506 * 5507 * Here is the racy part. Since it's possible >1 concurrent, 5508 * overlapping TXes will appear complete with a TX completion in 5509 * another thread, it's possible that the concurrent TIM calls will 5510 * clash. We can't hold the node lock here because setting the 5511 * TIM grabs the net80211 comlock and this may cause a LOR. 5512 * The solution is either to totally serialise _everything_ at 5513 * this point (ie, all TX, completion and any reset/flush go into 5514 * one taskqueue) or a new "ath TIM lock" needs to be created that 5515 * just wraps the driver state change and this call to avp->av_set_tim(). 5516 * 5517 * The same race exists in the net80211 power save queue handling 5518 * as well. Since multiple transmitting threads may queue frames 5519 * into the driver, as well as ps-poll and the driver transmitting 5520 * frames (and thus clearing the psq), it's quite possible that 5521 * a packet entering the PSQ and a ps-poll being handled will 5522 * race, causing the TIM to be cleared and not re-set. 5523 */ 5524 static int 5525 ath_node_set_tim(struct ieee80211_node *ni, int enable) 5526 { 5527 #ifdef ATH_SW_PSQ 5528 struct ieee80211com *ic = ni->ni_ic; 5529 struct ath_softc *sc = ic->ic_ifp->if_softc; 5530 struct ath_node *an = ATH_NODE(ni); 5531 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 5532 int changed = 0; 5533 5534 ATH_NODE_UNLOCK_ASSERT(an); 5535 5536 /* 5537 * For now, just track and then update the TIM. 5538 */ 5539 ATH_NODE_LOCK(an); 5540 an->an_stack_psq = enable; 5541 5542 /* 5543 * This will get called for all operating modes, 5544 * even if avp->av_set_tim is unset. 5545 * It's currently set for hostap/ibss modes; but 5546 * the same infrastructure is used for both STA 5547 * and AP/IBSS node power save. 5548 */ 5549 if (avp->av_set_tim == NULL) { 5550 ATH_NODE_UNLOCK(an); 5551 return (0); 5552 } 5553 5554 /* 5555 * If setting the bit, always set it here. 5556 * If clearing the bit, only clear it if the 5557 * software queue is also empty. 5558 * 5559 * If the node has left power save, just clear the TIM 5560 * bit regardless of the state of the power save queue. 5561 * 5562 * XXX TODO: although atomics are used, it's quite possible 5563 * that a race will occur between this and setting/clearing 5564 * in another thread. TX completion will occur always in 5565 * one thread, however setting/clearing the TIM bit can come 5566 * from a variety of different process contexts! 5567 */ 5568 if (enable && an->an_tim_set == 1) { 5569 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5570 "%s: an=%p, enable=%d, tim_set=1, ignoring\n", 5571 __func__, an, enable); 5572 ATH_NODE_UNLOCK(an); 5573 } else if (enable) { 5574 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5575 "%s: an=%p, enable=%d, enabling TIM\n", 5576 __func__, an, enable); 5577 an->an_tim_set = 1; 5578 ATH_NODE_UNLOCK(an); 5579 changed = avp->av_set_tim(ni, enable); 5580 } else if (atomic_load_acq_int(&an->an_swq_depth) == 0) { 5581 /* disable */ 5582 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5583 "%s: an=%p, enable=%d, an_swq_depth == 0, disabling\n", 5584 __func__, an, enable); 5585 an->an_tim_set = 0; 5586 ATH_NODE_UNLOCK(an); 5587 changed = avp->av_set_tim(ni, enable); 5588 } else if (! an->an_is_powersave) { 5589 /* 5590 * disable regardless; the node isn't in powersave now 5591 */ 5592 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5593 "%s: an=%p, enable=%d, an_pwrsave=0, disabling\n", 5594 __func__, an, enable); 5595 an->an_tim_set = 0; 5596 ATH_NODE_UNLOCK(an); 5597 changed = avp->av_set_tim(ni, enable); 5598 } else { 5599 /* 5600 * psq disable, node is currently in powersave, node 5601 * software queue isn't empty, so don't clear the TIM bit 5602 * for now. 5603 */ 5604 ATH_NODE_UNLOCK(an); 5605 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5606 "%s: enable=%d, an_swq_depth > 0, ignoring\n", 5607 __func__, enable); 5608 changed = 0; 5609 } 5610 5611 return (changed); 5612 #else 5613 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 5614 5615 /* 5616 * Some operating omdes don't set av_set_tim(), so don't 5617 * update it here. 5618 */ 5619 if (avp->av_set_tim == NULL) 5620 return (0); 5621 5622 return (avp->av_set_tim(ni, enable)); 5623 #endif /* ATH_SW_PSQ */ 5624 } 5625 5626 /* 5627 * Set or update the TIM from the software queue. 5628 * 5629 * Check the software queue depth before attempting to do lock 5630 * anything; that avoids trying to obtain the lock. Then, 5631 * re-check afterwards to ensure nothing has changed in the 5632 * meantime. 5633 * 5634 * set: This is designed to be called from the TX path, after 5635 * a frame has been queued; to see if the swq > 0. 5636 * 5637 * clear: This is designed to be called from the buffer completion point 5638 * (right now it's ath_tx_default_comp()) where the state of 5639 * a software queue has changed. 5640 * 5641 * It makes sense to place it at buffer free / completion rather 5642 * than after each software queue operation, as there's no real 5643 * point in churning the TIM bit as the last frames in the software 5644 * queue are transmitted. If they fail and we retry them, we'd 5645 * just be setting the TIM bit again anyway. 5646 */ 5647 void 5648 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni, 5649 int enable) 5650 { 5651 #ifdef ATH_SW_PSQ 5652 struct ath_node *an; 5653 struct ath_vap *avp; 5654 5655 /* Don't do this for broadcast/etc frames */ 5656 if (ni == NULL) 5657 return; 5658 5659 an = ATH_NODE(ni); 5660 avp = ATH_VAP(ni->ni_vap); 5661 5662 /* 5663 * And for operating modes without the TIM handler set, let's 5664 * just skip those. 5665 */ 5666 if (avp->av_set_tim == NULL) 5667 return; 5668 5669 ATH_NODE_UNLOCK_ASSERT(an); 5670 5671 if (enable) { 5672 /* 5673 * Don't bother grabbing the lock unless the queue is not 5674 * empty. 5675 */ 5676 if (atomic_load_acq_int(&an->an_swq_depth) == 0) 5677 return; 5678 5679 ATH_NODE_LOCK(an); 5680 if (an->an_is_powersave && 5681 an->an_tim_set == 0 && 5682 atomic_load_acq_int(&an->an_swq_depth) != 0) { 5683 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5684 "%s: an=%p, swq_depth>0, tim_set=0, set!\n", 5685 __func__, an); 5686 an->an_tim_set = 1; 5687 ATH_NODE_UNLOCK(an); 5688 (void) avp->av_set_tim(ni, 1); 5689 } else { 5690 ATH_NODE_UNLOCK(an); 5691 } 5692 } else { 5693 /* 5694 * Don't bother grabbing the lock unless the queue is empty. 5695 */ 5696 if (atomic_load_acq_int(&an->an_swq_depth) != 0) 5697 return; 5698 5699 ATH_NODE_LOCK(an); 5700 if (an->an_is_powersave && 5701 an->an_stack_psq == 0 && 5702 an->an_tim_set == 1 && 5703 atomic_load_acq_int(&an->an_swq_depth) == 0) { 5704 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 5705 "%s: an=%p, swq_depth=0, tim_set=1, psq_set=0," 5706 " clear!\n", 5707 __func__, an); 5708 an->an_tim_set = 0; 5709 ATH_NODE_UNLOCK(an); 5710 (void) avp->av_set_tim(ni, 0); 5711 } else { 5712 ATH_NODE_UNLOCK(an); 5713 } 5714 } 5715 #else 5716 return; 5717 #endif /* ATH_SW_PSQ */ 5718 } 5719 5720 MODULE_VERSION(if_ath, 1); 5721 MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */ 5722 #if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) 5723 MODULE_DEPEND(if_ath, alq, 1, 1, 1); 5724 #endif 5725