1 /*- 2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 /* 41 * Driver for the Atheros Wireless LAN controller. 42 * 43 * This software is derived from work of Atsushi Onoe; his contribution 44 * is greatly appreciated. 45 */ 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/lock.h> 55 #include <sys/mutex.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/errno.h> 60 #include <sys/callout.h> 61 #include <sys/bus.h> 62 #include <sys/endian.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_arp.h> 70 #include <net/ethernet.h> 71 #include <net/if_llc.h> 72 73 #include <net80211/ieee80211_var.h> 74 75 #include <net/bpf.h> 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/if_ether.h> 80 #endif 81 82 #define AR_DEBUG 83 #include <dev/ath/if_athvar.h> 84 #include <contrib/dev/ath/ah_desc.h> 85 86 /* unalligned little endian access */ 87 #define LE_READ_2(p) \ 88 ((u_int16_t) \ 89 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 90 #define LE_READ_4(p) \ 91 ((u_int32_t) \ 92 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 93 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 94 95 static void ath_init(void *); 96 static void ath_stop(struct ifnet *); 97 static void ath_start(struct ifnet *); 98 static void ath_reset(struct ath_softc *); 99 static int ath_media_change(struct ifnet *); 100 static void ath_watchdog(struct ifnet *); 101 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 102 static void ath_fatal_proc(void *, int); 103 static void ath_rxorn_proc(void *, int); 104 static void ath_bmiss_proc(void *, int); 105 static void ath_initkeytable(struct ath_softc *); 106 static void ath_mode_init(struct ath_softc *); 107 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 108 static void ath_beacon_proc(void *, int); 109 static void ath_beacon_free(struct ath_softc *); 110 static void ath_beacon_config(struct ath_softc *); 111 static int ath_desc_alloc(struct ath_softc *); 112 static void ath_desc_free(struct ath_softc *); 113 static struct ieee80211_node *ath_node_alloc(struct ieee80211com *); 114 static void ath_node_free(struct ieee80211com *, struct ieee80211_node *); 115 static void ath_node_copy(struct ieee80211com *, 116 struct ieee80211_node *, const struct ieee80211_node *); 117 static u_int8_t ath_node_getrssi(struct ieee80211com *, 118 struct ieee80211_node *); 119 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 120 static void ath_rx_proc(void *, int); 121 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 122 struct ath_buf *, struct mbuf *); 123 static void ath_tx_proc(void *, int); 124 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 125 static void ath_draintxq(struct ath_softc *); 126 static void ath_stoprecv(struct ath_softc *); 127 static int ath_startrecv(struct ath_softc *); 128 static void ath_next_scan(void *); 129 static void ath_calibrate(void *); 130 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 131 static void ath_newassoc(struct ieee80211com *, 132 struct ieee80211_node *, int); 133 static int ath_getchannels(struct ath_softc *, u_int cc, HAL_BOOL outdoor); 134 135 static int ath_rate_setup(struct ath_softc *sc, u_int mode); 136 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 137 static void ath_rate_ctl_reset(struct ath_softc *, enum ieee80211_state); 138 static void ath_rate_ctl(void *, struct ieee80211_node *); 139 140 SYSCTL_DECL(_hw_ath); 141 142 /* XXX validate sysctl values */ 143 static int ath_dwelltime = 200; /* 5 channels/second */ 144 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 145 0, "channel dwell time (ms) for AP/station scanning"); 146 static int ath_calinterval = 30; /* calibrate every 30 secs */ 147 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 148 0, "chip calibration interval (secs)"); 149 static int ath_outdoor = AH_TRUE; /* outdoor operation */ 150 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 151 0, "enable/disable outdoor operation"); 152 static int ath_countrycode = CTRY_DEFAULT; /* country code */ 153 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 154 0, "country code"); 155 static int ath_regdomain = 0; /* regulatory domain */ 156 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 157 0, "regulatory domain"); 158 159 #ifdef AR_DEBUG 160 int ath_debug = 0; 161 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 162 0, "control debugging printfs"); 163 #define IFF_DUMPPKTS(_ifp) \ 164 (ath_debug || \ 165 ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 166 static void ath_printrxbuf(struct ath_buf *bf, int); 167 static void ath_printtxbuf(struct ath_buf *bf, int); 168 #define DPRINTF(X) if (ath_debug) printf X 169 #define DPRINTF2(X) if (ath_debug > 1) printf X 170 #else 171 #define IFF_DUMPPKTS(_ifp) \ 172 (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 173 #define DPRINTF(X) 174 #define DPRINTF2(X) 175 #endif 176 177 int 178 ath_attach(u_int16_t devid, struct ath_softc *sc) 179 { 180 struct ieee80211com *ic = &sc->sc_ic; 181 struct ifnet *ifp = &ic->ic_if; 182 struct ath_hal *ah; 183 HAL_STATUS status; 184 int error = 0; 185 186 DPRINTF(("ath_attach: devid 0x%x\n", devid)); 187 188 /* set these up early for if_printf use */ 189 ifp->if_unit = device_get_unit(sc->sc_dev); 190 ifp->if_name = "ath"; 191 192 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 193 if (ah == NULL) { 194 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 195 status); 196 error = ENXIO; 197 goto bad; 198 } 199 sc->sc_ah = ah; 200 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 201 202 /* 203 * Collect the channel list using the default country 204 * code and including outdoor channels. The 802.11 layer 205 * is resposible for filtering this list based on settings 206 * like the phy mode. 207 */ 208 error = ath_getchannels(sc, ath_countrycode, ath_outdoor); 209 if (error != 0) 210 goto bad; 211 /* 212 * Copy these back; they are set as a side effect 213 * of constructing the channel list. 214 */ 215 ath_regdomain = ath_hal_getregdomain(ah); 216 ath_countrycode = ath_hal_getcountrycode(ah); 217 218 /* 219 * Setup rate tables for all potential media types. 220 */ 221 ath_rate_setup(sc, IEEE80211_MODE_11A); 222 ath_rate_setup(sc, IEEE80211_MODE_11B); 223 ath_rate_setup(sc, IEEE80211_MODE_11G); 224 ath_rate_setup(sc, IEEE80211_MODE_TURBO); 225 226 error = ath_desc_alloc(sc); 227 if (error != 0) { 228 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 229 goto bad; 230 } 231 callout_init(&sc->sc_scan_ch, CALLOUT_MPSAFE); 232 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 233 234 mtx_init(&sc->sc_txbuflock, 235 device_get_nameunit(sc->sc_dev), "xmit buf q", MTX_DEF); 236 mtx_init(&sc->sc_txqlock, 237 device_get_nameunit(sc->sc_dev), "xmit q", MTX_DEF); 238 239 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 240 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 241 TASK_INIT(&sc->sc_swbatask, 0, ath_beacon_proc, sc); 242 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 243 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 244 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 245 246 /* 247 * For now just pre-allocate one data queue and one 248 * beacon queue. Note that the HAL handles resetting 249 * them at the needed time. Eventually we'll want to 250 * allocate more tx queues for splitting management 251 * frames and for QOS support. 252 */ 253 sc->sc_txhalq = ath_hal_setuptxqueue(ah, 254 HAL_TX_QUEUE_DATA, 255 AH_TRUE /* enable interrupts */ 256 ); 257 if (sc->sc_txhalq == (u_int) -1) { 258 if_printf(ifp, "unable to setup a data xmit queue!\n"); 259 goto bad; 260 } 261 sc->sc_bhalq = ath_hal_setuptxqueue(ah, 262 HAL_TX_QUEUE_BEACON, 263 AH_TRUE /* enable interrupts */ 264 ); 265 if (sc->sc_bhalq == (u_int) -1) { 266 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 267 goto bad; 268 } 269 270 ifp->if_softc = sc; 271 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 272 ifp->if_start = ath_start; 273 ifp->if_watchdog = ath_watchdog; 274 ifp->if_ioctl = ath_ioctl; 275 ifp->if_init = ath_init; 276 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 277 278 ic->ic_softc = sc; 279 ic->ic_newassoc = ath_newassoc; 280 /* XXX not right but it's not used anywhere important */ 281 ic->ic_phytype = IEEE80211_T_OFDM; 282 ic->ic_opmode = IEEE80211_M_STA; 283 ic->ic_caps = IEEE80211_C_WEP | IEEE80211_C_IBSS | IEEE80211_C_HOSTAP 284 | IEEE80211_C_MONITOR | IEEE80211_C_SHPREAMBLE; 285 286 /* get mac address from hardware */ 287 ath_hal_getmac(ah, ic->ic_myaddr); 288 289 /* call MI attach routine. */ 290 ieee80211_ifattach(ifp); 291 /* override default methods */ 292 ic->ic_node_alloc = ath_node_alloc; 293 ic->ic_node_free = ath_node_free; 294 ic->ic_node_copy = ath_node_copy; 295 ic->ic_node_getrssi = ath_node_getrssi; 296 sc->sc_newstate = ic->ic_newstate; 297 ic->ic_newstate = ath_newstate; 298 /* complete initialization */ 299 ieee80211_media_init(ifp, ath_media_change, ieee80211_media_status); 300 301 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 302 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 303 &sc->sc_drvbpf); 304 /* 305 * Initialize constant fields. 306 * 307 * NB: the channel is setup each time we transition to the 308 * RUN state to avoid filling it in for each frame. 309 */ 310 sc->sc_tx_th.wt_ihdr.it_len = sizeof(sc->sc_tx_th); 311 sc->sc_tx_th.wt_ihdr.it_present = ATH_TX_RADIOTAP_PRESENT; 312 313 sc->sc_rx_th.wr_ihdr.it_len = sizeof(sc->sc_rx_th); 314 sc->sc_rx_th.wr_ihdr.it_present = ATH_RX_RADIOTAP_PRESENT; 315 316 if_printf(ifp, "802.11 address: %s\n", ether_sprintf(ic->ic_myaddr)); 317 318 return 0; 319 bad: 320 if (ah) 321 ath_hal_detach(ah); 322 sc->sc_invalid = 1; 323 return error; 324 } 325 326 int 327 ath_detach(struct ath_softc *sc) 328 { 329 struct ifnet *ifp = &sc->sc_ic.ic_if; 330 331 DPRINTF(("ath_detach: if_flags %x\n", ifp->if_flags)); 332 333 mtx_lock(&sc->sc_mtx); 334 ath_stop(ifp); 335 bpfdetach(ifp); 336 ath_desc_free(sc); 337 ath_hal_detach(sc->sc_ah); 338 ieee80211_ifdetach(ifp); 339 mtx_unlock(&sc->sc_mtx); 340 return 0; 341 } 342 343 void 344 ath_suspend(struct ath_softc *sc) 345 { 346 struct ifnet *ifp = &sc->sc_ic.ic_if; 347 348 DPRINTF(("ath_suspend: if_flags %x\n", ifp->if_flags)); 349 350 ath_stop(ifp); 351 } 352 353 void 354 ath_resume(struct ath_softc *sc) 355 { 356 struct ifnet *ifp = &sc->sc_ic.ic_if; 357 358 DPRINTF(("ath_resume: if_flags %x\n", ifp->if_flags)); 359 360 if (ifp->if_flags & IFF_UP) { 361 ath_init(ifp); 362 if (ifp->if_flags & IFF_RUNNING) 363 ath_start(ifp); 364 } 365 } 366 367 void 368 ath_shutdown(struct ath_softc *sc) 369 { 370 struct ifnet *ifp = &sc->sc_ic.ic_if; 371 372 DPRINTF(("ath_shutdown: if_flags %x\n", ifp->if_flags)); 373 374 ath_stop(ifp); 375 } 376 377 void 378 ath_intr(void *arg) 379 { 380 struct ath_softc *sc = arg; 381 struct ieee80211com *ic = &sc->sc_ic; 382 struct ifnet *ifp = &ic->ic_if; 383 struct ath_hal *ah = sc->sc_ah; 384 HAL_INT status; 385 386 if (sc->sc_invalid) { 387 /* 388 * The hardware is not ready/present, don't touch anything. 389 * Note this can happen early on if the IRQ is shared. 390 */ 391 DPRINTF(("ath_intr: invalid; ignored\n")); 392 return; 393 } 394 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 395 DPRINTF(("ath_intr: if_flags 0x%x\n", ifp->if_flags)); 396 ath_hal_getisr(ah, &status); /* clear ISR */ 397 ath_hal_intrset(ah, 0); /* disable further intr's */ 398 return; 399 } 400 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 401 DPRINTF2(("ath_intr: status 0x%x\n", status)); 402 #ifdef AR_DEBUG 403 if (ath_debug && 404 (status & (HAL_INT_FATAL|HAL_INT_RXORN|HAL_INT_BMISS))) { 405 if_printf(ifp, "ath_intr: status 0x%x\n", status); 406 ath_hal_dumpstate(ah); 407 } 408 #endif /* AR_DEBUG */ 409 status &= sc->sc_imask; /* discard unasked for bits */ 410 if (status & HAL_INT_FATAL) { 411 sc->sc_stats.ast_hardware++; 412 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 413 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask); 414 } else if (status & HAL_INT_RXORN) { 415 sc->sc_stats.ast_rxorn++; 416 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 417 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask); 418 } else { 419 if (status & HAL_INT_RXEOL) { 420 /* 421 * NB: the hardware should re-read the link when 422 * RXE bit is written, but it doesn't work at 423 * least on older hardware revs. 424 */ 425 sc->sc_stats.ast_rxeol++; 426 sc->sc_rxlink = NULL; 427 } 428 if (status & HAL_INT_TXURN) { 429 sc->sc_stats.ast_txurn++; 430 /* bump tx trigger level */ 431 ath_hal_updatetxtriglevel(ah, AH_TRUE); 432 } 433 if (status & HAL_INT_RX) 434 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask); 435 if (status & HAL_INT_TX) 436 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask); 437 if (status & HAL_INT_SWBA) 438 taskqueue_enqueue(taskqueue_swi, &sc->sc_swbatask); 439 if (status & HAL_INT_BMISS) { 440 sc->sc_stats.ast_bmiss++; 441 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask); 442 } 443 } 444 } 445 446 static void 447 ath_fatal_proc(void *arg, int pending) 448 { 449 struct ath_softc *sc = arg; 450 451 device_printf(sc->sc_dev, "hardware error; resetting\n"); 452 ath_reset(sc); 453 } 454 455 static void 456 ath_rxorn_proc(void *arg, int pending) 457 { 458 struct ath_softc *sc = arg; 459 460 device_printf(sc->sc_dev, "rx FIFO overrun; resetting\n"); 461 ath_reset(sc); 462 } 463 464 static void 465 ath_bmiss_proc(void *arg, int pending) 466 { 467 struct ath_softc *sc = arg; 468 struct ieee80211com *ic = &sc->sc_ic; 469 470 DPRINTF(("ath_bmiss_proc: pending %u\n", pending)); 471 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 472 ("unexpect operating mode %u", ic->ic_opmode)); 473 if (ic->ic_state == IEEE80211_S_RUN) 474 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 475 } 476 477 static u_int 478 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 479 { 480 static const u_int modeflags[] = { 481 0, /* IEEE80211_MODE_AUTO */ 482 CHANNEL_A, /* IEEE80211_MODE_11A */ 483 CHANNEL_B, /* IEEE80211_MODE_11B */ 484 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 485 CHANNEL_T /* IEEE80211_MODE_TURBO */ 486 }; 487 return modeflags[ieee80211_chan2mode(ic, chan)]; 488 } 489 490 static void 491 ath_init(void *arg) 492 { 493 struct ath_softc *sc = (struct ath_softc *) arg; 494 struct ieee80211com *ic = &sc->sc_ic; 495 struct ifnet *ifp = &ic->ic_if; 496 struct ieee80211_node *ni; 497 enum ieee80211_phymode mode; 498 struct ath_hal *ah = sc->sc_ah; 499 HAL_STATUS status; 500 HAL_CHANNEL hchan; 501 502 DPRINTF(("ath_init: if_flags 0x%x\n", ifp->if_flags)); 503 504 mtx_lock(&sc->sc_mtx); 505 /* 506 * Stop anything previously setup. This is safe 507 * whether this is the first time through or not. 508 */ 509 ath_stop(ifp); 510 511 /* 512 * The basic interface to setting the hardware in a good 513 * state is ``reset''. On return the hardware is known to 514 * be powered up and with interrupts disabled. This must 515 * be followed by initialization of the appropriate bits 516 * and then setup of the interrupt mask. 517 */ 518 hchan.channel = ic->ic_ibss_chan->ic_freq; 519 hchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 520 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_FALSE, &status)) { 521 if_printf(ifp, "unable to reset hardware; hal status %u\n", 522 status); 523 goto done; 524 } 525 526 /* 527 * Setup the hardware after reset: the key cache 528 * is filled as needed and the receive engine is 529 * set going. Frame transmit is handled entirely 530 * in the frame output path; there's nothing to do 531 * here except setup the interrupt mask. 532 */ 533 if (ic->ic_flags & IEEE80211_F_WEPON) 534 ath_initkeytable(sc); 535 if (ath_startrecv(sc) != 0) { 536 if_printf(ifp, "unable to start recv logic\n"); 537 goto done; 538 } 539 540 /* 541 * Enable interrupts. 542 */ 543 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 544 | HAL_INT_RXEOL | HAL_INT_RXORN 545 | HAL_INT_FATAL | HAL_INT_GLOBAL; 546 ath_hal_intrset(ah, sc->sc_imask); 547 548 ifp->if_flags |= IFF_RUNNING; 549 ic->ic_state = IEEE80211_S_INIT; 550 551 /* 552 * The hardware should be ready to go now so it's safe 553 * to kick the 802.11 state machine as it's likely to 554 * immediately call back to us to send mgmt frames. 555 */ 556 ni = ic->ic_bss; 557 ni->ni_chan = ic->ic_ibss_chan; 558 mode = ieee80211_chan2mode(ic, ni->ni_chan); 559 if (mode != sc->sc_curmode) 560 ath_setcurmode(sc, mode); 561 if (ic->ic_opmode != IEEE80211_M_MONITOR) 562 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 563 else 564 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 565 done: 566 mtx_unlock(&sc->sc_mtx); 567 } 568 569 static void 570 ath_stop(struct ifnet *ifp) 571 { 572 struct ieee80211com *ic = (struct ieee80211com *) ifp; 573 struct ath_softc *sc = ifp->if_softc; 574 struct ath_hal *ah = sc->sc_ah; 575 576 DPRINTF(("ath_stop: invalid %u if_flags 0x%x\n", 577 sc->sc_invalid, ifp->if_flags)); 578 579 mtx_lock(&sc->sc_mtx); 580 if (ifp->if_flags & IFF_RUNNING) { 581 /* 582 * Shutdown the hardware and driver: 583 * disable interrupts 584 * turn off timers 585 * clear transmit machinery 586 * clear receive machinery 587 * drain and release tx queues 588 * reclaim beacon resources 589 * reset 802.11 state machine 590 * power down hardware 591 * 592 * Note that some of this work is not possible if the 593 * hardware is gone (invalid). 594 */ 595 ifp->if_flags &= ~IFF_RUNNING; 596 ifp->if_timer = 0; 597 if (!sc->sc_invalid) 598 ath_hal_intrset(ah, 0); 599 ath_draintxq(sc); 600 if (!sc->sc_invalid) 601 ath_stoprecv(sc); 602 else 603 sc->sc_rxlink = NULL; 604 IF_DRAIN(&ifp->if_snd); 605 ath_beacon_free(sc); 606 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 607 if (!sc->sc_invalid) 608 ath_hal_setpower(ah, HAL_PM_FULL_SLEEP, 0); 609 } 610 mtx_unlock(&sc->sc_mtx); 611 } 612 613 /* 614 * Reset the hardware w/o losing operational state. This is 615 * basically a more efficient way of doing ath_stop, ath_init, 616 * followed by state transitions to the current 802.11 617 * operational state. Used to recover from errors rx overrun 618 * and to reset the hardware when rf gain settings must be reset. 619 */ 620 static void 621 ath_reset(struct ath_softc *sc) 622 { 623 struct ieee80211com *ic = &sc->sc_ic; 624 struct ifnet *ifp = &ic->ic_if; 625 struct ath_hal *ah = sc->sc_ah; 626 struct ieee80211_channel *c; 627 HAL_STATUS status; 628 HAL_CHANNEL hchan; 629 630 /* 631 * Convert to a HAL channel description with the flags 632 * constrained to reflect the current operating mode. 633 */ 634 c = ic->ic_ibss_chan; 635 hchan.channel = c->ic_freq; 636 hchan.channelFlags = ath_chan2flags(ic, c); 637 638 ath_hal_intrset(ah, 0); /* disable interrupts */ 639 ath_draintxq(sc); /* stop xmit side */ 640 ath_stoprecv(sc); /* stop recv side */ 641 /* NB: indicate channel change so we do a full reset */ 642 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) 643 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 644 __func__, status); 645 ath_hal_intrset(ah, sc->sc_imask); 646 if (ath_startrecv(sc) != 0) /* restart recv */ 647 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 648 ath_start(ifp); /* restart xmit */ 649 if (ic->ic_state == IEEE80211_S_RUN) 650 ath_beacon_config(sc); /* restart beacons */ 651 } 652 653 static void 654 ath_start(struct ifnet *ifp) 655 { 656 struct ath_softc *sc = ifp->if_softc; 657 struct ath_hal *ah = sc->sc_ah; 658 struct ieee80211com *ic = &sc->sc_ic; 659 struct ieee80211_node *ni; 660 struct ath_buf *bf; 661 struct mbuf *m; 662 struct ieee80211_frame *wh; 663 664 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 665 return; 666 for (;;) { 667 /* 668 * Grab a TX buffer and associated resources. 669 */ 670 mtx_lock(&sc->sc_txbuflock); 671 bf = TAILQ_FIRST(&sc->sc_txbuf); 672 if (bf != NULL) 673 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 674 mtx_unlock(&sc->sc_txbuflock); 675 if (bf == NULL) { 676 DPRINTF(("ath_start: out of xmit buffers\n")); 677 sc->sc_stats.ast_tx_qstop++; 678 ifp->if_flags |= IFF_OACTIVE; 679 break; 680 } 681 /* 682 * Poll the management queue for frames; they 683 * have priority over normal data frames. 684 */ 685 IF_DEQUEUE(&ic->ic_mgtq, m); 686 if (m == NULL) { 687 /* 688 * No data frames go out unless we're associated. 689 */ 690 if (ic->ic_state != IEEE80211_S_RUN) { 691 DPRINTF(("ath_start: ignore data packet, " 692 "state %u\n", ic->ic_state)); 693 sc->sc_stats.ast_tx_discard++; 694 mtx_lock(&sc->sc_txbuflock); 695 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 696 mtx_unlock(&sc->sc_txbuflock); 697 break; 698 } 699 IF_DEQUEUE(&ifp->if_snd, m); 700 if (m == NULL) { 701 mtx_lock(&sc->sc_txbuflock); 702 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 703 mtx_unlock(&sc->sc_txbuflock); 704 break; 705 } 706 ifp->if_opackets++; 707 BPF_MTAP(ifp, m); 708 /* 709 * Encapsulate the packet in prep for transmission. 710 */ 711 m = ieee80211_encap(ifp, m, &ni); 712 if (m == NULL) { 713 DPRINTF(("ath_start: encapsulation failure\n")); 714 sc->sc_stats.ast_tx_encap++; 715 goto bad; 716 } 717 wh = mtod(m, struct ieee80211_frame *); 718 if (ic->ic_flags & IEEE80211_F_WEPON) 719 wh->i_fc[1] |= IEEE80211_FC1_WEP; 720 } else { 721 /* 722 * Hack! The referenced node pointer is in the 723 * rcvif field of the packet header. This is 724 * placed there by ieee80211_mgmt_output because 725 * we need to hold the reference with the frame 726 * and there's no other way (other than packet 727 * tags which we consider too expensive to use) 728 * to pass it along. 729 */ 730 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 731 m->m_pkthdr.rcvif = NULL; 732 733 wh = mtod(m, struct ieee80211_frame *); 734 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 735 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 736 /* fill time stamp */ 737 u_int64_t tsf; 738 u_int32_t *tstamp; 739 740 tsf = ath_hal_gettsf64(ah); 741 /* XXX: adjust 100us delay to xmit */ 742 tsf += 100; 743 tstamp = (u_int32_t *)&wh[1]; 744 tstamp[0] = htole32(tsf & 0xffffffff); 745 tstamp[1] = htole32(tsf >> 32); 746 } 747 sc->sc_stats.ast_tx_mgmt++; 748 } 749 if (ic->ic_rawbpf) 750 bpf_mtap(ic->ic_rawbpf, m); 751 752 if (sc->sc_drvbpf) { 753 struct mbuf *mb; 754 755 MGETHDR(mb, M_DONTWAIT, m->m_type); 756 if (mb != NULL) { 757 sc->sc_tx_th.wt_rate = 758 ni->ni_rates.rs_rates[ni->ni_txrate]; 759 760 mb->m_next = m; 761 mb->m_data = (caddr_t)&sc->sc_tx_th; 762 mb->m_len = sizeof(sc->sc_tx_th); 763 mb->m_pkthdr.len += mb->m_len; 764 bpf_mtap(sc->sc_drvbpf, mb); 765 m_free(mb); 766 } 767 } 768 769 if (ath_tx_start(sc, ni, bf, m)) { 770 bad: 771 mtx_lock(&sc->sc_txbuflock); 772 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 773 mtx_unlock(&sc->sc_txbuflock); 774 ifp->if_oerrors++; 775 if (ni && ni != ic->ic_bss) 776 ieee80211_free_node(ic, ni); 777 continue; 778 } 779 780 sc->sc_tx_timer = 5; 781 ifp->if_timer = 1; 782 } 783 } 784 785 static int 786 ath_media_change(struct ifnet *ifp) 787 { 788 int error; 789 790 error = ieee80211_media_change(ifp); 791 if (error == ENETRESET) { 792 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 793 (IFF_RUNNING|IFF_UP)) 794 ath_init(ifp); /* XXX lose error */ 795 error = 0; 796 } 797 return error; 798 } 799 800 static void 801 ath_watchdog(struct ifnet *ifp) 802 { 803 struct ath_softc *sc = ifp->if_softc; 804 struct ieee80211com *ic = &sc->sc_ic; 805 806 ifp->if_timer = 0; 807 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 808 return; 809 if (sc->sc_tx_timer) { 810 if (--sc->sc_tx_timer == 0) { 811 if_printf(ifp, "device timeout\n"); 812 #ifdef AR_DEBUG 813 if (ath_debug) 814 ath_hal_dumpstate(sc->sc_ah); 815 #endif /* AR_DEBUG */ 816 ath_init(ifp); /* XXX ath_reset??? */ 817 ifp->if_oerrors++; 818 sc->sc_stats.ast_watchdog++; 819 return; 820 } 821 ifp->if_timer = 1; 822 } 823 if (ic->ic_fixed_rate == -1) { 824 /* 825 * Run the rate control algorithm if we're not 826 * locked at a fixed rate. 827 */ 828 if (ic->ic_opmode == IEEE80211_M_STA) 829 ath_rate_ctl(sc, ic->ic_bss); 830 else 831 ieee80211_iterate_nodes(ic, ath_rate_ctl, sc); 832 } 833 ieee80211_watchdog(ifp); 834 } 835 836 static int 837 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 838 { 839 struct ath_softc *sc = ifp->if_softc; 840 struct ifreq *ifr = (struct ifreq *)data; 841 int error = 0; 842 843 mtx_lock(&sc->sc_mtx); 844 switch (cmd) { 845 case SIOCSIFFLAGS: 846 if (ifp->if_flags & IFF_UP) { 847 if (ifp->if_flags & IFF_RUNNING) { 848 /* 849 * To avoid rescanning another access point, 850 * do not call ath_init() here. Instead, 851 * only reflect promisc mode settings. 852 */ 853 ath_mode_init(sc); 854 } else 855 ath_init(ifp); /* XXX lose error */ 856 } else 857 ath_stop(ifp); 858 break; 859 case SIOCADDMULTI: 860 case SIOCDELMULTI: 861 /* 862 * The upper layer has already installed/removed 863 * the multicast address(es), just recalculate the 864 * multicast filter for the card. 865 */ 866 if (ifp->if_flags & IFF_RUNNING) 867 ath_mode_init(sc); 868 break; 869 case SIOCGATHSTATS: 870 copyout(&sc->sc_stats, ifr->ifr_data, sizeof (sc->sc_stats)); 871 break; 872 default: 873 error = ieee80211_ioctl(ifp, cmd, data); 874 if (error == ENETRESET) { 875 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 876 (IFF_RUNNING|IFF_UP)) 877 ath_init(ifp); /* XXX lose error */ 878 error = 0; 879 } 880 break; 881 } 882 mtx_unlock(&sc->sc_mtx); 883 return error; 884 } 885 886 /* 887 * Fill the hardware key cache with key entries. 888 */ 889 static void 890 ath_initkeytable(struct ath_softc *sc) 891 { 892 struct ieee80211com *ic = &sc->sc_ic; 893 struct ath_hal *ah = sc->sc_ah; 894 int i; 895 896 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 897 struct ieee80211_wepkey *k = &ic->ic_nw_keys[i]; 898 if (k->wk_len == 0) 899 ath_hal_keyreset(ah, i); 900 else 901 /* XXX return value */ 902 /* NB: this uses HAL_KEYVAL == ieee80211_wepkey */ 903 ath_hal_keyset(ah, i, (const HAL_KEYVAL *) k); 904 } 905 } 906 907 static void 908 ath_mode_init(struct ath_softc *sc) 909 { 910 struct ieee80211com *ic = &sc->sc_ic; 911 struct ath_hal *ah = sc->sc_ah; 912 struct ifnet *ifp = &ic->ic_if; 913 u_int32_t rfilt, mfilt[2], val; 914 u_int8_t pos; 915 struct ifmultiaddr *ifma; 916 917 /* configure operational mode */ 918 ath_hal_setopmode(ah, ic->ic_opmode); 919 920 /* receive filter */ 921 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 922 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 923 if (ic->ic_opmode != IEEE80211_M_STA) 924 rfilt |= HAL_RX_FILTER_PROBEREQ; 925 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 926 (ifp->if_flags & IFF_PROMISC)) 927 rfilt |= HAL_RX_FILTER_PROM; 928 if (ic->ic_opmode == IEEE80211_M_STA || 929 ic->ic_state == IEEE80211_S_SCAN) 930 rfilt |= HAL_RX_FILTER_BEACON; 931 ath_hal_setrxfilter(ah, rfilt); 932 933 /* calculate and install multicast filter */ 934 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 935 mfilt[0] = mfilt[1] = 0; 936 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 937 caddr_t dl; 938 939 /* calculate XOR of eight 6bit values */ 940 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 941 val = LE_READ_4(dl + 0); 942 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 943 val = LE_READ_4(dl + 3); 944 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 945 pos &= 0x3f; 946 mfilt[pos / 32] |= (1 << (pos % 32)); 947 } 948 } else { 949 mfilt[0] = mfilt[1] = ~0; 950 } 951 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 952 DPRINTF(("ath_mode_init: RX filter 0x%x, MC filter %08x:%08x\n", 953 rfilt, mfilt[0], mfilt[1])); 954 } 955 956 static void 957 ath_mbuf_load_cb(void *arg, bus_dma_segment_t *seg, int nseg, bus_size_t mapsize, int error) 958 { 959 struct ath_buf *bf = arg; 960 961 KASSERT(nseg <= ATH_MAX_SCATTER, 962 ("ath_mbuf_load_cb: too many DMA segments %u", nseg)); 963 bf->bf_mapsize = mapsize; 964 bf->bf_nseg = nseg; 965 bcopy(seg, bf->bf_segs, nseg * sizeof (seg[0])); 966 } 967 968 static int 969 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 970 { 971 struct ieee80211com *ic = &sc->sc_ic; 972 struct ifnet *ifp = &ic->ic_if; 973 struct ath_hal *ah = sc->sc_ah; 974 struct ieee80211_frame *wh; 975 struct ath_buf *bf; 976 struct ath_desc *ds; 977 struct mbuf *m; 978 int error, pktlen; 979 u_int8_t *frm, rate; 980 u_int16_t capinfo; 981 struct ieee80211_rateset *rs; 982 const HAL_RATE_TABLE *rt; 983 984 bf = sc->sc_bcbuf; 985 if (bf->bf_m != NULL) { 986 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 987 m_freem(bf->bf_m); 988 bf->bf_m = NULL; 989 bf->bf_node = NULL; 990 } 991 /* 992 * NB: the beacon data buffer must be 32-bit aligned; 993 * we assume the mbuf routines will return us something 994 * with this alignment (perhaps should assert). 995 */ 996 rs = &ni->ni_rates; 997 pktlen = sizeof (struct ieee80211_frame) 998 + 8 + 2 + 2 + 2+ni->ni_esslen + 2+rs->rs_nrates + 6; 999 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 1000 pktlen += 2; 1001 if (pktlen <= MHLEN) 1002 MGETHDR(m, M_DONTWAIT, MT_DATA); 1003 else 1004 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1005 if (m == NULL) { 1006 DPRINTF(("ath_beacon_alloc: cannot get mbuf/cluster; size %u\n", 1007 pktlen)); 1008 sc->sc_stats.ast_be_nombuf++; 1009 return ENOMEM; 1010 } 1011 1012 wh = mtod(m, struct ieee80211_frame *); 1013 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1014 IEEE80211_FC0_SUBTYPE_BEACON; 1015 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1016 *(u_int16_t *)wh->i_dur = 0; 1017 memcpy(wh->i_addr1, ifp->if_broadcastaddr, IEEE80211_ADDR_LEN); 1018 memcpy(wh->i_addr2, ic->ic_myaddr, IEEE80211_ADDR_LEN); 1019 memcpy(wh->i_addr3, ni->ni_bssid, IEEE80211_ADDR_LEN); 1020 *(u_int16_t *)wh->i_seq = 0; 1021 1022 /* 1023 * beacon frame format 1024 * [8] time stamp 1025 * [2] beacon interval 1026 * [2] cabability information 1027 * [tlv] ssid 1028 * [tlv] supported rates 1029 * [tlv] parameter set (IBSS) 1030 * [tlv] extended supported rates 1031 */ 1032 frm = (u_int8_t *)&wh[1]; 1033 memset(frm, 0, 8); /* timestamp is set by hardware */ 1034 frm += 8; 1035 *(u_int16_t *)frm = htole16(ni->ni_intval); 1036 frm += 2; 1037 if (ic->ic_opmode == IEEE80211_M_IBSS) 1038 capinfo = IEEE80211_CAPINFO_IBSS; 1039 else 1040 capinfo = IEEE80211_CAPINFO_ESS; 1041 if (ic->ic_flags & IEEE80211_F_WEPON) 1042 capinfo |= IEEE80211_CAPINFO_PRIVACY; 1043 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1044 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 1045 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 1046 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1047 capinfo |= IEEE80211_CAPINFO_SHORT_SLOTTIME; 1048 *(u_int16_t *)frm = htole16(capinfo); 1049 frm += 2; 1050 *frm++ = IEEE80211_ELEMID_SSID; 1051 *frm++ = ni->ni_esslen; 1052 memcpy(frm, ni->ni_essid, ni->ni_esslen); 1053 frm += ni->ni_esslen; 1054 frm = ieee80211_add_rates(frm, rs); 1055 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1056 *frm++ = IEEE80211_ELEMID_IBSSPARMS; 1057 *frm++ = 2; 1058 *frm++ = 0; *frm++ = 0; /* TODO: ATIM window */ 1059 } else { 1060 /* TODO: TIM */ 1061 *frm++ = IEEE80211_ELEMID_TIM; 1062 *frm++ = 4; /* length */ 1063 *frm++ = 0; /* DTIM count */ 1064 *frm++ = 1; /* DTIM period */ 1065 *frm++ = 0; /* bitmap control */ 1066 *frm++ = 0; /* Partial Virtual Bitmap (variable length) */ 1067 } 1068 frm = ieee80211_add_xrates(frm, rs); 1069 m->m_pkthdr.len = m->m_len = frm - mtod(m, u_int8_t *); 1070 KASSERT(m->m_pkthdr.len <= pktlen, 1071 ("beacon bigger than expected, len %u calculated %u", 1072 m->m_pkthdr.len, pktlen)); 1073 1074 DPRINTF2(("ath_beacon_alloc: m %p len %u\n", m, m->m_len)); 1075 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1076 ath_mbuf_load_cb, bf, 1077 BUS_DMA_NOWAIT); 1078 if (error != 0) { 1079 m_freem(m); 1080 return error; 1081 } 1082 KASSERT(bf->bf_nseg == 1, 1083 ("ath_beacon_alloc: multi-segment packet; nseg %u", 1084 bf->bf_nseg)); 1085 bf->bf_m = m; 1086 1087 /* setup descriptors */ 1088 ds = bf->bf_desc; 1089 1090 ds->ds_link = 0; 1091 ds->ds_data = bf->bf_segs[0].ds_addr; 1092 /* 1093 * Calculate rate code. 1094 * XXX everything at min xmit rate 1095 */ 1096 rt = sc->sc_currates; 1097 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1098 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1099 rate = rt->info[0].rateCode | rt->info[0].shortPreamble; 1100 else 1101 rate = rt->info[0].rateCode; 1102 ath_hal_setuptxdesc(ah, ds 1103 , m->m_pkthdr.len + IEEE80211_CRC_LEN /* packet length */ 1104 , sizeof(struct ieee80211_frame) /* header length */ 1105 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1106 , 0x20 /* txpower XXX */ 1107 , rate, 1 /* series 0 rate/tries */ 1108 , HAL_TXKEYIX_INVALID /* no encryption */ 1109 , 0 /* antenna mode */ 1110 , HAL_TXDESC_NOACK /* no ack for beacons */ 1111 , 0 /* rts/cts rate */ 1112 , 0 /* rts/cts duration */ 1113 ); 1114 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1115 /* XXX verify mbuf data area covers this roundup */ 1116 ath_hal_filltxdesc(ah, ds 1117 , roundup(bf->bf_segs[0].ds_len, 4) /* buffer length */ 1118 , AH_TRUE /* first segment */ 1119 , AH_TRUE /* last segment */ 1120 ); 1121 1122 return 0; 1123 } 1124 1125 static void 1126 ath_beacon_proc(void *arg, int pending) 1127 { 1128 struct ath_softc *sc = arg; 1129 struct ieee80211com *ic = &sc->sc_ic; 1130 struct ath_buf *bf = sc->sc_bcbuf; 1131 struct ath_hal *ah = sc->sc_ah; 1132 1133 DPRINTF2(("%s: pending %u\n", __func__, pending)); 1134 if (ic->ic_opmode == IEEE80211_M_STA || 1135 bf == NULL || bf->bf_m == NULL) { 1136 DPRINTF(("%s: ic_flags=%x bf=%p bf_m=%p\n", 1137 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL)); 1138 return; 1139 } 1140 /* TODO: update beacon to reflect PS poll state */ 1141 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1142 DPRINTF(("%s: beacon queue %u did not stop?", 1143 __func__, sc->sc_bhalq)); 1144 return; /* busy, XXX is this right? */ 1145 } 1146 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1147 1148 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 1149 ath_hal_txstart(ah, sc->sc_bhalq); 1150 DPRINTF2(("%s: TXDP%u = %p (%p)\n", __func__, 1151 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1152 } 1153 1154 static void 1155 ath_beacon_free(struct ath_softc *sc) 1156 { 1157 struct ath_buf *bf = sc->sc_bcbuf; 1158 1159 if (bf->bf_m != NULL) { 1160 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1161 m_freem(bf->bf_m); 1162 bf->bf_m = NULL; 1163 bf->bf_node = NULL; 1164 } 1165 } 1166 1167 /* 1168 * Configure the beacon and sleep timers. 1169 * 1170 * When operating as an AP this resets the TSF and sets 1171 * up the hardware to notify us when we need to issue beacons. 1172 * 1173 * When operating in station mode this sets up the beacon 1174 * timers according to the timestamp of the last received 1175 * beacon and the current TSF, configures PCF and DTIM 1176 * handling, programs the sleep registers so the hardware 1177 * will wakeup in time to receive beacons, and configures 1178 * the beacon miss handling so we'll receive a BMISS 1179 * interrupt when we stop seeing beacons from the AP 1180 * we've associated with. 1181 */ 1182 static void 1183 ath_beacon_config(struct ath_softc *sc) 1184 { 1185 struct ath_hal *ah = sc->sc_ah; 1186 struct ieee80211com *ic = &sc->sc_ic; 1187 struct ieee80211_node *ni = ic->ic_bss; 1188 u_int32_t nexttbtt; 1189 1190 nexttbtt = (LE_READ_4(ni->ni_tstamp + 4) << 22) | 1191 (LE_READ_4(ni->ni_tstamp) >> 10); 1192 DPRINTF(("%s: nexttbtt=%u\n", __func__, nexttbtt)); 1193 nexttbtt += ni->ni_intval; 1194 if (ic->ic_opmode == IEEE80211_M_STA) { 1195 HAL_BEACON_STATE bs; 1196 u_int32_t bmisstime; 1197 1198 /* NB: no PCF support right now */ 1199 memset(&bs, 0, sizeof(bs)); 1200 bs.bs_intval = ni->ni_intval; 1201 bs.bs_nexttbtt = nexttbtt; 1202 bs.bs_dtimperiod = bs.bs_intval; 1203 bs.bs_nextdtim = nexttbtt; 1204 /* 1205 * Calculate the number of consecutive beacons to miss 1206 * before taking a BMISS interrupt. The configuration 1207 * is specified in ms, so we need to convert that to 1208 * TU's and then calculate based on the beacon interval. 1209 * Note that we clamp the result to at most 10 beacons. 1210 */ 1211 bmisstime = (ic->ic_bmisstimeout * 1000) / 1024; 1212 bs.bs_bmissthreshold = howmany(bmisstime,ni->ni_intval); 1213 if (bs.bs_bmissthreshold > 10) 1214 bs.bs_bmissthreshold = 10; 1215 else if (bs.bs_bmissthreshold <= 0) 1216 bs.bs_bmissthreshold = 1; 1217 1218 /* 1219 * Calculate sleep duration. The configuration is 1220 * given in ms. We insure a multiple of the beacon 1221 * period is used. Also, if the sleep duration is 1222 * greater than the DTIM period then it makes senses 1223 * to make it a multiple of that. 1224 * 1225 * XXX fixed at 100ms 1226 */ 1227 bs.bs_sleepduration = 1228 roundup((100 * 1000) / 1024, bs.bs_intval); 1229 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1230 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1231 1232 DPRINTF(("%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u\n" 1233 , __func__ 1234 , bs.bs_intval 1235 , bs.bs_nexttbtt 1236 , bs.bs_dtimperiod 1237 , bs.bs_nextdtim 1238 , bs.bs_bmissthreshold 1239 , bs.bs_sleepduration 1240 )); 1241 ath_hal_intrset(ah, 0); 1242 /* 1243 * Reset our tsf so the hardware will update the 1244 * tsf register to reflect timestamps found in 1245 * received beacons. 1246 */ 1247 ath_hal_resettsf(ah); 1248 ath_hal_beacontimers(ah, &bs, 0/*XXX*/, 0, 0); 1249 sc->sc_imask |= HAL_INT_BMISS; 1250 ath_hal_intrset(ah, sc->sc_imask); 1251 } else { 1252 DPRINTF(("%s: intval %u nexttbtt %u\n", 1253 __func__, ni->ni_intval, nexttbtt)); 1254 ath_hal_intrset(ah, 0); 1255 ath_hal_beaconinit(ah, ic->ic_opmode, 1256 nexttbtt, ni->ni_intval); 1257 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1258 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1259 ath_hal_intrset(ah, sc->sc_imask); 1260 } 1261 } 1262 1263 static void 1264 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1265 { 1266 bus_addr_t *paddr = (bus_addr_t*) arg; 1267 *paddr = segs->ds_addr; 1268 } 1269 1270 static int 1271 ath_desc_alloc(struct ath_softc *sc) 1272 { 1273 int i, bsize, error; 1274 struct ath_desc *ds; 1275 struct ath_buf *bf; 1276 1277 /* allocate descriptors */ 1278 sc->sc_desc_len = sizeof(struct ath_desc) * 1279 (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + 1); 1280 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1281 if (error != 0) 1282 return error; 1283 1284 error = bus_dmamem_alloc(sc->sc_dmat, (void**) &sc->sc_desc, 1285 BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1286 if (error != 0) 1287 goto fail0; 1288 1289 error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, 1290 sc->sc_desc, sc->sc_desc_len, 1291 ath_load_cb, &sc->sc_desc_paddr, 1292 BUS_DMA_NOWAIT); 1293 if (error != 0) 1294 goto fail1; 1295 1296 ds = sc->sc_desc; 1297 DPRINTF(("ath_desc_alloc: DMA map: %p (%d) -> %p (%lu)\n", 1298 ds, sc->sc_desc_len, 1299 (caddr_t) sc->sc_desc_paddr, /*XXX*/ (u_long) sc->sc_desc_len)); 1300 1301 /* allocate buffers */ 1302 bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 1); 1303 bf = malloc(bsize, M_DEVBUF, M_NOWAIT | M_ZERO); 1304 if (bf == NULL) 1305 goto fail2; 1306 sc->sc_bufptr = bf; 1307 1308 TAILQ_INIT(&sc->sc_rxbuf); 1309 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 1310 bf->bf_desc = ds; 1311 bf->bf_daddr = sc->sc_desc_paddr + 1312 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1313 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1314 &bf->bf_dmamap); 1315 if (error != 0) 1316 break; 1317 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1318 } 1319 1320 TAILQ_INIT(&sc->sc_txbuf); 1321 for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { 1322 bf->bf_desc = ds; 1323 bf->bf_daddr = sc->sc_desc_paddr + 1324 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1325 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1326 &bf->bf_dmamap); 1327 if (error != 0) 1328 break; 1329 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1330 } 1331 TAILQ_INIT(&sc->sc_txq); 1332 1333 /* beacon buffer */ 1334 bf->bf_desc = ds; 1335 bf->bf_daddr = sc->sc_desc_paddr + ((caddr_t)ds - (caddr_t)sc->sc_desc); 1336 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &bf->bf_dmamap); 1337 if (error != 0) 1338 return error; 1339 sc->sc_bcbuf = bf; 1340 return 0; 1341 1342 fail2: 1343 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1344 fail1: 1345 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1346 fail0: 1347 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1348 sc->sc_ddmamap = NULL; 1349 return error; 1350 } 1351 1352 static void 1353 ath_desc_free(struct ath_softc *sc) 1354 { 1355 struct ath_buf *bf; 1356 1357 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1358 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1359 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1360 1361 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1362 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1363 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1364 m_freem(bf->bf_m); 1365 } 1366 TAILQ_FOREACH(bf, &sc->sc_txbuf, bf_list) 1367 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1368 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1369 if (bf->bf_m) { 1370 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1371 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1372 m_freem(bf->bf_m); 1373 bf->bf_m = NULL; 1374 } 1375 } 1376 if (sc->sc_bcbuf != NULL) { 1377 bus_dmamap_unload(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1378 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1379 sc->sc_bcbuf = NULL; 1380 } 1381 1382 TAILQ_INIT(&sc->sc_rxbuf); 1383 TAILQ_INIT(&sc->sc_txbuf); 1384 TAILQ_INIT(&sc->sc_txq); 1385 free(sc->sc_bufptr, M_DEVBUF); 1386 sc->sc_bufptr = NULL; 1387 } 1388 1389 static struct ieee80211_node * 1390 ath_node_alloc(struct ieee80211com *ic) 1391 { 1392 struct ath_node *an = 1393 malloc(sizeof(struct ath_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1394 if (an) { 1395 int i; 1396 for (i = 0; i < ATH_RHIST_SIZE; i++) 1397 an->an_rx_hist[i].arh_ticks = ATH_RHIST_NOTIME; 1398 an->an_rx_hist_next = ATH_RHIST_SIZE-1; 1399 return &an->an_node; 1400 } else 1401 return NULL; 1402 } 1403 1404 static void 1405 ath_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 1406 { 1407 struct ath_softc *sc = ic->ic_if.if_softc; 1408 struct ath_buf *bf; 1409 1410 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1411 if (bf->bf_node == ni) 1412 bf->bf_node = NULL; 1413 } 1414 free(ni, M_DEVBUF); 1415 } 1416 1417 static void 1418 ath_node_copy(struct ieee80211com *ic, 1419 struct ieee80211_node *dst, const struct ieee80211_node *src) 1420 { 1421 *(struct ath_node *)dst = *(const struct ath_node *)src; 1422 } 1423 1424 1425 static u_int8_t 1426 ath_node_getrssi(struct ieee80211com *ic, struct ieee80211_node *ni) 1427 { 1428 struct ath_node *an = ATH_NODE(ni); 1429 int i, now, nsamples, rssi; 1430 1431 /* 1432 * Calculate the average over the last second of sampled data. 1433 */ 1434 now = ticks; 1435 nsamples = 0; 1436 rssi = 0; 1437 i = an->an_rx_hist_next; 1438 do { 1439 struct ath_recv_hist *rh = &an->an_rx_hist[i]; 1440 if (rh->arh_ticks == ATH_RHIST_NOTIME) 1441 goto done; 1442 if (now - rh->arh_ticks > hz) 1443 goto done; 1444 rssi += rh->arh_rssi; 1445 nsamples++; 1446 if (i == 0) 1447 i = ATH_RHIST_SIZE-1; 1448 else 1449 i--; 1450 } while (i != an->an_rx_hist_next); 1451 done: 1452 /* 1453 * Return either the average or the last known 1454 * value if there is no recent data. 1455 */ 1456 return (nsamples ? rssi / nsamples : an->an_rx_hist[i].arh_rssi); 1457 } 1458 1459 static int 1460 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 1461 { 1462 struct ath_hal *ah = sc->sc_ah; 1463 int error; 1464 struct mbuf *m; 1465 struct ath_desc *ds; 1466 1467 m = bf->bf_m; 1468 if (m == NULL) { 1469 /* 1470 * NB: by assigning a page to the rx dma buffer we 1471 * implicitly satisfy the Atheros requirement that 1472 * this buffer be cache-line-aligned and sized to be 1473 * multiple of the cache line size. Not doing this 1474 * causes weird stuff to happen (for the 5210 at least). 1475 */ 1476 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1477 if (m == NULL) { 1478 DPRINTF(("ath_rxbuf_init: no mbuf/cluster\n")); 1479 sc->sc_stats.ast_rx_nombuf++; 1480 return ENOMEM; 1481 } 1482 bf->bf_m = m; 1483 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1484 1485 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1486 ath_mbuf_load_cb, bf, 1487 BUS_DMA_NOWAIT); 1488 if (error != 0) { 1489 DPRINTF(("ath_rxbuf_init: bus_dmamap_load_mbuf failed;" 1490 " error %d\n", error)); 1491 sc->sc_stats.ast_rx_busdma++; 1492 return error; 1493 } 1494 KASSERT(bf->bf_nseg == 1, 1495 ("ath_rxbuf_init: multi-segment packet; nseg %u", 1496 bf->bf_nseg)); 1497 } 1498 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 1499 1500 /* setup descriptors */ 1501 ds = bf->bf_desc; 1502 ds->ds_link = 0; 1503 ds->ds_data = bf->bf_segs[0].ds_addr; 1504 ath_hal_setuprxdesc(ah, ds 1505 , m->m_len /* buffer size */ 1506 , 0 1507 ); 1508 1509 if (sc->sc_rxlink != NULL) 1510 *sc->sc_rxlink = bf->bf_daddr; 1511 sc->sc_rxlink = &ds->ds_link; 1512 return 0; 1513 } 1514 1515 static void 1516 ath_rx_proc(void *arg, int npending) 1517 { 1518 struct ath_softc *sc = arg; 1519 struct ath_buf *bf; 1520 struct ieee80211com *ic = &sc->sc_ic; 1521 struct ifnet *ifp = &ic->ic_if; 1522 struct ath_hal *ah = sc->sc_ah; 1523 struct ath_desc *ds; 1524 struct mbuf *m; 1525 struct ieee80211_frame *wh, whbuf; 1526 struct ieee80211_node *ni; 1527 struct ath_node *an; 1528 struct ath_recv_hist *rh; 1529 int len; 1530 u_int phyerr; 1531 HAL_STATUS status; 1532 1533 DPRINTF2(("ath_rx_proc: pending %u\n", npending)); 1534 do { 1535 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1536 if (bf == NULL) { /* NB: shouldn't happen */ 1537 if_printf(ifp, "ath_rx_proc: no buffer!\n"); 1538 break; 1539 } 1540 m = bf->bf_m; 1541 if (m == NULL) { /* NB: shouldn't happen */ 1542 if_printf(ifp, "ath_rx_proc: no mbuf!\n"); 1543 continue; 1544 } 1545 ds = bf->bf_desc; 1546 status = ath_hal_rxprocdesc(ah, ds); 1547 #ifdef AR_DEBUG 1548 if (ath_debug > 1) 1549 ath_printrxbuf(bf, status == HAL_OK); 1550 #endif 1551 if (status == HAL_EINPROGRESS) 1552 break; 1553 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1554 if (ds->ds_rxstat.rs_status != 0) { 1555 ifp->if_ierrors++; 1556 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 1557 sc->sc_stats.ast_rx_crcerr++; 1558 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 1559 sc->sc_stats.ast_rx_fifoerr++; 1560 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) 1561 sc->sc_stats.ast_rx_badcrypt++; 1562 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 1563 sc->sc_stats.ast_rx_phyerr++; 1564 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 1565 sc->sc_stats.ast_rx_phy[phyerr]++; 1566 } 1567 goto rx_next; 1568 } 1569 1570 len = ds->ds_rxstat.rs_datalen; 1571 if (len < IEEE80211_MIN_LEN) { 1572 DPRINTF(("ath_rx_proc: short packet %d\n", len)); 1573 sc->sc_stats.ast_rx_tooshort++; 1574 goto rx_next; 1575 } 1576 1577 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 1578 BUS_DMASYNC_POSTREAD); 1579 1580 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1581 bf->bf_m = NULL; 1582 m->m_pkthdr.rcvif = ifp; 1583 m->m_pkthdr.len = m->m_len = len; 1584 1585 if (sc->sc_drvbpf) { 1586 struct mbuf *mb; 1587 1588 /* XXX pre-allocate space when setting up recv's */ 1589 MGETHDR(mb, M_DONTWAIT, m->m_type); 1590 if (mb != NULL) { 1591 sc->sc_rx_th.wr_rate = 1592 sc->sc_hwmap[ds->ds_rxstat.rs_rate]; 1593 sc->sc_rx_th.wr_antsignal = 1594 ds->ds_rxstat.rs_rssi; 1595 sc->sc_rx_th.wr_antenna = 1596 ds->ds_rxstat.rs_antenna; 1597 /* XXX TSF */ 1598 1599 (void) m_dup_pkthdr(mb, m, M_DONTWAIT); 1600 mb->m_next = m; 1601 mb->m_data = (caddr_t)&sc->sc_rx_th; 1602 mb->m_len = sizeof(sc->sc_rx_th); 1603 mb->m_pkthdr.len += mb->m_len; 1604 bpf_mtap(sc->sc_drvbpf, mb); 1605 m_free(mb); 1606 } 1607 } 1608 1609 m_adj(m, -IEEE80211_CRC_LEN); 1610 wh = mtod(m, struct ieee80211_frame *); 1611 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1612 /* 1613 * WEP is decrypted by hardware. Clear WEP bit 1614 * and trim WEP header for ieee80211_input(). 1615 */ 1616 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 1617 memcpy(&whbuf, wh, sizeof(whbuf)); 1618 m_adj(m, IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN); 1619 memcpy(mtod(m, caddr_t), &whbuf, sizeof(whbuf)); 1620 /* 1621 * Also trim WEP ICV from the tail. 1622 */ 1623 m_adj(m, -IEEE80211_WEP_CRCLEN); 1624 } 1625 1626 /* 1627 * Locate the node for sender, track state, and 1628 * then pass this node (referenced) up to the 802.11 1629 * layer for its use. We are required to pass 1630 * something so we fall back to ic_bss when this frame 1631 * is from an unknown sender. 1632 */ 1633 if (ic->ic_opmode != IEEE80211_M_STA) { 1634 ni = ieee80211_find_node(ic, wh->i_addr2); 1635 if (ni == NULL) 1636 ni = ieee80211_ref_node(ic->ic_bss); 1637 } else 1638 ni = ieee80211_ref_node(ic->ic_bss); 1639 1640 /* 1641 * Record driver-specific state. 1642 */ 1643 an = ATH_NODE(ni); 1644 if (++(an->an_rx_hist_next) == ATH_RHIST_SIZE) 1645 an->an_rx_hist_next = 0; 1646 rh = &an->an_rx_hist[an->an_rx_hist_next]; 1647 rh->arh_ticks = ticks; 1648 rh->arh_rssi = ds->ds_rxstat.rs_rssi; 1649 rh->arh_antenna = ds->ds_rxstat.rs_antenna; 1650 1651 /* 1652 * Send frame up for processing. 1653 */ 1654 ieee80211_input(ifp, m, ni, 1655 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 1656 1657 /* 1658 * The frame may have caused the node to be marked for 1659 * reclamation (e.g. in response to a DEAUTH message) 1660 * so use free_node here instead of unref_node. 1661 */ 1662 if (ni == ic->ic_bss) 1663 ieee80211_unref_node(&ni); 1664 else 1665 ieee80211_free_node(ic, ni); 1666 rx_next: 1667 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1668 } while (ath_rxbuf_init(sc, bf) == 0); 1669 1670 ath_hal_rxmonitor(ah); /* rx signal state monitoring */ 1671 ath_hal_rxena(ah); /* in case of RXEOL */ 1672 } 1673 1674 /* 1675 * XXX Size of an ACK control frame in bytes. 1676 */ 1677 #define IEEE80211_ACK_SIZE (2+2+IEEE80211_ADDR_LEN+4) 1678 1679 static int 1680 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 1681 struct mbuf *m0) 1682 { 1683 struct ieee80211com *ic = &sc->sc_ic; 1684 struct ath_hal *ah = sc->sc_ah; 1685 struct ifnet *ifp = &sc->sc_ic.ic_if; 1686 int i, error, iswep, hdrlen, pktlen; 1687 u_int8_t rix, cix, txrate, ctsrate; 1688 struct ath_desc *ds; 1689 struct mbuf *m; 1690 struct ieee80211_frame *wh; 1691 u_int32_t iv; 1692 u_int8_t *ivp; 1693 u_int8_t hdrbuf[sizeof(struct ieee80211_frame) + 1694 IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN]; 1695 u_int subtype, flags, ctsduration, antenna; 1696 HAL_PKT_TYPE atype; 1697 const HAL_RATE_TABLE *rt; 1698 HAL_BOOL shortPreamble; 1699 struct ath_node *an; 1700 1701 wh = mtod(m0, struct ieee80211_frame *); 1702 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1703 hdrlen = sizeof(struct ieee80211_frame); 1704 pktlen = m0->m_pkthdr.len; 1705 1706 if (iswep) { 1707 memcpy(hdrbuf, mtod(m0, caddr_t), hdrlen); 1708 m_adj(m0, hdrlen); 1709 M_PREPEND(m0, sizeof(hdrbuf), M_DONTWAIT); 1710 if (m0 == NULL) { 1711 sc->sc_stats.ast_tx_nombuf++; 1712 return ENOMEM; 1713 } 1714 ivp = hdrbuf + hdrlen; 1715 /* 1716 * XXX 1717 * IV must not duplicate during the lifetime of the key. 1718 * But no mechanism to renew keys is defined in IEEE 802.11 1719 * WEP. And IV may be duplicated between other stations 1720 * because of the session key itself is shared. 1721 * So we use pseudo random IV for now, though it is not the 1722 * right way. 1723 */ 1724 iv = arc4random(); 1725 for (i = 0; i < IEEE80211_WEP_IVLEN; i++) { 1726 ivp[i] = iv; 1727 iv >>= 8; 1728 } 1729 ivp[i] = sc->sc_ic.ic_wep_txkey << 6; /* Key ID and pad */ 1730 memcpy(mtod(m0, caddr_t), hdrbuf, sizeof(hdrbuf)); 1731 /* 1732 * The ICV length must be included into hdrlen and pktlen. 1733 */ 1734 hdrlen = sizeof(hdrbuf) + IEEE80211_WEP_CRCLEN; 1735 pktlen = m0->m_pkthdr.len + IEEE80211_WEP_CRCLEN; 1736 } 1737 pktlen += IEEE80211_CRC_LEN; 1738 1739 /* 1740 * Load the DMA map so any coalescing is done. This 1741 * also calculates the number of descriptors we need. 1742 */ 1743 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1744 ath_mbuf_load_cb, bf, 1745 BUS_DMA_NOWAIT); 1746 if (error != 0) { 1747 sc->sc_stats.ast_tx_busdma++; 1748 m_freem(m0); 1749 return error; 1750 } 1751 /* 1752 * Discard null packets and check for packets that 1753 * require too many TX descriptors. We try to convert 1754 * the latter to a cluster. 1755 */ 1756 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 1757 sc->sc_stats.ast_tx_linear++; 1758 MGETHDR(m, M_DONTWAIT, MT_DATA); 1759 if (m == NULL) { 1760 sc->sc_stats.ast_tx_nombuf++; 1761 m_freem(m0); 1762 return ENOMEM; 1763 } 1764 M_MOVE_PKTHDR(m, m0); 1765 MCLGET(m, M_DONTWAIT); 1766 if ((m->m_flags & M_EXT) == 0) { 1767 sc->sc_stats.ast_tx_nomcl++; 1768 m_freem(m0); 1769 m_free(m); 1770 return ENOMEM; 1771 } 1772 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1773 m_freem(m0); 1774 m->m_len = m->m_pkthdr.len; 1775 m0 = m; 1776 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1777 ath_mbuf_load_cb, bf, 1778 BUS_DMA_NOWAIT); 1779 if (error != 0) { 1780 sc->sc_stats.ast_tx_busdma++; 1781 m_freem(m0); 1782 return error; 1783 } 1784 KASSERT(bf->bf_nseg == 1, 1785 ("ath_tx_start: packet not one segment; nseg %u", 1786 bf->bf_nseg)); 1787 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 1788 sc->sc_stats.ast_tx_nodata++; 1789 m_freem(m0); 1790 return EIO; 1791 } 1792 DPRINTF2(("ath_tx_start: m %p len %u\n", m0, pktlen)); 1793 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1794 bf->bf_m = m0; 1795 bf->bf_node = ni; /* NB: held reference */ 1796 1797 /* setup descriptors */ 1798 ds = bf->bf_desc; 1799 rt = sc->sc_currates; 1800 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1801 1802 /* 1803 * Calculate Atheros packet type from IEEE80211 packet header 1804 * and setup for rate calculations. 1805 */ 1806 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1807 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1808 case IEEE80211_FC0_TYPE_MGT: 1809 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1810 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1811 atype = HAL_PKT_TYPE_BEACON; 1812 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1813 atype = HAL_PKT_TYPE_PROBE_RESP; 1814 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1815 atype = HAL_PKT_TYPE_ATIM; 1816 rix = 0; /* XXX lowest rate */ 1817 break; 1818 case IEEE80211_FC0_TYPE_CTL: 1819 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1820 if (subtype == IEEE80211_FC0_SUBTYPE_PS_POLL) 1821 atype = HAL_PKT_TYPE_PSPOLL; 1822 rix = 0; /* XXX lowest rate */ 1823 break; 1824 default: 1825 rix = sc->sc_rixmap[ni->ni_rates.rs_rates[ni->ni_txrate] & 1826 IEEE80211_RATE_VAL]; 1827 if (rix == 0xff) { 1828 if_printf(ifp, "bogus xmit rate 0x%x\n", 1829 ni->ni_rates.rs_rates[ni->ni_txrate]); 1830 sc->sc_stats.ast_tx_badrate++; 1831 m_freem(m0); 1832 return EIO; 1833 } 1834 break; 1835 } 1836 /* 1837 * NB: the 802.11 layer marks whether or not we should 1838 * use short preamble based on the current mode and 1839 * negotiated parameters. 1840 */ 1841 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1842 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1843 txrate = rt->info[rix].rateCode | rt->info[rix].shortPreamble; 1844 shortPreamble = AH_TRUE; 1845 sc->sc_stats.ast_tx_shortpre++; 1846 } else { 1847 txrate = rt->info[rix].rateCode; 1848 shortPreamble = AH_FALSE; 1849 } 1850 1851 /* 1852 * Calculate miscellaneous flags. 1853 */ 1854 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for wep errors */ 1855 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1856 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1857 sc->sc_stats.ast_tx_noack++; 1858 } else if (pktlen > ic->ic_rtsthreshold) { 1859 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1860 sc->sc_stats.ast_tx_rts++; 1861 } 1862 1863 /* 1864 * Calculate duration. This logically belongs in the 802.11 1865 * layer but it lacks sufficient information to calculate it. 1866 */ 1867 if ((flags & HAL_TXDESC_NOACK) == 0 && 1868 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 1869 u_int16_t dur; 1870 /* 1871 * XXX not right with fragmentation. 1872 */ 1873 dur = ath_hal_computetxtime(ah, rt, IEEE80211_ACK_SIZE, 1874 rix, shortPreamble); 1875 *((u_int16_t*) wh->i_dur) = htole16(dur); 1876 } 1877 1878 /* 1879 * Calculate RTS/CTS rate and duration if needed. 1880 */ 1881 ctsduration = 0; 1882 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 1883 /* 1884 * CTS transmit rate is derived from the transmit rate 1885 * by looking in the h/w rate table. We must also factor 1886 * in whether or not a short preamble is to be used. 1887 */ 1888 cix = rt->info[rix].controlRate; 1889 ctsrate = rt->info[cix].rateCode; 1890 if (shortPreamble) 1891 ctsrate |= rt->info[cix].shortPreamble; 1892 /* 1893 * Compute the transmit duration based on the size 1894 * of an ACK frame. We call into the HAL to do the 1895 * computation since it depends on the characteristics 1896 * of the actual PHY being used. 1897 */ 1898 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 1899 ctsduration += ath_hal_computetxtime(ah, 1900 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 1901 } 1902 /* SIFS + data */ 1903 ctsduration += ath_hal_computetxtime(ah, 1904 rt, pktlen, rix, shortPreamble); 1905 if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 1906 ctsduration += ath_hal_computetxtime(ah, 1907 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 1908 } 1909 } else 1910 ctsrate = 0; 1911 1912 /* 1913 * For now use the antenna on which the last good 1914 * frame was received on. We assume this field is 1915 * initialized to 0 which gives us ``auto'' or the 1916 * ``default'' antenna. 1917 */ 1918 an = (struct ath_node *) ni; 1919 if (an->an_tx_antenna) 1920 antenna = an->an_tx_antenna; 1921 else 1922 antenna = an->an_rx_hist[an->an_rx_hist_next].arh_antenna; 1923 1924 /* 1925 * Formulate first tx descriptor with tx controls. 1926 */ 1927 /* XXX check return value? */ 1928 ath_hal_setuptxdesc(ah, ds 1929 , pktlen /* packet length */ 1930 , hdrlen /* header length */ 1931 , atype /* Atheros packet type */ 1932 , 60 /* txpower XXX */ 1933 , txrate, 1+10 /* series 0 rate/tries */ 1934 , iswep ? sc->sc_ic.ic_wep_txkey : HAL_TXKEYIX_INVALID 1935 , antenna /* antenna mode */ 1936 , flags /* flags */ 1937 , ctsrate /* rts/cts rate */ 1938 , ctsduration /* rts/cts duration */ 1939 ); 1940 #ifdef notyet 1941 ath_hal_setupxtxdesc(ah, ds 1942 , AH_FALSE /* short preamble */ 1943 , 0, 0 /* series 1 rate/tries */ 1944 , 0, 0 /* series 2 rate/tries */ 1945 , 0, 0 /* series 3 rate/tries */ 1946 ); 1947 #endif 1948 /* 1949 * Fillin the remainder of the descriptor info. 1950 */ 1951 for (i = 0; i < bf->bf_nseg; i++, ds++) { 1952 ds->ds_data = bf->bf_segs[i].ds_addr; 1953 if (i == bf->bf_nseg - 1) 1954 ds->ds_link = 0; 1955 else 1956 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 1957 ath_hal_filltxdesc(ah, ds 1958 , bf->bf_segs[i].ds_len /* segment length */ 1959 , i == 0 /* first segment */ 1960 , i == bf->bf_nseg - 1 /* last segment */ 1961 ); 1962 DPRINTF2(("ath_tx_start: %d: %08x %08x %08x %08x %08x %08x\n", 1963 i, ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, 1964 ds->ds_hw[0], ds->ds_hw[1])); 1965 } 1966 1967 /* 1968 * Insert the frame on the outbound list and 1969 * pass it on to the hardware. 1970 */ 1971 mtx_lock(&sc->sc_txqlock); 1972 TAILQ_INSERT_TAIL(&sc->sc_txq, bf, bf_list); 1973 if (sc->sc_txlink == NULL) { 1974 ath_hal_puttxbuf(ah, sc->sc_txhalq, bf->bf_daddr); 1975 DPRINTF2(("ath_tx_start: TXDP0 = %p (%p)\n", 1976 (caddr_t)bf->bf_daddr, bf->bf_desc)); 1977 } else { 1978 *sc->sc_txlink = bf->bf_daddr; 1979 DPRINTF2(("ath_tx_start: link(%p)=%p (%p)\n", 1980 sc->sc_txlink, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1981 } 1982 sc->sc_txlink = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 1983 mtx_unlock(&sc->sc_txqlock); 1984 1985 ath_hal_txstart(ah, sc->sc_txhalq); 1986 return 0; 1987 } 1988 1989 static void 1990 ath_tx_proc(void *arg, int npending) 1991 { 1992 struct ath_softc *sc = arg; 1993 struct ath_hal *ah = sc->sc_ah; 1994 struct ath_buf *bf; 1995 struct ieee80211com *ic = &sc->sc_ic; 1996 struct ifnet *ifp = &ic->ic_if; 1997 struct ath_desc *ds; 1998 struct ieee80211_node *ni; 1999 struct ath_node *an; 2000 int sr, lr; 2001 HAL_STATUS status; 2002 2003 DPRINTF2(("ath_tx_proc: pending %u tx queue %p, link %p\n", 2004 npending, (caddr_t) ath_hal_gettxbuf(sc->sc_ah, sc->sc_txhalq), 2005 sc->sc_txlink)); 2006 for (;;) { 2007 mtx_lock(&sc->sc_txqlock); 2008 bf = TAILQ_FIRST(&sc->sc_txq); 2009 if (bf == NULL) { 2010 sc->sc_txlink = NULL; 2011 mtx_unlock(&sc->sc_txqlock); 2012 break; 2013 } 2014 /* only the last descriptor is needed */ 2015 ds = &bf->bf_desc[bf->bf_nseg - 1]; 2016 status = ath_hal_txprocdesc(ah, ds); 2017 #ifdef AR_DEBUG 2018 if (ath_debug > 1) 2019 ath_printtxbuf(bf, status == HAL_OK); 2020 #endif 2021 if (status == HAL_EINPROGRESS) { 2022 mtx_unlock(&sc->sc_txqlock); 2023 break; 2024 } 2025 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2026 mtx_unlock(&sc->sc_txqlock); 2027 2028 ni = bf->bf_node; 2029 if (ni != NULL) { 2030 an = (struct ath_node *) ni; 2031 if (ds->ds_txstat.ts_status == 0) { 2032 an->an_tx_ok++; 2033 an->an_tx_antenna = ds->ds_txstat.ts_antenna; 2034 } else { 2035 an->an_tx_err++; 2036 ifp->if_oerrors++; 2037 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 2038 sc->sc_stats.ast_tx_xretries++; 2039 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 2040 sc->sc_stats.ast_tx_fifoerr++; 2041 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 2042 sc->sc_stats.ast_tx_filtered++; 2043 an->an_tx_antenna = 0; /* invalidate */ 2044 } 2045 sr = ds->ds_txstat.ts_shortretry; 2046 lr = ds->ds_txstat.ts_longretry; 2047 sc->sc_stats.ast_tx_shortretry += sr; 2048 sc->sc_stats.ast_tx_longretry += lr; 2049 if (sr + lr) 2050 an->an_tx_retr++; 2051 /* 2052 * Reclaim reference to node. 2053 * 2054 * NB: the node may be reclaimed here if, for example 2055 * this is a DEAUTH message that was sent and the 2056 * node was timed out due to inactivity. 2057 */ 2058 if (ni != ic->ic_bss) 2059 ieee80211_free_node(ic, ni); 2060 } 2061 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2062 BUS_DMASYNC_POSTWRITE); 2063 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2064 m_freem(bf->bf_m); 2065 bf->bf_m = NULL; 2066 bf->bf_node = NULL; 2067 2068 mtx_lock(&sc->sc_txbuflock); 2069 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2070 mtx_unlock(&sc->sc_txbuflock); 2071 } 2072 ifp->if_flags &= ~IFF_OACTIVE; 2073 sc->sc_tx_timer = 0; 2074 2075 ath_start(ifp); 2076 } 2077 2078 /* 2079 * Drain the transmit queue and reclaim resources. 2080 */ 2081 static void 2082 ath_draintxq(struct ath_softc *sc) 2083 { 2084 struct ath_hal *ah = sc->sc_ah; 2085 struct ifnet *ifp = &sc->sc_ic.ic_if; 2086 struct ath_buf *bf; 2087 2088 /* XXX return value */ 2089 if (!sc->sc_invalid) { 2090 /* don't touch the hardware if marked invalid */ 2091 (void) ath_hal_stoptxdma(ah, sc->sc_txhalq); 2092 DPRINTF(("ath_draintxq: tx queue %p, link %p\n", 2093 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_txhalq), 2094 sc->sc_txlink)); 2095 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 2096 DPRINTF(("ath_draintxq: beacon queue %p\n", 2097 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq))); 2098 } 2099 for (;;) { 2100 mtx_lock(&sc->sc_txqlock); 2101 bf = TAILQ_FIRST(&sc->sc_txq); 2102 if (bf == NULL) { 2103 sc->sc_txlink = NULL; 2104 mtx_unlock(&sc->sc_txqlock); 2105 break; 2106 } 2107 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2108 mtx_unlock(&sc->sc_txqlock); 2109 #ifdef AR_DEBUG 2110 if (ath_debug) 2111 ath_printtxbuf(bf, 2112 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 2113 #endif /* AR_DEBUG */ 2114 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2115 m_freem(bf->bf_m); 2116 bf->bf_m = NULL; 2117 bf->bf_node = NULL; 2118 mtx_lock(&sc->sc_txbuflock); 2119 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2120 mtx_unlock(&sc->sc_txbuflock); 2121 } 2122 ifp->if_flags &= ~IFF_OACTIVE; 2123 sc->sc_tx_timer = 0; 2124 } 2125 2126 /* 2127 * Disable the receive h/w in preparation for a reset. 2128 */ 2129 static void 2130 ath_stoprecv(struct ath_softc *sc) 2131 { 2132 struct ath_hal *ah = sc->sc_ah; 2133 2134 ath_hal_stoppcurecv(ah); /* disable PCU */ 2135 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 2136 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 2137 DELAY(3000); /* long enough for 1 frame */ 2138 #ifdef AR_DEBUG 2139 if (ath_debug) { 2140 struct ath_buf *bf; 2141 2142 DPRINTF(("ath_stoprecv: rx queue %p, link %p\n", 2143 (caddr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink)); 2144 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2145 if (ath_hal_rxprocdesc(ah, bf->bf_desc) == HAL_OK) 2146 ath_printrxbuf(bf, 1); 2147 } 2148 } 2149 #endif 2150 sc->sc_rxlink = NULL; /* just in case */ 2151 } 2152 2153 /* 2154 * Enable the receive h/w following a reset. 2155 */ 2156 static int 2157 ath_startrecv(struct ath_softc *sc) 2158 { 2159 struct ath_hal *ah = sc->sc_ah; 2160 struct ath_buf *bf; 2161 2162 sc->sc_rxlink = NULL; 2163 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2164 int error = ath_rxbuf_init(sc, bf); 2165 if (error != 0) { 2166 DPRINTF(("ath_startrecv: ath_rxbuf_init failed %d\n", 2167 error)); 2168 return error; 2169 } 2170 } 2171 2172 bf = TAILQ_FIRST(&sc->sc_rxbuf); 2173 ath_hal_putrxbuf(ah, bf->bf_daddr); 2174 ath_hal_rxena(ah); /* enable recv descriptors */ 2175 ath_mode_init(sc); /* set filters, etc. */ 2176 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 2177 return 0; 2178 } 2179 2180 /* 2181 * Set/change channels. If the channel is really being changed, 2182 * it's done by resetting the chip. To accomplish this we must 2183 * first cleanup any pending DMA, then restart stuff after a la 2184 * ath_init. 2185 */ 2186 static int 2187 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 2188 { 2189 struct ath_hal *ah = sc->sc_ah; 2190 struct ieee80211com *ic = &sc->sc_ic; 2191 2192 DPRINTF(("ath_chan_set: %u (%u MHz) -> %u (%u MHz)\n", 2193 ieee80211_chan2ieee(ic, ic->ic_ibss_chan), 2194 ic->ic_ibss_chan->ic_freq, 2195 ieee80211_chan2ieee(ic, chan), chan->ic_freq)); 2196 if (chan != ic->ic_ibss_chan) { 2197 HAL_STATUS status; 2198 HAL_CHANNEL hchan; 2199 enum ieee80211_phymode mode; 2200 2201 /* 2202 * To switch channels clear any pending DMA operations; 2203 * wait long enough for the RX fifo to drain, reset the 2204 * hardware at the new frequency, and then re-enable 2205 * the relevant bits of the h/w. 2206 */ 2207 ath_hal_intrset(ah, 0); /* disable interrupts */ 2208 ath_draintxq(sc); /* clear pending tx frames */ 2209 ath_stoprecv(sc); /* turn off frame recv */ 2210 /* 2211 * Convert to a HAL channel description with 2212 * the flags constrained to reflect the current 2213 * operating mode. 2214 */ 2215 hchan.channel = chan->ic_freq; 2216 hchan.channelFlags = ath_chan2flags(ic, chan); 2217 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 2218 if_printf(&ic->ic_if, "ath_chan_set: unable to reset " 2219 "channel %u (%u Mhz)\n", 2220 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 2221 return EIO; 2222 } 2223 /* 2224 * Re-enable rx framework. 2225 */ 2226 if (ath_startrecv(sc) != 0) { 2227 if_printf(&ic->ic_if, 2228 "ath_chan_set: unable to restart recv logic\n"); 2229 return EIO; 2230 } 2231 2232 /* 2233 * Update BPF state. 2234 */ 2235 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 2236 htole16(chan->ic_freq); 2237 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 2238 htole16(chan->ic_flags); 2239 2240 /* 2241 * Change channels and update the h/w rate map 2242 * if we're switching; e.g. 11a to 11b/g. 2243 */ 2244 ic->ic_ibss_chan = chan; 2245 mode = ieee80211_chan2mode(ic, chan); 2246 if (mode != sc->sc_curmode) 2247 ath_setcurmode(sc, mode); 2248 2249 /* 2250 * Re-enable interrupts. 2251 */ 2252 ath_hal_intrset(ah, sc->sc_imask); 2253 } 2254 return 0; 2255 } 2256 2257 static void 2258 ath_next_scan(void *arg) 2259 { 2260 struct ath_softc *sc = arg; 2261 struct ieee80211com *ic = &sc->sc_ic; 2262 struct ifnet *ifp = &ic->ic_if; 2263 2264 if (ic->ic_state == IEEE80211_S_SCAN) 2265 ieee80211_next_scan(ifp); 2266 } 2267 2268 /* 2269 * Periodically recalibrate the PHY to account 2270 * for temperature/environment changes. 2271 */ 2272 static void 2273 ath_calibrate(void *arg) 2274 { 2275 struct ath_softc *sc = arg; 2276 struct ath_hal *ah = sc->sc_ah; 2277 struct ieee80211com *ic = &sc->sc_ic; 2278 struct ieee80211_channel *c; 2279 HAL_CHANNEL hchan; 2280 2281 sc->sc_stats.ast_per_cal++; 2282 2283 /* 2284 * Convert to a HAL channel description with the flags 2285 * constrained to reflect the current operating mode. 2286 */ 2287 c = ic->ic_ibss_chan; 2288 hchan.channel = c->ic_freq; 2289 hchan.channelFlags = ath_chan2flags(ic, c); 2290 2291 DPRINTF(("%s: channel %u/%x\n", __func__, c->ic_freq, c->ic_flags)); 2292 2293 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 2294 /* 2295 * Rfgain is out of bounds, reset the chip 2296 * to load new gain values. 2297 */ 2298 sc->sc_stats.ast_per_rfgain++; 2299 ath_reset(sc); 2300 } 2301 if (!ath_hal_calibrate(ah, &hchan)) { 2302 DPRINTF(("%s: calibration of channel %u failed\n", 2303 __func__, c->ic_freq)); 2304 sc->sc_stats.ast_per_calfail++; 2305 } 2306 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, ath_calibrate, sc); 2307 } 2308 2309 static int 2310 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2311 { 2312 struct ifnet *ifp = &ic->ic_if; 2313 struct ath_softc *sc = ifp->if_softc; 2314 struct ath_hal *ah = sc->sc_ah; 2315 struct ieee80211_node *ni; 2316 int i, error; 2317 u_int8_t *bssid; 2318 u_int32_t rfilt; 2319 static const HAL_LED_STATE leds[] = { 2320 HAL_LED_INIT, /* IEEE80211_S_INIT */ 2321 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 2322 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 2323 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 2324 HAL_LED_RUN, /* IEEE80211_S_RUN */ 2325 }; 2326 2327 DPRINTF(("%s: %s -> %s\n", __func__, 2328 ieee80211_state_name[ic->ic_state], 2329 ieee80211_state_name[nstate])); 2330 2331 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 2332 2333 if (nstate == IEEE80211_S_INIT) { 2334 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2335 ath_hal_intrset(ah, sc->sc_imask); 2336 callout_stop(&sc->sc_scan_ch); 2337 callout_stop(&sc->sc_cal_ch); 2338 return (*sc->sc_newstate)(ic, nstate, arg); 2339 } 2340 ni = ic->ic_bss; 2341 error = ath_chan_set(sc, ni->ni_chan); 2342 if (error != 0) 2343 goto bad; 2344 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 2345 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2346 if (ic->ic_opmode != IEEE80211_M_STA) 2347 rfilt |= HAL_RX_FILTER_PROBEREQ; 2348 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2349 (ifp->if_flags & IFF_PROMISC)) 2350 rfilt |= HAL_RX_FILTER_PROM; 2351 if (ic->ic_opmode == IEEE80211_M_STA || 2352 ic->ic_state == IEEE80211_S_SCAN) 2353 rfilt |= HAL_RX_FILTER_BEACON; 2354 if (nstate == IEEE80211_S_SCAN) { 2355 callout_reset(&sc->sc_scan_ch, (hz * ath_dwelltime) / 1000, 2356 ath_next_scan, sc); 2357 bssid = ifp->if_broadcastaddr; 2358 } else { 2359 callout_stop(&sc->sc_scan_ch); 2360 bssid = ni->ni_bssid; 2361 } 2362 ath_hal_setrxfilter(ah, rfilt); 2363 DPRINTF(("%s: RX filter 0x%x bssid %s\n", 2364 __func__, rfilt, ether_sprintf(bssid))); 2365 2366 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 2367 ath_hal_setassocid(ah, bssid, ni->ni_associd); 2368 else 2369 ath_hal_setassocid(ah, bssid, 0); 2370 if (ic->ic_flags & IEEE80211_F_WEPON) { 2371 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2372 if (ath_hal_keyisvalid(ah, i)) 2373 ath_hal_keysetmac(ah, i, bssid); 2374 } 2375 2376 if (nstate == IEEE80211_S_RUN) { 2377 DPRINTF(("%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 2378 "capinfo=0x%04x chan=%d\n" 2379 , __func__ 2380 , ic->ic_flags 2381 , ni->ni_intval 2382 , ether_sprintf(ni->ni_bssid) 2383 , ni->ni_capinfo 2384 , ieee80211_chan2ieee(ic, ni->ni_chan))); 2385 2386 /* 2387 * Allocate and setup the beacon frame for AP or adhoc mode. 2388 */ 2389 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2390 ic->ic_opmode == IEEE80211_M_IBSS) { 2391 error = ath_beacon_alloc(sc, ni); 2392 if (error != 0) 2393 goto bad; 2394 } 2395 2396 /* 2397 * Configure the beacon and sleep timers. 2398 */ 2399 ath_beacon_config(sc); 2400 2401 /* start periodic recalibration timer */ 2402 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, 2403 ath_calibrate, sc); 2404 } else { 2405 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2406 ath_hal_intrset(ah, sc->sc_imask); 2407 callout_stop(&sc->sc_cal_ch); /* no calibration */ 2408 } 2409 /* 2410 * Reset the rate control state. 2411 */ 2412 ath_rate_ctl_reset(sc, nstate); 2413 /* 2414 * Invoke the parent method to complete the work. 2415 */ 2416 return (*sc->sc_newstate)(ic, nstate, arg); 2417 bad: 2418 callout_stop(&sc->sc_scan_ch); 2419 callout_stop(&sc->sc_cal_ch); 2420 /* NB: do not invoke the parent */ 2421 return error; 2422 } 2423 2424 /* 2425 * Setup driver-specific state for a newly associated node. 2426 * Note that we're called also on a re-associate, the isnew 2427 * param tells us if this is the first time or not. 2428 */ 2429 static void 2430 ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2431 { 2432 if (isnew) { 2433 struct ath_node *an = (struct ath_node *) ni; 2434 2435 an->an_tx_ok = an->an_tx_err = 2436 an->an_tx_retr = an->an_tx_upper = 0; 2437 /* start with highest negotiated rate */ 2438 /* 2439 * XXX should do otherwise but only when 2440 * the rate control algorithm is better. 2441 */ 2442 KASSERT(ni->ni_rates.rs_nrates > 0, 2443 ("new association w/ no rates!")); 2444 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2445 } 2446 } 2447 2448 static int 2449 ath_getchannels(struct ath_softc *sc, u_int cc, HAL_BOOL outdoor) 2450 { 2451 struct ieee80211com *ic = &sc->sc_ic; 2452 struct ifnet *ifp = &ic->ic_if; 2453 struct ath_hal *ah = sc->sc_ah; 2454 HAL_CHANNEL *chans; 2455 int i, ix, nchan; 2456 2457 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 2458 M_TEMP, M_NOWAIT); 2459 if (chans == NULL) { 2460 if_printf(ifp, "unable to allocate channel table\n"); 2461 return ENOMEM; 2462 } 2463 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 2464 cc, HAL_MODE_ALL, outdoor)) { 2465 if_printf(ifp, "unable to collect channel list from hal\n"); 2466 free(chans, M_TEMP); 2467 return EINVAL; 2468 } 2469 2470 /* 2471 * Convert HAL channels to ieee80211 ones and insert 2472 * them in the table according to their channel number. 2473 */ 2474 for (i = 0; i < nchan; i++) { 2475 HAL_CHANNEL *c = &chans[i]; 2476 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 2477 if (ix > IEEE80211_CHAN_MAX) { 2478 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 2479 ix, c->channel, c->channelFlags); 2480 continue; 2481 } 2482 /* NB: flags are known to be compatible */ 2483 if (ic->ic_channels[ix].ic_freq == 0) { 2484 ic->ic_channels[ix].ic_freq = c->channel; 2485 ic->ic_channels[ix].ic_flags = c->channelFlags; 2486 } else { 2487 /* channels overlap; e.g. 11g and 11b */ 2488 ic->ic_channels[ix].ic_flags |= c->channelFlags; 2489 } 2490 } 2491 free(chans, M_TEMP); 2492 return 0; 2493 } 2494 2495 static int 2496 ath_rate_setup(struct ath_softc *sc, u_int mode) 2497 { 2498 struct ath_hal *ah = sc->sc_ah; 2499 struct ieee80211com *ic = &sc->sc_ic; 2500 const HAL_RATE_TABLE *rt; 2501 struct ieee80211_rateset *rs; 2502 int i, maxrates; 2503 2504 switch (mode) { 2505 case IEEE80211_MODE_11A: 2506 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 2507 break; 2508 case IEEE80211_MODE_11B: 2509 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 2510 break; 2511 case IEEE80211_MODE_11G: 2512 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 2513 break; 2514 case IEEE80211_MODE_TURBO: 2515 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 2516 break; 2517 default: 2518 DPRINTF(("%s: invalid mode %u\n", __func__, mode)); 2519 return 0; 2520 } 2521 rt = sc->sc_rates[mode]; 2522 if (rt == NULL) 2523 return 0; 2524 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 2525 DPRINTF(("%s: rate table too small (%u > %u)\n", 2526 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE)); 2527 maxrates = IEEE80211_RATE_MAXSIZE; 2528 } else 2529 maxrates = rt->rateCount; 2530 rs = &ic->ic_sup_rates[mode]; 2531 for (i = 0; i < maxrates; i++) 2532 rs->rs_rates[i] = rt->info[i].dot11Rate; 2533 rs->rs_nrates = maxrates; 2534 return 1; 2535 } 2536 2537 static void 2538 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 2539 { 2540 const HAL_RATE_TABLE *rt; 2541 int i; 2542 2543 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 2544 rt = sc->sc_rates[mode]; 2545 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 2546 for (i = 0; i < rt->rateCount; i++) 2547 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 2548 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 2549 for (i = 0; i < 32; i++) 2550 sc->sc_hwmap[i] = rt->info[rt->rateCodeToIndex[i]].dot11Rate; 2551 sc->sc_currates = rt; 2552 sc->sc_curmode = mode; 2553 } 2554 2555 /* 2556 * Reset the rate control state for each 802.11 state transition. 2557 */ 2558 static void 2559 ath_rate_ctl_reset(struct ath_softc *sc, enum ieee80211_state state) 2560 { 2561 struct ieee80211com *ic = &sc->sc_ic; 2562 struct ieee80211_node *ni; 2563 struct ath_node *an; 2564 2565 an = (struct ath_node *) ic->ic_bss; 2566 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = an->an_tx_upper = 0; 2567 if (ic->ic_opmode == IEEE80211_M_STA) { 2568 ni = ic->ic_bss; 2569 if (state == IEEE80211_S_RUN) { 2570 /* start with highest negotiated rate */ 2571 KASSERT(ni->ni_rates.rs_nrates > 0, 2572 ("transition to RUN state w/ no rates!")); 2573 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2574 } else { 2575 /* use lowest rate */ 2576 ni->ni_txrate = 0; 2577 } 2578 } else { 2579 TAILQ_FOREACH(ni, &ic->ic_node, ni_list) { 2580 ni->ni_txrate = 0; /* use lowest rate */ 2581 an = (struct ath_node *) ni; 2582 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 2583 an->an_tx_upper = 0; 2584 } 2585 } 2586 } 2587 2588 /* 2589 * Examine and potentially adjust the transmit rate. 2590 */ 2591 static void 2592 ath_rate_ctl(void *arg, struct ieee80211_node *ni) 2593 { 2594 struct ath_softc *sc = arg; 2595 struct ath_node *an = (struct ath_node *) ni; 2596 struct ieee80211_rateset *rs = &ni->ni_rates; 2597 int mod = 0, orate, enough; 2598 2599 /* 2600 * Rate control 2601 * XXX: very primitive version. 2602 */ 2603 sc->sc_stats.ast_rate_calls++; 2604 2605 enough = (an->an_tx_ok + an->an_tx_err >= 10); 2606 2607 /* no packet reached -> down */ 2608 if (an->an_tx_err > 0 && an->an_tx_ok == 0) 2609 mod = -1; 2610 2611 /* all packets needs retry in average -> down */ 2612 if (enough && an->an_tx_ok < an->an_tx_retr) 2613 mod = -1; 2614 2615 /* no error and less than 10% of packets needs retry -> up */ 2616 if (enough && an->an_tx_err == 0 && an->an_tx_ok > an->an_tx_retr * 10) 2617 mod = 1; 2618 2619 orate = ni->ni_txrate; 2620 switch (mod) { 2621 case 0: 2622 if (enough && an->an_tx_upper > 0) 2623 an->an_tx_upper--; 2624 break; 2625 case -1: 2626 if (ni->ni_txrate > 0) { 2627 ni->ni_txrate--; 2628 sc->sc_stats.ast_rate_drop++; 2629 } 2630 an->an_tx_upper = 0; 2631 break; 2632 case 1: 2633 if (++an->an_tx_upper < 2) 2634 break; 2635 an->an_tx_upper = 0; 2636 if (ni->ni_txrate + 1 < rs->rs_nrates) { 2637 ni->ni_txrate++; 2638 sc->sc_stats.ast_rate_raise++; 2639 } 2640 break; 2641 } 2642 2643 if (ni->ni_txrate != orate) { 2644 printf("%s: %dM -> %dM (%d ok, %d err, %d retr)\n", 2645 __func__, 2646 (rs->rs_rates[orate] & IEEE80211_RATE_VAL) / 2, 2647 (rs->rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL) / 2, 2648 an->an_tx_ok, an->an_tx_err, an->an_tx_retr); 2649 } 2650 if (ni->ni_txrate != orate || enough) 2651 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 0; 2652 } 2653 2654 #ifdef AR_DEBUG 2655 static int 2656 sysctl_hw_ath_dump(SYSCTL_HANDLER_ARGS) 2657 { 2658 char dmode[64]; 2659 int error; 2660 2661 strncpy(dmode, "", sizeof(dmode) - 1); 2662 dmode[sizeof(dmode) - 1] = '\0'; 2663 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2664 2665 if (error == 0 && req->newptr != NULL) { 2666 struct ifnet *ifp; 2667 struct ath_softc *sc; 2668 2669 ifp = ifunit("ath0"); /* XXX */ 2670 if (!ifp) 2671 return EINVAL; 2672 sc = ifp->if_softc; 2673 if (strcmp(dmode, "hal") == 0) 2674 ath_hal_dumpstate(sc->sc_ah); 2675 else if (strcmp(dmode, "eeprom") == 0) 2676 ath_hal_dumpeeprom(sc->sc_ah); 2677 else if (strcmp(dmode, "rfgain") == 0) 2678 ath_hal_dumprfgain(sc->sc_ah); 2679 else if (strcmp(dmode, "ani") == 0) 2680 ath_hal_dumpani(sc->sc_ah); 2681 else 2682 return EINVAL; 2683 } 2684 return error; 2685 } 2686 SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2687 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state"); 2688 2689 static void 2690 ath_printrxbuf(struct ath_buf *bf, int done) 2691 { 2692 struct ath_desc *ds; 2693 int i; 2694 2695 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2696 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 2697 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2698 ds->ds_link, ds->ds_data, 2699 ds->ds_ctl0, ds->ds_ctl1, 2700 ds->ds_hw[0], ds->ds_hw[1], 2701 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 2702 } 2703 } 2704 2705 static void 2706 ath_printtxbuf(struct ath_buf *bf, int done) 2707 { 2708 struct ath_desc *ds; 2709 int i; 2710 2711 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2712 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 2713 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2714 ds->ds_link, ds->ds_data, 2715 ds->ds_ctl0, ds->ds_ctl1, 2716 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 2717 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 2718 } 2719 } 2720 #endif /* AR_DEBUG */ 2721