1 /*- 2 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 /* 41 * Driver for the Atheros Wireless LAN controller. 42 * 43 * This software is derived from work of Atsushi Onoe; his contribution 44 * is greatly appreciated. 45 */ 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/lock.h> 55 #include <sys/mutex.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/errno.h> 60 #include <sys/callout.h> 61 #include <sys/bus.h> 62 #include <sys/endian.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_arp.h> 70 #include <net/ethernet.h> 71 #include <net/if_llc.h> 72 73 #include <net80211/ieee80211_var.h> 74 75 #include <net/bpf.h> 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/if_ether.h> 80 #endif 81 82 #define AR_DEBUG 83 #include <dev/ath/if_athvar.h> 84 #include <contrib/dev/ath/ah_desc.h> 85 86 /* unalligned little endian access */ 87 #define LE_READ_2(p) \ 88 ((u_int16_t) \ 89 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 90 #define LE_READ_4(p) \ 91 ((u_int32_t) \ 92 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 93 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 94 95 static void ath_init(void *); 96 static void ath_stop(struct ifnet *); 97 static void ath_start(struct ifnet *); 98 static void ath_reset(struct ath_softc *); 99 static int ath_media_change(struct ifnet *); 100 static void ath_watchdog(struct ifnet *); 101 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 102 static void ath_fatal_proc(void *, int); 103 static void ath_rxorn_proc(void *, int); 104 static void ath_bmiss_proc(void *, int); 105 static void ath_initkeytable(struct ath_softc *); 106 static void ath_mode_init(struct ath_softc *); 107 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 108 static void ath_beacon_proc(void *, int); 109 static void ath_beacon_free(struct ath_softc *); 110 static void ath_beacon_config(struct ath_softc *); 111 static int ath_desc_alloc(struct ath_softc *); 112 static void ath_desc_free(struct ath_softc *); 113 static struct ieee80211_node *ath_node_alloc(struct ieee80211com *); 114 static void ath_node_free(struct ieee80211com *, struct ieee80211_node *); 115 static void ath_node_copy(struct ieee80211com *, 116 struct ieee80211_node *, const struct ieee80211_node *); 117 static u_int8_t ath_node_getrssi(struct ieee80211com *, 118 struct ieee80211_node *); 119 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 120 static void ath_rx_proc(void *, int); 121 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 122 struct ath_buf *, struct mbuf *); 123 static void ath_tx_proc(void *, int); 124 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 125 static void ath_draintxq(struct ath_softc *); 126 static void ath_stoprecv(struct ath_softc *); 127 static int ath_startrecv(struct ath_softc *); 128 static void ath_next_scan(void *); 129 static void ath_calibrate(void *); 130 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 131 static void ath_newassoc(struct ieee80211com *, 132 struct ieee80211_node *, int); 133 static int ath_getchannels(struct ath_softc *, u_int cc, HAL_BOOL outdoor); 134 135 static int ath_rate_setup(struct ath_softc *sc, u_int mode); 136 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 137 static void ath_rate_ctl_reset(struct ath_softc *, enum ieee80211_state); 138 static void ath_rate_ctl(void *, struct ieee80211_node *); 139 140 SYSCTL_DECL(_hw_ath); 141 142 /* XXX validate sysctl values */ 143 static int ath_dwelltime = 200; /* 5 channels/second */ 144 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 145 0, "channel dwell time (ms) for AP/station scanning"); 146 static int ath_calinterval = 30; /* calibrate every 30 secs */ 147 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 148 0, "chip calibration interval (secs)"); 149 static int ath_outdoor = AH_TRUE; /* outdoor operation */ 150 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 151 0, "enable/disable outdoor operation"); 152 TUNABLE_INT("hw.ath.outdoor", &ath_outdoor); 153 static int ath_countrycode = CTRY_DEFAULT; /* country code */ 154 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 155 0, "country code"); 156 TUNABLE_INT("hw.ath.countrycode", &ath_countrycode); 157 static int ath_regdomain = 0; /* regulatory domain */ 158 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 159 0, "regulatory domain"); 160 161 #ifdef AR_DEBUG 162 int ath_debug = 0; 163 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 164 0, "control debugging printfs"); 165 TUNABLE_INT("hw.ath.debug", &ath_debug); 166 #define IFF_DUMPPKTS(_ifp, _m) \ 167 ((ath_debug & _m) || \ 168 ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 169 static void ath_printrxbuf(struct ath_buf *bf, int); 170 static void ath_printtxbuf(struct ath_buf *bf, int); 171 enum { 172 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 173 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 174 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 175 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 176 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 177 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 178 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 179 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 180 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 181 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 182 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 183 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 184 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 185 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 186 ATH_DEBUG_ANY = 0xffffffff 187 }; 188 #define DPRINTF(_m,X) if (ath_debug & _m) printf X 189 #else 190 #define IFF_DUMPPKTS(_ifp, _m) \ 191 (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 192 #define DPRINTF(_m, X) 193 #endif 194 195 int 196 ath_attach(u_int16_t devid, struct ath_softc *sc) 197 { 198 struct ieee80211com *ic = &sc->sc_ic; 199 struct ifnet *ifp = &ic->ic_if; 200 struct ath_hal *ah; 201 HAL_STATUS status; 202 int error = 0; 203 204 DPRINTF(ATH_DEBUG_ANY, ("%s: devid 0x%x\n", __func__, devid)); 205 206 /* set these up early for if_printf use */ 207 if_initname(ifp, device_get_name(sc->sc_dev), 208 device_get_unit(sc->sc_dev)); 209 210 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 211 if (ah == NULL) { 212 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 213 status); 214 error = ENXIO; 215 goto bad; 216 } 217 if (ah->ah_abi != HAL_ABI_VERSION) { 218 if_printf(ifp, "HAL ABI mismatch detected (0x%x != 0x%x)\n", 219 ah->ah_abi, HAL_ABI_VERSION); 220 error = ENXIO; 221 goto bad; 222 } 223 if_printf(ifp, "mac %d.%d phy %d.%d", 224 ah->ah_macVersion, ah->ah_macRev, 225 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 226 if (ah->ah_analog5GhzRev) 227 printf(" 5ghz radio %d.%d", 228 ah->ah_analog5GhzRev >> 4, ah->ah_analog5GhzRev & 0xf); 229 if (ah->ah_analog2GhzRev) 230 printf(" 2ghz radio %d.%d", 231 ah->ah_analog2GhzRev >> 4, ah->ah_analog2GhzRev & 0xf); 232 printf("\n"); 233 sc->sc_ah = ah; 234 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 235 236 /* 237 * Collect the channel list using the default country 238 * code and including outdoor channels. The 802.11 layer 239 * is resposible for filtering this list based on settings 240 * like the phy mode. 241 */ 242 error = ath_getchannels(sc, ath_countrycode, ath_outdoor); 243 if (error != 0) 244 goto bad; 245 /* 246 * Copy these back; they are set as a side effect 247 * of constructing the channel list. 248 */ 249 ath_regdomain = ath_hal_getregdomain(ah); 250 ath_countrycode = ath_hal_getcountrycode(ah); 251 252 /* 253 * Setup rate tables for all potential media types. 254 */ 255 ath_rate_setup(sc, IEEE80211_MODE_11A); 256 ath_rate_setup(sc, IEEE80211_MODE_11B); 257 ath_rate_setup(sc, IEEE80211_MODE_11G); 258 ath_rate_setup(sc, IEEE80211_MODE_TURBO); 259 260 error = ath_desc_alloc(sc); 261 if (error != 0) { 262 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 263 goto bad; 264 } 265 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 266 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 267 268 ATH_TXBUF_LOCK_INIT(sc); 269 ATH_TXQ_LOCK_INIT(sc); 270 271 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 272 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 273 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 274 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 275 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 276 277 /* 278 * For now just pre-allocate one data queue and one 279 * beacon queue. Note that the HAL handles resetting 280 * them at the needed time. Eventually we'll want to 281 * allocate more tx queues for splitting management 282 * frames and for QOS support. 283 */ 284 sc->sc_txhalq = ath_hal_setuptxqueue(ah, 285 HAL_TX_QUEUE_DATA, 286 AH_TRUE /* enable interrupts */ 287 ); 288 if (sc->sc_txhalq == (u_int) -1) { 289 if_printf(ifp, "unable to setup a data xmit queue!\n"); 290 goto bad2; 291 } 292 sc->sc_bhalq = ath_hal_setuptxqueue(ah, 293 HAL_TX_QUEUE_BEACON, 294 AH_TRUE /* enable interrupts */ 295 ); 296 if (sc->sc_bhalq == (u_int) -1) { 297 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 298 goto bad2; 299 } 300 301 ifp->if_softc = sc; 302 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 303 ifp->if_start = ath_start; 304 ifp->if_watchdog = ath_watchdog; 305 ifp->if_ioctl = ath_ioctl; 306 ifp->if_init = ath_init; 307 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 308 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 309 IFQ_SET_READY(&ifp->if_snd); 310 311 ic->ic_softc = sc; 312 ic->ic_newassoc = ath_newassoc; 313 /* XXX not right but it's not used anywhere important */ 314 ic->ic_phytype = IEEE80211_T_OFDM; 315 ic->ic_opmode = IEEE80211_M_STA; 316 ic->ic_caps = IEEE80211_C_WEP /* wep supported */ 317 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 318 | IEEE80211_C_HOSTAP /* hostap mode */ 319 | IEEE80211_C_MONITOR /* monitor mode */ 320 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 321 ; 322 323 /* get mac address from hardware */ 324 ath_hal_getmac(ah, ic->ic_myaddr); 325 326 /* call MI attach routine. */ 327 ieee80211_ifattach(ifp); 328 /* override default methods */ 329 ic->ic_node_alloc = ath_node_alloc; 330 sc->sc_node_free = ic->ic_node_free; 331 ic->ic_node_free = ath_node_free; 332 sc->sc_node_copy = ic->ic_node_copy; 333 ic->ic_node_copy = ath_node_copy; 334 ic->ic_node_getrssi = ath_node_getrssi; 335 sc->sc_newstate = ic->ic_newstate; 336 ic->ic_newstate = ath_newstate; 337 /* complete initialization */ 338 ieee80211_media_init(ifp, ath_media_change, ieee80211_media_status); 339 340 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 341 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 342 &sc->sc_drvbpf); 343 /* 344 * Initialize constant fields. 345 * XXX make header lengths a multiple of 32-bits so subsequent 346 * headers are properly aligned; this is a kludge to keep 347 * certain applications happy. 348 * 349 * NB: the channel is setup each time we transition to the 350 * RUN state to avoid filling it in for each frame. 351 */ 352 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 353 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 354 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 355 356 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 357 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 358 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 359 360 return 0; 361 bad2: 362 ath_desc_free(sc); 363 bad: 364 if (ah) 365 ath_hal_detach(ah); 366 sc->sc_invalid = 1; 367 return error; 368 } 369 370 int 371 ath_detach(struct ath_softc *sc) 372 { 373 struct ifnet *ifp = &sc->sc_ic.ic_if; 374 375 DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags %x\n", __func__, ifp->if_flags)); 376 377 ath_stop(ifp); 378 bpfdetach(ifp); 379 ath_desc_free(sc); 380 ath_hal_detach(sc->sc_ah); 381 ieee80211_ifdetach(ifp); 382 383 ATH_TXBUF_LOCK_DESTROY(sc); 384 ATH_TXQ_LOCK_DESTROY(sc); 385 386 return 0; 387 } 388 389 void 390 ath_suspend(struct ath_softc *sc) 391 { 392 struct ifnet *ifp = &sc->sc_ic.ic_if; 393 394 DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags %x\n", __func__, ifp->if_flags)); 395 396 ath_stop(ifp); 397 } 398 399 void 400 ath_resume(struct ath_softc *sc) 401 { 402 struct ifnet *ifp = &sc->sc_ic.ic_if; 403 404 DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags %x\n", __func__, ifp->if_flags)); 405 406 if (ifp->if_flags & IFF_UP) { 407 ath_init(ifp); 408 if (ifp->if_flags & IFF_RUNNING) 409 ath_start(ifp); 410 } 411 } 412 413 void 414 ath_shutdown(struct ath_softc *sc) 415 { 416 struct ifnet *ifp = &sc->sc_ic.ic_if; 417 418 DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags %x\n", __func__, ifp->if_flags)); 419 420 ath_stop(ifp); 421 } 422 423 void 424 ath_intr(void *arg) 425 { 426 struct ath_softc *sc = arg; 427 struct ieee80211com *ic = &sc->sc_ic; 428 struct ifnet *ifp = &ic->ic_if; 429 struct ath_hal *ah = sc->sc_ah; 430 HAL_INT status; 431 432 if (sc->sc_invalid) { 433 /* 434 * The hardware is not ready/present, don't touch anything. 435 * Note this can happen early on if the IRQ is shared. 436 */ 437 DPRINTF(ATH_DEBUG_ANY, ("%s: invalid; ignored\n", __func__)); 438 return; 439 } 440 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 441 return; 442 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 443 DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags 0x%x\n", 444 __func__, ifp->if_flags)); 445 ath_hal_getisr(ah, &status); /* clear ISR */ 446 ath_hal_intrset(ah, 0); /* disable further intr's */ 447 return; 448 } 449 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 450 DPRINTF(ATH_DEBUG_INTR, ("%s: status 0x%x\n", __func__, status)); 451 #ifdef AR_DEBUG 452 if (ath_debug && 453 (status & (HAL_INT_FATAL|HAL_INT_RXORN|HAL_INT_BMISS))) { 454 if_printf(ifp, "ath_intr: status 0x%x\n", status); 455 ath_hal_dumpstate(ah); 456 } 457 #endif /* AR_DEBUG */ 458 status &= sc->sc_imask; /* discard unasked for bits */ 459 if (status & HAL_INT_FATAL) { 460 sc->sc_stats.ast_hardware++; 461 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 462 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask); 463 } else if (status & HAL_INT_RXORN) { 464 sc->sc_stats.ast_rxorn++; 465 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 466 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask); 467 } else { 468 if (status & HAL_INT_RXEOL) { 469 /* 470 * NB: the hardware should re-read the link when 471 * RXE bit is written, but it doesn't work at 472 * least on older hardware revs. 473 */ 474 sc->sc_stats.ast_rxeol++; 475 sc->sc_rxlink = NULL; 476 } 477 if (status & HAL_INT_TXURN) { 478 sc->sc_stats.ast_txurn++; 479 /* bump tx trigger level */ 480 ath_hal_updatetxtriglevel(ah, AH_TRUE); 481 } 482 if (status & HAL_INT_RX) 483 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask); 484 if (status & HAL_INT_TX) 485 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask); 486 if (status & HAL_INT_SWBA) { 487 /* 488 * Handle beacon transmission directly; deferring 489 * this is too slow to meet timing constraints 490 * under load. 491 */ 492 ath_beacon_proc(sc, 0); 493 } 494 if (status & HAL_INT_BMISS) { 495 sc->sc_stats.ast_bmiss++; 496 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask); 497 } 498 } 499 } 500 501 static void 502 ath_fatal_proc(void *arg, int pending) 503 { 504 struct ath_softc *sc = arg; 505 506 device_printf(sc->sc_dev, "hardware error; resetting\n"); 507 ath_reset(sc); 508 } 509 510 static void 511 ath_rxorn_proc(void *arg, int pending) 512 { 513 struct ath_softc *sc = arg; 514 515 device_printf(sc->sc_dev, "rx FIFO overrun; resetting\n"); 516 ath_reset(sc); 517 } 518 519 static void 520 ath_bmiss_proc(void *arg, int pending) 521 { 522 struct ath_softc *sc = arg; 523 struct ieee80211com *ic = &sc->sc_ic; 524 525 DPRINTF(ATH_DEBUG_ANY, ("%s: pending %u\n", __func__, pending)); 526 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 527 ("unexpect operating mode %u", ic->ic_opmode)); 528 if (ic->ic_state == IEEE80211_S_RUN) { 529 /* 530 * Rather than go directly to scan state, try to 531 * reassociate first. If that fails then the state 532 * machine will drop us into scanning after timing 533 * out waiting for a probe response. 534 */ 535 NET_LOCK_GIANT(); 536 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); 537 NET_UNLOCK_GIANT(); 538 } 539 } 540 541 static u_int 542 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 543 { 544 static const u_int modeflags[] = { 545 0, /* IEEE80211_MODE_AUTO */ 546 CHANNEL_A, /* IEEE80211_MODE_11A */ 547 CHANNEL_B, /* IEEE80211_MODE_11B */ 548 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 549 CHANNEL_T /* IEEE80211_MODE_TURBO */ 550 }; 551 return modeflags[ieee80211_chan2mode(ic, chan)]; 552 } 553 554 static void 555 ath_init(void *arg) 556 { 557 struct ath_softc *sc = (struct ath_softc *) arg; 558 struct ieee80211com *ic = &sc->sc_ic; 559 struct ifnet *ifp = &ic->ic_if; 560 struct ieee80211_node *ni; 561 enum ieee80211_phymode mode; 562 struct ath_hal *ah = sc->sc_ah; 563 HAL_STATUS status; 564 HAL_CHANNEL hchan; 565 566 DPRINTF(ATH_DEBUG_ANY, ("%s: if_flags 0x%x\n", 567 __func__, ifp->if_flags)); 568 569 ATH_LOCK(sc); 570 /* 571 * Stop anything previously setup. This is safe 572 * whether this is the first time through or not. 573 */ 574 ath_stop(ifp); 575 576 /* 577 * The basic interface to setting the hardware in a good 578 * state is ``reset''. On return the hardware is known to 579 * be powered up and with interrupts disabled. This must 580 * be followed by initialization of the appropriate bits 581 * and then setup of the interrupt mask. 582 */ 583 hchan.channel = ic->ic_ibss_chan->ic_freq; 584 hchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 585 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_FALSE, &status)) { 586 if_printf(ifp, "unable to reset hardware; hal status %u\n", 587 status); 588 goto done; 589 } 590 591 /* 592 * Setup the hardware after reset: the key cache 593 * is filled as needed and the receive engine is 594 * set going. Frame transmit is handled entirely 595 * in the frame output path; there's nothing to do 596 * here except setup the interrupt mask. 597 */ 598 if (ic->ic_flags & IEEE80211_F_WEPON) 599 ath_initkeytable(sc); 600 if (ath_startrecv(sc) != 0) { 601 if_printf(ifp, "unable to start recv logic\n"); 602 goto done; 603 } 604 605 /* 606 * Enable interrupts. 607 */ 608 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 609 | HAL_INT_RXEOL | HAL_INT_RXORN 610 | HAL_INT_FATAL | HAL_INT_GLOBAL; 611 ath_hal_intrset(ah, sc->sc_imask); 612 613 ifp->if_flags |= IFF_RUNNING; 614 ic->ic_state = IEEE80211_S_INIT; 615 616 /* 617 * The hardware should be ready to go now so it's safe 618 * to kick the 802.11 state machine as it's likely to 619 * immediately call back to us to send mgmt frames. 620 */ 621 ni = ic->ic_bss; 622 ni->ni_chan = ic->ic_ibss_chan; 623 mode = ieee80211_chan2mode(ic, ni->ni_chan); 624 if (mode != sc->sc_curmode) 625 ath_setcurmode(sc, mode); 626 if (ic->ic_opmode != IEEE80211_M_MONITOR) 627 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 628 else 629 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 630 done: 631 ATH_UNLOCK(sc); 632 } 633 634 static void 635 ath_stop(struct ifnet *ifp) 636 { 637 struct ieee80211com *ic = (struct ieee80211com *) ifp; 638 struct ath_softc *sc = ifp->if_softc; 639 struct ath_hal *ah = sc->sc_ah; 640 641 DPRINTF(ATH_DEBUG_ANY, ("%s: invalid %u if_flags 0x%x\n", 642 __func__, sc->sc_invalid, ifp->if_flags)); 643 644 ATH_LOCK(sc); 645 if (ifp->if_flags & IFF_RUNNING) { 646 /* 647 * Shutdown the hardware and driver: 648 * disable interrupts 649 * turn off timers 650 * clear transmit machinery 651 * clear receive machinery 652 * drain and release tx queues 653 * reclaim beacon resources 654 * reset 802.11 state machine 655 * power down hardware 656 * 657 * Note that some of this work is not possible if the 658 * hardware is gone (invalid). 659 */ 660 ifp->if_flags &= ~IFF_RUNNING; 661 ifp->if_timer = 0; 662 if (!sc->sc_invalid) 663 ath_hal_intrset(ah, 0); 664 ath_draintxq(sc); 665 if (!sc->sc_invalid) 666 ath_stoprecv(sc); 667 else 668 sc->sc_rxlink = NULL; 669 IFQ_DRV_PURGE(&ifp->if_snd); 670 ath_beacon_free(sc); 671 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 672 if (!sc->sc_invalid) 673 ath_hal_setpower(ah, HAL_PM_FULL_SLEEP, 0); 674 } 675 ATH_UNLOCK(sc); 676 } 677 678 /* 679 * Reset the hardware w/o losing operational state. This is 680 * basically a more efficient way of doing ath_stop, ath_init, 681 * followed by state transitions to the current 802.11 682 * operational state. Used to recover from errors rx overrun 683 * and to reset the hardware when rf gain settings must be reset. 684 */ 685 static void 686 ath_reset(struct ath_softc *sc) 687 { 688 struct ieee80211com *ic = &sc->sc_ic; 689 struct ifnet *ifp = &ic->ic_if; 690 struct ath_hal *ah = sc->sc_ah; 691 struct ieee80211_channel *c; 692 HAL_STATUS status; 693 HAL_CHANNEL hchan; 694 695 /* 696 * Convert to a HAL channel description with the flags 697 * constrained to reflect the current operating mode. 698 */ 699 c = ic->ic_ibss_chan; 700 hchan.channel = c->ic_freq; 701 hchan.channelFlags = ath_chan2flags(ic, c); 702 703 ath_hal_intrset(ah, 0); /* disable interrupts */ 704 ath_draintxq(sc); /* stop xmit side */ 705 ath_stoprecv(sc); /* stop recv side */ 706 /* NB: indicate channel change so we do a full reset */ 707 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) 708 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 709 __func__, status); 710 ath_hal_intrset(ah, sc->sc_imask); 711 if (ath_startrecv(sc) != 0) /* restart recv */ 712 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 713 ath_start(ifp); /* restart xmit */ 714 if (ic->ic_state == IEEE80211_S_RUN) 715 ath_beacon_config(sc); /* restart beacons */ 716 } 717 718 static void 719 ath_start(struct ifnet *ifp) 720 { 721 struct ath_softc *sc = ifp->if_softc; 722 struct ath_hal *ah = sc->sc_ah; 723 struct ieee80211com *ic = &sc->sc_ic; 724 struct ieee80211_node *ni; 725 struct ath_buf *bf; 726 struct mbuf *m; 727 struct ieee80211_frame *wh; 728 729 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 730 return; 731 for (;;) { 732 /* 733 * Grab a TX buffer and associated resources. 734 */ 735 ATH_TXBUF_LOCK(sc); 736 bf = TAILQ_FIRST(&sc->sc_txbuf); 737 if (bf != NULL) 738 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 739 ATH_TXBUF_UNLOCK(sc); 740 if (bf == NULL) { 741 DPRINTF(ATH_DEBUG_ANY, ("%s: out of xmit buffers\n", 742 __func__)); 743 sc->sc_stats.ast_tx_qstop++; 744 ifp->if_flags |= IFF_OACTIVE; 745 break; 746 } 747 /* 748 * Poll the management queue for frames; they 749 * have priority over normal data frames. 750 */ 751 IF_DEQUEUE(&ic->ic_mgtq, m); 752 if (m == NULL) { 753 /* 754 * No data frames go out unless we're associated. 755 */ 756 if (ic->ic_state != IEEE80211_S_RUN) { 757 DPRINTF(ATH_DEBUG_ANY, 758 ("%s: ignore data packet, state %u\n", 759 __func__, ic->ic_state)); 760 sc->sc_stats.ast_tx_discard++; 761 ATH_TXBUF_LOCK(sc); 762 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 763 ATH_TXBUF_UNLOCK(sc); 764 break; 765 } 766 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 767 if (m == NULL) { 768 ATH_TXBUF_LOCK(sc); 769 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 770 ATH_TXBUF_UNLOCK(sc); 771 break; 772 } 773 ifp->if_opackets++; 774 BPF_MTAP(ifp, m); 775 /* 776 * Encapsulate the packet in prep for transmission. 777 */ 778 m = ieee80211_encap(ifp, m, &ni); 779 if (m == NULL) { 780 DPRINTF(ATH_DEBUG_ANY, 781 ("%s: encapsulation failure\n", 782 __func__)); 783 sc->sc_stats.ast_tx_encap++; 784 goto bad; 785 } 786 wh = mtod(m, struct ieee80211_frame *); 787 if (ic->ic_flags & IEEE80211_F_WEPON) 788 wh->i_fc[1] |= IEEE80211_FC1_WEP; 789 } else { 790 /* 791 * Hack! The referenced node pointer is in the 792 * rcvif field of the packet header. This is 793 * placed there by ieee80211_mgmt_output because 794 * we need to hold the reference with the frame 795 * and there's no other way (other than packet 796 * tags which we consider too expensive to use) 797 * to pass it along. 798 */ 799 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 800 m->m_pkthdr.rcvif = NULL; 801 802 wh = mtod(m, struct ieee80211_frame *); 803 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 804 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 805 /* fill time stamp */ 806 u_int64_t tsf; 807 u_int32_t *tstamp; 808 809 tsf = ath_hal_gettsf64(ah); 810 /* XXX: adjust 100us delay to xmit */ 811 tsf += 100; 812 tstamp = (u_int32_t *)&wh[1]; 813 tstamp[0] = htole32(tsf & 0xffffffff); 814 tstamp[1] = htole32(tsf >> 32); 815 } 816 sc->sc_stats.ast_tx_mgmt++; 817 } 818 819 if (ath_tx_start(sc, ni, bf, m)) { 820 bad: 821 ATH_TXBUF_LOCK(sc); 822 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 823 ATH_TXBUF_UNLOCK(sc); 824 ifp->if_oerrors++; 825 if (ni && ni != ic->ic_bss) 826 ieee80211_free_node(ic, ni); 827 continue; 828 } 829 830 sc->sc_tx_timer = 5; 831 ifp->if_timer = 1; 832 } 833 } 834 835 static int 836 ath_media_change(struct ifnet *ifp) 837 { 838 int error; 839 840 error = ieee80211_media_change(ifp); 841 if (error == ENETRESET) { 842 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 843 (IFF_RUNNING|IFF_UP)) 844 ath_init(ifp); /* XXX lose error */ 845 error = 0; 846 } 847 return error; 848 } 849 850 static void 851 ath_watchdog(struct ifnet *ifp) 852 { 853 struct ath_softc *sc = ifp->if_softc; 854 struct ieee80211com *ic = &sc->sc_ic; 855 856 ifp->if_timer = 0; 857 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 858 return; 859 if (sc->sc_tx_timer) { 860 if (--sc->sc_tx_timer == 0) { 861 if_printf(ifp, "device timeout\n"); 862 #ifdef AR_DEBUG 863 if (ath_debug & ATH_DEBUG_WATCHDOG) 864 ath_hal_dumpstate(sc->sc_ah); 865 #endif /* AR_DEBUG */ 866 ath_reset(sc); 867 ifp->if_oerrors++; 868 sc->sc_stats.ast_watchdog++; 869 return; 870 } 871 ifp->if_timer = 1; 872 } 873 if (ic->ic_fixed_rate == -1) { 874 /* 875 * Run the rate control algorithm if we're not 876 * locked at a fixed rate. 877 */ 878 if (ic->ic_opmode == IEEE80211_M_STA) 879 ath_rate_ctl(sc, ic->ic_bss); 880 else 881 ieee80211_iterate_nodes(ic, ath_rate_ctl, sc); 882 } 883 ieee80211_watchdog(ifp); 884 } 885 886 static int 887 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 888 { 889 struct ath_softc *sc = ifp->if_softc; 890 struct ifreq *ifr = (struct ifreq *)data; 891 int error = 0; 892 893 ATH_LOCK(sc); 894 switch (cmd) { 895 case SIOCSIFFLAGS: 896 if (ifp->if_flags & IFF_UP) { 897 if (ifp->if_flags & IFF_RUNNING) { 898 /* 899 * To avoid rescanning another access point, 900 * do not call ath_init() here. Instead, 901 * only reflect promisc mode settings. 902 */ 903 ath_mode_init(sc); 904 } else { 905 /* 906 * Beware of being called during detach to 907 * reset promiscuous mode. In that case we 908 * will still be marked UP but not RUNNING. 909 * However trying to re-init the interface 910 * is the wrong thing to do as we've already 911 * torn down much of our state. There's 912 * probably a better way to deal with this. 913 */ 914 if (!sc->sc_invalid) 915 ath_init(ifp); /* XXX lose error */ 916 } 917 } else 918 ath_stop(ifp); 919 break; 920 case SIOCADDMULTI: 921 case SIOCDELMULTI: 922 /* 923 * The upper layer has already installed/removed 924 * the multicast address(es), just recalculate the 925 * multicast filter for the card. 926 */ 927 if (ifp->if_flags & IFF_RUNNING) 928 ath_mode_init(sc); 929 break; 930 case SIOCGATHSTATS: 931 error = copyout(&sc->sc_stats, 932 ifr->ifr_data, sizeof (sc->sc_stats)); 933 break; 934 case SIOCGATHDIAG: { 935 struct ath_diag *ad = (struct ath_diag *)data; 936 struct ath_hal *ah = sc->sc_ah; 937 void *data; 938 u_int size; 939 940 if (ath_hal_getdiagstate(ah, ad->ad_id, &data, &size)) { 941 if (size < ad->ad_size) 942 ad->ad_size = size; 943 if (data) 944 error = copyout(data, ad->ad_data, ad->ad_size); 945 } else 946 error = EINVAL; 947 break; 948 } 949 default: 950 error = ieee80211_ioctl(ifp, cmd, data); 951 if (error == ENETRESET) { 952 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 953 (IFF_RUNNING|IFF_UP)) 954 ath_init(ifp); /* XXX lose error */ 955 error = 0; 956 } 957 break; 958 } 959 ATH_UNLOCK(sc); 960 return error; 961 } 962 963 /* 964 * Fill the hardware key cache with key entries. 965 */ 966 static void 967 ath_initkeytable(struct ath_softc *sc) 968 { 969 struct ieee80211com *ic = &sc->sc_ic; 970 struct ath_hal *ah = sc->sc_ah; 971 int i; 972 973 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 974 struct ieee80211_wepkey *k = &ic->ic_nw_keys[i]; 975 if (k->wk_len == 0) 976 ath_hal_keyreset(ah, i); 977 else 978 /* XXX return value */ 979 /* NB: this uses HAL_KEYVAL == ieee80211_wepkey */ 980 ath_hal_keyset(ah, i, (const HAL_KEYVAL *) k); 981 } 982 } 983 984 /* 985 * Calculate the receive filter according to the 986 * operating mode and state: 987 * 988 * o always accept unicast, broadcast, and multicast traffic 989 * o maintain current state of phy error reception 990 * o probe request frames are accepted only when operating in 991 * hostap, adhoc, or monitor modes 992 * o enable promiscuous mode according to the interface state 993 * o accept beacons: 994 * - when operating in adhoc mode so the 802.11 layer creates 995 * node table entries for peers, 996 * - when operating in station mode for collecting rssi data when 997 * the station is otherwise quiet, or 998 * - when scanning 999 */ 1000 static u_int32_t 1001 ath_calcrxfilter(struct ath_softc *sc) 1002 { 1003 struct ieee80211com *ic = &sc->sc_ic; 1004 struct ath_hal *ah = sc->sc_ah; 1005 struct ifnet *ifp = &ic->ic_if; 1006 u_int32_t rfilt; 1007 1008 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1009 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1010 if (ic->ic_opmode != IEEE80211_M_STA) 1011 rfilt |= HAL_RX_FILTER_PROBEREQ; 1012 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1013 (ifp->if_flags & IFF_PROMISC)) 1014 rfilt |= HAL_RX_FILTER_PROM; 1015 if (ic->ic_opmode == IEEE80211_M_STA || 1016 ic->ic_opmode == IEEE80211_M_IBSS || 1017 ic->ic_state == IEEE80211_S_SCAN) 1018 rfilt |= HAL_RX_FILTER_BEACON; 1019 return rfilt; 1020 } 1021 1022 static void 1023 ath_mode_init(struct ath_softc *sc) 1024 { 1025 struct ieee80211com *ic = &sc->sc_ic; 1026 struct ath_hal *ah = sc->sc_ah; 1027 struct ifnet *ifp = &ic->ic_if; 1028 u_int32_t rfilt, mfilt[2], val; 1029 u_int8_t pos; 1030 struct ifmultiaddr *ifma; 1031 1032 /* configure rx filter */ 1033 rfilt = ath_calcrxfilter(sc); 1034 ath_hal_setrxfilter(ah, rfilt); 1035 1036 /* configure operational mode */ 1037 ath_hal_setopmode(ah, ic->ic_opmode); 1038 1039 /* calculate and install multicast filter */ 1040 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1041 mfilt[0] = mfilt[1] = 0; 1042 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1043 caddr_t dl; 1044 1045 /* calculate XOR of eight 6bit values */ 1046 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1047 val = LE_READ_4(dl + 0); 1048 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1049 val = LE_READ_4(dl + 3); 1050 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1051 pos &= 0x3f; 1052 mfilt[pos / 32] |= (1 << (pos % 32)); 1053 } 1054 } else { 1055 mfilt[0] = mfilt[1] = ~0; 1056 } 1057 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1058 DPRINTF(ATH_DEBUG_MODE, ("%s: RX filter 0x%x, MC filter %08x:%08x\n", 1059 __func__, rfilt, mfilt[0], mfilt[1])); 1060 } 1061 1062 static void 1063 ath_mbuf_load_cb(void *arg, bus_dma_segment_t *seg, int nseg, bus_size_t mapsize, int error) 1064 { 1065 struct ath_buf *bf = arg; 1066 1067 KASSERT(nseg <= ATH_MAX_SCATTER, 1068 ("ath_mbuf_load_cb: too many DMA segments %u", nseg)); 1069 bf->bf_mapsize = mapsize; 1070 bf->bf_nseg = nseg; 1071 bcopy(seg, bf->bf_segs, nseg * sizeof (seg[0])); 1072 } 1073 1074 static int 1075 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1076 { 1077 struct ieee80211com *ic = &sc->sc_ic; 1078 struct ifnet *ifp = &ic->ic_if; 1079 struct ath_hal *ah = sc->sc_ah; 1080 struct ieee80211_frame *wh; 1081 struct ath_buf *bf; 1082 struct ath_desc *ds; 1083 struct mbuf *m; 1084 int error, pktlen; 1085 u_int8_t *frm, rate; 1086 u_int16_t capinfo; 1087 struct ieee80211_rateset *rs; 1088 const HAL_RATE_TABLE *rt; 1089 1090 bf = sc->sc_bcbuf; 1091 if (bf->bf_m != NULL) { 1092 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1093 m_freem(bf->bf_m); 1094 bf->bf_m = NULL; 1095 bf->bf_node = NULL; 1096 } 1097 /* 1098 * NB: the beacon data buffer must be 32-bit aligned; 1099 * we assume the mbuf routines will return us something 1100 * with this alignment (perhaps should assert). 1101 */ 1102 rs = &ni->ni_rates; 1103 pktlen = sizeof (struct ieee80211_frame) 1104 + 8 + 2 + 2 + 2+ni->ni_esslen + 2+rs->rs_nrates + 3 + 6; 1105 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 1106 pktlen += 2; 1107 if (pktlen <= MHLEN) 1108 MGETHDR(m, M_DONTWAIT, MT_DATA); 1109 else 1110 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1111 if (m == NULL) { 1112 DPRINTF(ATH_DEBUG_BEACON, 1113 ("%s: cannot get mbuf/cluster; size %u\n", 1114 __func__, pktlen)); 1115 sc->sc_stats.ast_be_nombuf++; 1116 return ENOMEM; 1117 } 1118 1119 wh = mtod(m, struct ieee80211_frame *); 1120 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1121 IEEE80211_FC0_SUBTYPE_BEACON; 1122 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1123 *(u_int16_t *)wh->i_dur = 0; 1124 memcpy(wh->i_addr1, ifp->if_broadcastaddr, IEEE80211_ADDR_LEN); 1125 memcpy(wh->i_addr2, ic->ic_myaddr, IEEE80211_ADDR_LEN); 1126 memcpy(wh->i_addr3, ni->ni_bssid, IEEE80211_ADDR_LEN); 1127 *(u_int16_t *)wh->i_seq = 0; 1128 1129 /* 1130 * beacon frame format 1131 * [8] time stamp 1132 * [2] beacon interval 1133 * [2] cabability information 1134 * [tlv] ssid 1135 * [tlv] supported rates 1136 * [tlv] parameter set (IBSS) 1137 * [tlv] extended supported rates 1138 */ 1139 frm = (u_int8_t *)&wh[1]; 1140 memset(frm, 0, 8); /* timestamp is set by hardware */ 1141 frm += 8; 1142 *(u_int16_t *)frm = htole16(ni->ni_intval); 1143 frm += 2; 1144 if (ic->ic_opmode == IEEE80211_M_IBSS) 1145 capinfo = IEEE80211_CAPINFO_IBSS; 1146 else 1147 capinfo = IEEE80211_CAPINFO_ESS; 1148 if (ic->ic_flags & IEEE80211_F_WEPON) 1149 capinfo |= IEEE80211_CAPINFO_PRIVACY; 1150 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1151 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 1152 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 1153 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1154 capinfo |= IEEE80211_CAPINFO_SHORT_SLOTTIME; 1155 *(u_int16_t *)frm = htole16(capinfo); 1156 frm += 2; 1157 *frm++ = IEEE80211_ELEMID_SSID; 1158 *frm++ = ni->ni_esslen; 1159 memcpy(frm, ni->ni_essid, ni->ni_esslen); 1160 frm += ni->ni_esslen; 1161 frm = ieee80211_add_rates(frm, rs); 1162 *frm++ = IEEE80211_ELEMID_DSPARMS; 1163 *frm++ = 1; 1164 *frm++ = ieee80211_chan2ieee(ic, ni->ni_chan); 1165 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1166 *frm++ = IEEE80211_ELEMID_IBSSPARMS; 1167 *frm++ = 2; 1168 *frm++ = 0; *frm++ = 0; /* TODO: ATIM window */ 1169 } else { 1170 /* TODO: TIM */ 1171 *frm++ = IEEE80211_ELEMID_TIM; 1172 *frm++ = 4; /* length */ 1173 *frm++ = 0; /* DTIM count */ 1174 *frm++ = 1; /* DTIM period */ 1175 *frm++ = 0; /* bitmap control */ 1176 *frm++ = 0; /* Partial Virtual Bitmap (variable length) */ 1177 } 1178 frm = ieee80211_add_xrates(frm, rs); 1179 m->m_pkthdr.len = m->m_len = frm - mtod(m, u_int8_t *); 1180 KASSERT(m->m_pkthdr.len <= pktlen, 1181 ("beacon bigger than expected, len %u calculated %u", 1182 m->m_pkthdr.len, pktlen)); 1183 1184 DPRINTF(ATH_DEBUG_BEACON, ("%s: m %p len %u\n", __func__, m, m->m_len)); 1185 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1186 ath_mbuf_load_cb, bf, 1187 BUS_DMA_NOWAIT); 1188 if (error != 0) { 1189 m_freem(m); 1190 return error; 1191 } 1192 KASSERT(bf->bf_nseg == 1, 1193 ("%s: multi-segment packet; nseg %u", __func__, bf->bf_nseg)); 1194 bf->bf_m = m; 1195 1196 /* setup descriptors */ 1197 ds = bf->bf_desc; 1198 1199 ds->ds_link = 0; 1200 ds->ds_data = bf->bf_segs[0].ds_addr; 1201 /* 1202 * Calculate rate code. 1203 * XXX everything at min xmit rate 1204 */ 1205 rt = sc->sc_currates; 1206 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1207 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1208 rate = rt->info[0].rateCode | rt->info[0].shortPreamble; 1209 else 1210 rate = rt->info[0].rateCode; 1211 ath_hal_setuptxdesc(ah, ds 1212 , m->m_pkthdr.len + IEEE80211_CRC_LEN /* packet length */ 1213 , sizeof(struct ieee80211_frame) /* header length */ 1214 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1215 , 0x20 /* txpower XXX */ 1216 , rate, 1 /* series 0 rate/tries */ 1217 , HAL_TXKEYIX_INVALID /* no encryption */ 1218 , 0 /* antenna mode */ 1219 , HAL_TXDESC_NOACK /* no ack for beacons */ 1220 , 0 /* rts/cts rate */ 1221 , 0 /* rts/cts duration */ 1222 ); 1223 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1224 /* XXX verify mbuf data area covers this roundup */ 1225 ath_hal_filltxdesc(ah, ds 1226 , roundup(bf->bf_segs[0].ds_len, 4) /* buffer length */ 1227 , AH_TRUE /* first segment */ 1228 , AH_TRUE /* last segment */ 1229 ); 1230 1231 return 0; 1232 } 1233 1234 static void 1235 ath_beacon_proc(void *arg, int pending) 1236 { 1237 struct ath_softc *sc = arg; 1238 struct ieee80211com *ic = &sc->sc_ic; 1239 struct ath_buf *bf = sc->sc_bcbuf; 1240 struct ath_hal *ah = sc->sc_ah; 1241 1242 DPRINTF(ATH_DEBUG_BEACON_PROC, ("%s: pending %u\n", __func__, pending)); 1243 if (ic->ic_opmode == IEEE80211_M_STA || 1244 bf == NULL || bf->bf_m == NULL) { 1245 DPRINTF(ATH_DEBUG_ANY, ("%s: ic_flags=%x bf=%p bf_m=%p\n", 1246 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL)); 1247 return; 1248 } 1249 /* TODO: update beacon to reflect PS poll state */ 1250 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1251 DPRINTF(ATH_DEBUG_ANY, ("%s: beacon queue %u did not stop?\n", 1252 __func__, sc->sc_bhalq)); 1253 /* NB: the HAL still stops DMA, so proceed */ 1254 } 1255 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1256 1257 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 1258 ath_hal_txstart(ah, sc->sc_bhalq); 1259 DPRINTF(ATH_DEBUG_BEACON_PROC, 1260 ("%s: TXDP%u = %p (%p)\n", __func__, 1261 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1262 } 1263 1264 static void 1265 ath_beacon_free(struct ath_softc *sc) 1266 { 1267 struct ath_buf *bf = sc->sc_bcbuf; 1268 1269 if (bf->bf_m != NULL) { 1270 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1271 m_freem(bf->bf_m); 1272 bf->bf_m = NULL; 1273 bf->bf_node = NULL; 1274 } 1275 } 1276 1277 /* 1278 * Configure the beacon and sleep timers. 1279 * 1280 * When operating as an AP this resets the TSF and sets 1281 * up the hardware to notify us when we need to issue beacons. 1282 * 1283 * When operating in station mode this sets up the beacon 1284 * timers according to the timestamp of the last received 1285 * beacon and the current TSF, configures PCF and DTIM 1286 * handling, programs the sleep registers so the hardware 1287 * will wakeup in time to receive beacons, and configures 1288 * the beacon miss handling so we'll receive a BMISS 1289 * interrupt when we stop seeing beacons from the AP 1290 * we've associated with. 1291 */ 1292 static void 1293 ath_beacon_config(struct ath_softc *sc) 1294 { 1295 struct ath_hal *ah = sc->sc_ah; 1296 struct ieee80211com *ic = &sc->sc_ic; 1297 struct ieee80211_node *ni = ic->ic_bss; 1298 u_int32_t nexttbtt; 1299 1300 nexttbtt = (LE_READ_4(ni->ni_tstamp + 4) << 22) | 1301 (LE_READ_4(ni->ni_tstamp) >> 10); 1302 DPRINTF(ATH_DEBUG_BEACON, ("%s: nexttbtt=%u\n", __func__, nexttbtt)); 1303 nexttbtt += ni->ni_intval; 1304 if (ic->ic_opmode == IEEE80211_M_STA) { 1305 HAL_BEACON_STATE bs; 1306 u_int32_t bmisstime; 1307 1308 /* NB: no PCF support right now */ 1309 memset(&bs, 0, sizeof(bs)); 1310 bs.bs_intval = ni->ni_intval; 1311 bs.bs_nexttbtt = nexttbtt; 1312 bs.bs_dtimperiod = bs.bs_intval; 1313 bs.bs_nextdtim = nexttbtt; 1314 /* 1315 * Calculate the number of consecutive beacons to miss 1316 * before taking a BMISS interrupt. The configuration 1317 * is specified in ms, so we need to convert that to 1318 * TU's and then calculate based on the beacon interval. 1319 * Note that we clamp the result to at most 10 beacons. 1320 */ 1321 bmisstime = (ic->ic_bmisstimeout * 1000) / 1024; 1322 bs.bs_bmissthreshold = howmany(bmisstime,ni->ni_intval); 1323 if (bs.bs_bmissthreshold > 10) 1324 bs.bs_bmissthreshold = 10; 1325 else if (bs.bs_bmissthreshold <= 0) 1326 bs.bs_bmissthreshold = 1; 1327 1328 /* 1329 * Calculate sleep duration. The configuration is 1330 * given in ms. We insure a multiple of the beacon 1331 * period is used. Also, if the sleep duration is 1332 * greater than the DTIM period then it makes senses 1333 * to make it a multiple of that. 1334 * 1335 * XXX fixed at 100ms 1336 */ 1337 bs.bs_sleepduration = 1338 roundup((100 * 1000) / 1024, bs.bs_intval); 1339 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1340 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1341 1342 DPRINTF(ATH_DEBUG_BEACON, 1343 ("%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u\n" 1344 , __func__ 1345 , bs.bs_intval 1346 , bs.bs_nexttbtt 1347 , bs.bs_dtimperiod 1348 , bs.bs_nextdtim 1349 , bs.bs_bmissthreshold 1350 , bs.bs_sleepduration 1351 )); 1352 ath_hal_intrset(ah, 0); 1353 /* 1354 * Reset our tsf so the hardware will update the 1355 * tsf register to reflect timestamps found in 1356 * received beacons. 1357 */ 1358 ath_hal_resettsf(ah); 1359 ath_hal_beacontimers(ah, &bs, 0/*XXX*/, 0, 0); 1360 sc->sc_imask |= HAL_INT_BMISS; 1361 ath_hal_intrset(ah, sc->sc_imask); 1362 } else { 1363 DPRINTF(ATH_DEBUG_BEACON, ("%s: intval %u nexttbtt %u\n", 1364 __func__, ni->ni_intval, nexttbtt)); 1365 ath_hal_intrset(ah, 0); 1366 ath_hal_beaconinit(ah, ic->ic_opmode, 1367 nexttbtt, ni->ni_intval); 1368 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1369 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1370 ath_hal_intrset(ah, sc->sc_imask); 1371 } 1372 } 1373 1374 static void 1375 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1376 { 1377 bus_addr_t *paddr = (bus_addr_t*) arg; 1378 *paddr = segs->ds_addr; 1379 } 1380 1381 static int 1382 ath_desc_alloc(struct ath_softc *sc) 1383 { 1384 int i, bsize, error; 1385 struct ath_desc *ds; 1386 struct ath_buf *bf; 1387 1388 /* allocate descriptors */ 1389 sc->sc_desc_len = sizeof(struct ath_desc) * 1390 (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + 1); 1391 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1392 if (error != 0) 1393 return error; 1394 1395 error = bus_dmamem_alloc(sc->sc_dmat, (void**) &sc->sc_desc, 1396 BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1397 if (error != 0) 1398 goto fail0; 1399 1400 error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, 1401 sc->sc_desc, sc->sc_desc_len, 1402 ath_load_cb, &sc->sc_desc_paddr, 1403 BUS_DMA_NOWAIT); 1404 if (error != 0) 1405 goto fail1; 1406 1407 ds = sc->sc_desc; 1408 DPRINTF(ATH_DEBUG_ANY, ("%s: DMA map: %p (%lu) -> %p (%lu)\n", 1409 __func__, ds, (u_long) sc->sc_desc_len, (caddr_t) sc->sc_desc_paddr, 1410 /*XXX*/ (u_long) sc->sc_desc_len)); 1411 1412 /* allocate buffers */ 1413 bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 1); 1414 bf = malloc(bsize, M_DEVBUF, M_NOWAIT | M_ZERO); 1415 if (bf == NULL) 1416 goto fail2; 1417 sc->sc_bufptr = bf; 1418 1419 TAILQ_INIT(&sc->sc_rxbuf); 1420 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 1421 bf->bf_desc = ds; 1422 bf->bf_daddr = sc->sc_desc_paddr + 1423 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1424 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1425 &bf->bf_dmamap); 1426 if (error != 0) 1427 break; 1428 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1429 } 1430 1431 TAILQ_INIT(&sc->sc_txbuf); 1432 for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { 1433 bf->bf_desc = ds; 1434 bf->bf_daddr = sc->sc_desc_paddr + 1435 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1436 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1437 &bf->bf_dmamap); 1438 if (error != 0) 1439 break; 1440 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1441 } 1442 TAILQ_INIT(&sc->sc_txq); 1443 1444 /* beacon buffer */ 1445 bf->bf_desc = ds; 1446 bf->bf_daddr = sc->sc_desc_paddr + ((caddr_t)ds - (caddr_t)sc->sc_desc); 1447 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &bf->bf_dmamap); 1448 if (error != 0) 1449 return error; 1450 sc->sc_bcbuf = bf; 1451 return 0; 1452 1453 fail2: 1454 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1455 fail1: 1456 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1457 fail0: 1458 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1459 sc->sc_ddmamap = NULL; 1460 return error; 1461 } 1462 1463 static void 1464 ath_desc_free(struct ath_softc *sc) 1465 { 1466 struct ath_buf *bf; 1467 1468 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1469 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1470 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1471 1472 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1473 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1474 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1475 m_freem(bf->bf_m); 1476 } 1477 TAILQ_FOREACH(bf, &sc->sc_txbuf, bf_list) 1478 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1479 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1480 if (bf->bf_m) { 1481 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1482 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1483 m_freem(bf->bf_m); 1484 bf->bf_m = NULL; 1485 } 1486 } 1487 if (sc->sc_bcbuf != NULL) { 1488 bus_dmamap_unload(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1489 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1490 sc->sc_bcbuf = NULL; 1491 } 1492 1493 TAILQ_INIT(&sc->sc_rxbuf); 1494 TAILQ_INIT(&sc->sc_txbuf); 1495 TAILQ_INIT(&sc->sc_txq); 1496 free(sc->sc_bufptr, M_DEVBUF); 1497 sc->sc_bufptr = NULL; 1498 } 1499 1500 static struct ieee80211_node * 1501 ath_node_alloc(struct ieee80211com *ic) 1502 { 1503 struct ath_node *an = 1504 malloc(sizeof(struct ath_node), M_80211_NODE, M_NOWAIT|M_ZERO); 1505 if (an) { 1506 int i; 1507 for (i = 0; i < ATH_RHIST_SIZE; i++) 1508 an->an_rx_hist[i].arh_ticks = ATH_RHIST_NOTIME; 1509 an->an_rx_hist_next = ATH_RHIST_SIZE-1; 1510 return &an->an_node; 1511 } else 1512 return NULL; 1513 } 1514 1515 static void 1516 ath_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 1517 { 1518 struct ath_softc *sc = ic->ic_if.if_softc; 1519 struct ath_buf *bf; 1520 1521 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1522 if (bf->bf_node == ni) 1523 bf->bf_node = NULL; 1524 } 1525 (*sc->sc_node_free)(ic, ni); 1526 } 1527 1528 static void 1529 ath_node_copy(struct ieee80211com *ic, 1530 struct ieee80211_node *dst, const struct ieee80211_node *src) 1531 { 1532 struct ath_softc *sc = ic->ic_if.if_softc; 1533 1534 memcpy(&dst[1], &src[1], 1535 sizeof(struct ath_node) - sizeof(struct ieee80211_node)); 1536 (*sc->sc_node_copy)(ic, dst, src); 1537 } 1538 1539 1540 static u_int8_t 1541 ath_node_getrssi(struct ieee80211com *ic, struct ieee80211_node *ni) 1542 { 1543 struct ath_node *an = ATH_NODE(ni); 1544 int i, now, nsamples, rssi; 1545 1546 /* 1547 * Calculate the average over the last second of sampled data. 1548 */ 1549 now = ticks; 1550 nsamples = 0; 1551 rssi = 0; 1552 i = an->an_rx_hist_next; 1553 do { 1554 struct ath_recv_hist *rh = &an->an_rx_hist[i]; 1555 if (rh->arh_ticks == ATH_RHIST_NOTIME) 1556 goto done; 1557 if (now - rh->arh_ticks > hz) 1558 goto done; 1559 rssi += rh->arh_rssi; 1560 nsamples++; 1561 if (i == 0) 1562 i = ATH_RHIST_SIZE-1; 1563 else 1564 i--; 1565 } while (i != an->an_rx_hist_next); 1566 done: 1567 /* 1568 * Return either the average or the last known 1569 * value if there is no recent data. 1570 */ 1571 return (nsamples ? rssi / nsamples : an->an_rx_hist[i].arh_rssi); 1572 } 1573 1574 static int 1575 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 1576 { 1577 struct ath_hal *ah = sc->sc_ah; 1578 int error; 1579 struct mbuf *m; 1580 struct ath_desc *ds; 1581 1582 m = bf->bf_m; 1583 if (m == NULL) { 1584 /* 1585 * NB: by assigning a page to the rx dma buffer we 1586 * implicitly satisfy the Atheros requirement that 1587 * this buffer be cache-line-aligned and sized to be 1588 * multiple of the cache line size. Not doing this 1589 * causes weird stuff to happen (for the 5210 at least). 1590 */ 1591 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1592 if (m == NULL) { 1593 DPRINTF(ATH_DEBUG_ANY, 1594 ("%s: no mbuf/cluster\n", __func__)); 1595 sc->sc_stats.ast_rx_nombuf++; 1596 return ENOMEM; 1597 } 1598 bf->bf_m = m; 1599 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1600 1601 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1602 ath_mbuf_load_cb, bf, 1603 BUS_DMA_NOWAIT); 1604 if (error != 0) { 1605 DPRINTF(ATH_DEBUG_ANY, 1606 ("%s: bus_dmamap_load_mbuf failed; error %d\n", 1607 __func__, error)); 1608 sc->sc_stats.ast_rx_busdma++; 1609 return error; 1610 } 1611 KASSERT(bf->bf_nseg == 1, 1612 ("ath_rxbuf_init: multi-segment packet; nseg %u", 1613 bf->bf_nseg)); 1614 } 1615 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 1616 1617 /* 1618 * Setup descriptors. For receive we always terminate 1619 * the descriptor list with a self-linked entry so we'll 1620 * not get overrun under high load (as can happen with a 1621 * 5212 when ANI processing enables PHY errors). 1622 * 1623 * To insure the last descriptor is self-linked we create 1624 * each descriptor as self-linked and add it to the end. As 1625 * each additional descriptor is added the previous self-linked 1626 * entry is ``fixed'' naturally. This should be safe even 1627 * if DMA is happening. When processing RX interrupts we 1628 * never remove/process the last, self-linked, entry on the 1629 * descriptor list. This insures the hardware always has 1630 * someplace to write a new frame. 1631 */ 1632 ds = bf->bf_desc; 1633 ds->ds_link = bf->bf_daddr; /* link to self */ 1634 ds->ds_data = bf->bf_segs[0].ds_addr; 1635 ath_hal_setuprxdesc(ah, ds 1636 , m->m_len /* buffer size */ 1637 , 0 1638 ); 1639 1640 if (sc->sc_rxlink != NULL) 1641 *sc->sc_rxlink = bf->bf_daddr; 1642 sc->sc_rxlink = &ds->ds_link; 1643 return 0; 1644 } 1645 1646 static void 1647 ath_rx_proc(void *arg, int npending) 1648 { 1649 #define PA2DESC(_sc, _pa) \ 1650 ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \ 1651 ((_pa) - (_sc)->sc_desc_paddr))) 1652 struct ath_softc *sc = arg; 1653 struct ath_buf *bf; 1654 struct ieee80211com *ic = &sc->sc_ic; 1655 struct ifnet *ifp = &ic->ic_if; 1656 struct ath_hal *ah = sc->sc_ah; 1657 struct ath_desc *ds; 1658 struct mbuf *m; 1659 struct ieee80211_frame *wh, whbuf; 1660 struct ieee80211_node *ni; 1661 struct ath_node *an; 1662 struct ath_recv_hist *rh; 1663 int len; 1664 u_int phyerr; 1665 HAL_STATUS status; 1666 1667 NET_LOCK_GIANT(); /* XXX */ 1668 1669 DPRINTF(ATH_DEBUG_RX_PROC, ("%s: pending %u\n", __func__, npending)); 1670 do { 1671 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1672 if (bf == NULL) { /* NB: shouldn't happen */ 1673 if_printf(ifp, "ath_rx_proc: no buffer!\n"); 1674 break; 1675 } 1676 ds = bf->bf_desc; 1677 if (ds->ds_link == bf->bf_daddr) { 1678 /* NB: never process the self-linked entry at the end */ 1679 break; 1680 } 1681 m = bf->bf_m; 1682 if (m == NULL) { /* NB: shouldn't happen */ 1683 if_printf(ifp, "ath_rx_proc: no mbuf!\n"); 1684 continue; 1685 } 1686 /* XXX sync descriptor memory */ 1687 /* 1688 * Must provide the virtual address of the current 1689 * descriptor, the physical address, and the virtual 1690 * address of the next descriptor in the h/w chain. 1691 * This allows the HAL to look ahead to see if the 1692 * hardware is done with a descriptor by checking the 1693 * done bit in the following descriptor and the address 1694 * of the current descriptor the DMA engine is working 1695 * on. All this is necessary because of our use of 1696 * a self-linked list to avoid rx overruns. 1697 */ 1698 status = ath_hal_rxprocdesc(ah, ds, 1699 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 1700 #ifdef AR_DEBUG 1701 if (ath_debug & ATH_DEBUG_RECV_DESC) 1702 ath_printrxbuf(bf, status == HAL_OK); 1703 #endif 1704 if (status == HAL_EINPROGRESS) 1705 break; 1706 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1707 if (ds->ds_rxstat.rs_status != 0) { 1708 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 1709 sc->sc_stats.ast_rx_crcerr++; 1710 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 1711 sc->sc_stats.ast_rx_fifoerr++; 1712 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) 1713 sc->sc_stats.ast_rx_badcrypt++; 1714 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 1715 sc->sc_stats.ast_rx_phyerr++; 1716 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 1717 sc->sc_stats.ast_rx_phy[phyerr]++; 1718 } else { 1719 /* 1720 * NB: don't count PHY errors as input errors; 1721 * we enable them on the 5212 to collect info 1722 * about environmental noise and, in that 1723 * setting, they don't really reflect tx/rx 1724 * errors. 1725 */ 1726 ifp->if_ierrors++; 1727 } 1728 goto rx_next; 1729 } 1730 1731 len = ds->ds_rxstat.rs_datalen; 1732 if (len < IEEE80211_MIN_LEN) { 1733 DPRINTF(ATH_DEBUG_RECV, ("%s: short packet %d\n", 1734 __func__, len)); 1735 sc->sc_stats.ast_rx_tooshort++; 1736 goto rx_next; 1737 } 1738 1739 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 1740 BUS_DMASYNC_POSTREAD); 1741 1742 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1743 bf->bf_m = NULL; 1744 m->m_pkthdr.rcvif = ifp; 1745 m->m_pkthdr.len = m->m_len = len; 1746 1747 if (sc->sc_drvbpf) { 1748 sc->sc_rx_th.wr_rate = 1749 sc->sc_hwmap[ds->ds_rxstat.rs_rate]; 1750 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi; 1751 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 1752 /* XXX TSF */ 1753 1754 bpf_mtap2(sc->sc_drvbpf, 1755 &sc->sc_rx_th, sc->sc_rx_th_len, m); 1756 } 1757 1758 m_adj(m, -IEEE80211_CRC_LEN); 1759 wh = mtod(m, struct ieee80211_frame *); 1760 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1761 /* 1762 * WEP is decrypted by hardware. Clear WEP bit 1763 * and trim WEP header for ieee80211_input(). 1764 */ 1765 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 1766 memcpy(&whbuf, wh, sizeof(whbuf)); 1767 m_adj(m, IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN); 1768 wh = mtod(m, struct ieee80211_frame *); 1769 memcpy(wh, &whbuf, sizeof(whbuf)); 1770 /* 1771 * Also trim WEP ICV from the tail. 1772 */ 1773 m_adj(m, -IEEE80211_WEP_CRCLEN); 1774 } 1775 1776 /* 1777 * Locate the node for sender, track state, and 1778 * then pass this node (referenced) up to the 802.11 1779 * layer for its use. We are required to pass 1780 * something so we fall back to ic_bss when this frame 1781 * is from an unknown sender. 1782 */ 1783 if (ic->ic_opmode != IEEE80211_M_STA) { 1784 ni = ieee80211_find_node(ic, wh->i_addr2); 1785 if (ni == NULL) 1786 ni = ieee80211_ref_node(ic->ic_bss); 1787 } else 1788 ni = ieee80211_ref_node(ic->ic_bss); 1789 1790 /* 1791 * Record driver-specific state. 1792 */ 1793 an = ATH_NODE(ni); 1794 if (++(an->an_rx_hist_next) == ATH_RHIST_SIZE) 1795 an->an_rx_hist_next = 0; 1796 rh = &an->an_rx_hist[an->an_rx_hist_next]; 1797 rh->arh_ticks = ticks; 1798 rh->arh_rssi = ds->ds_rxstat.rs_rssi; 1799 rh->arh_antenna = ds->ds_rxstat.rs_antenna; 1800 1801 /* 1802 * Send frame up for processing. 1803 */ 1804 ieee80211_input(ifp, m, ni, 1805 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 1806 1807 /* 1808 * The frame may have caused the node to be marked for 1809 * reclamation (e.g. in response to a DEAUTH message) 1810 * so use free_node here instead of unref_node. 1811 */ 1812 if (ni == ic->ic_bss) 1813 ieee80211_unref_node(&ni); 1814 else 1815 ieee80211_free_node(ic, ni); 1816 rx_next: 1817 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1818 } while (ath_rxbuf_init(sc, bf) == 0); 1819 1820 ath_hal_rxmonitor(ah); /* rx signal state monitoring */ 1821 ath_hal_rxena(ah); /* in case of RXEOL */ 1822 1823 NET_UNLOCK_GIANT(); /* XXX */ 1824 #undef PA2DESC 1825 } 1826 1827 /* 1828 * XXX Size of an ACK control frame in bytes. 1829 */ 1830 #define IEEE80211_ACK_SIZE (2+2+IEEE80211_ADDR_LEN+4) 1831 1832 static int 1833 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 1834 struct mbuf *m0) 1835 { 1836 struct ieee80211com *ic = &sc->sc_ic; 1837 struct ath_hal *ah = sc->sc_ah; 1838 struct ifnet *ifp = &sc->sc_ic.ic_if; 1839 int i, error, iswep, hdrlen, pktlen; 1840 u_int8_t rix, cix, txrate, ctsrate; 1841 struct ath_desc *ds; 1842 struct mbuf *m; 1843 struct ieee80211_frame *wh; 1844 u_int32_t iv; 1845 u_int8_t *ivp; 1846 u_int8_t hdrbuf[sizeof(struct ieee80211_frame) + 1847 IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN]; 1848 u_int subtype, flags, ctsduration, antenna; 1849 HAL_PKT_TYPE atype; 1850 const HAL_RATE_TABLE *rt; 1851 HAL_BOOL shortPreamble; 1852 struct ath_node *an; 1853 1854 wh = mtod(m0, struct ieee80211_frame *); 1855 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1856 hdrlen = sizeof(struct ieee80211_frame); 1857 pktlen = m0->m_pkthdr.len; 1858 1859 if (iswep) { 1860 memcpy(hdrbuf, mtod(m0, caddr_t), hdrlen); 1861 m_adj(m0, hdrlen); 1862 M_PREPEND(m0, sizeof(hdrbuf), M_DONTWAIT); 1863 if (m0 == NULL) { 1864 sc->sc_stats.ast_tx_nombuf++; 1865 return ENOMEM; 1866 } 1867 ivp = hdrbuf + hdrlen; 1868 wh = mtod(m0, struct ieee80211_frame *); 1869 /* 1870 * XXX 1871 * IV must not duplicate during the lifetime of the key. 1872 * But no mechanism to renew keys is defined in IEEE 802.11 1873 * WEP. And IV may be duplicated between other stations 1874 * because of the session key itself is shared. 1875 * So we use pseudo random IV for now, though it is not the 1876 * right way. 1877 */ 1878 iv = ic->ic_iv; 1879 /* 1880 * Skip 'bad' IVs from Fluhrer/Mantin/Shamir: 1881 * (B, 255, N) with 3 <= B < 8 1882 */ 1883 if (iv >= 0x03ff00 && (iv & 0xf8ff00) == 0x00ff00) 1884 iv += 0x000100; 1885 ic->ic_iv = iv + 1; 1886 for (i = 0; i < IEEE80211_WEP_IVLEN; i++) { 1887 ivp[i] = iv; 1888 iv >>= 8; 1889 } 1890 ivp[i] = sc->sc_ic.ic_wep_txkey << 6; /* Key ID and pad */ 1891 memcpy(mtod(m0, caddr_t), hdrbuf, sizeof(hdrbuf)); 1892 /* 1893 * The ICV length must be included into hdrlen and pktlen. 1894 */ 1895 hdrlen = sizeof(hdrbuf) + IEEE80211_WEP_CRCLEN; 1896 pktlen = m0->m_pkthdr.len + IEEE80211_WEP_CRCLEN; 1897 } 1898 pktlen += IEEE80211_CRC_LEN; 1899 1900 /* 1901 * Load the DMA map so any coalescing is done. This 1902 * also calculates the number of descriptors we need. 1903 */ 1904 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1905 ath_mbuf_load_cb, bf, 1906 BUS_DMA_NOWAIT); 1907 if (error == EFBIG) { 1908 /* XXX packet requires too many descriptors */ 1909 bf->bf_nseg = ATH_TXDESC+1; 1910 } else if (error != 0) { 1911 sc->sc_stats.ast_tx_busdma++; 1912 m_freem(m0); 1913 return error; 1914 } 1915 /* 1916 * Discard null packets and check for packets that 1917 * require too many TX descriptors. We try to convert 1918 * the latter to a cluster. 1919 */ 1920 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 1921 sc->sc_stats.ast_tx_linear++; 1922 MGETHDR(m, M_DONTWAIT, MT_DATA); 1923 if (m == NULL) { 1924 sc->sc_stats.ast_tx_nombuf++; 1925 m_freem(m0); 1926 return ENOMEM; 1927 } 1928 M_MOVE_PKTHDR(m, m0); 1929 MCLGET(m, M_DONTWAIT); 1930 if ((m->m_flags & M_EXT) == 0) { 1931 sc->sc_stats.ast_tx_nomcl++; 1932 m_freem(m0); 1933 m_free(m); 1934 return ENOMEM; 1935 } 1936 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1937 m_freem(m0); 1938 m->m_len = m->m_pkthdr.len; 1939 m0 = m; 1940 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1941 ath_mbuf_load_cb, bf, 1942 BUS_DMA_NOWAIT); 1943 if (error != 0) { 1944 sc->sc_stats.ast_tx_busdma++; 1945 m_freem(m0); 1946 return error; 1947 } 1948 KASSERT(bf->bf_nseg == 1, 1949 ("ath_tx_start: packet not one segment; nseg %u", 1950 bf->bf_nseg)); 1951 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 1952 sc->sc_stats.ast_tx_nodata++; 1953 m_freem(m0); 1954 return EIO; 1955 } 1956 DPRINTF(ATH_DEBUG_XMIT, ("%s: m %p len %u\n", __func__, m0, pktlen)); 1957 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1958 bf->bf_m = m0; 1959 bf->bf_node = ni; /* NB: held reference */ 1960 1961 /* setup descriptors */ 1962 ds = bf->bf_desc; 1963 rt = sc->sc_currates; 1964 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1965 1966 /* 1967 * Calculate Atheros packet type from IEEE80211 packet header 1968 * and setup for rate calculations. 1969 */ 1970 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1971 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1972 case IEEE80211_FC0_TYPE_MGT: 1973 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1974 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1975 atype = HAL_PKT_TYPE_BEACON; 1976 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1977 atype = HAL_PKT_TYPE_PROBE_RESP; 1978 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1979 atype = HAL_PKT_TYPE_ATIM; 1980 rix = 0; /* XXX lowest rate */ 1981 break; 1982 case IEEE80211_FC0_TYPE_CTL: 1983 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1984 if (subtype == IEEE80211_FC0_SUBTYPE_PS_POLL) 1985 atype = HAL_PKT_TYPE_PSPOLL; 1986 rix = 0; /* XXX lowest rate */ 1987 break; 1988 default: 1989 rix = sc->sc_rixmap[ni->ni_rates.rs_rates[ni->ni_txrate] & 1990 IEEE80211_RATE_VAL]; 1991 if (rix == 0xff) { 1992 if_printf(ifp, "bogus xmit rate 0x%x\n", 1993 ni->ni_rates.rs_rates[ni->ni_txrate]); 1994 sc->sc_stats.ast_tx_badrate++; 1995 m_freem(m0); 1996 return EIO; 1997 } 1998 break; 1999 } 2000 /* 2001 * NB: the 802.11 layer marks whether or not we should 2002 * use short preamble based on the current mode and 2003 * negotiated parameters. 2004 */ 2005 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2006 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 2007 txrate = rt->info[rix].rateCode | rt->info[rix].shortPreamble; 2008 shortPreamble = AH_TRUE; 2009 sc->sc_stats.ast_tx_shortpre++; 2010 } else { 2011 txrate = rt->info[rix].rateCode; 2012 shortPreamble = AH_FALSE; 2013 } 2014 2015 /* 2016 * Calculate miscellaneous flags. 2017 */ 2018 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for wep errors */ 2019 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2020 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 2021 sc->sc_stats.ast_tx_noack++; 2022 } else if (pktlen > ic->ic_rtsthreshold) { 2023 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 2024 sc->sc_stats.ast_tx_rts++; 2025 } 2026 2027 /* 2028 * Calculate duration. This logically belongs in the 802.11 2029 * layer but it lacks sufficient information to calculate it. 2030 */ 2031 if ((flags & HAL_TXDESC_NOACK) == 0 && 2032 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 2033 u_int16_t dur; 2034 /* 2035 * XXX not right with fragmentation. 2036 */ 2037 dur = ath_hal_computetxtime(ah, rt, IEEE80211_ACK_SIZE, 2038 rix, shortPreamble); 2039 *((u_int16_t*) wh->i_dur) = htole16(dur); 2040 } 2041 2042 /* 2043 * Calculate RTS/CTS rate and duration if needed. 2044 */ 2045 ctsduration = 0; 2046 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 2047 /* 2048 * CTS transmit rate is derived from the transmit rate 2049 * by looking in the h/w rate table. We must also factor 2050 * in whether or not a short preamble is to be used. 2051 */ 2052 cix = rt->info[rix].controlRate; 2053 ctsrate = rt->info[cix].rateCode; 2054 if (shortPreamble) 2055 ctsrate |= rt->info[cix].shortPreamble; 2056 /* 2057 * Compute the transmit duration based on the size 2058 * of an ACK frame. We call into the HAL to do the 2059 * computation since it depends on the characteristics 2060 * of the actual PHY being used. 2061 */ 2062 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 2063 ctsduration += ath_hal_computetxtime(ah, 2064 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 2065 } 2066 /* SIFS + data */ 2067 ctsduration += ath_hal_computetxtime(ah, 2068 rt, pktlen, rix, shortPreamble); 2069 if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 2070 ctsduration += ath_hal_computetxtime(ah, 2071 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 2072 } 2073 } else 2074 ctsrate = 0; 2075 2076 /* 2077 * For now use the antenna on which the last good 2078 * frame was received on. We assume this field is 2079 * initialized to 0 which gives us ``auto'' or the 2080 * ``default'' antenna. 2081 */ 2082 an = (struct ath_node *) ni; 2083 if (an->an_tx_antenna) 2084 antenna = an->an_tx_antenna; 2085 else 2086 antenna = an->an_rx_hist[an->an_rx_hist_next].arh_antenna; 2087 2088 if (ic->ic_rawbpf) 2089 bpf_mtap(ic->ic_rawbpf, m0); 2090 if (sc->sc_drvbpf) { 2091 sc->sc_tx_th.wt_flags = 0; 2092 if (shortPreamble) 2093 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2094 if (iswep) 2095 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2096 sc->sc_tx_th.wt_rate = ni->ni_rates.rs_rates[ni->ni_txrate]; 2097 sc->sc_tx_th.wt_txpower = 60/2; /* XXX */ 2098 sc->sc_tx_th.wt_antenna = antenna; 2099 2100 bpf_mtap2(sc->sc_drvbpf, 2101 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 2102 } 2103 2104 /* 2105 * Formulate first tx descriptor with tx controls. 2106 */ 2107 /* XXX check return value? */ 2108 ath_hal_setuptxdesc(ah, ds 2109 , pktlen /* packet length */ 2110 , hdrlen /* header length */ 2111 , atype /* Atheros packet type */ 2112 , 60 /* txpower XXX */ 2113 , txrate, 1+10 /* series 0 rate/tries */ 2114 , iswep ? sc->sc_ic.ic_wep_txkey : HAL_TXKEYIX_INVALID 2115 , antenna /* antenna mode */ 2116 , flags /* flags */ 2117 , ctsrate /* rts/cts rate */ 2118 , ctsduration /* rts/cts duration */ 2119 ); 2120 #ifdef notyet 2121 ath_hal_setupxtxdesc(ah, ds 2122 , AH_FALSE /* short preamble */ 2123 , 0, 0 /* series 1 rate/tries */ 2124 , 0, 0 /* series 2 rate/tries */ 2125 , 0, 0 /* series 3 rate/tries */ 2126 ); 2127 #endif 2128 /* 2129 * Fillin the remainder of the descriptor info. 2130 */ 2131 for (i = 0; i < bf->bf_nseg; i++, ds++) { 2132 ds->ds_data = bf->bf_segs[i].ds_addr; 2133 if (i == bf->bf_nseg - 1) 2134 ds->ds_link = 0; 2135 else 2136 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 2137 ath_hal_filltxdesc(ah, ds 2138 , bf->bf_segs[i].ds_len /* segment length */ 2139 , i == 0 /* first segment */ 2140 , i == bf->bf_nseg - 1 /* last segment */ 2141 ); 2142 DPRINTF(ATH_DEBUG_XMIT, 2143 ("%s: %d: %08x %08x %08x %08x %08x %08x\n", 2144 __func__, i, ds->ds_link, ds->ds_data, 2145 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1])); 2146 } 2147 2148 /* 2149 * Insert the frame on the outbound list and 2150 * pass it on to the hardware. 2151 */ 2152 ATH_TXQ_LOCK(sc); 2153 TAILQ_INSERT_TAIL(&sc->sc_txq, bf, bf_list); 2154 if (sc->sc_txlink == NULL) { 2155 ath_hal_puttxbuf(ah, sc->sc_txhalq, bf->bf_daddr); 2156 DPRINTF(ATH_DEBUG_XMIT, ("%s: TXDP0 = %p (%p)\n", __func__, 2157 (caddr_t)bf->bf_daddr, bf->bf_desc)); 2158 } else { 2159 *sc->sc_txlink = bf->bf_daddr; 2160 DPRINTF(ATH_DEBUG_XMIT, ("%s: link(%p)=%p (%p)\n", __func__, 2161 sc->sc_txlink, (caddr_t)bf->bf_daddr, bf->bf_desc)); 2162 } 2163 sc->sc_txlink = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 2164 ATH_TXQ_UNLOCK(sc); 2165 2166 ath_hal_txstart(ah, sc->sc_txhalq); 2167 return 0; 2168 } 2169 2170 static void 2171 ath_tx_proc(void *arg, int npending) 2172 { 2173 struct ath_softc *sc = arg; 2174 struct ath_hal *ah = sc->sc_ah; 2175 struct ath_buf *bf; 2176 struct ieee80211com *ic = &sc->sc_ic; 2177 struct ifnet *ifp = &ic->ic_if; 2178 struct ath_desc *ds; 2179 struct ieee80211_node *ni; 2180 struct ath_node *an; 2181 int sr, lr; 2182 HAL_STATUS status; 2183 2184 DPRINTF(ATH_DEBUG_TX_PROC, ("%s: pending %u tx queue %p, link %p\n", 2185 __func__, npending, 2186 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, sc->sc_txhalq), 2187 sc->sc_txlink)); 2188 for (;;) { 2189 ATH_TXQ_LOCK(sc); 2190 bf = TAILQ_FIRST(&sc->sc_txq); 2191 if (bf == NULL) { 2192 sc->sc_txlink = NULL; 2193 ATH_TXQ_UNLOCK(sc); 2194 break; 2195 } 2196 /* only the last descriptor is needed */ 2197 ds = &bf->bf_desc[bf->bf_nseg - 1]; 2198 status = ath_hal_txprocdesc(ah, ds); 2199 #ifdef AR_DEBUG 2200 if (ath_debug & ATH_DEBUG_XMIT_DESC) 2201 ath_printtxbuf(bf, status == HAL_OK); 2202 #endif 2203 if (status == HAL_EINPROGRESS) { 2204 ATH_TXQ_UNLOCK(sc); 2205 break; 2206 } 2207 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2208 ATH_TXQ_UNLOCK(sc); 2209 2210 ni = bf->bf_node; 2211 if (ni != NULL) { 2212 an = (struct ath_node *) ni; 2213 if (ds->ds_txstat.ts_status == 0) { 2214 an->an_tx_ok++; 2215 an->an_tx_antenna = ds->ds_txstat.ts_antenna; 2216 } else { 2217 an->an_tx_err++; 2218 ifp->if_oerrors++; 2219 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 2220 sc->sc_stats.ast_tx_xretries++; 2221 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 2222 sc->sc_stats.ast_tx_fifoerr++; 2223 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 2224 sc->sc_stats.ast_tx_filtered++; 2225 an->an_tx_antenna = 0; /* invalidate */ 2226 } 2227 sr = ds->ds_txstat.ts_shortretry; 2228 lr = ds->ds_txstat.ts_longretry; 2229 sc->sc_stats.ast_tx_shortretry += sr; 2230 sc->sc_stats.ast_tx_longretry += lr; 2231 if (sr + lr) 2232 an->an_tx_retr++; 2233 /* 2234 * Reclaim reference to node. 2235 * 2236 * NB: the node may be reclaimed here if, for example 2237 * this is a DEAUTH message that was sent and the 2238 * node was timed out due to inactivity. 2239 */ 2240 if (ni != ic->ic_bss) 2241 ieee80211_free_node(ic, ni); 2242 } 2243 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2244 BUS_DMASYNC_POSTWRITE); 2245 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2246 m_freem(bf->bf_m); 2247 bf->bf_m = NULL; 2248 bf->bf_node = NULL; 2249 2250 ATH_TXBUF_LOCK(sc); 2251 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2252 ATH_TXBUF_UNLOCK(sc); 2253 } 2254 ifp->if_flags &= ~IFF_OACTIVE; 2255 sc->sc_tx_timer = 0; 2256 2257 ath_start(ifp); 2258 } 2259 2260 /* 2261 * Drain the transmit queue and reclaim resources. 2262 */ 2263 static void 2264 ath_draintxq(struct ath_softc *sc) 2265 { 2266 struct ath_hal *ah = sc->sc_ah; 2267 struct ieee80211com *ic = &sc->sc_ic; 2268 struct ifnet *ifp = &ic->ic_if; 2269 struct ieee80211_node *ni; 2270 struct ath_buf *bf; 2271 2272 /* XXX return value */ 2273 if (!sc->sc_invalid) { 2274 /* don't touch the hardware if marked invalid */ 2275 (void) ath_hal_stoptxdma(ah, sc->sc_txhalq); 2276 DPRINTF(ATH_DEBUG_RESET, 2277 ("%s: tx queue %p, link %p\n", __func__, 2278 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_txhalq), 2279 sc->sc_txlink)); 2280 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 2281 DPRINTF(ATH_DEBUG_RESET, 2282 ("%s: beacon queue %p\n", __func__, 2283 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq))); 2284 } 2285 for (;;) { 2286 ATH_TXQ_LOCK(sc); 2287 bf = TAILQ_FIRST(&sc->sc_txq); 2288 if (bf == NULL) { 2289 sc->sc_txlink = NULL; 2290 ATH_TXQ_UNLOCK(sc); 2291 break; 2292 } 2293 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2294 ATH_TXQ_UNLOCK(sc); 2295 #ifdef AR_DEBUG 2296 if (ath_debug & ATH_DEBUG_RESET) 2297 ath_printtxbuf(bf, 2298 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 2299 #endif /* AR_DEBUG */ 2300 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2301 m_freem(bf->bf_m); 2302 bf->bf_m = NULL; 2303 ni = bf->bf_node; 2304 bf->bf_node = NULL; 2305 if (ni != NULL && ni != ic->ic_bss) { 2306 /* 2307 * Reclaim node reference. 2308 */ 2309 ieee80211_free_node(ic, ni); 2310 } 2311 ATH_TXBUF_LOCK(sc); 2312 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2313 ATH_TXBUF_UNLOCK(sc); 2314 } 2315 ifp->if_flags &= ~IFF_OACTIVE; 2316 sc->sc_tx_timer = 0; 2317 } 2318 2319 /* 2320 * Disable the receive h/w in preparation for a reset. 2321 */ 2322 static void 2323 ath_stoprecv(struct ath_softc *sc) 2324 { 2325 #define PA2DESC(_sc, _pa) \ 2326 ((struct ath_desc *)((caddr_t)(_sc)->sc_desc + \ 2327 ((_pa) - (_sc)->sc_desc_paddr))) 2328 struct ath_hal *ah = sc->sc_ah; 2329 2330 ath_hal_stoppcurecv(ah); /* disable PCU */ 2331 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 2332 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 2333 DELAY(3000); /* long enough for 1 frame */ 2334 #ifdef AR_DEBUG 2335 if (ath_debug & ATH_DEBUG_RESET) { 2336 struct ath_buf *bf; 2337 2338 printf("%s: rx queue %p, link %p\n", __func__, 2339 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 2340 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2341 struct ath_desc *ds = bf->bf_desc; 2342 if (ath_hal_rxprocdesc(ah, ds, bf->bf_daddr, 2343 PA2DESC(sc, ds->ds_link)) == HAL_OK) 2344 ath_printrxbuf(bf, 1); 2345 } 2346 } 2347 #endif 2348 sc->sc_rxlink = NULL; /* just in case */ 2349 #undef PA2DESC 2350 } 2351 2352 /* 2353 * Enable the receive h/w following a reset. 2354 */ 2355 static int 2356 ath_startrecv(struct ath_softc *sc) 2357 { 2358 struct ath_hal *ah = sc->sc_ah; 2359 struct ath_buf *bf; 2360 2361 sc->sc_rxlink = NULL; 2362 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2363 int error = ath_rxbuf_init(sc, bf); 2364 if (error != 0) { 2365 DPRINTF(ATH_DEBUG_RECV, 2366 ("%s: ath_rxbuf_init failed %d\n", 2367 __func__, error)); 2368 return error; 2369 } 2370 } 2371 2372 bf = TAILQ_FIRST(&sc->sc_rxbuf); 2373 ath_hal_putrxbuf(ah, bf->bf_daddr); 2374 ath_hal_rxena(ah); /* enable recv descriptors */ 2375 ath_mode_init(sc); /* set filters, etc. */ 2376 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 2377 return 0; 2378 } 2379 2380 /* 2381 * Set/change channels. If the channel is really being changed, 2382 * it's done by resetting the chip. To accomplish this we must 2383 * first cleanup any pending DMA, then restart stuff after a la 2384 * ath_init. 2385 */ 2386 static int 2387 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 2388 { 2389 struct ath_hal *ah = sc->sc_ah; 2390 struct ieee80211com *ic = &sc->sc_ic; 2391 2392 DPRINTF(ATH_DEBUG_ANY, ("%s: %u (%u MHz) -> %u (%u MHz)\n", __func__, 2393 ieee80211_chan2ieee(ic, ic->ic_ibss_chan), 2394 ic->ic_ibss_chan->ic_freq, 2395 ieee80211_chan2ieee(ic, chan), chan->ic_freq)); 2396 if (chan != ic->ic_ibss_chan) { 2397 HAL_STATUS status; 2398 HAL_CHANNEL hchan; 2399 enum ieee80211_phymode mode; 2400 2401 /* 2402 * To switch channels clear any pending DMA operations; 2403 * wait long enough for the RX fifo to drain, reset the 2404 * hardware at the new frequency, and then re-enable 2405 * the relevant bits of the h/w. 2406 */ 2407 ath_hal_intrset(ah, 0); /* disable interrupts */ 2408 ath_draintxq(sc); /* clear pending tx frames */ 2409 ath_stoprecv(sc); /* turn off frame recv */ 2410 /* 2411 * Convert to a HAL channel description with 2412 * the flags constrained to reflect the current 2413 * operating mode. 2414 */ 2415 hchan.channel = chan->ic_freq; 2416 hchan.channelFlags = ath_chan2flags(ic, chan); 2417 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 2418 if_printf(&ic->ic_if, "ath_chan_set: unable to reset " 2419 "channel %u (%u Mhz)\n", 2420 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 2421 return EIO; 2422 } 2423 /* 2424 * Re-enable rx framework. 2425 */ 2426 if (ath_startrecv(sc) != 0) { 2427 if_printf(&ic->ic_if, 2428 "ath_chan_set: unable to restart recv logic\n"); 2429 return EIO; 2430 } 2431 2432 /* 2433 * Update BPF state. 2434 */ 2435 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 2436 htole16(chan->ic_freq); 2437 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 2438 htole16(chan->ic_flags); 2439 2440 /* 2441 * Change channels and update the h/w rate map 2442 * if we're switching; e.g. 11a to 11b/g. 2443 */ 2444 ic->ic_ibss_chan = chan; 2445 mode = ieee80211_chan2mode(ic, chan); 2446 if (mode != sc->sc_curmode) 2447 ath_setcurmode(sc, mode); 2448 2449 /* 2450 * Re-enable interrupts. 2451 */ 2452 ath_hal_intrset(ah, sc->sc_imask); 2453 } 2454 return 0; 2455 } 2456 2457 static void 2458 ath_next_scan(void *arg) 2459 { 2460 struct ath_softc *sc = arg; 2461 struct ieee80211com *ic = &sc->sc_ic; 2462 struct ifnet *ifp = &ic->ic_if; 2463 2464 if (ic->ic_state == IEEE80211_S_SCAN) 2465 ieee80211_next_scan(ifp); 2466 } 2467 2468 /* 2469 * Periodically recalibrate the PHY to account 2470 * for temperature/environment changes. 2471 */ 2472 static void 2473 ath_calibrate(void *arg) 2474 { 2475 struct ath_softc *sc = arg; 2476 struct ath_hal *ah = sc->sc_ah; 2477 struct ieee80211com *ic = &sc->sc_ic; 2478 struct ieee80211_channel *c; 2479 HAL_CHANNEL hchan; 2480 2481 sc->sc_stats.ast_per_cal++; 2482 2483 /* 2484 * Convert to a HAL channel description with the flags 2485 * constrained to reflect the current operating mode. 2486 */ 2487 c = ic->ic_ibss_chan; 2488 hchan.channel = c->ic_freq; 2489 hchan.channelFlags = ath_chan2flags(ic, c); 2490 2491 DPRINTF(ATH_DEBUG_CALIBRATE, 2492 ("%s: channel %u/%x\n", __func__, c->ic_freq, c->ic_flags)); 2493 2494 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 2495 /* 2496 * Rfgain is out of bounds, reset the chip 2497 * to load new gain values. 2498 */ 2499 sc->sc_stats.ast_per_rfgain++; 2500 ath_reset(sc); 2501 } 2502 if (!ath_hal_calibrate(ah, &hchan)) { 2503 DPRINTF(ATH_DEBUG_ANY, 2504 ("%s: calibration of channel %u failed\n", 2505 __func__, c->ic_freq)); 2506 sc->sc_stats.ast_per_calfail++; 2507 } 2508 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, ath_calibrate, sc); 2509 } 2510 2511 static int 2512 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2513 { 2514 struct ifnet *ifp = &ic->ic_if; 2515 struct ath_softc *sc = ifp->if_softc; 2516 struct ath_hal *ah = sc->sc_ah; 2517 struct ieee80211_node *ni; 2518 int i, error; 2519 const u_int8_t *bssid; 2520 u_int32_t rfilt; 2521 static const HAL_LED_STATE leds[] = { 2522 HAL_LED_INIT, /* IEEE80211_S_INIT */ 2523 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 2524 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 2525 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 2526 HAL_LED_RUN, /* IEEE80211_S_RUN */ 2527 }; 2528 2529 DPRINTF(ATH_DEBUG_ANY, ("%s: %s -> %s\n", __func__, 2530 ieee80211_state_name[ic->ic_state], 2531 ieee80211_state_name[nstate])); 2532 2533 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 2534 2535 if (nstate == IEEE80211_S_INIT) { 2536 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2537 ath_hal_intrset(ah, sc->sc_imask); 2538 callout_stop(&sc->sc_scan_ch); 2539 callout_stop(&sc->sc_cal_ch); 2540 return (*sc->sc_newstate)(ic, nstate, arg); 2541 } 2542 ni = ic->ic_bss; 2543 error = ath_chan_set(sc, ni->ni_chan); 2544 if (error != 0) 2545 goto bad; 2546 rfilt = ath_calcrxfilter(sc); 2547 if (nstate == IEEE80211_S_SCAN) { 2548 callout_reset(&sc->sc_scan_ch, (hz * ath_dwelltime) / 1000, 2549 ath_next_scan, sc); 2550 bssid = ifp->if_broadcastaddr; 2551 } else { 2552 callout_stop(&sc->sc_scan_ch); 2553 bssid = ni->ni_bssid; 2554 } 2555 ath_hal_setrxfilter(ah, rfilt); 2556 DPRINTF(ATH_DEBUG_ANY, ("%s: RX filter 0x%x bssid %s\n", 2557 __func__, rfilt, ether_sprintf(bssid))); 2558 2559 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 2560 ath_hal_setassocid(ah, bssid, ni->ni_associd); 2561 else 2562 ath_hal_setassocid(ah, bssid, 0); 2563 if (ic->ic_flags & IEEE80211_F_WEPON) { 2564 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2565 if (ath_hal_keyisvalid(ah, i)) 2566 ath_hal_keysetmac(ah, i, bssid); 2567 } 2568 2569 if (nstate == IEEE80211_S_RUN) { 2570 DPRINTF(ATH_DEBUG_ANY, ("%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 2571 "capinfo=0x%04x chan=%d\n" 2572 , __func__ 2573 , ic->ic_flags 2574 , ni->ni_intval 2575 , ether_sprintf(ni->ni_bssid) 2576 , ni->ni_capinfo 2577 , ieee80211_chan2ieee(ic, ni->ni_chan))); 2578 2579 /* 2580 * Allocate and setup the beacon frame for AP or adhoc mode. 2581 */ 2582 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2583 ic->ic_opmode == IEEE80211_M_IBSS) { 2584 error = ath_beacon_alloc(sc, ni); 2585 if (error != 0) 2586 goto bad; 2587 } 2588 2589 /* 2590 * Configure the beacon and sleep timers. 2591 */ 2592 ath_beacon_config(sc); 2593 2594 /* start periodic recalibration timer */ 2595 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, 2596 ath_calibrate, sc); 2597 } else { 2598 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2599 ath_hal_intrset(ah, sc->sc_imask); 2600 callout_stop(&sc->sc_cal_ch); /* no calibration */ 2601 } 2602 /* 2603 * Reset the rate control state. 2604 */ 2605 ath_rate_ctl_reset(sc, nstate); 2606 /* 2607 * Invoke the parent method to complete the work. 2608 */ 2609 return (*sc->sc_newstate)(ic, nstate, arg); 2610 bad: 2611 callout_stop(&sc->sc_scan_ch); 2612 callout_stop(&sc->sc_cal_ch); 2613 /* NB: do not invoke the parent */ 2614 return error; 2615 } 2616 2617 /* 2618 * Setup driver-specific state for a newly associated node. 2619 * Note that we're called also on a re-associate, the isnew 2620 * param tells us if this is the first time or not. 2621 */ 2622 static void 2623 ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2624 { 2625 if (isnew) { 2626 struct ath_node *an = (struct ath_node *) ni; 2627 2628 an->an_tx_ok = an->an_tx_err = 2629 an->an_tx_retr = an->an_tx_upper = 0; 2630 /* start with highest negotiated rate */ 2631 /* 2632 * XXX should do otherwise but only when 2633 * the rate control algorithm is better. 2634 */ 2635 KASSERT(ni->ni_rates.rs_nrates > 0, 2636 ("new association w/ no rates!")); 2637 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2638 } 2639 } 2640 2641 static int 2642 ath_getchannels(struct ath_softc *sc, u_int cc, HAL_BOOL outdoor) 2643 { 2644 struct ieee80211com *ic = &sc->sc_ic; 2645 struct ifnet *ifp = &ic->ic_if; 2646 struct ath_hal *ah = sc->sc_ah; 2647 HAL_CHANNEL *chans; 2648 int i, ix, nchan; 2649 2650 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 2651 M_TEMP, M_NOWAIT); 2652 if (chans == NULL) { 2653 if_printf(ifp, "unable to allocate channel table\n"); 2654 return ENOMEM; 2655 } 2656 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 2657 cc, HAL_MODE_ALL, outdoor)) { 2658 if_printf(ifp, "unable to collect channel list from hal\n"); 2659 free(chans, M_TEMP); 2660 return EINVAL; 2661 } 2662 2663 /* 2664 * Convert HAL channels to ieee80211 ones and insert 2665 * them in the table according to their channel number. 2666 */ 2667 for (i = 0; i < nchan; i++) { 2668 HAL_CHANNEL *c = &chans[i]; 2669 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 2670 if (ix > IEEE80211_CHAN_MAX) { 2671 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 2672 ix, c->channel, c->channelFlags); 2673 continue; 2674 } 2675 /* NB: flags are known to be compatible */ 2676 if (ic->ic_channels[ix].ic_freq == 0) { 2677 ic->ic_channels[ix].ic_freq = c->channel; 2678 ic->ic_channels[ix].ic_flags = c->channelFlags; 2679 } else { 2680 /* channels overlap; e.g. 11g and 11b */ 2681 ic->ic_channels[ix].ic_flags |= c->channelFlags; 2682 } 2683 } 2684 free(chans, M_TEMP); 2685 return 0; 2686 } 2687 2688 static int 2689 ath_rate_setup(struct ath_softc *sc, u_int mode) 2690 { 2691 struct ath_hal *ah = sc->sc_ah; 2692 struct ieee80211com *ic = &sc->sc_ic; 2693 const HAL_RATE_TABLE *rt; 2694 struct ieee80211_rateset *rs; 2695 int i, maxrates; 2696 2697 switch (mode) { 2698 case IEEE80211_MODE_11A: 2699 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 2700 break; 2701 case IEEE80211_MODE_11B: 2702 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 2703 break; 2704 case IEEE80211_MODE_11G: 2705 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 2706 break; 2707 case IEEE80211_MODE_TURBO: 2708 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 2709 break; 2710 default: 2711 DPRINTF(ATH_DEBUG_ANY, 2712 ("%s: invalid mode %u\n", __func__, mode)); 2713 return 0; 2714 } 2715 rt = sc->sc_rates[mode]; 2716 if (rt == NULL) 2717 return 0; 2718 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 2719 DPRINTF(ATH_DEBUG_ANY, 2720 ("%s: rate table too small (%u > %u)\n", 2721 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE)); 2722 maxrates = IEEE80211_RATE_MAXSIZE; 2723 } else 2724 maxrates = rt->rateCount; 2725 rs = &ic->ic_sup_rates[mode]; 2726 for (i = 0; i < maxrates; i++) 2727 rs->rs_rates[i] = rt->info[i].dot11Rate; 2728 rs->rs_nrates = maxrates; 2729 return 1; 2730 } 2731 2732 static void 2733 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 2734 { 2735 const HAL_RATE_TABLE *rt; 2736 int i; 2737 2738 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 2739 rt = sc->sc_rates[mode]; 2740 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 2741 for (i = 0; i < rt->rateCount; i++) 2742 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 2743 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 2744 for (i = 0; i < 32; i++) 2745 sc->sc_hwmap[i] = rt->info[rt->rateCodeToIndex[i]].dot11Rate; 2746 sc->sc_currates = rt; 2747 sc->sc_curmode = mode; 2748 } 2749 2750 /* 2751 * Reset the rate control state for each 802.11 state transition. 2752 */ 2753 static void 2754 ath_rate_ctl_reset(struct ath_softc *sc, enum ieee80211_state state) 2755 { 2756 struct ieee80211com *ic = &sc->sc_ic; 2757 struct ieee80211_node *ni; 2758 struct ath_node *an; 2759 2760 if (ic->ic_opmode != IEEE80211_M_STA) { 2761 /* 2762 * When operating as a station the node table holds 2763 * the AP's that were discovered during scanning. 2764 * For any other operating mode we want to reset the 2765 * tx rate state of each node. 2766 */ 2767 TAILQ_FOREACH(ni, &ic->ic_node, ni_list) { 2768 ni->ni_txrate = 0; /* use lowest rate */ 2769 an = (struct ath_node *) ni; 2770 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 2771 an->an_tx_upper = 0; 2772 } 2773 } 2774 /* 2775 * Reset local xmit state; this is really only meaningful 2776 * when operating in station or adhoc mode. 2777 */ 2778 ni = ic->ic_bss; 2779 an = (struct ath_node *) ni; 2780 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = an->an_tx_upper = 0; 2781 if (state == IEEE80211_S_RUN) { 2782 /* start with highest negotiated rate */ 2783 KASSERT(ni->ni_rates.rs_nrates > 0, 2784 ("transition to RUN state w/ no rates!")); 2785 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2786 } else { 2787 /* use lowest rate */ 2788 ni->ni_txrate = 0; 2789 } 2790 } 2791 2792 /* 2793 * Examine and potentially adjust the transmit rate. 2794 */ 2795 static void 2796 ath_rate_ctl(void *arg, struct ieee80211_node *ni) 2797 { 2798 struct ath_softc *sc = arg; 2799 struct ath_node *an = (struct ath_node *) ni; 2800 struct ieee80211_rateset *rs = &ni->ni_rates; 2801 int mod = 0, orate, enough; 2802 2803 /* 2804 * Rate control 2805 * XXX: very primitive version. 2806 */ 2807 sc->sc_stats.ast_rate_calls++; 2808 2809 enough = (an->an_tx_ok + an->an_tx_err >= 10); 2810 2811 /* no packet reached -> down */ 2812 if (an->an_tx_err > 0 && an->an_tx_ok == 0) 2813 mod = -1; 2814 2815 /* all packets needs retry in average -> down */ 2816 if (enough && an->an_tx_ok < an->an_tx_retr) 2817 mod = -1; 2818 2819 /* no error and less than 10% of packets needs retry -> up */ 2820 if (enough && an->an_tx_err == 0 && an->an_tx_ok > an->an_tx_retr * 10) 2821 mod = 1; 2822 2823 orate = ni->ni_txrate; 2824 switch (mod) { 2825 case 0: 2826 if (enough && an->an_tx_upper > 0) 2827 an->an_tx_upper--; 2828 break; 2829 case -1: 2830 if (ni->ni_txrate > 0) { 2831 ni->ni_txrate--; 2832 sc->sc_stats.ast_rate_drop++; 2833 } 2834 an->an_tx_upper = 0; 2835 break; 2836 case 1: 2837 if (++an->an_tx_upper < 2) 2838 break; 2839 an->an_tx_upper = 0; 2840 if (ni->ni_txrate + 1 < rs->rs_nrates) { 2841 ni->ni_txrate++; 2842 sc->sc_stats.ast_rate_raise++; 2843 } 2844 break; 2845 } 2846 2847 if (ni->ni_txrate != orate) { 2848 DPRINTF(ATH_DEBUG_RATE, 2849 ("%s: %dM -> %dM (%d ok, %d err, %d retr)\n", 2850 __func__, 2851 (rs->rs_rates[orate] & IEEE80211_RATE_VAL) / 2, 2852 (rs->rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL) / 2, 2853 an->an_tx_ok, an->an_tx_err, an->an_tx_retr)); 2854 } 2855 if (ni->ni_txrate != orate || enough) 2856 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 0; 2857 } 2858 2859 #ifdef AR_DEBUG 2860 static int 2861 sysctl_hw_ath_dump(SYSCTL_HANDLER_ARGS) 2862 { 2863 char dmode[64]; 2864 int error; 2865 2866 strncpy(dmode, "", sizeof(dmode) - 1); 2867 dmode[sizeof(dmode) - 1] = '\0'; 2868 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2869 2870 if (error == 0 && req->newptr != NULL) { 2871 struct ifnet *ifp; 2872 struct ath_softc *sc; 2873 2874 ifp = ifunit("ath0"); /* XXX */ 2875 if (!ifp) 2876 return EINVAL; 2877 sc = ifp->if_softc; 2878 if (strcmp(dmode, "hal") == 0) 2879 ath_hal_dumpstate(sc->sc_ah); 2880 else 2881 return EINVAL; 2882 } 2883 return error; 2884 } 2885 SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2886 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state"); 2887 2888 static void 2889 ath_printrxbuf(struct ath_buf *bf, int done) 2890 { 2891 struct ath_desc *ds; 2892 int i; 2893 2894 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2895 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 2896 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2897 ds->ds_link, ds->ds_data, 2898 ds->ds_ctl0, ds->ds_ctl1, 2899 ds->ds_hw[0], ds->ds_hw[1], 2900 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 2901 } 2902 } 2903 2904 static void 2905 ath_printtxbuf(struct ath_buf *bf, int done) 2906 { 2907 struct ath_desc *ds; 2908 int i; 2909 2910 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2911 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 2912 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2913 ds->ds_link, ds->ds_data, 2914 ds->ds_ctl0, ds->ds_ctl1, 2915 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 2916 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 2917 } 2918 } 2919 #endif /* AR_DEBUG */ 2920