1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Driver for the Atheros Wireless LAN controller. 37 * 38 * This software is derived from work of Atsushi Onoe; his contribution 39 * is greatly appreciated. 40 */ 41 42 #include "opt_inet.h" 43 #include "opt_ath.h" 44 /* 45 * This is needed for register operations which are performed 46 * by the driver - eg, calls to ath_hal_gettsf32(). 47 * 48 * It's also required for any AH_DEBUG checks in here, eg the 49 * module dependencies. 50 */ 51 #include "opt_ah.h" 52 #include "opt_wlan.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sysctl.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/kernel.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 #include <sys/errno.h> 65 #include <sys/callout.h> 66 #include <sys/bus.h> 67 #include <sys/endian.h> 68 #include <sys/kthread.h> 69 #include <sys/taskqueue.h> 70 #include <sys/priv.h> 71 #include <sys/module.h> 72 #include <sys/ktr.h> 73 #include <sys/smp.h> /* for mp_ncpus */ 74 75 #include <machine/bus.h> 76 77 #include <net/if.h> 78 #include <net/if_var.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 #include <net/if_arp.h> 83 #include <net/ethernet.h> 84 #include <net/if_llc.h> 85 86 #include <net80211/ieee80211_var.h> 87 #include <net80211/ieee80211_regdomain.h> 88 #ifdef IEEE80211_SUPPORT_SUPERG 89 #include <net80211/ieee80211_superg.h> 90 #endif 91 #ifdef IEEE80211_SUPPORT_TDMA 92 #include <net80211/ieee80211_tdma.h> 93 #endif 94 95 #include <net/bpf.h> 96 97 #ifdef INET 98 #include <netinet/in.h> 99 #include <netinet/if_ether.h> 100 #endif 101 102 #include <dev/ath/if_athvar.h> 103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 104 #include <dev/ath/ath_hal/ah_diagcodes.h> 105 106 #include <dev/ath/if_ath_debug.h> 107 #include <dev/ath/if_ath_misc.h> 108 #include <dev/ath/if_ath_tsf.h> 109 #include <dev/ath/if_ath_tx.h> 110 #include <dev/ath/if_ath_sysctl.h> 111 #include <dev/ath/if_ath_led.h> 112 #include <dev/ath/if_ath_keycache.h> 113 #include <dev/ath/if_ath_rx.h> 114 #include <dev/ath/if_ath_rx_edma.h> 115 #include <dev/ath/if_ath_tx_edma.h> 116 #include <dev/ath/if_ath_beacon.h> 117 #include <dev/ath/if_ath_btcoex.h> 118 #include <dev/ath/if_ath_btcoex_mci.h> 119 #include <dev/ath/if_ath_spectral.h> 120 #include <dev/ath/if_ath_lna_div.h> 121 #include <dev/ath/if_athdfs.h> 122 #include <dev/ath/if_ath_ioctl.h> 123 #include <dev/ath/if_ath_descdma.h> 124 125 #ifdef ATH_TX99_DIAG 126 #include <dev/ath/ath_tx99/ath_tx99.h> 127 #endif 128 129 #ifdef ATH_DEBUG_ALQ 130 #include <dev/ath/if_ath_alq.h> 131 #endif 132 133 /* 134 * Only enable this if you're working on PS-POLL support. 135 */ 136 #define ATH_SW_PSQ 137 138 /* 139 * ATH_BCBUF determines the number of vap's that can transmit 140 * beacons and also (currently) the number of vap's that can 141 * have unique mac addresses/bssid. When staggering beacons 142 * 4 is probably a good max as otherwise the beacons become 143 * very closely spaced and there is limited time for cab q traffic 144 * to go out. You can burst beacons instead but that is not good 145 * for stations in power save and at some point you really want 146 * another radio (and channel). 147 * 148 * The limit on the number of mac addresses is tied to our use of 149 * the U/L bit and tracking addresses in a byte; it would be 150 * worthwhile to allow more for applications like proxy sta. 151 */ 152 CTASSERT(ATH_BCBUF <= 8); 153 154 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 155 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 156 const uint8_t [IEEE80211_ADDR_LEN], 157 const uint8_t [IEEE80211_ADDR_LEN]); 158 static void ath_vap_delete(struct ieee80211vap *); 159 static int ath_init(struct ath_softc *); 160 static void ath_stop(struct ath_softc *); 161 static int ath_reset_vap(struct ieee80211vap *, u_long); 162 static int ath_transmit(struct ieee80211com *, struct mbuf *); 163 static int ath_media_change(struct ifnet *); 164 static void ath_watchdog(void *); 165 static void ath_parent(struct ieee80211com *); 166 static void ath_fatal_proc(void *, int); 167 static void ath_bmiss_vap(struct ieee80211vap *); 168 static void ath_bmiss_proc(void *, int); 169 static void ath_key_update_begin(struct ieee80211vap *); 170 static void ath_key_update_end(struct ieee80211vap *); 171 static void ath_update_mcast_hw(struct ath_softc *); 172 static void ath_update_mcast(struct ieee80211com *); 173 static void ath_update_promisc(struct ieee80211com *); 174 static void ath_updateslot(struct ieee80211com *); 175 static void ath_bstuck_proc(void *, int); 176 static void ath_reset_proc(void *, int); 177 static int ath_desc_alloc(struct ath_softc *); 178 static void ath_desc_free(struct ath_softc *); 179 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 180 const uint8_t [IEEE80211_ADDR_LEN]); 181 static void ath_node_cleanup(struct ieee80211_node *); 182 static void ath_node_free(struct ieee80211_node *); 183 static void ath_node_getsignal(const struct ieee80211_node *, 184 int8_t *, int8_t *); 185 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 186 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 187 static int ath_tx_setup(struct ath_softc *, int, int); 188 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 189 static void ath_tx_cleanup(struct ath_softc *); 190 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, 191 int dosched); 192 static void ath_tx_proc_q0(void *, int); 193 static void ath_tx_proc_q0123(void *, int); 194 static void ath_tx_proc(void *, int); 195 static void ath_txq_sched_tasklet(void *, int); 196 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 197 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 198 static void ath_scan_start(struct ieee80211com *); 199 static void ath_scan_end(struct ieee80211com *); 200 static void ath_set_channel(struct ieee80211com *); 201 #ifdef ATH_ENABLE_11N 202 static void ath_update_chw(struct ieee80211com *); 203 #endif /* ATH_ENABLE_11N */ 204 static int ath_set_quiet_ie(struct ieee80211_node *, uint8_t *); 205 static void ath_calibrate(void *); 206 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 207 static void ath_setup_stationkey(struct ieee80211_node *); 208 static void ath_newassoc(struct ieee80211_node *, int); 209 static int ath_setregdomain(struct ieee80211com *, 210 struct ieee80211_regdomain *, int, 211 struct ieee80211_channel []); 212 static void ath_getradiocaps(struct ieee80211com *, int, int *, 213 struct ieee80211_channel []); 214 static int ath_getchannels(struct ath_softc *); 215 216 static int ath_rate_setup(struct ath_softc *, u_int mode); 217 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 218 219 static void ath_announce(struct ath_softc *); 220 221 static void ath_dfs_tasklet(void *, int); 222 static void ath_node_powersave(struct ieee80211_node *, int); 223 static int ath_node_set_tim(struct ieee80211_node *, int); 224 static void ath_node_recv_pspoll(struct ieee80211_node *, struct mbuf *); 225 226 #ifdef IEEE80211_SUPPORT_TDMA 227 #include <dev/ath/if_ath_tdma.h> 228 #endif 229 230 SYSCTL_DECL(_hw_ath); 231 232 /* XXX validate sysctl values */ 233 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 234 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 235 0, "long chip calibration interval (secs)"); 236 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 237 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 238 0, "short chip calibration interval (msecs)"); 239 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 240 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 241 0, "reset chip calibration results (secs)"); 242 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */ 243 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval, 244 0, "ANI calibration (msecs)"); 245 246 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 247 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &ath_rxbuf, 248 0, "rx buffers allocated"); 249 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 250 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RWTUN, &ath_txbuf, 251 0, "tx buffers allocated"); 252 int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */ 253 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RWTUN, &ath_txbuf_mgmt, 254 0, "tx (mgmt) buffers allocated"); 255 256 int ath_bstuck_threshold = 4; /* max missed beacons */ 257 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 258 0, "max missed beacon xmits before chip reset"); 259 260 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 261 262 void 263 ath_legacy_attach_comp_func(struct ath_softc *sc) 264 { 265 266 /* 267 * Special case certain configurations. Note the 268 * CAB queue is handled by these specially so don't 269 * include them when checking the txq setup mask. 270 */ 271 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 272 case 0x01: 273 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 274 break; 275 case 0x0f: 276 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 277 break; 278 default: 279 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 280 break; 281 } 282 } 283 284 /* 285 * Set the target power mode. 286 * 287 * If this is called during a point in time where 288 * the hardware is being programmed elsewhere, it will 289 * simply store it away and update it when all current 290 * uses of the hardware are completed. 291 * 292 * If the chip is going into network sleep or power off, then 293 * we will wait until all uses of the chip are done before 294 * going into network sleep or power off. 295 * 296 * If the chip is being programmed full-awake, then immediately 297 * program it full-awake so we can actually stay awake rather than 298 * the chip potentially going to sleep underneath us. 299 */ 300 void 301 _ath_power_setpower(struct ath_softc *sc, int power_state, int selfgen, 302 const char *file, int line) 303 { 304 ATH_LOCK_ASSERT(sc); 305 306 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d, target=%d, cur=%d\n", 307 __func__, 308 file, 309 line, 310 power_state, 311 sc->sc_powersave_refcnt, 312 sc->sc_target_powerstate, 313 sc->sc_cur_powerstate); 314 315 sc->sc_target_powerstate = power_state; 316 317 /* 318 * Don't program the chip into network sleep if the chip 319 * is being programmed elsewhere. 320 * 321 * However, if the chip is being programmed /awake/, force 322 * the chip awake so we stay awake. 323 */ 324 if ((sc->sc_powersave_refcnt == 0 || power_state == HAL_PM_AWAKE) && 325 power_state != sc->sc_cur_powerstate) { 326 sc->sc_cur_powerstate = power_state; 327 ath_hal_setpower(sc->sc_ah, power_state); 328 329 /* 330 * If the NIC is force-awake, then set the 331 * self-gen frame state appropriately. 332 * 333 * If the nic is in network sleep or full-sleep, 334 * we let the above call leave the self-gen 335 * state as "sleep". 336 */ 337 if (selfgen && 338 sc->sc_cur_powerstate == HAL_PM_AWAKE && 339 sc->sc_target_selfgen_state != HAL_PM_AWAKE) { 340 ath_hal_setselfgenpower(sc->sc_ah, 341 sc->sc_target_selfgen_state); 342 } 343 } 344 } 345 346 /* 347 * Set the current self-generated frames state. 348 * 349 * This is separate from the target power mode. The chip may be 350 * awake but the desired state is "sleep", so frames sent to the 351 * destination has PWRMGT=1 in the 802.11 header. The NIC also 352 * needs to know to set PWRMGT=1 in self-generated frames. 353 */ 354 void 355 _ath_power_set_selfgen(struct ath_softc *sc, int power_state, const char *file, int line) 356 { 357 358 ATH_LOCK_ASSERT(sc); 359 360 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n", 361 __func__, 362 file, 363 line, 364 power_state, 365 sc->sc_target_selfgen_state); 366 367 sc->sc_target_selfgen_state = power_state; 368 369 /* 370 * If the NIC is force-awake, then set the power state. 371 * Network-state and full-sleep will already transition it to 372 * mark self-gen frames as sleeping - and we can't 373 * guarantee the NIC is awake to program the self-gen frame 374 * setting anyway. 375 */ 376 if (sc->sc_cur_powerstate == HAL_PM_AWAKE) { 377 ath_hal_setselfgenpower(sc->sc_ah, power_state); 378 } 379 } 380 381 /* 382 * Set the hardware power mode and take a reference. 383 * 384 * This doesn't update the target power mode in the driver; 385 * it just updates the hardware power state. 386 * 387 * XXX it should only ever force the hardware awake; it should 388 * never be called to set it asleep. 389 */ 390 void 391 _ath_power_set_power_state(struct ath_softc *sc, int power_state, const char *file, int line) 392 { 393 ATH_LOCK_ASSERT(sc); 394 395 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n", 396 __func__, 397 file, 398 line, 399 power_state, 400 sc->sc_powersave_refcnt); 401 402 sc->sc_powersave_refcnt++; 403 404 /* 405 * Only do the power state change if we're not programming 406 * it elsewhere. 407 */ 408 if (power_state != sc->sc_cur_powerstate) { 409 ath_hal_setpower(sc->sc_ah, power_state); 410 sc->sc_cur_powerstate = power_state; 411 /* 412 * Adjust the self-gen powerstate if appropriate. 413 */ 414 if (sc->sc_cur_powerstate == HAL_PM_AWAKE && 415 sc->sc_target_selfgen_state != HAL_PM_AWAKE) { 416 ath_hal_setselfgenpower(sc->sc_ah, 417 sc->sc_target_selfgen_state); 418 } 419 } 420 } 421 422 /* 423 * Restore the power save mode to what it once was. 424 * 425 * This will decrement the reference counter and once it hits 426 * zero, it'll restore the powersave state. 427 */ 428 void 429 _ath_power_restore_power_state(struct ath_softc *sc, const char *file, int line) 430 { 431 432 ATH_LOCK_ASSERT(sc); 433 434 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) refcnt=%d, target state=%d\n", 435 __func__, 436 file, 437 line, 438 sc->sc_powersave_refcnt, 439 sc->sc_target_powerstate); 440 441 if (sc->sc_powersave_refcnt == 0) 442 device_printf(sc->sc_dev, "%s: refcnt=0?\n", __func__); 443 else 444 sc->sc_powersave_refcnt--; 445 446 if (sc->sc_powersave_refcnt == 0 && 447 sc->sc_target_powerstate != sc->sc_cur_powerstate) { 448 sc->sc_cur_powerstate = sc->sc_target_powerstate; 449 ath_hal_setpower(sc->sc_ah, sc->sc_target_powerstate); 450 } 451 452 /* 453 * Adjust the self-gen powerstate if appropriate. 454 */ 455 if (sc->sc_cur_powerstate == HAL_PM_AWAKE && 456 sc->sc_target_selfgen_state != HAL_PM_AWAKE) { 457 ath_hal_setselfgenpower(sc->sc_ah, 458 sc->sc_target_selfgen_state); 459 } 460 461 } 462 463 /* 464 * Configure the initial HAL configuration values based on bus 465 * specific parameters. 466 * 467 * Some PCI IDs and other information may need tweaking. 468 * 469 * XXX TODO: ath9k and the Atheros HAL only program comm2g_switch_enable 470 * if BT antenna diversity isn't enabled. 471 * 472 * So, let's also figure out how to enable BT diversity for AR9485. 473 */ 474 static void 475 ath_setup_hal_config(struct ath_softc *sc, HAL_OPS_CONFIG *ah_config) 476 { 477 /* XXX TODO: only for PCI devices? */ 478 479 if (sc->sc_pci_devinfo & (ATH_PCI_CUS198 | ATH_PCI_CUS230)) { 480 ah_config->ath_hal_ext_lna_ctl_gpio = 0x200; /* bit 9 */ 481 ah_config->ath_hal_ext_atten_margin_cfg = AH_TRUE; 482 ah_config->ath_hal_min_gainidx = AH_TRUE; 483 ah_config->ath_hal_ant_ctrl_comm2g_switch_enable = 0x000bbb88; 484 /* XXX low_rssi_thresh */ 485 /* XXX fast_div_bias */ 486 device_printf(sc->sc_dev, "configuring for %s\n", 487 (sc->sc_pci_devinfo & ATH_PCI_CUS198) ? 488 "CUS198" : "CUS230"); 489 } 490 491 if (sc->sc_pci_devinfo & ATH_PCI_CUS217) 492 device_printf(sc->sc_dev, "CUS217 card detected\n"); 493 494 if (sc->sc_pci_devinfo & ATH_PCI_CUS252) 495 device_printf(sc->sc_dev, "CUS252 card detected\n"); 496 497 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_1ANT) 498 device_printf(sc->sc_dev, "WB335 1-ANT card detected\n"); 499 500 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_2ANT) 501 device_printf(sc->sc_dev, "WB335 2-ANT card detected\n"); 502 503 if (sc->sc_pci_devinfo & ATH_PCI_BT_ANT_DIV) 504 device_printf(sc->sc_dev, 505 "Bluetooth Antenna Diversity card detected\n"); 506 507 if (sc->sc_pci_devinfo & ATH_PCI_KILLER) 508 device_printf(sc->sc_dev, "Killer Wireless card detected\n"); 509 510 #if 0 511 /* 512 * Some WB335 cards do not support antenna diversity. Since 513 * we use a hardcoded value for AR9565 instead of using the 514 * EEPROM/OTP data, remove the combining feature from 515 * the HW capabilities bitmap. 516 */ 517 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 518 if (!(sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV)) 519 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 520 } 521 522 if (sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV) { 523 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 524 device_printf(sc->sc_dev, "Set BT/WLAN RX diversity capability\n"); 525 } 526 #endif 527 528 if (sc->sc_pci_devinfo & ATH_PCI_D3_L1_WAR) { 529 ah_config->ath_hal_pcie_waen = 0x0040473b; 530 device_printf(sc->sc_dev, "Enable WAR for ASPM D3/L1\n"); 531 } 532 533 #if 0 534 if (sc->sc_pci_devinfo & ATH9K_PCI_NO_PLL_PWRSAVE) { 535 ah->config.no_pll_pwrsave = true; 536 device_printf(sc->sc_dev, "Disable PLL PowerSave\n"); 537 } 538 #endif 539 540 } 541 542 /* 543 * Attempt to fetch the MAC address from the kernel environment. 544 * 545 * Returns 0, macaddr in macaddr if successful; -1 otherwise. 546 */ 547 static int 548 ath_fetch_mac_kenv(struct ath_softc *sc, uint8_t *macaddr) 549 { 550 char devid_str[32]; 551 int local_mac = 0; 552 char *local_macstr; 553 554 /* 555 * Fetch from the kenv rather than using hints. 556 * 557 * Hints would be nice but the transition to dynamic 558 * hints/kenv doesn't happen early enough for this 559 * to work reliably (eg on anything embedded.) 560 */ 561 snprintf(devid_str, 32, "hint.%s.%d.macaddr", 562 device_get_name(sc->sc_dev), 563 device_get_unit(sc->sc_dev)); 564 565 if ((local_macstr = kern_getenv(devid_str)) != NULL) { 566 uint32_t tmpmac[ETHER_ADDR_LEN]; 567 int count; 568 int i; 569 570 /* Have a MAC address; should use it */ 571 device_printf(sc->sc_dev, 572 "Overriding MAC address from environment: '%s'\n", 573 local_macstr); 574 575 /* Extract out the MAC address */ 576 count = sscanf(local_macstr, "%x%*c%x%*c%x%*c%x%*c%x%*c%x", 577 &tmpmac[0], &tmpmac[1], 578 &tmpmac[2], &tmpmac[3], 579 &tmpmac[4], &tmpmac[5]); 580 if (count == 6) { 581 /* Valid! */ 582 local_mac = 1; 583 for (i = 0; i < ETHER_ADDR_LEN; i++) 584 macaddr[i] = tmpmac[i]; 585 } 586 /* Done! */ 587 freeenv(local_macstr); 588 local_macstr = NULL; 589 } 590 591 if (local_mac) 592 return (0); 593 return (-1); 594 } 595 596 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20) 597 #define HAL_MODE_HT40 \ 598 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \ 599 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS) 600 int 601 ath_attach(u_int16_t devid, struct ath_softc *sc) 602 { 603 struct ieee80211com *ic = &sc->sc_ic; 604 struct ath_hal *ah = NULL; 605 HAL_STATUS status; 606 int error = 0, i; 607 u_int wmodes; 608 int rx_chainmask, tx_chainmask; 609 HAL_OPS_CONFIG ah_config; 610 611 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 612 613 ic->ic_softc = sc; 614 ic->ic_name = device_get_nameunit(sc->sc_dev); 615 616 /* 617 * Configure the initial configuration data. 618 * 619 * This is stuff that may be needed early during attach 620 * rather than done via configuration calls later. 621 */ 622 bzero(&ah_config, sizeof(ah_config)); 623 ath_setup_hal_config(sc, &ah_config); 624 625 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, 626 sc->sc_eepromdata, &ah_config, &status); 627 if (ah == NULL) { 628 device_printf(sc->sc_dev, 629 "unable to attach hardware; HAL status %u\n", status); 630 error = ENXIO; 631 goto bad; 632 } 633 sc->sc_ah = ah; 634 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 635 #ifdef ATH_DEBUG 636 sc->sc_debug = ath_debug; 637 #endif 638 639 /* 640 * Force the chip awake during setup, just to keep 641 * the HAL/driver power tracking happy. 642 * 643 * There are some methods (eg ath_hal_setmac()) 644 * that poke the hardware. 645 */ 646 ATH_LOCK(sc); 647 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 648 ATH_UNLOCK(sc); 649 650 /* 651 * Setup the DMA/EDMA functions based on the current 652 * hardware support. 653 * 654 * This is required before the descriptors are allocated. 655 */ 656 if (ath_hal_hasedma(sc->sc_ah)) { 657 sc->sc_isedma = 1; 658 ath_recv_setup_edma(sc); 659 ath_xmit_setup_edma(sc); 660 } else { 661 ath_recv_setup_legacy(sc); 662 ath_xmit_setup_legacy(sc); 663 } 664 665 if (ath_hal_hasmybeacon(sc->sc_ah)) { 666 sc->sc_do_mybeacon = 1; 667 } 668 669 /* 670 * Check if the MAC has multi-rate retry support. 671 * We do this by trying to setup a fake extended 672 * descriptor. MAC's that don't have support will 673 * return false w/o doing anything. MAC's that do 674 * support it will return true w/o doing anything. 675 */ 676 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 677 678 /* 679 * Check if the device has hardware counters for PHY 680 * errors. If so we need to enable the MIB interrupt 681 * so we can act on stat triggers. 682 */ 683 if (ath_hal_hwphycounters(ah)) 684 sc->sc_needmib = 1; 685 686 /* 687 * Get the hardware key cache size. 688 */ 689 sc->sc_keymax = ath_hal_keycachesize(ah); 690 if (sc->sc_keymax > ATH_KEYMAX) { 691 device_printf(sc->sc_dev, 692 "Warning, using only %u of %u key cache slots\n", 693 ATH_KEYMAX, sc->sc_keymax); 694 sc->sc_keymax = ATH_KEYMAX; 695 } 696 /* 697 * Reset the key cache since some parts do not 698 * reset the contents on initial power up. 699 */ 700 for (i = 0; i < sc->sc_keymax; i++) 701 ath_hal_keyreset(ah, i); 702 703 /* 704 * Collect the default channel list. 705 */ 706 error = ath_getchannels(sc); 707 if (error != 0) 708 goto bad; 709 710 /* 711 * Setup rate tables for all potential media types. 712 */ 713 ath_rate_setup(sc, IEEE80211_MODE_11A); 714 ath_rate_setup(sc, IEEE80211_MODE_11B); 715 ath_rate_setup(sc, IEEE80211_MODE_11G); 716 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 717 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 718 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 719 ath_rate_setup(sc, IEEE80211_MODE_11NA); 720 ath_rate_setup(sc, IEEE80211_MODE_11NG); 721 ath_rate_setup(sc, IEEE80211_MODE_HALF); 722 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 723 724 /* NB: setup here so ath_rate_update is happy */ 725 ath_setcurmode(sc, IEEE80211_MODE_11A); 726 727 /* 728 * Allocate TX descriptors and populate the lists. 729 */ 730 error = ath_desc_alloc(sc); 731 if (error != 0) { 732 device_printf(sc->sc_dev, 733 "failed to allocate TX descriptors: %d\n", error); 734 goto bad; 735 } 736 error = ath_txdma_setup(sc); 737 if (error != 0) { 738 device_printf(sc->sc_dev, 739 "failed to allocate TX descriptors: %d\n", error); 740 goto bad; 741 } 742 743 /* 744 * Allocate RX descriptors and populate the lists. 745 */ 746 error = ath_rxdma_setup(sc); 747 if (error != 0) { 748 device_printf(sc->sc_dev, 749 "failed to allocate RX descriptors: %d\n", error); 750 goto bad; 751 } 752 753 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 754 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 755 756 ATH_TXBUF_LOCK_INIT(sc); 757 758 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 759 taskqueue_thread_enqueue, &sc->sc_tq); 760 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 761 device_get_nameunit(sc->sc_dev)); 762 763 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc); 764 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 765 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 766 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc); 767 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc); 768 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 769 770 /* 771 * Allocate hardware transmit queues: one queue for 772 * beacon frames and one data queue for each QoS 773 * priority. Note that the hal handles resetting 774 * these queues at the needed time. 775 * 776 * XXX PS-Poll 777 */ 778 sc->sc_bhalq = ath_beaconq_setup(sc); 779 if (sc->sc_bhalq == (u_int) -1) { 780 device_printf(sc->sc_dev, 781 "unable to setup a beacon xmit queue!\n"); 782 error = EIO; 783 goto bad2; 784 } 785 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 786 if (sc->sc_cabq == NULL) { 787 device_printf(sc->sc_dev, "unable to setup CAB xmit queue!\n"); 788 error = EIO; 789 goto bad2; 790 } 791 /* NB: insure BK queue is the lowest priority h/w queue */ 792 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 793 device_printf(sc->sc_dev, 794 "unable to setup xmit queue for %s traffic!\n", 795 ieee80211_wme_acnames[WME_AC_BK]); 796 error = EIO; 797 goto bad2; 798 } 799 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 800 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 801 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 802 /* 803 * Not enough hardware tx queues to properly do WME; 804 * just punt and assign them all to the same h/w queue. 805 * We could do a better job of this if, for example, 806 * we allocate queues when we switch from station to 807 * AP mode. 808 */ 809 if (sc->sc_ac2q[WME_AC_VI] != NULL) 810 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 811 if (sc->sc_ac2q[WME_AC_BE] != NULL) 812 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 813 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 814 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 815 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 816 } 817 818 /* 819 * Attach the TX completion function. 820 * 821 * The non-EDMA chips may have some special case optimisations; 822 * this method gives everyone a chance to attach cleanly. 823 */ 824 sc->sc_tx.xmit_attach_comp_func(sc); 825 826 /* 827 * Setup rate control. Some rate control modules 828 * call back to change the anntena state so expose 829 * the necessary entry points. 830 * XXX maybe belongs in struct ath_ratectrl? 831 */ 832 sc->sc_setdefantenna = ath_setdefantenna; 833 sc->sc_rc = ath_rate_attach(sc); 834 if (sc->sc_rc == NULL) { 835 error = EIO; 836 goto bad2; 837 } 838 839 /* Attach DFS module */ 840 if (! ath_dfs_attach(sc)) { 841 device_printf(sc->sc_dev, 842 "%s: unable to attach DFS\n", __func__); 843 error = EIO; 844 goto bad2; 845 } 846 847 /* Attach spectral module */ 848 if (ath_spectral_attach(sc) < 0) { 849 device_printf(sc->sc_dev, 850 "%s: unable to attach spectral\n", __func__); 851 error = EIO; 852 goto bad2; 853 } 854 855 /* Attach bluetooth coexistence module */ 856 if (ath_btcoex_attach(sc) < 0) { 857 device_printf(sc->sc_dev, 858 "%s: unable to attach bluetooth coexistence\n", __func__); 859 error = EIO; 860 goto bad2; 861 } 862 863 /* Attach LNA diversity module */ 864 if (ath_lna_div_attach(sc) < 0) { 865 device_printf(sc->sc_dev, 866 "%s: unable to attach LNA diversity\n", __func__); 867 error = EIO; 868 goto bad2; 869 } 870 871 /* Start DFS processing tasklet */ 872 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc); 873 874 /* Configure LED state */ 875 sc->sc_blinking = 0; 876 sc->sc_ledstate = 1; 877 sc->sc_ledon = 0; /* low true */ 878 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 879 callout_init(&sc->sc_ledtimer, 1); 880 881 /* 882 * Don't setup hardware-based blinking. 883 * 884 * Although some NICs may have this configured in the 885 * default reset register values, the user may wish 886 * to alter which pins have which function. 887 * 888 * The reference driver attaches the MAC network LED to GPIO1 and 889 * the MAC power LED to GPIO2. However, the DWA-552 cardbus 890 * NIC has these reversed. 891 */ 892 sc->sc_hardled = (1 == 0); 893 sc->sc_led_net_pin = -1; 894 sc->sc_led_pwr_pin = -1; 895 /* 896 * Auto-enable soft led processing for IBM cards and for 897 * 5211 minipci cards. Users can also manually enable/disable 898 * support with a sysctl. 899 */ 900 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 901 ath_led_config(sc); 902 ath_hal_setledstate(ah, HAL_LED_INIT); 903 904 /* XXX not right but it's not used anywhere important */ 905 ic->ic_phytype = IEEE80211_T_OFDM; 906 ic->ic_opmode = IEEE80211_M_STA; 907 ic->ic_caps = 908 IEEE80211_C_STA /* station mode */ 909 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 910 | IEEE80211_C_HOSTAP /* hostap mode */ 911 | IEEE80211_C_MONITOR /* monitor mode */ 912 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 913 | IEEE80211_C_WDS /* 4-address traffic works */ 914 | IEEE80211_C_MBSS /* mesh point link mode */ 915 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 916 | IEEE80211_C_SHSLOT /* short slot time supported */ 917 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 918 #ifndef ATH_ENABLE_11N 919 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 920 #endif 921 | IEEE80211_C_TXFRAG /* handle tx frags */ 922 #ifdef ATH_ENABLE_DFS 923 | IEEE80211_C_DFS /* Enable radar detection */ 924 #endif 925 | IEEE80211_C_PMGT /* Station side power mgmt */ 926 | IEEE80211_C_SWSLEEP 927 ; 928 /* 929 * Query the hal to figure out h/w crypto support. 930 */ 931 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 932 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 933 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 934 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 935 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 936 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 937 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 938 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 939 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 940 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 941 /* 942 * Check if h/w does the MIC and/or whether the 943 * separate key cache entries are required to 944 * handle both tx+rx MIC keys. 945 */ 946 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 947 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 948 /* 949 * If the h/w supports storing tx+rx MIC keys 950 * in one cache slot automatically enable use. 951 */ 952 if (ath_hal_hastkipsplit(ah) || 953 !ath_hal_settkipsplit(ah, AH_FALSE)) 954 sc->sc_splitmic = 1; 955 /* 956 * If the h/w can do TKIP MIC together with WME then 957 * we use it; otherwise we force the MIC to be done 958 * in software by the net80211 layer. 959 */ 960 if (ath_hal_haswmetkipmic(ah)) 961 sc->sc_wmetkipmic = 1; 962 } 963 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 964 /* 965 * Check for multicast key search support. 966 */ 967 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 968 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 969 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 970 } 971 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 972 /* 973 * Mark key cache slots associated with global keys 974 * as in use. If we knew TKIP was not to be used we 975 * could leave the +32, +64, and +32+64 slots free. 976 */ 977 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 978 setbit(sc->sc_keymap, i); 979 setbit(sc->sc_keymap, i+64); 980 if (sc->sc_splitmic) { 981 setbit(sc->sc_keymap, i+32); 982 setbit(sc->sc_keymap, i+32+64); 983 } 984 } 985 /* 986 * TPC support can be done either with a global cap or 987 * per-packet support. The latter is not available on 988 * all parts. We're a bit pedantic here as all parts 989 * support a global cap. 990 */ 991 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 992 ic->ic_caps |= IEEE80211_C_TXPMGT; 993 994 /* 995 * Mark WME capability only if we have sufficient 996 * hardware queues to do proper priority scheduling. 997 */ 998 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 999 ic->ic_caps |= IEEE80211_C_WME; 1000 /* 1001 * Check for misc other capabilities. 1002 */ 1003 if (ath_hal_hasbursting(ah)) 1004 ic->ic_caps |= IEEE80211_C_BURST; 1005 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 1006 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 1007 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 1008 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah); 1009 1010 /* XXX TODO: just make this a "store tx/rx timestamp length" operation */ 1011 if (ath_hal_get_rx_tsf_prec(ah, &i)) { 1012 if (i == 32) { 1013 sc->sc_rxtsf32 = 1; 1014 } 1015 if (bootverbose) 1016 device_printf(sc->sc_dev, "RX timestamp: %d bits\n", i); 1017 } 1018 if (ath_hal_get_tx_tsf_prec(ah, &i)) { 1019 if (bootverbose) 1020 device_printf(sc->sc_dev, "TX timestamp: %d bits\n", i); 1021 } 1022 1023 sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah); 1024 sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah); 1025 sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah); 1026 1027 /* 1028 * Some WB335 cards do not support antenna diversity. Since 1029 * we use a hardcoded value for AR9565 instead of using the 1030 * EEPROM/OTP data, remove the combining feature from 1031 * the HW capabilities bitmap. 1032 */ 1033 /* 1034 * XXX TODO: check reference driver and ath9k for what to do 1035 * here for WB335. I think we have to actually disable the 1036 * LNA div processing in the HAL and instead use the hard 1037 * coded values; and then use BT diversity. 1038 * 1039 * .. but also need to setup MCI too for WB335.. 1040 */ 1041 #if 0 1042 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 1043 device_printf(sc->sc_dev, "%s: WB335: disabling LNA mixer diversity\n", 1044 __func__); 1045 sc->sc_dolnadiv = 0; 1046 } 1047 #endif 1048 1049 if (ath_hal_hasfastframes(ah)) 1050 ic->ic_caps |= IEEE80211_C_FF; 1051 wmodes = ath_hal_getwirelessmodes(ah); 1052 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 1053 ic->ic_caps |= IEEE80211_C_TURBOP; 1054 #ifdef IEEE80211_SUPPORT_TDMA 1055 if (ath_hal_macversion(ah) > 0x78) { 1056 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 1057 ic->ic_tdma_update = ath_tdma_update; 1058 } 1059 #endif 1060 1061 /* 1062 * TODO: enforce that at least this many frames are available 1063 * in the txbuf list before allowing data frames (raw or 1064 * otherwise) to be transmitted. 1065 */ 1066 sc->sc_txq_data_minfree = 10; 1067 1068 /* 1069 * Shorten this to 64 packets, or 1/4 ath_txbuf, whichever 1070 * is smaller. 1071 * 1072 * Anything bigger can potentially see the cabq consume 1073 * almost all buffers, starving everything else, only to 1074 * see most fail to transmit in the given beacon interval. 1075 */ 1076 sc->sc_txq_mcastq_maxdepth = MIN(64, ath_txbuf / 4); 1077 1078 /* 1079 * How deep can the node software TX queue get whilst it's asleep. 1080 */ 1081 sc->sc_txq_node_psq_maxdepth = 16; 1082 1083 /* 1084 * Default the maximum queue to 1/4'th the TX buffers, or 1085 * 64, whichever is smaller. 1086 */ 1087 sc->sc_txq_node_maxdepth = MIN(64, ath_txbuf / 4); 1088 1089 /* Enable CABQ by default */ 1090 sc->sc_cabq_enable = 1; 1091 1092 /* 1093 * Allow the TX and RX chainmasks to be overridden by 1094 * environment variables and/or device.hints. 1095 * 1096 * This must be done early - before the hardware is 1097 * calibrated or before the 802.11n stream calculation 1098 * is done. 1099 */ 1100 if (resource_int_value(device_get_name(sc->sc_dev), 1101 device_get_unit(sc->sc_dev), "rx_chainmask", 1102 &rx_chainmask) == 0) { 1103 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n", 1104 rx_chainmask); 1105 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask); 1106 } 1107 if (resource_int_value(device_get_name(sc->sc_dev), 1108 device_get_unit(sc->sc_dev), "tx_chainmask", 1109 &tx_chainmask) == 0) { 1110 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n", 1111 tx_chainmask); 1112 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask); 1113 } 1114 1115 /* 1116 * Query the TX/RX chainmask configuration. 1117 * 1118 * This is only relevant for 11n devices. 1119 */ 1120 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask); 1121 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask); 1122 1123 /* 1124 * Disable MRR with protected frames by default. 1125 * Only 802.11n series NICs can handle this. 1126 */ 1127 sc->sc_mrrprot = 0; /* XXX should be a capability */ 1128 1129 /* 1130 * Query the enterprise mode information the HAL. 1131 */ 1132 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0, 1133 &sc->sc_ent_cfg) == HAL_OK) 1134 sc->sc_use_ent = 1; 1135 1136 #ifdef ATH_ENABLE_11N 1137 /* 1138 * Query HT capabilities 1139 */ 1140 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK && 1141 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) { 1142 uint32_t rxs, txs; 1143 uint32_t ldpc; 1144 1145 device_printf(sc->sc_dev, "[HT] enabling HT modes\n"); 1146 1147 sc->sc_mrrprot = 1; /* XXX should be a capability */ 1148 1149 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */ 1150 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */ 1151 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */ 1152 | IEEE80211_HTCAP_MAXAMSDU_3839 1153 /* max A-MSDU length */ 1154 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */ 1155 1156 /* 1157 * Enable short-GI for HT20 only if the hardware 1158 * advertises support. 1159 * Notably, anything earlier than the AR9287 doesn't. 1160 */ 1161 if ((ath_hal_getcapability(ah, 1162 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) && 1163 (wmodes & HAL_MODE_HT20)) { 1164 device_printf(sc->sc_dev, 1165 "[HT] enabling short-GI in 20MHz mode\n"); 1166 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20; 1167 } 1168 1169 if (wmodes & HAL_MODE_HT40) 1170 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40 1171 | IEEE80211_HTCAP_SHORTGI40; 1172 1173 /* 1174 * TX/RX streams need to be taken into account when 1175 * negotiating which MCS rates it'll receive and 1176 * what MCS rates are available for TX. 1177 */ 1178 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs); 1179 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs); 1180 ic->ic_txstream = txs; 1181 ic->ic_rxstream = rxs; 1182 1183 /* 1184 * Setup TX and RX STBC based on what the HAL allows and 1185 * the currently configured chainmask set. 1186 * Ie - don't enable STBC TX if only one chain is enabled. 1187 * STBC RX is fine on a single RX chain; it just won't 1188 * provide any real benefit. 1189 */ 1190 if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0, 1191 NULL) == HAL_OK) { 1192 sc->sc_rx_stbc = 1; 1193 device_printf(sc->sc_dev, 1194 "[HT] 1 stream STBC receive enabled\n"); 1195 ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM; 1196 } 1197 if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0, 1198 NULL) == HAL_OK) { 1199 sc->sc_tx_stbc = 1; 1200 device_printf(sc->sc_dev, 1201 "[HT] 1 stream STBC transmit enabled\n"); 1202 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC; 1203 } 1204 1205 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1, 1206 &sc->sc_rts_aggr_limit); 1207 if (sc->sc_rts_aggr_limit != (64 * 1024)) 1208 device_printf(sc->sc_dev, 1209 "[HT] RTS aggregates limited to %d KiB\n", 1210 sc->sc_rts_aggr_limit / 1024); 1211 1212 /* 1213 * LDPC 1214 */ 1215 if ((ath_hal_getcapability(ah, HAL_CAP_LDPC, 0, &ldpc)) 1216 == HAL_OK && (ldpc == 1)) { 1217 sc->sc_has_ldpc = 1; 1218 device_printf(sc->sc_dev, 1219 "[HT] LDPC transmit/receive enabled\n"); 1220 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC | 1221 IEEE80211_HTC_TXLDPC; 1222 } 1223 1224 1225 device_printf(sc->sc_dev, 1226 "[HT] %d RX streams; %d TX streams\n", rxs, txs); 1227 } 1228 #endif 1229 1230 /* 1231 * Initial aggregation settings. 1232 */ 1233 sc->sc_hwq_limit_aggr = ATH_AGGR_MIN_QDEPTH; 1234 sc->sc_hwq_limit_nonaggr = ATH_NONAGGR_MIN_QDEPTH; 1235 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW; 1236 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH; 1237 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE; 1238 sc->sc_delim_min_pad = 0; 1239 1240 /* 1241 * Check if the hardware requires PCI register serialisation. 1242 * Some of the Owl based MACs require this. 1243 */ 1244 if (mp_ncpus > 1 && 1245 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR, 1246 0, NULL) == HAL_OK) { 1247 sc->sc_ah->ah_config.ah_serialise_reg_war = 1; 1248 device_printf(sc->sc_dev, 1249 "Enabling register serialisation\n"); 1250 } 1251 1252 /* 1253 * Initialise the deferred completed RX buffer list. 1254 */ 1255 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]); 1256 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]); 1257 1258 /* 1259 * Indicate we need the 802.11 header padded to a 1260 * 32-bit boundary for 4-address and QoS frames. 1261 */ 1262 ic->ic_flags |= IEEE80211_F_DATAPAD; 1263 1264 /* 1265 * Query the hal about antenna support. 1266 */ 1267 sc->sc_defant = ath_hal_getdefantenna(ah); 1268 1269 /* 1270 * Not all chips have the VEOL support we want to 1271 * use with IBSS beacons; check here for it. 1272 */ 1273 sc->sc_hasveol = ath_hal_hasveol(ah); 1274 1275 /* get mac address from kenv first, then hardware */ 1276 if (ath_fetch_mac_kenv(sc, ic->ic_macaddr) == 0) { 1277 /* Tell the HAL now about the new MAC */ 1278 ath_hal_setmac(ah, ic->ic_macaddr); 1279 } else { 1280 ath_hal_getmac(ah, ic->ic_macaddr); 1281 } 1282 1283 if (sc->sc_hasbmask) 1284 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 1285 1286 /* NB: used to size node table key mapping array */ 1287 ic->ic_max_keyix = sc->sc_keymax; 1288 /* call MI attach routine. */ 1289 ieee80211_ifattach(ic); 1290 ic->ic_setregdomain = ath_setregdomain; 1291 ic->ic_getradiocaps = ath_getradiocaps; 1292 sc->sc_opmode = HAL_M_STA; 1293 1294 /* override default methods */ 1295 ic->ic_ioctl = ath_ioctl; 1296 ic->ic_parent = ath_parent; 1297 ic->ic_transmit = ath_transmit; 1298 ic->ic_newassoc = ath_newassoc; 1299 ic->ic_updateslot = ath_updateslot; 1300 ic->ic_wme.wme_update = ath_wme_update; 1301 ic->ic_vap_create = ath_vap_create; 1302 ic->ic_vap_delete = ath_vap_delete; 1303 ic->ic_raw_xmit = ath_raw_xmit; 1304 ic->ic_update_mcast = ath_update_mcast; 1305 ic->ic_update_promisc = ath_update_promisc; 1306 ic->ic_node_alloc = ath_node_alloc; 1307 sc->sc_node_free = ic->ic_node_free; 1308 ic->ic_node_free = ath_node_free; 1309 sc->sc_node_cleanup = ic->ic_node_cleanup; 1310 ic->ic_node_cleanup = ath_node_cleanup; 1311 ic->ic_node_getsignal = ath_node_getsignal; 1312 ic->ic_scan_start = ath_scan_start; 1313 ic->ic_scan_end = ath_scan_end; 1314 ic->ic_set_channel = ath_set_channel; 1315 #ifdef ATH_ENABLE_11N 1316 /* 802.11n specific - but just override anyway */ 1317 sc->sc_addba_request = ic->ic_addba_request; 1318 sc->sc_addba_response = ic->ic_addba_response; 1319 sc->sc_addba_stop = ic->ic_addba_stop; 1320 sc->sc_bar_response = ic->ic_bar_response; 1321 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout; 1322 1323 ic->ic_addba_request = ath_addba_request; 1324 ic->ic_addba_response = ath_addba_response; 1325 ic->ic_addba_response_timeout = ath_addba_response_timeout; 1326 ic->ic_addba_stop = ath_addba_stop; 1327 ic->ic_bar_response = ath_bar_response; 1328 1329 ic->ic_update_chw = ath_update_chw; 1330 #endif /* ATH_ENABLE_11N */ 1331 ic->ic_set_quiet = ath_set_quiet_ie; 1332 1333 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 1334 /* 1335 * There's one vendor bitmap entry in the RX radiotap 1336 * header; make sure that's taken into account. 1337 */ 1338 ieee80211_radiotap_attachv(ic, 1339 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0, 1340 ATH_TX_RADIOTAP_PRESENT, 1341 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1, 1342 ATH_RX_RADIOTAP_PRESENT); 1343 #else 1344 /* 1345 * No vendor bitmap/extensions are present. 1346 */ 1347 ieee80211_radiotap_attach(ic, 1348 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 1349 ATH_TX_RADIOTAP_PRESENT, 1350 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1351 ATH_RX_RADIOTAP_PRESENT); 1352 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 1353 1354 /* 1355 * Setup the ALQ logging if required 1356 */ 1357 #ifdef ATH_DEBUG_ALQ 1358 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev)); 1359 if_ath_alq_setcfg(&sc->sc_alq, 1360 sc->sc_ah->ah_macVersion, 1361 sc->sc_ah->ah_macRev, 1362 sc->sc_ah->ah_phyRev, 1363 sc->sc_ah->ah_magic); 1364 #endif 1365 1366 /* 1367 * Setup dynamic sysctl's now that country code and 1368 * regdomain are available from the hal. 1369 */ 1370 ath_sysctlattach(sc); 1371 ath_sysctl_stats_attach(sc); 1372 ath_sysctl_hal_attach(sc); 1373 1374 if (bootverbose) 1375 ieee80211_announce(ic); 1376 ath_announce(sc); 1377 1378 /* 1379 * Put it to sleep for now. 1380 */ 1381 ATH_LOCK(sc); 1382 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1); 1383 ATH_UNLOCK(sc); 1384 1385 return 0; 1386 bad2: 1387 ath_tx_cleanup(sc); 1388 ath_desc_free(sc); 1389 ath_txdma_teardown(sc); 1390 ath_rxdma_teardown(sc); 1391 1392 bad: 1393 if (ah) 1394 ath_hal_detach(ah); 1395 sc->sc_invalid = 1; 1396 return error; 1397 } 1398 1399 int 1400 ath_detach(struct ath_softc *sc) 1401 { 1402 1403 /* 1404 * NB: the order of these is important: 1405 * o stop the chip so no more interrupts will fire 1406 * o call the 802.11 layer before detaching the hal to 1407 * insure callbacks into the driver to delete global 1408 * key cache entries can be handled 1409 * o free the taskqueue which drains any pending tasks 1410 * o reclaim the tx queue data structures after calling 1411 * the 802.11 layer as we'll get called back to reclaim 1412 * node state and potentially want to use them 1413 * o to cleanup the tx queues the hal is called, so detach 1414 * it last 1415 * Other than that, it's straightforward... 1416 */ 1417 1418 /* 1419 * XXX Wake the hardware up first. ath_stop() will still 1420 * wake it up first, but I'd rather do it here just to 1421 * ensure it's awake. 1422 */ 1423 ATH_LOCK(sc); 1424 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1425 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 1426 1427 /* 1428 * Stop things cleanly. 1429 */ 1430 ath_stop(sc); 1431 ATH_UNLOCK(sc); 1432 1433 ieee80211_ifdetach(&sc->sc_ic); 1434 taskqueue_free(sc->sc_tq); 1435 #ifdef ATH_TX99_DIAG 1436 if (sc->sc_tx99 != NULL) 1437 sc->sc_tx99->detach(sc->sc_tx99); 1438 #endif 1439 ath_rate_detach(sc->sc_rc); 1440 #ifdef ATH_DEBUG_ALQ 1441 if_ath_alq_tidyup(&sc->sc_alq); 1442 #endif 1443 ath_lna_div_detach(sc); 1444 ath_btcoex_detach(sc); 1445 ath_spectral_detach(sc); 1446 ath_dfs_detach(sc); 1447 ath_desc_free(sc); 1448 ath_txdma_teardown(sc); 1449 ath_rxdma_teardown(sc); 1450 ath_tx_cleanup(sc); 1451 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 1452 1453 return 0; 1454 } 1455 1456 /* 1457 * MAC address handling for multiple BSS on the same radio. 1458 * The first vap uses the MAC address from the EEPROM. For 1459 * subsequent vap's we set the U/L bit (bit 1) in the MAC 1460 * address and use the next six bits as an index. 1461 */ 1462 static void 1463 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 1464 { 1465 int i; 1466 1467 if (clone && sc->sc_hasbmask) { 1468 /* NB: we only do this if h/w supports multiple bssid */ 1469 for (i = 0; i < 8; i++) 1470 if ((sc->sc_bssidmask & (1<<i)) == 0) 1471 break; 1472 if (i != 0) 1473 mac[0] |= (i << 2)|0x2; 1474 } else 1475 i = 0; 1476 sc->sc_bssidmask |= 1<<i; 1477 sc->sc_hwbssidmask[0] &= ~mac[0]; 1478 if (i == 0) 1479 sc->sc_nbssid0++; 1480 } 1481 1482 static void 1483 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 1484 { 1485 int i = mac[0] >> 2; 1486 uint8_t mask; 1487 1488 if (i != 0 || --sc->sc_nbssid0 == 0) { 1489 sc->sc_bssidmask &= ~(1<<i); 1490 /* recalculate bssid mask from remaining addresses */ 1491 mask = 0xff; 1492 for (i = 1; i < 8; i++) 1493 if (sc->sc_bssidmask & (1<<i)) 1494 mask &= ~((i<<2)|0x2); 1495 sc->sc_hwbssidmask[0] |= mask; 1496 } 1497 } 1498 1499 /* 1500 * Assign a beacon xmit slot. We try to space out 1501 * assignments so when beacons are staggered the 1502 * traffic coming out of the cab q has maximal time 1503 * to go out before the next beacon is scheduled. 1504 */ 1505 static int 1506 assign_bslot(struct ath_softc *sc) 1507 { 1508 u_int slot, free; 1509 1510 free = 0; 1511 for (slot = 0; slot < ATH_BCBUF; slot++) 1512 if (sc->sc_bslot[slot] == NULL) { 1513 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 1514 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 1515 return slot; 1516 free = slot; 1517 /* NB: keep looking for a double slot */ 1518 } 1519 return free; 1520 } 1521 1522 static struct ieee80211vap * 1523 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1524 enum ieee80211_opmode opmode, int flags, 1525 const uint8_t bssid[IEEE80211_ADDR_LEN], 1526 const uint8_t mac0[IEEE80211_ADDR_LEN]) 1527 { 1528 struct ath_softc *sc = ic->ic_softc; 1529 struct ath_vap *avp; 1530 struct ieee80211vap *vap; 1531 uint8_t mac[IEEE80211_ADDR_LEN]; 1532 int needbeacon, error; 1533 enum ieee80211_opmode ic_opmode; 1534 1535 avp = malloc(sizeof(struct ath_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1536 needbeacon = 0; 1537 IEEE80211_ADDR_COPY(mac, mac0); 1538 1539 ATH_LOCK(sc); 1540 ic_opmode = opmode; /* default to opmode of new vap */ 1541 switch (opmode) { 1542 case IEEE80211_M_STA: 1543 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 1544 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 1545 goto bad; 1546 } 1547 if (sc->sc_nvaps) { 1548 /* 1549 * With multiple vaps we must fall back 1550 * to s/w beacon miss handling. 1551 */ 1552 flags |= IEEE80211_CLONE_NOBEACONS; 1553 } 1554 if (flags & IEEE80211_CLONE_NOBEACONS) { 1555 /* 1556 * Station mode w/o beacons are implemented w/ AP mode. 1557 */ 1558 ic_opmode = IEEE80211_M_HOSTAP; 1559 } 1560 break; 1561 case IEEE80211_M_IBSS: 1562 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 1563 device_printf(sc->sc_dev, 1564 "only 1 ibss vap supported\n"); 1565 goto bad; 1566 } 1567 needbeacon = 1; 1568 break; 1569 case IEEE80211_M_AHDEMO: 1570 #ifdef IEEE80211_SUPPORT_TDMA 1571 if (flags & IEEE80211_CLONE_TDMA) { 1572 if (sc->sc_nvaps != 0) { 1573 device_printf(sc->sc_dev, 1574 "only 1 tdma vap supported\n"); 1575 goto bad; 1576 } 1577 needbeacon = 1; 1578 flags |= IEEE80211_CLONE_NOBEACONS; 1579 } 1580 /* fall thru... */ 1581 #endif 1582 case IEEE80211_M_MONITOR: 1583 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 1584 /* 1585 * Adopt existing mode. Adding a monitor or ahdemo 1586 * vap to an existing configuration is of dubious 1587 * value but should be ok. 1588 */ 1589 /* XXX not right for monitor mode */ 1590 ic_opmode = ic->ic_opmode; 1591 } 1592 break; 1593 case IEEE80211_M_HOSTAP: 1594 case IEEE80211_M_MBSS: 1595 needbeacon = 1; 1596 break; 1597 case IEEE80211_M_WDS: 1598 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 1599 device_printf(sc->sc_dev, 1600 "wds not supported in sta mode\n"); 1601 goto bad; 1602 } 1603 /* 1604 * Silently remove any request for a unique 1605 * bssid; WDS vap's always share the local 1606 * mac address. 1607 */ 1608 flags &= ~IEEE80211_CLONE_BSSID; 1609 if (sc->sc_nvaps == 0) 1610 ic_opmode = IEEE80211_M_HOSTAP; 1611 else 1612 ic_opmode = ic->ic_opmode; 1613 break; 1614 default: 1615 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 1616 goto bad; 1617 } 1618 /* 1619 * Check that a beacon buffer is available; the code below assumes it. 1620 */ 1621 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) { 1622 device_printf(sc->sc_dev, "no beacon buffer available\n"); 1623 goto bad; 1624 } 1625 1626 /* STA, AHDEMO? */ 1627 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS || opmode == IEEE80211_M_STA) { 1628 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 1629 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1630 } 1631 1632 vap = &avp->av_vap; 1633 /* XXX can't hold mutex across if_alloc */ 1634 ATH_UNLOCK(sc); 1635 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1636 ATH_LOCK(sc); 1637 if (error != 0) { 1638 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 1639 __func__, error); 1640 goto bad2; 1641 } 1642 1643 /* h/w crypto support */ 1644 vap->iv_key_alloc = ath_key_alloc; 1645 vap->iv_key_delete = ath_key_delete; 1646 vap->iv_key_set = ath_key_set; 1647 vap->iv_key_update_begin = ath_key_update_begin; 1648 vap->iv_key_update_end = ath_key_update_end; 1649 1650 /* override various methods */ 1651 avp->av_recv_mgmt = vap->iv_recv_mgmt; 1652 vap->iv_recv_mgmt = ath_recv_mgmt; 1653 vap->iv_reset = ath_reset_vap; 1654 vap->iv_update_beacon = ath_beacon_update; 1655 avp->av_newstate = vap->iv_newstate; 1656 vap->iv_newstate = ath_newstate; 1657 avp->av_bmiss = vap->iv_bmiss; 1658 vap->iv_bmiss = ath_bmiss_vap; 1659 1660 avp->av_node_ps = vap->iv_node_ps; 1661 vap->iv_node_ps = ath_node_powersave; 1662 1663 avp->av_set_tim = vap->iv_set_tim; 1664 vap->iv_set_tim = ath_node_set_tim; 1665 1666 avp->av_recv_pspoll = vap->iv_recv_pspoll; 1667 vap->iv_recv_pspoll = ath_node_recv_pspoll; 1668 1669 /* Set default parameters */ 1670 1671 /* 1672 * Anything earlier than some AR9300 series MACs don't 1673 * support a smaller MPDU density. 1674 */ 1675 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8; 1676 /* 1677 * All NICs can handle the maximum size, however 1678 * AR5416 based MACs can only TX aggregates w/ RTS 1679 * protection when the total aggregate size is <= 8k. 1680 * However, for now that's enforced by the TX path. 1681 */ 1682 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1683 vap->iv_ampdu_limit = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1684 1685 avp->av_bslot = -1; 1686 if (needbeacon) { 1687 /* 1688 * Allocate beacon state and setup the q for buffered 1689 * multicast frames. We know a beacon buffer is 1690 * available because we checked above. 1691 */ 1692 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf); 1693 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list); 1694 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1695 /* 1696 * Assign the vap to a beacon xmit slot. As above 1697 * this cannot fail to find a free one. 1698 */ 1699 avp->av_bslot = assign_bslot(sc); 1700 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1701 ("beacon slot %u not empty", avp->av_bslot)); 1702 sc->sc_bslot[avp->av_bslot] = vap; 1703 sc->sc_nbcnvaps++; 1704 } 1705 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1706 /* 1707 * Multple vaps are to transmit beacons and we 1708 * have h/w support for TSF adjusting; enable 1709 * use of staggered beacons. 1710 */ 1711 sc->sc_stagbeacons = 1; 1712 } 1713 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1714 } 1715 1716 ic->ic_opmode = ic_opmode; 1717 if (opmode != IEEE80211_M_WDS) { 1718 sc->sc_nvaps++; 1719 if (opmode == IEEE80211_M_STA) 1720 sc->sc_nstavaps++; 1721 if (opmode == IEEE80211_M_MBSS) 1722 sc->sc_nmeshvaps++; 1723 } 1724 switch (ic_opmode) { 1725 case IEEE80211_M_IBSS: 1726 sc->sc_opmode = HAL_M_IBSS; 1727 break; 1728 case IEEE80211_M_STA: 1729 sc->sc_opmode = HAL_M_STA; 1730 break; 1731 case IEEE80211_M_AHDEMO: 1732 #ifdef IEEE80211_SUPPORT_TDMA 1733 if (vap->iv_caps & IEEE80211_C_TDMA) { 1734 sc->sc_tdma = 1; 1735 /* NB: disable tsf adjust */ 1736 sc->sc_stagbeacons = 0; 1737 } 1738 /* 1739 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1740 * just ap mode. 1741 */ 1742 /* fall thru... */ 1743 #endif 1744 case IEEE80211_M_HOSTAP: 1745 case IEEE80211_M_MBSS: 1746 sc->sc_opmode = HAL_M_HOSTAP; 1747 break; 1748 case IEEE80211_M_MONITOR: 1749 sc->sc_opmode = HAL_M_MONITOR; 1750 break; 1751 default: 1752 /* XXX should not happen */ 1753 break; 1754 } 1755 if (sc->sc_hastsfadd) { 1756 /* 1757 * Configure whether or not TSF adjust should be done. 1758 */ 1759 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1760 } 1761 if (flags & IEEE80211_CLONE_NOBEACONS) { 1762 /* 1763 * Enable s/w beacon miss handling. 1764 */ 1765 sc->sc_swbmiss = 1; 1766 } 1767 ATH_UNLOCK(sc); 1768 1769 /* complete setup */ 1770 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status, 1771 mac); 1772 return vap; 1773 bad2: 1774 reclaim_address(sc, mac); 1775 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1776 bad: 1777 free(avp, M_80211_VAP); 1778 ATH_UNLOCK(sc); 1779 return NULL; 1780 } 1781 1782 static void 1783 ath_vap_delete(struct ieee80211vap *vap) 1784 { 1785 struct ieee80211com *ic = vap->iv_ic; 1786 struct ath_softc *sc = ic->ic_softc; 1787 struct ath_hal *ah = sc->sc_ah; 1788 struct ath_vap *avp = ATH_VAP(vap); 1789 1790 ATH_LOCK(sc); 1791 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1792 ATH_UNLOCK(sc); 1793 1794 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 1795 if (sc->sc_running) { 1796 /* 1797 * Quiesce the hardware while we remove the vap. In 1798 * particular we need to reclaim all references to 1799 * the vap state by any frames pending on the tx queues. 1800 */ 1801 ath_hal_intrset(ah, 0); /* disable interrupts */ 1802 /* XXX Do all frames from all vaps/nodes need draining here? */ 1803 ath_stoprecv(sc, 1); /* stop recv side */ 1804 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */ 1805 } 1806 1807 /* .. leave the hardware awake for now. */ 1808 1809 ieee80211_vap_detach(vap); 1810 1811 /* 1812 * XXX Danger Will Robinson! Danger! 1813 * 1814 * Because ieee80211_vap_detach() can queue a frame (the station 1815 * diassociate message?) after we've drained the TXQ and 1816 * flushed the software TXQ, we will end up with a frame queued 1817 * to a node whose vap is about to be freed. 1818 * 1819 * To work around this, flush the hardware/software again. 1820 * This may be racy - the ath task may be running and the packet 1821 * may be being scheduled between sw->hw txq. Tsk. 1822 * 1823 * TODO: figure out why a new node gets allocated somewhere around 1824 * here (after the ath_tx_swq() call; and after an ath_stop() 1825 * call!) 1826 */ 1827 1828 ath_draintxq(sc, ATH_RESET_DEFAULT); 1829 1830 ATH_LOCK(sc); 1831 /* 1832 * Reclaim beacon state. Note this must be done before 1833 * the vap instance is reclaimed as we may have a reference 1834 * to it in the buffer for the beacon frame. 1835 */ 1836 if (avp->av_bcbuf != NULL) { 1837 if (avp->av_bslot != -1) { 1838 sc->sc_bslot[avp->av_bslot] = NULL; 1839 sc->sc_nbcnvaps--; 1840 } 1841 ath_beacon_return(sc, avp->av_bcbuf); 1842 avp->av_bcbuf = NULL; 1843 if (sc->sc_nbcnvaps == 0) { 1844 sc->sc_stagbeacons = 0; 1845 if (sc->sc_hastsfadd) 1846 ath_hal_settsfadjust(sc->sc_ah, 0); 1847 } 1848 /* 1849 * Reclaim any pending mcast frames for the vap. 1850 */ 1851 ath_tx_draintxq(sc, &avp->av_mcastq); 1852 } 1853 /* 1854 * Update bookkeeping. 1855 */ 1856 if (vap->iv_opmode == IEEE80211_M_STA) { 1857 sc->sc_nstavaps--; 1858 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1859 sc->sc_swbmiss = 0; 1860 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1861 vap->iv_opmode == IEEE80211_M_STA || 1862 vap->iv_opmode == IEEE80211_M_MBSS) { 1863 reclaim_address(sc, vap->iv_myaddr); 1864 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1865 if (vap->iv_opmode == IEEE80211_M_MBSS) 1866 sc->sc_nmeshvaps--; 1867 } 1868 if (vap->iv_opmode != IEEE80211_M_WDS) 1869 sc->sc_nvaps--; 1870 #ifdef IEEE80211_SUPPORT_TDMA 1871 /* TDMA operation ceases when the last vap is destroyed */ 1872 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1873 sc->sc_tdma = 0; 1874 sc->sc_swbmiss = 0; 1875 } 1876 #endif 1877 free(avp, M_80211_VAP); 1878 1879 if (sc->sc_running) { 1880 /* 1881 * Restart rx+tx machines if still running (RUNNING will 1882 * be reset if we just destroyed the last vap). 1883 */ 1884 if (ath_startrecv(sc) != 0) 1885 device_printf(sc->sc_dev, 1886 "%s: unable to restart recv logic\n", __func__); 1887 if (sc->sc_beacons) { /* restart beacons */ 1888 #ifdef IEEE80211_SUPPORT_TDMA 1889 if (sc->sc_tdma) 1890 ath_tdma_config(sc, NULL); 1891 else 1892 #endif 1893 ath_beacon_config(sc, NULL); 1894 } 1895 ath_hal_intrset(ah, sc->sc_imask); 1896 } 1897 1898 /* Ok, let the hardware asleep. */ 1899 ath_power_restore_power_state(sc); 1900 ATH_UNLOCK(sc); 1901 } 1902 1903 void 1904 ath_suspend(struct ath_softc *sc) 1905 { 1906 struct ieee80211com *ic = &sc->sc_ic; 1907 1908 sc->sc_resume_up = ic->ic_nrunning != 0; 1909 1910 ieee80211_suspend_all(ic); 1911 /* 1912 * NB: don't worry about putting the chip in low power 1913 * mode; pci will power off our socket on suspend and 1914 * CardBus detaches the device. 1915 * 1916 * XXX TODO: well, that's great, except for non-cardbus 1917 * devices! 1918 */ 1919 1920 /* 1921 * XXX This doesn't wait until all pending taskqueue 1922 * items and parallel transmit/receive/other threads 1923 * are running! 1924 */ 1925 ath_hal_intrset(sc->sc_ah, 0); 1926 taskqueue_block(sc->sc_tq); 1927 1928 ATH_LOCK(sc); 1929 callout_stop(&sc->sc_cal_ch); 1930 ATH_UNLOCK(sc); 1931 1932 /* 1933 * XXX ensure sc_invalid is 1 1934 */ 1935 1936 /* Disable the PCIe PHY, complete with workarounds */ 1937 ath_hal_enablepcie(sc->sc_ah, 1, 1); 1938 } 1939 1940 /* 1941 * Reset the key cache since some parts do not reset the 1942 * contents on resume. First we clear all entries, then 1943 * re-load keys that the 802.11 layer assumes are setup 1944 * in h/w. 1945 */ 1946 static void 1947 ath_reset_keycache(struct ath_softc *sc) 1948 { 1949 struct ieee80211com *ic = &sc->sc_ic; 1950 struct ath_hal *ah = sc->sc_ah; 1951 int i; 1952 1953 ATH_LOCK(sc); 1954 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1955 for (i = 0; i < sc->sc_keymax; i++) 1956 ath_hal_keyreset(ah, i); 1957 ath_power_restore_power_state(sc); 1958 ATH_UNLOCK(sc); 1959 ieee80211_crypto_reload_keys(ic); 1960 } 1961 1962 /* 1963 * Fetch the current chainmask configuration based on the current 1964 * operating channel and options. 1965 */ 1966 static void 1967 ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan) 1968 { 1969 1970 /* 1971 * Set TX chainmask to the currently configured chainmask; 1972 * the TX chainmask depends upon the current operating mode. 1973 */ 1974 sc->sc_cur_rxchainmask = sc->sc_rxchainmask; 1975 if (IEEE80211_IS_CHAN_HT(chan)) { 1976 sc->sc_cur_txchainmask = sc->sc_txchainmask; 1977 } else { 1978 sc->sc_cur_txchainmask = 1; 1979 } 1980 1981 DPRINTF(sc, ATH_DEBUG_RESET, 1982 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n", 1983 __func__, 1984 sc->sc_cur_txchainmask, 1985 sc->sc_cur_rxchainmask); 1986 } 1987 1988 void 1989 ath_resume(struct ath_softc *sc) 1990 { 1991 struct ieee80211com *ic = &sc->sc_ic; 1992 struct ath_hal *ah = sc->sc_ah; 1993 HAL_STATUS status; 1994 1995 ath_hal_enablepcie(ah, 0, 0); 1996 1997 /* 1998 * Must reset the chip before we reload the 1999 * keycache as we were powered down on suspend. 2000 */ 2001 ath_update_chainmasks(sc, 2002 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan); 2003 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2004 sc->sc_cur_rxchainmask); 2005 2006 /* Ensure we set the current power state to on */ 2007 ATH_LOCK(sc); 2008 ath_power_setselfgen(sc, HAL_PM_AWAKE); 2009 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2010 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 2011 ATH_UNLOCK(sc); 2012 2013 ath_hal_reset(ah, sc->sc_opmode, 2014 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 2015 AH_FALSE, HAL_RESET_NORMAL, &status); 2016 ath_reset_keycache(sc); 2017 2018 ATH_RX_LOCK(sc); 2019 sc->sc_rx_stopped = 1; 2020 sc->sc_rx_resetted = 1; 2021 ATH_RX_UNLOCK(sc); 2022 2023 /* Let DFS at it in case it's a DFS channel */ 2024 ath_dfs_radar_enable(sc, ic->ic_curchan); 2025 2026 /* Let spectral at in case spectral is enabled */ 2027 ath_spectral_enable(sc, ic->ic_curchan); 2028 2029 /* 2030 * Let bluetooth coexistence at in case it's needed for this channel 2031 */ 2032 ath_btcoex_enable(sc, ic->ic_curchan); 2033 2034 /* 2035 * If we're doing TDMA, enforce the TXOP limitation for chips that 2036 * support it. 2037 */ 2038 if (sc->sc_hasenforcetxop && sc->sc_tdma) 2039 ath_hal_setenforcetxop(sc->sc_ah, 1); 2040 else 2041 ath_hal_setenforcetxop(sc->sc_ah, 0); 2042 2043 /* Restore the LED configuration */ 2044 ath_led_config(sc); 2045 ath_hal_setledstate(ah, HAL_LED_INIT); 2046 2047 if (sc->sc_resume_up) 2048 ieee80211_resume_all(ic); 2049 2050 ATH_LOCK(sc); 2051 ath_power_restore_power_state(sc); 2052 ATH_UNLOCK(sc); 2053 2054 /* XXX beacons ? */ 2055 } 2056 2057 void 2058 ath_shutdown(struct ath_softc *sc) 2059 { 2060 2061 ATH_LOCK(sc); 2062 ath_stop(sc); 2063 ATH_UNLOCK(sc); 2064 /* NB: no point powering down chip as we're about to reboot */ 2065 } 2066 2067 /* 2068 * Interrupt handler. Most of the actual processing is deferred. 2069 */ 2070 void 2071 ath_intr(void *arg) 2072 { 2073 struct ath_softc *sc = arg; 2074 struct ath_hal *ah = sc->sc_ah; 2075 HAL_INT status = 0; 2076 uint32_t txqs; 2077 2078 /* 2079 * If we're inside a reset path, just print a warning and 2080 * clear the ISR. The reset routine will finish it for us. 2081 */ 2082 ATH_PCU_LOCK(sc); 2083 if (sc->sc_inreset_cnt) { 2084 HAL_INT status; 2085 ath_hal_getisr(ah, &status); /* clear ISR */ 2086 ath_hal_intrset(ah, 0); /* disable further intr's */ 2087 DPRINTF(sc, ATH_DEBUG_ANY, 2088 "%s: in reset, ignoring: status=0x%x\n", 2089 __func__, status); 2090 ATH_PCU_UNLOCK(sc); 2091 return; 2092 } 2093 2094 if (sc->sc_invalid) { 2095 /* 2096 * The hardware is not ready/present, don't touch anything. 2097 * Note this can happen early on if the IRQ is shared. 2098 */ 2099 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 2100 ATH_PCU_UNLOCK(sc); 2101 return; 2102 } 2103 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */ 2104 ATH_PCU_UNLOCK(sc); 2105 return; 2106 } 2107 2108 ATH_LOCK(sc); 2109 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2110 ATH_UNLOCK(sc); 2111 2112 if (sc->sc_ic.ic_nrunning == 0 && sc->sc_running == 0) { 2113 HAL_INT status; 2114 2115 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_nrunning %d sc_running %d\n", 2116 __func__, sc->sc_ic.ic_nrunning, sc->sc_running); 2117 ath_hal_getisr(ah, &status); /* clear ISR */ 2118 ath_hal_intrset(ah, 0); /* disable further intr's */ 2119 ATH_PCU_UNLOCK(sc); 2120 2121 ATH_LOCK(sc); 2122 ath_power_restore_power_state(sc); 2123 ATH_UNLOCK(sc); 2124 return; 2125 } 2126 2127 /* 2128 * Figure out the reason(s) for the interrupt. Note 2129 * that the hal returns a pseudo-ISR that may include 2130 * bits we haven't explicitly enabled so we mask the 2131 * value to insure we only process bits we requested. 2132 */ 2133 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 2134 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 2135 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status); 2136 #ifdef ATH_DEBUG_ALQ 2137 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate, 2138 ah->ah_syncstate); 2139 #endif /* ATH_DEBUG_ALQ */ 2140 #ifdef ATH_KTR_INTR_DEBUG 2141 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5, 2142 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x", 2143 ah->ah_intrstate[0], 2144 ah->ah_intrstate[1], 2145 ah->ah_intrstate[2], 2146 ah->ah_intrstate[3], 2147 ah->ah_intrstate[6]); 2148 #endif 2149 2150 /* Squirrel away SYNC interrupt debugging */ 2151 if (ah->ah_syncstate != 0) { 2152 int i; 2153 for (i = 0; i < 32; i++) 2154 if (ah->ah_syncstate & (1 << i)) 2155 sc->sc_intr_stats.sync_intr[i]++; 2156 } 2157 2158 status &= sc->sc_imask; /* discard unasked for bits */ 2159 2160 /* Short-circuit un-handled interrupts */ 2161 if (status == 0x0) { 2162 ATH_PCU_UNLOCK(sc); 2163 2164 ATH_LOCK(sc); 2165 ath_power_restore_power_state(sc); 2166 ATH_UNLOCK(sc); 2167 2168 return; 2169 } 2170 2171 /* 2172 * Take a note that we're inside the interrupt handler, so 2173 * the reset routines know to wait. 2174 */ 2175 sc->sc_intr_cnt++; 2176 ATH_PCU_UNLOCK(sc); 2177 2178 /* 2179 * Handle the interrupt. We won't run concurrent with the reset 2180 * or channel change routines as they'll wait for sc_intr_cnt 2181 * to be 0 before continuing. 2182 */ 2183 if (status & HAL_INT_FATAL) { 2184 sc->sc_stats.ast_hardware++; 2185 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 2186 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask); 2187 } else { 2188 if (status & HAL_INT_SWBA) { 2189 /* 2190 * Software beacon alert--time to send a beacon. 2191 * Handle beacon transmission directly; deferring 2192 * this is too slow to meet timing constraints 2193 * under load. 2194 */ 2195 #ifdef IEEE80211_SUPPORT_TDMA 2196 if (sc->sc_tdma) { 2197 if (sc->sc_tdmaswba == 0) { 2198 struct ieee80211com *ic = &sc->sc_ic; 2199 struct ieee80211vap *vap = 2200 TAILQ_FIRST(&ic->ic_vaps); 2201 ath_tdma_beacon_send(sc, vap); 2202 sc->sc_tdmaswba = 2203 vap->iv_tdma->tdma_bintval; 2204 } else 2205 sc->sc_tdmaswba--; 2206 } else 2207 #endif 2208 { 2209 ath_beacon_proc(sc, 0); 2210 #ifdef IEEE80211_SUPPORT_SUPERG 2211 /* 2212 * Schedule the rx taskq in case there's no 2213 * traffic so any frames held on the staging 2214 * queue are aged and potentially flushed. 2215 */ 2216 sc->sc_rx.recv_sched(sc, 1); 2217 #endif 2218 } 2219 } 2220 if (status & HAL_INT_RXEOL) { 2221 int imask; 2222 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL"); 2223 if (! sc->sc_isedma) { 2224 ATH_PCU_LOCK(sc); 2225 /* 2226 * NB: the hardware should re-read the link when 2227 * RXE bit is written, but it doesn't work at 2228 * least on older hardware revs. 2229 */ 2230 sc->sc_stats.ast_rxeol++; 2231 /* 2232 * Disable RXEOL/RXORN - prevent an interrupt 2233 * storm until the PCU logic can be reset. 2234 * In case the interface is reset some other 2235 * way before "sc_kickpcu" is called, don't 2236 * modify sc_imask - that way if it is reset 2237 * by a call to ath_reset() somehow, the 2238 * interrupt mask will be correctly reprogrammed. 2239 */ 2240 imask = sc->sc_imask; 2241 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN); 2242 ath_hal_intrset(ah, imask); 2243 /* 2244 * Only blank sc_rxlink if we've not yet kicked 2245 * the PCU. 2246 * 2247 * This isn't entirely correct - the correct solution 2248 * would be to have a PCU lock and engage that for 2249 * the duration of the PCU fiddling; which would include 2250 * running the RX process. Otherwise we could end up 2251 * messing up the RX descriptor chain and making the 2252 * RX desc list much shorter. 2253 */ 2254 if (! sc->sc_kickpcu) 2255 sc->sc_rxlink = NULL; 2256 sc->sc_kickpcu = 1; 2257 ATH_PCU_UNLOCK(sc); 2258 } 2259 /* 2260 * Enqueue an RX proc to handle whatever 2261 * is in the RX queue. 2262 * This will then kick the PCU if required. 2263 */ 2264 sc->sc_rx.recv_sched(sc, 1); 2265 } 2266 if (status & HAL_INT_TXURN) { 2267 sc->sc_stats.ast_txurn++; 2268 /* bump tx trigger level */ 2269 ath_hal_updatetxtriglevel(ah, AH_TRUE); 2270 } 2271 /* 2272 * Handle both the legacy and RX EDMA interrupt bits. 2273 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC. 2274 */ 2275 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) { 2276 sc->sc_stats.ast_rx_intr++; 2277 sc->sc_rx.recv_sched(sc, 1); 2278 } 2279 if (status & HAL_INT_TX) { 2280 sc->sc_stats.ast_tx_intr++; 2281 /* 2282 * Grab all the currently set bits in the HAL txq bitmap 2283 * and blank them. This is the only place we should be 2284 * doing this. 2285 */ 2286 if (! sc->sc_isedma) { 2287 ATH_PCU_LOCK(sc); 2288 txqs = 0xffffffff; 2289 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs); 2290 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3, 2291 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x", 2292 txqs, 2293 sc->sc_txq_active, 2294 sc->sc_txq_active | txqs); 2295 sc->sc_txq_active |= txqs; 2296 ATH_PCU_UNLOCK(sc); 2297 } 2298 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 2299 } 2300 if (status & HAL_INT_BMISS) { 2301 sc->sc_stats.ast_bmiss++; 2302 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 2303 } 2304 if (status & HAL_INT_GTT) 2305 sc->sc_stats.ast_tx_timeout++; 2306 if (status & HAL_INT_CST) 2307 sc->sc_stats.ast_tx_cst++; 2308 if (status & HAL_INT_MIB) { 2309 sc->sc_stats.ast_mib++; 2310 ATH_PCU_LOCK(sc); 2311 /* 2312 * Disable interrupts until we service the MIB 2313 * interrupt; otherwise it will continue to fire. 2314 */ 2315 ath_hal_intrset(ah, 0); 2316 /* 2317 * Let the hal handle the event. We assume it will 2318 * clear whatever condition caused the interrupt. 2319 */ 2320 ath_hal_mibevent(ah, &sc->sc_halstats); 2321 /* 2322 * Don't reset the interrupt if we've just 2323 * kicked the PCU, or we may get a nested 2324 * RXEOL before the rxproc has had a chance 2325 * to run. 2326 */ 2327 if (sc->sc_kickpcu == 0) 2328 ath_hal_intrset(ah, sc->sc_imask); 2329 ATH_PCU_UNLOCK(sc); 2330 } 2331 if (status & HAL_INT_RXORN) { 2332 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 2333 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN"); 2334 sc->sc_stats.ast_rxorn++; 2335 } 2336 if (status & HAL_INT_TSFOOR) { 2337 /* out of range beacon - wake the chip up, 2338 * but don't modify self-gen frame config */ 2339 device_printf(sc->sc_dev, "%s: TSFOOR\n", __func__); 2340 sc->sc_syncbeacon = 1; 2341 ATH_LOCK(sc); 2342 ath_power_setpower(sc, HAL_PM_AWAKE, 0); 2343 ATH_UNLOCK(sc); 2344 } 2345 if (status & HAL_INT_MCI) { 2346 ath_btcoex_mci_intr(sc); 2347 } 2348 } 2349 ATH_PCU_LOCK(sc); 2350 sc->sc_intr_cnt--; 2351 ATH_PCU_UNLOCK(sc); 2352 2353 ATH_LOCK(sc); 2354 ath_power_restore_power_state(sc); 2355 ATH_UNLOCK(sc); 2356 } 2357 2358 static void 2359 ath_fatal_proc(void *arg, int pending) 2360 { 2361 struct ath_softc *sc = arg; 2362 u_int32_t *state; 2363 u_int32_t len; 2364 void *sp; 2365 2366 if (sc->sc_invalid) 2367 return; 2368 2369 device_printf(sc->sc_dev, "hardware error; resetting\n"); 2370 /* 2371 * Fatal errors are unrecoverable. Typically these 2372 * are caused by DMA errors. Collect h/w state from 2373 * the hal so we can diagnose what's going on. 2374 */ 2375 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 2376 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 2377 state = sp; 2378 device_printf(sc->sc_dev, 2379 "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", state[0], 2380 state[1] , state[2], state[3], state[4], state[5]); 2381 } 2382 ath_reset(sc, ATH_RESET_NOLOSS); 2383 } 2384 2385 static void 2386 ath_bmiss_vap(struct ieee80211vap *vap) 2387 { 2388 struct ath_softc *sc = vap->iv_ic->ic_softc; 2389 2390 /* 2391 * Workaround phantom bmiss interrupts by sanity-checking 2392 * the time of our last rx'd frame. If it is within the 2393 * beacon miss interval then ignore the interrupt. If it's 2394 * truly a bmiss we'll get another interrupt soon and that'll 2395 * be dispatched up for processing. Note this applies only 2396 * for h/w beacon miss events. 2397 */ 2398 2399 /* 2400 * XXX TODO: Just read the TSF during the interrupt path; 2401 * that way we don't have to wake up again just to read it 2402 * again. 2403 */ 2404 ATH_LOCK(sc); 2405 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2406 ATH_UNLOCK(sc); 2407 2408 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 2409 u_int64_t lastrx = sc->sc_lastrx; 2410 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 2411 /* XXX should take a locked ref to iv_bss */ 2412 u_int bmisstimeout = 2413 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 2414 2415 DPRINTF(sc, ATH_DEBUG_BEACON, 2416 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 2417 __func__, (unsigned long long) tsf, 2418 (unsigned long long)(tsf - lastrx), 2419 (unsigned long long) lastrx, bmisstimeout); 2420 2421 if (tsf - lastrx <= bmisstimeout) { 2422 sc->sc_stats.ast_bmiss_phantom++; 2423 2424 ATH_LOCK(sc); 2425 ath_power_restore_power_state(sc); 2426 ATH_UNLOCK(sc); 2427 2428 return; 2429 } 2430 } 2431 2432 /* 2433 * Keep the hardware awake if it's asleep (and leave self-gen 2434 * frame config alone) until the next beacon, so we can resync 2435 * against the next beacon. 2436 * 2437 * This handles three common beacon miss cases in STA powersave mode - 2438 * (a) the beacon TBTT isnt a multiple of bintval; 2439 * (b) the beacon was missed; and 2440 * (c) the beacons are being delayed because the AP is busy and 2441 * isn't reliably able to meet its TBTT. 2442 */ 2443 ATH_LOCK(sc); 2444 ath_power_setpower(sc, HAL_PM_AWAKE, 0); 2445 ath_power_restore_power_state(sc); 2446 ATH_UNLOCK(sc); 2447 DPRINTF(sc, ATH_DEBUG_BEACON, 2448 "%s: forced awake; force syncbeacon=1\n", __func__); 2449 2450 /* 2451 * Attempt to force a beacon resync. 2452 */ 2453 sc->sc_syncbeacon = 1; 2454 2455 ATH_VAP(vap)->av_bmiss(vap); 2456 } 2457 2458 /* XXX this needs a force wakeup! */ 2459 int 2460 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 2461 { 2462 uint32_t rsize; 2463 void *sp; 2464 2465 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize)) 2466 return 0; 2467 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 2468 *hangs = *(uint32_t *)sp; 2469 return 1; 2470 } 2471 2472 static void 2473 ath_bmiss_proc(void *arg, int pending) 2474 { 2475 struct ath_softc *sc = arg; 2476 uint32_t hangs; 2477 2478 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 2479 2480 ATH_LOCK(sc); 2481 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2482 ATH_UNLOCK(sc); 2483 2484 ath_beacon_miss(sc); 2485 2486 /* 2487 * Do a reset upon any becaon miss event. 2488 * 2489 * It may be a non-recognised RX clear hang which needs a reset 2490 * to clear. 2491 */ 2492 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 2493 ath_reset(sc, ATH_RESET_NOLOSS); 2494 device_printf(sc->sc_dev, 2495 "bb hang detected (0x%x), resetting\n", hangs); 2496 } else { 2497 ath_reset(sc, ATH_RESET_NOLOSS); 2498 ieee80211_beacon_miss(&sc->sc_ic); 2499 } 2500 2501 /* Force a beacon resync, in case they've drifted */ 2502 sc->sc_syncbeacon = 1; 2503 2504 ATH_LOCK(sc); 2505 ath_power_restore_power_state(sc); 2506 ATH_UNLOCK(sc); 2507 } 2508 2509 /* 2510 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 2511 * calcs together with WME. If necessary disable the crypto 2512 * hardware and mark the 802.11 state so keys will be setup 2513 * with the MIC work done in software. 2514 */ 2515 static void 2516 ath_settkipmic(struct ath_softc *sc) 2517 { 2518 struct ieee80211com *ic = &sc->sc_ic; 2519 2520 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 2521 if (ic->ic_flags & IEEE80211_F_WME) { 2522 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 2523 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 2524 } else { 2525 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 2526 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 2527 } 2528 } 2529 } 2530 2531 static void 2532 ath_vap_clear_quiet_ie(struct ath_softc *sc) 2533 { 2534 struct ieee80211com *ic = &sc->sc_ic; 2535 struct ieee80211vap *vap; 2536 struct ath_vap *avp; 2537 2538 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 2539 avp = ATH_VAP(vap); 2540 /* Quiet time handling - ensure we resync */ 2541 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 2542 } 2543 } 2544 2545 static int 2546 ath_init(struct ath_softc *sc) 2547 { 2548 struct ieee80211com *ic = &sc->sc_ic; 2549 struct ath_hal *ah = sc->sc_ah; 2550 HAL_STATUS status; 2551 2552 ATH_LOCK_ASSERT(sc); 2553 2554 /* 2555 * Force the sleep state awake. 2556 */ 2557 ath_power_setselfgen(sc, HAL_PM_AWAKE); 2558 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2559 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 2560 2561 /* 2562 * Stop anything previously setup. This is safe 2563 * whether this is the first time through or not. 2564 */ 2565 ath_stop(sc); 2566 2567 /* 2568 * The basic interface to setting the hardware in a good 2569 * state is ``reset''. On return the hardware is known to 2570 * be powered up and with interrupts disabled. This must 2571 * be followed by initialization of the appropriate bits 2572 * and then setup of the interrupt mask. 2573 */ 2574 ath_settkipmic(sc); 2575 ath_update_chainmasks(sc, ic->ic_curchan); 2576 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2577 sc->sc_cur_rxchainmask); 2578 2579 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, 2580 HAL_RESET_NORMAL, &status)) { 2581 device_printf(sc->sc_dev, 2582 "unable to reset hardware; hal status %u\n", status); 2583 return (ENODEV); 2584 } 2585 2586 ATH_RX_LOCK(sc); 2587 sc->sc_rx_stopped = 1; 2588 sc->sc_rx_resetted = 1; 2589 ATH_RX_UNLOCK(sc); 2590 2591 /* Clear quiet IE state for each VAP */ 2592 ath_vap_clear_quiet_ie(sc); 2593 2594 ath_chan_change(sc, ic->ic_curchan); 2595 2596 /* Let DFS at it in case it's a DFS channel */ 2597 ath_dfs_radar_enable(sc, ic->ic_curchan); 2598 2599 /* Let spectral at in case spectral is enabled */ 2600 ath_spectral_enable(sc, ic->ic_curchan); 2601 2602 /* 2603 * Let bluetooth coexistence at in case it's needed for this channel 2604 */ 2605 ath_btcoex_enable(sc, ic->ic_curchan); 2606 2607 /* 2608 * If we're doing TDMA, enforce the TXOP limitation for chips that 2609 * support it. 2610 */ 2611 if (sc->sc_hasenforcetxop && sc->sc_tdma) 2612 ath_hal_setenforcetxop(sc->sc_ah, 1); 2613 else 2614 ath_hal_setenforcetxop(sc->sc_ah, 0); 2615 2616 /* 2617 * Likewise this is set during reset so update 2618 * state cached in the driver. 2619 */ 2620 sc->sc_diversity = ath_hal_getdiversity(ah); 2621 sc->sc_lastlongcal = ticks; 2622 sc->sc_resetcal = 1; 2623 sc->sc_lastcalreset = 0; 2624 sc->sc_lastani = ticks; 2625 sc->sc_lastshortcal = ticks; 2626 sc->sc_doresetcal = AH_FALSE; 2627 /* 2628 * Beacon timers were cleared here; give ath_newstate() 2629 * a hint that the beacon timers should be poked when 2630 * things transition to the RUN state. 2631 */ 2632 sc->sc_beacons = 0; 2633 2634 /* 2635 * Setup the hardware after reset: the key cache 2636 * is filled as needed and the receive engine is 2637 * set going. Frame transmit is handled entirely 2638 * in the frame output path; there's nothing to do 2639 * here except setup the interrupt mask. 2640 */ 2641 if (ath_startrecv(sc) != 0) { 2642 device_printf(sc->sc_dev, "unable to start recv logic\n"); 2643 ath_power_restore_power_state(sc); 2644 return (ENODEV); 2645 } 2646 2647 /* 2648 * Enable interrupts. 2649 */ 2650 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 2651 | HAL_INT_RXORN | HAL_INT_TXURN 2652 | HAL_INT_FATAL | HAL_INT_GLOBAL; 2653 2654 /* 2655 * Enable RX EDMA bits. Note these overlap with 2656 * HAL_INT_RX and HAL_INT_RXDESC respectively. 2657 */ 2658 if (sc->sc_isedma) 2659 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP); 2660 2661 /* 2662 * If we're an EDMA NIC, we don't care about RXEOL. 2663 * Writing a new descriptor in will simply restart 2664 * RX DMA. 2665 */ 2666 if (! sc->sc_isedma) 2667 sc->sc_imask |= HAL_INT_RXEOL; 2668 2669 /* 2670 * Enable MCI interrupt for MCI devices. 2671 */ 2672 if (sc->sc_btcoex_mci) 2673 sc->sc_imask |= HAL_INT_MCI; 2674 2675 /* 2676 * Enable MIB interrupts when there are hardware phy counters. 2677 * Note we only do this (at the moment) for station mode. 2678 */ 2679 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 2680 sc->sc_imask |= HAL_INT_MIB; 2681 2682 /* 2683 * XXX add capability for this. 2684 * 2685 * If we're in STA mode (and maybe IBSS?) then register for 2686 * TSFOOR interrupts. 2687 */ 2688 if (ic->ic_opmode == IEEE80211_M_STA) 2689 sc->sc_imask |= HAL_INT_TSFOOR; 2690 2691 /* Enable global TX timeout and carrier sense timeout if available */ 2692 if (ath_hal_gtxto_supported(ah)) 2693 sc->sc_imask |= HAL_INT_GTT; 2694 2695 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n", 2696 __func__, sc->sc_imask); 2697 2698 sc->sc_running = 1; 2699 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 2700 ath_hal_intrset(ah, sc->sc_imask); 2701 2702 ath_power_restore_power_state(sc); 2703 2704 return (0); 2705 } 2706 2707 static void 2708 ath_stop(struct ath_softc *sc) 2709 { 2710 struct ath_hal *ah = sc->sc_ah; 2711 2712 ATH_LOCK_ASSERT(sc); 2713 2714 /* 2715 * Wake the hardware up before fiddling with it. 2716 */ 2717 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2718 2719 if (sc->sc_running) { 2720 /* 2721 * Shutdown the hardware and driver: 2722 * reset 802.11 state machine 2723 * turn off timers 2724 * disable interrupts 2725 * turn off the radio 2726 * clear transmit machinery 2727 * clear receive machinery 2728 * drain and release tx queues 2729 * reclaim beacon resources 2730 * power down hardware 2731 * 2732 * Note that some of this work is not possible if the 2733 * hardware is gone (invalid). 2734 */ 2735 #ifdef ATH_TX99_DIAG 2736 if (sc->sc_tx99 != NULL) 2737 sc->sc_tx99->stop(sc->sc_tx99); 2738 #endif 2739 callout_stop(&sc->sc_wd_ch); 2740 sc->sc_wd_timer = 0; 2741 sc->sc_running = 0; 2742 if (!sc->sc_invalid) { 2743 if (sc->sc_softled) { 2744 callout_stop(&sc->sc_ledtimer); 2745 ath_hal_gpioset(ah, sc->sc_ledpin, 2746 !sc->sc_ledon); 2747 sc->sc_blinking = 0; 2748 } 2749 ath_hal_intrset(ah, 0); 2750 } 2751 /* XXX we should stop RX regardless of whether it's valid */ 2752 if (!sc->sc_invalid) { 2753 ath_stoprecv(sc, 1); 2754 ath_hal_phydisable(ah); 2755 } else 2756 sc->sc_rxlink = NULL; 2757 ath_draintxq(sc, ATH_RESET_DEFAULT); 2758 ath_beacon_free(sc); /* XXX not needed */ 2759 } 2760 2761 /* And now, restore the current power state */ 2762 ath_power_restore_power_state(sc); 2763 } 2764 2765 /* 2766 * Wait until all pending TX/RX has completed. 2767 * 2768 * This waits until all existing transmit, receive and interrupts 2769 * have completed. It's assumed that the caller has first 2770 * grabbed the reset lock so it doesn't try to do overlapping 2771 * chip resets. 2772 */ 2773 #define MAX_TXRX_ITERATIONS 100 2774 static void 2775 ath_txrx_stop_locked(struct ath_softc *sc) 2776 { 2777 int i = MAX_TXRX_ITERATIONS; 2778 2779 ATH_UNLOCK_ASSERT(sc); 2780 ATH_PCU_LOCK_ASSERT(sc); 2781 2782 /* 2783 * Sleep until all the pending operations have completed. 2784 * 2785 * The caller must ensure that reset has been incremented 2786 * or the pending operations may continue being queued. 2787 */ 2788 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt || 2789 sc->sc_txstart_cnt || sc->sc_intr_cnt) { 2790 if (i <= 0) 2791 break; 2792 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 2793 msecs_to_ticks(10)); 2794 i--; 2795 } 2796 2797 if (i <= 0) 2798 device_printf(sc->sc_dev, 2799 "%s: didn't finish after %d iterations\n", 2800 __func__, MAX_TXRX_ITERATIONS); 2801 } 2802 #undef MAX_TXRX_ITERATIONS 2803 2804 #if 0 2805 static void 2806 ath_txrx_stop(struct ath_softc *sc) 2807 { 2808 ATH_UNLOCK_ASSERT(sc); 2809 ATH_PCU_UNLOCK_ASSERT(sc); 2810 2811 ATH_PCU_LOCK(sc); 2812 ath_txrx_stop_locked(sc); 2813 ATH_PCU_UNLOCK(sc); 2814 } 2815 #endif 2816 2817 static void 2818 ath_txrx_start(struct ath_softc *sc) 2819 { 2820 2821 taskqueue_unblock(sc->sc_tq); 2822 } 2823 2824 /* 2825 * Grab the reset lock, and wait around until no one else 2826 * is trying to do anything with it. 2827 * 2828 * This is totally horrible but we can't hold this lock for 2829 * long enough to do TX/RX or we end up with net80211/ip stack 2830 * LORs and eventual deadlock. 2831 * 2832 * "dowait" signals whether to spin, waiting for the reset 2833 * lock count to reach 0. This should (for now) only be used 2834 * during the reset path, as the rest of the code may not 2835 * be locking-reentrant enough to behave correctly. 2836 * 2837 * Another, cleaner way should be found to serialise all of 2838 * these operations. 2839 */ 2840 #define MAX_RESET_ITERATIONS 25 2841 static int 2842 ath_reset_grablock(struct ath_softc *sc, int dowait) 2843 { 2844 int w = 0; 2845 int i = MAX_RESET_ITERATIONS; 2846 2847 ATH_PCU_LOCK_ASSERT(sc); 2848 do { 2849 if (sc->sc_inreset_cnt == 0) { 2850 w = 1; 2851 break; 2852 } 2853 if (dowait == 0) { 2854 w = 0; 2855 break; 2856 } 2857 ATH_PCU_UNLOCK(sc); 2858 /* 2859 * 1 tick is likely not enough time for long calibrations 2860 * to complete. So we should wait quite a while. 2861 */ 2862 pause("ath_reset_grablock", msecs_to_ticks(100)); 2863 i--; 2864 ATH_PCU_LOCK(sc); 2865 } while (i > 0); 2866 2867 /* 2868 * We always increment the refcounter, regardless 2869 * of whether we succeeded to get it in an exclusive 2870 * way. 2871 */ 2872 sc->sc_inreset_cnt++; 2873 2874 if (i <= 0) 2875 device_printf(sc->sc_dev, 2876 "%s: didn't finish after %d iterations\n", 2877 __func__, MAX_RESET_ITERATIONS); 2878 2879 if (w == 0) 2880 device_printf(sc->sc_dev, 2881 "%s: warning, recursive reset path!\n", 2882 __func__); 2883 2884 return w; 2885 } 2886 #undef MAX_RESET_ITERATIONS 2887 2888 /* 2889 * Reset the hardware w/o losing operational state. This is 2890 * basically a more efficient way of doing ath_stop, ath_init, 2891 * followed by state transitions to the current 802.11 2892 * operational state. Used to recover from various errors and 2893 * to reset or reload hardware state. 2894 */ 2895 int 2896 ath_reset(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 2897 { 2898 struct ieee80211com *ic = &sc->sc_ic; 2899 struct ath_hal *ah = sc->sc_ah; 2900 HAL_STATUS status; 2901 int i; 2902 2903 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 2904 2905 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */ 2906 ATH_PCU_UNLOCK_ASSERT(sc); 2907 ATH_UNLOCK_ASSERT(sc); 2908 2909 /* Try to (stop any further TX/RX from occurring */ 2910 taskqueue_block(sc->sc_tq); 2911 2912 /* 2913 * Wake the hardware up. 2914 */ 2915 ATH_LOCK(sc); 2916 ath_power_set_power_state(sc, HAL_PM_AWAKE); 2917 ATH_UNLOCK(sc); 2918 2919 ATH_PCU_LOCK(sc); 2920 2921 /* 2922 * Grab the reset lock before TX/RX is stopped. 2923 * 2924 * This is needed to ensure that when the TX/RX actually does finish, 2925 * no further TX/RX/reset runs in parallel with this. 2926 */ 2927 if (ath_reset_grablock(sc, 1) == 0) { 2928 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 2929 __func__); 2930 } 2931 2932 /* disable interrupts */ 2933 ath_hal_intrset(ah, 0); 2934 2935 /* 2936 * Now, ensure that any in progress TX/RX completes before we 2937 * continue. 2938 */ 2939 ath_txrx_stop_locked(sc); 2940 2941 ATH_PCU_UNLOCK(sc); 2942 2943 /* 2944 * Regardless of whether we're doing a no-loss flush or 2945 * not, stop the PCU and handle what's in the RX queue. 2946 * That way frames aren't dropped which shouldn't be. 2947 */ 2948 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS)); 2949 ath_rx_flush(sc); 2950 2951 /* 2952 * Should now wait for pending TX/RX to complete 2953 * and block future ones from occurring. This needs to be 2954 * done before the TX queue is drained. 2955 */ 2956 ath_draintxq(sc, reset_type); /* stop xmit side */ 2957 2958 ath_settkipmic(sc); /* configure TKIP MIC handling */ 2959 /* NB: indicate channel change so we do a full reset */ 2960 ath_update_chainmasks(sc, ic->ic_curchan); 2961 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 2962 sc->sc_cur_rxchainmask); 2963 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, 2964 HAL_RESET_NORMAL, &status)) 2965 device_printf(sc->sc_dev, 2966 "%s: unable to reset hardware; hal status %u\n", 2967 __func__, status); 2968 sc->sc_diversity = ath_hal_getdiversity(ah); 2969 2970 ATH_RX_LOCK(sc); 2971 sc->sc_rx_stopped = 1; 2972 sc->sc_rx_resetted = 1; 2973 ATH_RX_UNLOCK(sc); 2974 2975 /* Quiet time handling - ensure we resync */ 2976 ath_vap_clear_quiet_ie(sc); 2977 2978 /* Let DFS at it in case it's a DFS channel */ 2979 ath_dfs_radar_enable(sc, ic->ic_curchan); 2980 2981 /* Let spectral at in case spectral is enabled */ 2982 ath_spectral_enable(sc, ic->ic_curchan); 2983 2984 /* 2985 * Let bluetooth coexistence at in case it's needed for this channel 2986 */ 2987 ath_btcoex_enable(sc, ic->ic_curchan); 2988 2989 /* 2990 * If we're doing TDMA, enforce the TXOP limitation for chips that 2991 * support it. 2992 */ 2993 if (sc->sc_hasenforcetxop && sc->sc_tdma) 2994 ath_hal_setenforcetxop(sc->sc_ah, 1); 2995 else 2996 ath_hal_setenforcetxop(sc->sc_ah, 0); 2997 2998 if (ath_startrecv(sc) != 0) /* restart recv */ 2999 device_printf(sc->sc_dev, 3000 "%s: unable to start recv logic\n", __func__); 3001 /* 3002 * We may be doing a reset in response to an ioctl 3003 * that changes the channel so update any state that 3004 * might change as a result. 3005 */ 3006 ath_chan_change(sc, ic->ic_curchan); 3007 if (sc->sc_beacons) { /* restart beacons */ 3008 #ifdef IEEE80211_SUPPORT_TDMA 3009 if (sc->sc_tdma) 3010 ath_tdma_config(sc, NULL); 3011 else 3012 #endif 3013 ath_beacon_config(sc, NULL); 3014 } 3015 3016 /* 3017 * Release the reset lock and re-enable interrupts here. 3018 * If an interrupt was being processed in ath_intr(), 3019 * it would disable interrupts at this point. So we have 3020 * to atomically enable interrupts and decrement the 3021 * reset counter - this way ath_intr() doesn't end up 3022 * disabling interrupts without a corresponding enable 3023 * in the rest or channel change path. 3024 * 3025 * Grab the TX reference in case we need to transmit. 3026 * That way a parallel transmit doesn't. 3027 */ 3028 ATH_PCU_LOCK(sc); 3029 sc->sc_inreset_cnt--; 3030 sc->sc_txstart_cnt++; 3031 /* XXX only do this if sc_inreset_cnt == 0? */ 3032 ath_hal_intrset(ah, sc->sc_imask); 3033 ATH_PCU_UNLOCK(sc); 3034 3035 /* 3036 * TX and RX can be started here. If it were started with 3037 * sc_inreset_cnt > 0, the TX and RX path would abort. 3038 * Thus if this is a nested call through the reset or 3039 * channel change code, TX completion will occur but 3040 * RX completion and ath_start / ath_tx_start will not 3041 * run. 3042 */ 3043 3044 /* Restart TX/RX as needed */ 3045 ath_txrx_start(sc); 3046 3047 /* XXX TODO: we need to hold the tx refcount here! */ 3048 3049 /* Restart TX completion and pending TX */ 3050 if (reset_type == ATH_RESET_NOLOSS) { 3051 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 3052 if (ATH_TXQ_SETUP(sc, i)) { 3053 ATH_TXQ_LOCK(&sc->sc_txq[i]); 3054 ath_txq_restart_dma(sc, &sc->sc_txq[i]); 3055 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 3056 3057 ATH_TX_LOCK(sc); 3058 ath_txq_sched(sc, &sc->sc_txq[i]); 3059 ATH_TX_UNLOCK(sc); 3060 } 3061 } 3062 } 3063 3064 ATH_LOCK(sc); 3065 ath_power_restore_power_state(sc); 3066 ATH_UNLOCK(sc); 3067 3068 ATH_PCU_LOCK(sc); 3069 sc->sc_txstart_cnt--; 3070 ATH_PCU_UNLOCK(sc); 3071 3072 /* Handle any frames in the TX queue */ 3073 /* 3074 * XXX should this be done by the caller, rather than 3075 * ath_reset() ? 3076 */ 3077 ath_tx_kick(sc); /* restart xmit */ 3078 return 0; 3079 } 3080 3081 static int 3082 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 3083 { 3084 struct ieee80211com *ic = vap->iv_ic; 3085 struct ath_softc *sc = ic->ic_softc; 3086 struct ath_hal *ah = sc->sc_ah; 3087 3088 switch (cmd) { 3089 case IEEE80211_IOC_TXPOWER: 3090 /* 3091 * If per-packet TPC is enabled, then we have nothing 3092 * to do; otherwise we need to force the global limit. 3093 * All this can happen directly; no need to reset. 3094 */ 3095 if (!ath_hal_gettpc(ah)) 3096 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 3097 return 0; 3098 } 3099 /* XXX? Full or NOLOSS? */ 3100 return ath_reset(sc, ATH_RESET_FULL); 3101 } 3102 3103 struct ath_buf * 3104 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype) 3105 { 3106 struct ath_buf *bf; 3107 3108 ATH_TXBUF_LOCK_ASSERT(sc); 3109 3110 if (btype == ATH_BUFTYPE_MGMT) 3111 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt); 3112 else 3113 bf = TAILQ_FIRST(&sc->sc_txbuf); 3114 3115 if (bf == NULL) { 3116 sc->sc_stats.ast_tx_getnobuf++; 3117 } else { 3118 if (bf->bf_flags & ATH_BUF_BUSY) { 3119 sc->sc_stats.ast_tx_getbusybuf++; 3120 bf = NULL; 3121 } 3122 } 3123 3124 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) { 3125 if (btype == ATH_BUFTYPE_MGMT) 3126 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list); 3127 else { 3128 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 3129 sc->sc_txbuf_cnt--; 3130 3131 /* 3132 * This shuldn't happen; however just to be 3133 * safe print a warning and fudge the txbuf 3134 * count. 3135 */ 3136 if (sc->sc_txbuf_cnt < 0) { 3137 device_printf(sc->sc_dev, 3138 "%s: sc_txbuf_cnt < 0?\n", 3139 __func__); 3140 sc->sc_txbuf_cnt = 0; 3141 } 3142 } 3143 } else 3144 bf = NULL; 3145 3146 if (bf == NULL) { 3147 /* XXX should check which list, mgmt or otherwise */ 3148 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 3149 TAILQ_FIRST(&sc->sc_txbuf) == NULL ? 3150 "out of xmit buffers" : "xmit buffer busy"); 3151 return NULL; 3152 } 3153 3154 /* XXX TODO: should do this at buffer list initialisation */ 3155 /* XXX (then, ensure the buffer has the right flag set) */ 3156 bf->bf_flags = 0; 3157 if (btype == ATH_BUFTYPE_MGMT) 3158 bf->bf_flags |= ATH_BUF_MGMT; 3159 else 3160 bf->bf_flags &= (~ATH_BUF_MGMT); 3161 3162 /* Valid bf here; clear some basic fields */ 3163 bf->bf_next = NULL; /* XXX just to be sure */ 3164 bf->bf_last = NULL; /* XXX again, just to be sure */ 3165 bf->bf_comp = NULL; /* XXX again, just to be sure */ 3166 bzero(&bf->bf_state, sizeof(bf->bf_state)); 3167 3168 /* 3169 * Track the descriptor ID only if doing EDMA 3170 */ 3171 if (sc->sc_isedma) { 3172 bf->bf_descid = sc->sc_txbuf_descid; 3173 sc->sc_txbuf_descid++; 3174 } 3175 3176 return bf; 3177 } 3178 3179 /* 3180 * When retrying a software frame, buffers marked ATH_BUF_BUSY 3181 * can't be thrown back on the queue as they could still be 3182 * in use by the hardware. 3183 * 3184 * This duplicates the buffer, or returns NULL. 3185 * 3186 * The descriptor is also copied but the link pointers and 3187 * the DMA segments aren't copied; this frame should thus 3188 * be again passed through the descriptor setup/chain routines 3189 * so the link is correct. 3190 * 3191 * The caller must free the buffer using ath_freebuf(). 3192 */ 3193 struct ath_buf * 3194 ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf) 3195 { 3196 struct ath_buf *tbf; 3197 3198 tbf = ath_getbuf(sc, 3199 (bf->bf_flags & ATH_BUF_MGMT) ? 3200 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL); 3201 if (tbf == NULL) 3202 return NULL; /* XXX failure? Why? */ 3203 3204 /* Copy basics */ 3205 tbf->bf_next = NULL; 3206 tbf->bf_nseg = bf->bf_nseg; 3207 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE; 3208 tbf->bf_status = bf->bf_status; 3209 tbf->bf_m = bf->bf_m; 3210 tbf->bf_node = bf->bf_node; 3211 KASSERT((bf->bf_node != NULL), ("%s: bf_node=NULL!", __func__)); 3212 /* will be setup by the chain/setup function */ 3213 tbf->bf_lastds = NULL; 3214 /* for now, last == self */ 3215 tbf->bf_last = tbf; 3216 tbf->bf_comp = bf->bf_comp; 3217 3218 /* NOTE: DMA segments will be setup by the setup/chain functions */ 3219 3220 /* The caller has to re-init the descriptor + links */ 3221 3222 /* 3223 * Free the DMA mapping here, before we NULL the mbuf. 3224 * We must only call bus_dmamap_unload() once per mbuf chain 3225 * or behaviour is undefined. 3226 */ 3227 if (bf->bf_m != NULL) { 3228 /* 3229 * XXX is this POSTWRITE call required? 3230 */ 3231 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3232 BUS_DMASYNC_POSTWRITE); 3233 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3234 } 3235 3236 bf->bf_m = NULL; 3237 bf->bf_node = NULL; 3238 3239 /* Copy state */ 3240 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state)); 3241 3242 return tbf; 3243 } 3244 3245 struct ath_buf * 3246 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype) 3247 { 3248 struct ath_buf *bf; 3249 3250 ATH_TXBUF_LOCK(sc); 3251 bf = _ath_getbuf_locked(sc, btype); 3252 /* 3253 * If a mgmt buffer was requested but we're out of those, 3254 * try requesting a normal one. 3255 */ 3256 if (bf == NULL && btype == ATH_BUFTYPE_MGMT) 3257 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 3258 ATH_TXBUF_UNLOCK(sc); 3259 if (bf == NULL) { 3260 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 3261 sc->sc_stats.ast_tx_qstop++; 3262 } 3263 return bf; 3264 } 3265 3266 /* 3267 * Transmit a single frame. 3268 * 3269 * net80211 will free the node reference if the transmit 3270 * fails, so don't free the node reference here. 3271 */ 3272 static int 3273 ath_transmit(struct ieee80211com *ic, struct mbuf *m) 3274 { 3275 struct ath_softc *sc = ic->ic_softc; 3276 struct ieee80211_node *ni; 3277 struct mbuf *next; 3278 struct ath_buf *bf; 3279 ath_bufhead frags; 3280 int retval = 0; 3281 3282 /* 3283 * Tell the reset path that we're currently transmitting. 3284 */ 3285 ATH_PCU_LOCK(sc); 3286 if (sc->sc_inreset_cnt > 0) { 3287 DPRINTF(sc, ATH_DEBUG_XMIT, 3288 "%s: sc_inreset_cnt > 0; bailing\n", __func__); 3289 ATH_PCU_UNLOCK(sc); 3290 sc->sc_stats.ast_tx_qstop++; 3291 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish"); 3292 return (ENOBUFS); /* XXX should be EINVAL or? */ 3293 } 3294 sc->sc_txstart_cnt++; 3295 ATH_PCU_UNLOCK(sc); 3296 3297 /* Wake the hardware up already */ 3298 ATH_LOCK(sc); 3299 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3300 ATH_UNLOCK(sc); 3301 3302 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: start"); 3303 /* 3304 * Grab the TX lock - it's ok to do this here; we haven't 3305 * yet started transmitting. 3306 */ 3307 ATH_TX_LOCK(sc); 3308 3309 /* 3310 * Node reference, if there's one. 3311 */ 3312 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 3313 3314 /* 3315 * Enforce how deep a node queue can get. 3316 * 3317 * XXX it would be nicer if we kept an mbuf queue per 3318 * node and only whacked them into ath_bufs when we 3319 * are ready to schedule some traffic from them. 3320 * .. that may come later. 3321 * 3322 * XXX we should also track the per-node hardware queue 3323 * depth so it is easy to limit the _SUM_ of the swq and 3324 * hwq frames. Since we only schedule two HWQ frames 3325 * at a time, this should be OK for now. 3326 */ 3327 if ((!(m->m_flags & M_EAPOL)) && 3328 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) { 3329 sc->sc_stats.ast_tx_nodeq_overflow++; 3330 retval = ENOBUFS; 3331 goto finish; 3332 } 3333 3334 /* 3335 * Check how many TX buffers are available. 3336 * 3337 * If this is for non-EAPOL traffic, just leave some 3338 * space free in order for buffer cloning and raw 3339 * frame transmission to occur. 3340 * 3341 * If it's for EAPOL traffic, ignore this for now. 3342 * Management traffic will be sent via the raw transmit 3343 * method which bypasses this check. 3344 * 3345 * This is needed to ensure that EAPOL frames during 3346 * (re) keying have a chance to go out. 3347 * 3348 * See kern/138379 for more information. 3349 */ 3350 if ((!(m->m_flags & M_EAPOL)) && 3351 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) { 3352 sc->sc_stats.ast_tx_nobuf++; 3353 retval = ENOBUFS; 3354 goto finish; 3355 } 3356 3357 /* 3358 * Grab a TX buffer and associated resources. 3359 * 3360 * If it's an EAPOL frame, allocate a MGMT ath_buf. 3361 * That way even with temporary buffer exhaustion due to 3362 * the data path doesn't leave us without the ability 3363 * to transmit management frames. 3364 * 3365 * Otherwise allocate a normal buffer. 3366 */ 3367 if (m->m_flags & M_EAPOL) 3368 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT); 3369 else 3370 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL); 3371 3372 if (bf == NULL) { 3373 /* 3374 * If we failed to allocate a buffer, fail. 3375 * 3376 * We shouldn't fail normally, due to the check 3377 * above. 3378 */ 3379 sc->sc_stats.ast_tx_nobuf++; 3380 retval = ENOBUFS; 3381 goto finish; 3382 } 3383 3384 /* 3385 * At this point we have a buffer; so we need to free it 3386 * if we hit any error conditions. 3387 */ 3388 3389 /* 3390 * Check for fragmentation. If this frame 3391 * has been broken up verify we have enough 3392 * buffers to send all the fragments so all 3393 * go out or none... 3394 */ 3395 TAILQ_INIT(&frags); 3396 if ((m->m_flags & M_FRAG) && 3397 !ath_txfrag_setup(sc, &frags, m, ni)) { 3398 DPRINTF(sc, ATH_DEBUG_XMIT, 3399 "%s: out of txfrag buffers\n", __func__); 3400 sc->sc_stats.ast_tx_nofrag++; 3401 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 3402 /* 3403 * XXXGL: is mbuf valid after ath_txfrag_setup? If yes, 3404 * we shouldn't free it but return back. 3405 */ 3406 ieee80211_free_mbuf(m); 3407 m = NULL; 3408 goto bad; 3409 } 3410 3411 /* 3412 * At this point if we have any TX fragments, then we will 3413 * have bumped the node reference once for each of those. 3414 */ 3415 3416 /* 3417 * XXX Is there anything actually _enforcing_ that the 3418 * fragments are being transmitted in one hit, rather than 3419 * being interleaved with other transmissions on that 3420 * hardware queue? 3421 * 3422 * The ATH TX output lock is the only thing serialising this 3423 * right now. 3424 */ 3425 3426 /* 3427 * Calculate the "next fragment" length field in ath_buf 3428 * in order to let the transmit path know enough about 3429 * what to next write to the hardware. 3430 */ 3431 if (m->m_flags & M_FRAG) { 3432 struct ath_buf *fbf = bf; 3433 struct ath_buf *n_fbf = NULL; 3434 struct mbuf *fm = m->m_nextpkt; 3435 3436 /* 3437 * We need to walk the list of fragments and set 3438 * the next size to the following buffer. 3439 * However, the first buffer isn't in the frag 3440 * list, so we have to do some gymnastics here. 3441 */ 3442 TAILQ_FOREACH(n_fbf, &frags, bf_list) { 3443 fbf->bf_nextfraglen = fm->m_pkthdr.len; 3444 fbf = n_fbf; 3445 fm = fm->m_nextpkt; 3446 } 3447 } 3448 3449 nextfrag: 3450 /* 3451 * Pass the frame to the h/w for transmission. 3452 * Fragmented frames have each frag chained together 3453 * with m_nextpkt. We know there are sufficient ath_buf's 3454 * to send all the frags because of work done by 3455 * ath_txfrag_setup. We leave m_nextpkt set while 3456 * calling ath_tx_start so it can use it to extend the 3457 * the tx duration to cover the subsequent frag and 3458 * so it can reclaim all the mbufs in case of an error; 3459 * ath_tx_start clears m_nextpkt once it commits to 3460 * handing the frame to the hardware. 3461 * 3462 * Note: if this fails, then the mbufs are freed but 3463 * not the node reference. 3464 * 3465 * So, we now have to free the node reference ourselves here 3466 * and return OK up to the stack. 3467 */ 3468 next = m->m_nextpkt; 3469 if (ath_tx_start(sc, ni, bf, m)) { 3470 bad: 3471 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 3472 reclaim: 3473 bf->bf_m = NULL; 3474 bf->bf_node = NULL; 3475 ATH_TXBUF_LOCK(sc); 3476 ath_returnbuf_head(sc, bf); 3477 /* 3478 * Free the rest of the node references and 3479 * buffers for the fragment list. 3480 */ 3481 ath_txfrag_cleanup(sc, &frags, ni); 3482 ATH_TXBUF_UNLOCK(sc); 3483 3484 /* 3485 * XXX: And free the node/return OK; ath_tx_start() may have 3486 * modified the buffer. We currently have no way to 3487 * signify that the mbuf was freed but there was an error. 3488 */ 3489 ieee80211_free_node(ni); 3490 retval = 0; 3491 goto finish; 3492 } 3493 3494 /* 3495 * Check here if the node is in power save state. 3496 */ 3497 ath_tx_update_tim(sc, ni, 1); 3498 3499 if (next != NULL) { 3500 /* 3501 * Beware of state changing between frags. 3502 * XXX check sta power-save state? 3503 */ 3504 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 3505 DPRINTF(sc, ATH_DEBUG_XMIT, 3506 "%s: flush fragmented packet, state %s\n", 3507 __func__, 3508 ieee80211_state_name[ni->ni_vap->iv_state]); 3509 /* XXX dmamap */ 3510 ieee80211_free_mbuf(next); 3511 goto reclaim; 3512 } 3513 m = next; 3514 bf = TAILQ_FIRST(&frags); 3515 KASSERT(bf != NULL, ("no buf for txfrag")); 3516 TAILQ_REMOVE(&frags, bf, bf_list); 3517 goto nextfrag; 3518 } 3519 3520 /* 3521 * Bump watchdog timer. 3522 */ 3523 sc->sc_wd_timer = 5; 3524 3525 finish: 3526 ATH_TX_UNLOCK(sc); 3527 3528 /* 3529 * Finished transmitting! 3530 */ 3531 ATH_PCU_LOCK(sc); 3532 sc->sc_txstart_cnt--; 3533 ATH_PCU_UNLOCK(sc); 3534 3535 /* Sleep the hardware if required */ 3536 ATH_LOCK(sc); 3537 ath_power_restore_power_state(sc); 3538 ATH_UNLOCK(sc); 3539 3540 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: finished"); 3541 3542 return (retval); 3543 } 3544 3545 static int 3546 ath_media_change(struct ifnet *ifp) 3547 { 3548 int error = ieee80211_media_change(ifp); 3549 /* NB: only the fixed rate can change and that doesn't need a reset */ 3550 return (error == ENETRESET ? 0 : error); 3551 } 3552 3553 /* 3554 * Block/unblock tx+rx processing while a key change is done. 3555 * We assume the caller serializes key management operations 3556 * so we only need to worry about synchronization with other 3557 * uses that originate in the driver. 3558 */ 3559 static void 3560 ath_key_update_begin(struct ieee80211vap *vap) 3561 { 3562 struct ath_softc *sc = vap->iv_ic->ic_softc; 3563 3564 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 3565 taskqueue_block(sc->sc_tq); 3566 } 3567 3568 static void 3569 ath_key_update_end(struct ieee80211vap *vap) 3570 { 3571 struct ath_softc *sc = vap->iv_ic->ic_softc; 3572 3573 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 3574 taskqueue_unblock(sc->sc_tq); 3575 } 3576 3577 static void 3578 ath_update_promisc(struct ieee80211com *ic) 3579 { 3580 struct ath_softc *sc = ic->ic_softc; 3581 u_int32_t rfilt; 3582 3583 /* configure rx filter */ 3584 ATH_LOCK(sc); 3585 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3586 rfilt = ath_calcrxfilter(sc); 3587 ath_hal_setrxfilter(sc->sc_ah, rfilt); 3588 ath_power_restore_power_state(sc); 3589 ATH_UNLOCK(sc); 3590 3591 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 3592 } 3593 3594 static u_int 3595 ath_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3596 { 3597 uint32_t val, *mfilt = arg; 3598 char *dl; 3599 uint8_t pos; 3600 3601 /* calculate XOR of eight 6bit values */ 3602 dl = LLADDR(sdl); 3603 val = le32dec(dl + 0); 3604 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 3605 val = le32dec(dl + 3); 3606 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 3607 pos &= 0x3f; 3608 mfilt[pos / 32] |= (1 << (pos % 32)); 3609 3610 return (1); 3611 } 3612 3613 /* 3614 * Driver-internal mcast update call. 3615 * 3616 * Assumes the hardware is already awake. 3617 */ 3618 static void 3619 ath_update_mcast_hw(struct ath_softc *sc) 3620 { 3621 struct ieee80211com *ic = &sc->sc_ic; 3622 u_int32_t mfilt[2]; 3623 3624 /* calculate and install multicast filter */ 3625 if (ic->ic_allmulti == 0) { 3626 struct ieee80211vap *vap; 3627 3628 /* 3629 * Merge multicast addresses to form the hardware filter. 3630 */ 3631 mfilt[0] = mfilt[1] = 0; 3632 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) 3633 if_foreach_llmaddr(vap->iv_ifp, ath_hash_maddr, &mfilt); 3634 } else 3635 mfilt[0] = mfilt[1] = ~0; 3636 3637 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 3638 3639 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 3640 __func__, mfilt[0], mfilt[1]); 3641 } 3642 3643 /* 3644 * Called from the net80211 layer - force the hardware 3645 * awake before operating. 3646 */ 3647 static void 3648 ath_update_mcast(struct ieee80211com *ic) 3649 { 3650 struct ath_softc *sc = ic->ic_softc; 3651 3652 ATH_LOCK(sc); 3653 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3654 ATH_UNLOCK(sc); 3655 3656 ath_update_mcast_hw(sc); 3657 3658 ATH_LOCK(sc); 3659 ath_power_restore_power_state(sc); 3660 ATH_UNLOCK(sc); 3661 } 3662 3663 void 3664 ath_mode_init(struct ath_softc *sc) 3665 { 3666 struct ieee80211com *ic = &sc->sc_ic; 3667 struct ath_hal *ah = sc->sc_ah; 3668 u_int32_t rfilt; 3669 3670 /* XXX power state? */ 3671 3672 /* configure rx filter */ 3673 rfilt = ath_calcrxfilter(sc); 3674 ath_hal_setrxfilter(ah, rfilt); 3675 3676 /* configure operational mode */ 3677 ath_hal_setopmode(ah); 3678 3679 /* handle any link-level address change */ 3680 ath_hal_setmac(ah, ic->ic_macaddr); 3681 3682 /* calculate and install multicast filter */ 3683 ath_update_mcast_hw(sc); 3684 } 3685 3686 /* 3687 * Set the slot time based on the current setting. 3688 */ 3689 void 3690 ath_setslottime(struct ath_softc *sc) 3691 { 3692 struct ieee80211com *ic = &sc->sc_ic; 3693 struct ath_hal *ah = sc->sc_ah; 3694 u_int usec; 3695 3696 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 3697 usec = 13; 3698 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 3699 usec = 21; 3700 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 3701 /* honor short/long slot time only in 11g */ 3702 /* XXX shouldn't honor on pure g or turbo g channel */ 3703 if (ic->ic_flags & IEEE80211_F_SHSLOT) 3704 usec = HAL_SLOT_TIME_9; 3705 else 3706 usec = HAL_SLOT_TIME_20; 3707 } else 3708 usec = HAL_SLOT_TIME_9; 3709 3710 DPRINTF(sc, ATH_DEBUG_RESET, 3711 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 3712 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 3713 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 3714 3715 /* Wake up the hardware first before updating the slot time */ 3716 ATH_LOCK(sc); 3717 ath_power_set_power_state(sc, HAL_PM_AWAKE); 3718 ath_hal_setslottime(ah, usec); 3719 ath_power_restore_power_state(sc); 3720 sc->sc_updateslot = OK; 3721 ATH_UNLOCK(sc); 3722 } 3723 3724 /* 3725 * Callback from the 802.11 layer to update the 3726 * slot time based on the current setting. 3727 */ 3728 static void 3729 ath_updateslot(struct ieee80211com *ic) 3730 { 3731 struct ath_softc *sc = ic->ic_softc; 3732 3733 /* 3734 * When not coordinating the BSS, change the hardware 3735 * immediately. For other operation we defer the change 3736 * until beacon updates have propagated to the stations. 3737 * 3738 * XXX sc_updateslot isn't changed behind a lock? 3739 */ 3740 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3741 ic->ic_opmode == IEEE80211_M_MBSS) 3742 sc->sc_updateslot = UPDATE; 3743 else 3744 ath_setslottime(sc); 3745 } 3746 3747 /* 3748 * Append the contents of src to dst; both queues 3749 * are assumed to be locked. 3750 */ 3751 void 3752 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 3753 { 3754 3755 ATH_TXQ_LOCK_ASSERT(src); 3756 ATH_TXQ_LOCK_ASSERT(dst); 3757 3758 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list); 3759 dst->axq_link = src->axq_link; 3760 src->axq_link = NULL; 3761 dst->axq_depth += src->axq_depth; 3762 dst->axq_aggr_depth += src->axq_aggr_depth; 3763 src->axq_depth = 0; 3764 src->axq_aggr_depth = 0; 3765 } 3766 3767 /* 3768 * Reset the hardware, with no loss. 3769 * 3770 * This can't be used for a general case reset. 3771 */ 3772 static void 3773 ath_reset_proc(void *arg, int pending) 3774 { 3775 struct ath_softc *sc = arg; 3776 3777 #if 0 3778 device_printf(sc->sc_dev, "%s: resetting\n", __func__); 3779 #endif 3780 ath_reset(sc, ATH_RESET_NOLOSS); 3781 } 3782 3783 /* 3784 * Reset the hardware after detecting beacons have stopped. 3785 */ 3786 static void 3787 ath_bstuck_proc(void *arg, int pending) 3788 { 3789 struct ath_softc *sc = arg; 3790 uint32_t hangs = 0; 3791 3792 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) 3793 device_printf(sc->sc_dev, "bb hang detected (0x%x)\n", hangs); 3794 3795 #ifdef ATH_DEBUG_ALQ 3796 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON)) 3797 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL); 3798 #endif 3799 3800 device_printf(sc->sc_dev, "stuck beacon; resetting (bmiss count %u)\n", 3801 sc->sc_bmisscount); 3802 sc->sc_stats.ast_bstuck++; 3803 /* 3804 * This assumes that there's no simultaneous channel mode change 3805 * occurring. 3806 */ 3807 ath_reset(sc, ATH_RESET_NOLOSS); 3808 } 3809 3810 static int 3811 ath_desc_alloc(struct ath_softc *sc) 3812 { 3813 int error; 3814 3815 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3816 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER); 3817 if (error != 0) { 3818 return error; 3819 } 3820 sc->sc_txbuf_cnt = ath_txbuf; 3821 3822 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt, 3823 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt, 3824 ATH_TXDESC); 3825 if (error != 0) { 3826 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3827 return error; 3828 } 3829 3830 /* 3831 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the 3832 * flag doesn't have to be set in ath_getbuf_locked(). 3833 */ 3834 3835 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3836 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1); 3837 if (error != 0) { 3838 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3839 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3840 &sc->sc_txbuf_mgmt); 3841 return error; 3842 } 3843 return 0; 3844 } 3845 3846 static void 3847 ath_desc_free(struct ath_softc *sc) 3848 { 3849 3850 if (sc->sc_bdma.dd_desc_len != 0) 3851 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3852 if (sc->sc_txdma.dd_desc_len != 0) 3853 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3854 if (sc->sc_txdma_mgmt.dd_desc_len != 0) 3855 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt, 3856 &sc->sc_txbuf_mgmt); 3857 } 3858 3859 static struct ieee80211_node * 3860 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3861 { 3862 struct ieee80211com *ic = vap->iv_ic; 3863 struct ath_softc *sc = ic->ic_softc; 3864 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3865 struct ath_node *an; 3866 3867 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3868 if (an == NULL) { 3869 /* XXX stat+msg */ 3870 return NULL; 3871 } 3872 ath_rate_node_init(sc, an); 3873 3874 /* Setup the mutex - there's no associd yet so set the name to NULL */ 3875 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p", 3876 device_get_nameunit(sc->sc_dev), an); 3877 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF); 3878 3879 /* XXX setup ath_tid */ 3880 ath_tx_tid_init(sc, an); 3881 3882 an->an_node_stats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 3883 an->an_node_stats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 3884 an->an_node_stats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 3885 3886 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an); 3887 return &an->an_node; 3888 } 3889 3890 static void 3891 ath_node_cleanup(struct ieee80211_node *ni) 3892 { 3893 struct ieee80211com *ic = ni->ni_ic; 3894 struct ath_softc *sc = ic->ic_softc; 3895 3896 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, 3897 ni->ni_macaddr, ":", ATH_NODE(ni)); 3898 3899 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */ 3900 ath_tx_node_flush(sc, ATH_NODE(ni)); 3901 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3902 sc->sc_node_cleanup(ni); 3903 } 3904 3905 static void 3906 ath_node_free(struct ieee80211_node *ni) 3907 { 3908 struct ieee80211com *ic = ni->ni_ic; 3909 struct ath_softc *sc = ic->ic_softc; 3910 3911 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, 3912 ni->ni_macaddr, ":", ATH_NODE(ni)); 3913 mtx_destroy(&ATH_NODE(ni)->an_mtx); 3914 sc->sc_node_free(ni); 3915 } 3916 3917 static void 3918 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3919 { 3920 struct ieee80211com *ic = ni->ni_ic; 3921 struct ath_softc *sc = ic->ic_softc; 3922 struct ath_hal *ah = sc->sc_ah; 3923 3924 *rssi = ic->ic_node_getrssi(ni); 3925 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3926 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3927 else 3928 *noise = -95; /* nominally correct */ 3929 } 3930 3931 /* 3932 * Set the default antenna. 3933 */ 3934 void 3935 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3936 { 3937 struct ath_hal *ah = sc->sc_ah; 3938 3939 /* XXX block beacon interrupts */ 3940 ath_hal_setdefantenna(ah, antenna); 3941 if (sc->sc_defant != antenna) 3942 sc->sc_stats.ast_ant_defswitch++; 3943 sc->sc_defant = antenna; 3944 sc->sc_rxotherant = 0; 3945 } 3946 3947 static void 3948 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 3949 { 3950 txq->axq_qnum = qnum; 3951 txq->axq_ac = 0; 3952 txq->axq_depth = 0; 3953 txq->axq_aggr_depth = 0; 3954 txq->axq_intrcnt = 0; 3955 txq->axq_link = NULL; 3956 txq->axq_softc = sc; 3957 TAILQ_INIT(&txq->axq_q); 3958 TAILQ_INIT(&txq->axq_tidq); 3959 TAILQ_INIT(&txq->fifo.axq_q); 3960 ATH_TXQ_LOCK_INIT(sc, txq); 3961 } 3962 3963 /* 3964 * Setup a h/w transmit queue. 3965 */ 3966 static struct ath_txq * 3967 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3968 { 3969 struct ath_hal *ah = sc->sc_ah; 3970 HAL_TXQ_INFO qi; 3971 int qnum; 3972 3973 memset(&qi, 0, sizeof(qi)); 3974 qi.tqi_subtype = subtype; 3975 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3976 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3977 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3978 /* 3979 * Enable interrupts only for EOL and DESC conditions. 3980 * We mark tx descriptors to receive a DESC interrupt 3981 * when a tx queue gets deep; otherwise waiting for the 3982 * EOL to reap descriptors. Note that this is done to 3983 * reduce interrupt load and this only defers reaping 3984 * descriptors, never transmitting frames. Aside from 3985 * reducing interrupts this also permits more concurrency. 3986 * The only potential downside is if the tx queue backs 3987 * up in which case the top half of the kernel may backup 3988 * due to a lack of tx descriptors. 3989 */ 3990 if (sc->sc_isedma) 3991 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | 3992 HAL_TXQ_TXOKINT_ENABLE; 3993 else 3994 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | 3995 HAL_TXQ_TXDESCINT_ENABLE; 3996 3997 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3998 if (qnum == -1) { 3999 /* 4000 * NB: don't print a message, this happens 4001 * normally on parts with too few tx queues 4002 */ 4003 return NULL; 4004 } 4005 if (qnum >= nitems(sc->sc_txq)) { 4006 device_printf(sc->sc_dev, 4007 "hal qnum %u out of range, max %zu!\n", 4008 qnum, nitems(sc->sc_txq)); 4009 ath_hal_releasetxqueue(ah, qnum); 4010 return NULL; 4011 } 4012 if (!ATH_TXQ_SETUP(sc, qnum)) { 4013 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4014 sc->sc_txqsetup |= 1<<qnum; 4015 } 4016 return &sc->sc_txq[qnum]; 4017 } 4018 4019 /* 4020 * Setup a hardware data transmit queue for the specified 4021 * access control. The hal may not support all requested 4022 * queues in which case it will return a reference to a 4023 * previously setup queue. We record the mapping from ac's 4024 * to h/w queues for use by ath_tx_start and also track 4025 * the set of h/w queues being used to optimize work in the 4026 * transmit interrupt handler and related routines. 4027 */ 4028 static int 4029 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4030 { 4031 struct ath_txq *txq; 4032 4033 if (ac >= nitems(sc->sc_ac2q)) { 4034 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4035 ac, nitems(sc->sc_ac2q)); 4036 return 0; 4037 } 4038 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4039 if (txq != NULL) { 4040 txq->axq_ac = ac; 4041 sc->sc_ac2q[ac] = txq; 4042 return 1; 4043 } else 4044 return 0; 4045 } 4046 4047 /* 4048 * Update WME parameters for a transmit queue. 4049 */ 4050 static int 4051 ath_txq_update(struct ath_softc *sc, int ac) 4052 { 4053 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4054 struct ieee80211com *ic = &sc->sc_ic; 4055 struct ath_txq *txq = sc->sc_ac2q[ac]; 4056 struct chanAccParams chp; 4057 struct wmeParams *wmep; 4058 struct ath_hal *ah = sc->sc_ah; 4059 HAL_TXQ_INFO qi; 4060 4061 ieee80211_wme_ic_getparams(ic, &chp); 4062 wmep = &chp.cap_wmeParams[ac]; 4063 4064 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4065 #ifdef IEEE80211_SUPPORT_TDMA 4066 if (sc->sc_tdma) { 4067 /* 4068 * AIFS is zero so there's no pre-transmit wait. The 4069 * burst time defines the slot duration and is configured 4070 * through net80211. The QCU is setup to not do post-xmit 4071 * back off, lockout all lower-priority QCU's, and fire 4072 * off the DMA beacon alert timer which is setup based 4073 * on the slot configuration. 4074 */ 4075 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4076 | HAL_TXQ_TXERRINT_ENABLE 4077 | HAL_TXQ_TXURNINT_ENABLE 4078 | HAL_TXQ_TXEOLINT_ENABLE 4079 | HAL_TXQ_DBA_GATED 4080 | HAL_TXQ_BACKOFF_DISABLE 4081 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4082 ; 4083 qi.tqi_aifs = 0; 4084 /* XXX +dbaprep? */ 4085 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4086 qi.tqi_burstTime = qi.tqi_readyTime; 4087 } else { 4088 #endif 4089 /* 4090 * XXX shouldn't this just use the default flags 4091 * used in the previous queue setup? 4092 */ 4093 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4094 | HAL_TXQ_TXERRINT_ENABLE 4095 | HAL_TXQ_TXDESCINT_ENABLE 4096 | HAL_TXQ_TXURNINT_ENABLE 4097 | HAL_TXQ_TXEOLINT_ENABLE 4098 ; 4099 qi.tqi_aifs = wmep->wmep_aifsn; 4100 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4101 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4102 qi.tqi_readyTime = 0; 4103 qi.tqi_burstTime = IEEE80211_TXOP_TO_US(wmep->wmep_txopLimit); 4104 #ifdef IEEE80211_SUPPORT_TDMA 4105 } 4106 #endif 4107 4108 DPRINTF(sc, ATH_DEBUG_RESET, 4109 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4110 __func__, txq->axq_qnum, qi.tqi_qflags, 4111 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4112 4113 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4114 device_printf(sc->sc_dev, "unable to update hardware queue " 4115 "parameters for %s traffic!\n", ieee80211_wme_acnames[ac]); 4116 return 0; 4117 } else { 4118 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4119 return 1; 4120 } 4121 #undef ATH_EXPONENT_TO_VALUE 4122 } 4123 4124 /* 4125 * Callback from the 802.11 layer to update WME parameters. 4126 */ 4127 int 4128 ath_wme_update(struct ieee80211com *ic) 4129 { 4130 struct ath_softc *sc = ic->ic_softc; 4131 4132 return !ath_txq_update(sc, WME_AC_BE) || 4133 !ath_txq_update(sc, WME_AC_BK) || 4134 !ath_txq_update(sc, WME_AC_VI) || 4135 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4136 } 4137 4138 /* 4139 * Reclaim resources for a setup queue. 4140 */ 4141 static void 4142 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4143 { 4144 4145 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4146 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4147 ATH_TXQ_LOCK_DESTROY(txq); 4148 } 4149 4150 /* 4151 * Reclaim all tx queue resources. 4152 */ 4153 static void 4154 ath_tx_cleanup(struct ath_softc *sc) 4155 { 4156 int i; 4157 4158 ATH_TXBUF_LOCK_DESTROY(sc); 4159 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4160 if (ATH_TXQ_SETUP(sc, i)) 4161 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4162 } 4163 4164 /* 4165 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 4166 * using the current rates in sc_rixmap. 4167 */ 4168 int 4169 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 4170 { 4171 int rix = sc->sc_rixmap[rate]; 4172 /* NB: return lowest rix for invalid rate */ 4173 return (rix == 0xff ? 0 : rix); 4174 } 4175 4176 static void 4177 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts, 4178 struct ath_buf *bf) 4179 { 4180 struct ieee80211_node *ni = bf->bf_node; 4181 struct ieee80211com *ic = &sc->sc_ic; 4182 int sr, lr, pri; 4183 4184 if (ts->ts_status == 0) { 4185 u_int8_t txant = ts->ts_antenna; 4186 sc->sc_stats.ast_ant_tx[txant]++; 4187 sc->sc_ant_tx[txant]++; 4188 if (ts->ts_finaltsi != 0) 4189 sc->sc_stats.ast_tx_altrate++; 4190 4191 /* XXX TODO: should do per-pri conuters */ 4192 pri = M_WME_GETAC(bf->bf_m); 4193 if (pri >= WME_AC_VO) 4194 ic->ic_wme.wme_hipri_traffic++; 4195 4196 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) 4197 ni->ni_inact = ni->ni_inact_reload; 4198 } else { 4199 if (ts->ts_status & HAL_TXERR_XRETRY) 4200 sc->sc_stats.ast_tx_xretries++; 4201 if (ts->ts_status & HAL_TXERR_FIFO) 4202 sc->sc_stats.ast_tx_fifoerr++; 4203 if (ts->ts_status & HAL_TXERR_FILT) 4204 sc->sc_stats.ast_tx_filtered++; 4205 if (ts->ts_status & HAL_TXERR_XTXOP) 4206 sc->sc_stats.ast_tx_xtxop++; 4207 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED) 4208 sc->sc_stats.ast_tx_timerexpired++; 4209 4210 if (bf->bf_m->m_flags & M_FF) 4211 sc->sc_stats.ast_ff_txerr++; 4212 } 4213 /* XXX when is this valid? */ 4214 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR) 4215 sc->sc_stats.ast_tx_desccfgerr++; 4216 /* 4217 * This can be valid for successful frame transmission! 4218 * If there's a TX FIFO underrun during aggregate transmission, 4219 * the MAC will pad the rest of the aggregate with delimiters. 4220 * If a BA is returned, the frame is marked as "OK" and it's up 4221 * to the TX completion code to notice which frames weren't 4222 * successfully transmitted. 4223 */ 4224 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN) 4225 sc->sc_stats.ast_tx_data_underrun++; 4226 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN) 4227 sc->sc_stats.ast_tx_delim_underrun++; 4228 4229 sr = ts->ts_shortretry; 4230 lr = ts->ts_longretry; 4231 sc->sc_stats.ast_tx_shortretry += sr; 4232 sc->sc_stats.ast_tx_longretry += lr; 4233 4234 } 4235 4236 /* 4237 * The default completion. If fail is 1, this means 4238 * "please don't retry the frame, and just return -1 status 4239 * to the net80211 stack. 4240 */ 4241 void 4242 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 4243 { 4244 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 4245 int st; 4246 4247 if (fail == 1) 4248 st = -1; 4249 else 4250 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ? 4251 ts->ts_status : HAL_TXERR_XRETRY; 4252 4253 #if 0 4254 if (bf->bf_state.bfs_dobaw) 4255 device_printf(sc->sc_dev, 4256 "%s: bf %p: seqno %d: dobaw should've been cleared!\n", 4257 __func__, 4258 bf, 4259 SEQNO(bf->bf_state.bfs_seqno)); 4260 #endif 4261 if (bf->bf_next != NULL) 4262 device_printf(sc->sc_dev, 4263 "%s: bf %p: seqno %d: bf_next not NULL!\n", 4264 __func__, 4265 bf, 4266 SEQNO(bf->bf_state.bfs_seqno)); 4267 4268 /* 4269 * Check if the node software queue is empty; if so 4270 * then clear the TIM. 4271 * 4272 * This needs to be done before the buffer is freed as 4273 * otherwise the node reference will have been released 4274 * and the node may not actually exist any longer. 4275 * 4276 * XXX I don't like this belonging here, but it's cleaner 4277 * to do it here right now then all the other places 4278 * where ath_tx_default_comp() is called. 4279 * 4280 * XXX TODO: during drain, ensure that the callback is 4281 * being called so we get a chance to update the TIM. 4282 */ 4283 if (bf->bf_node) { 4284 ATH_TX_LOCK(sc); 4285 ath_tx_update_tim(sc, bf->bf_node, 0); 4286 ATH_TX_UNLOCK(sc); 4287 } 4288 4289 /* 4290 * Do any tx complete callback. Note this must 4291 * be done before releasing the node reference. 4292 * This will free the mbuf, release the net80211 4293 * node and recycle the ath_buf. 4294 */ 4295 ath_tx_freebuf(sc, bf, st); 4296 } 4297 4298 /* 4299 * Update rate control with the given completion status. 4300 */ 4301 void 4302 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 4303 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen, 4304 int nframes, int nbad) 4305 { 4306 struct ath_node *an; 4307 4308 /* Only for unicast frames */ 4309 if (ni == NULL) 4310 return; 4311 4312 an = ATH_NODE(ni); 4313 ATH_NODE_UNLOCK_ASSERT(an); 4314 4315 if ((ts->ts_status & HAL_TXERR_FILT) == 0) { 4316 ATH_NODE_LOCK(an); 4317 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad); 4318 ATH_NODE_UNLOCK(an); 4319 } 4320 } 4321 4322 /* 4323 * Process the completion of the given buffer. 4324 * 4325 * This calls the rate control update and then the buffer completion. 4326 * This will either free the buffer or requeue it. In any case, the 4327 * bf pointer should be treated as invalid after this function is called. 4328 */ 4329 void 4330 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq, 4331 struct ath_tx_status *ts, struct ath_buf *bf) 4332 { 4333 struct ieee80211_node *ni = bf->bf_node; 4334 4335 ATH_TX_UNLOCK_ASSERT(sc); 4336 ATH_TXQ_UNLOCK_ASSERT(txq); 4337 4338 /* If unicast frame, update general statistics */ 4339 if (ni != NULL) { 4340 /* update statistics */ 4341 ath_tx_update_stats(sc, ts, bf); 4342 } 4343 4344 /* 4345 * Call the completion handler. 4346 * The completion handler is responsible for 4347 * calling the rate control code. 4348 * 4349 * Frames with no completion handler get the 4350 * rate control code called here. 4351 */ 4352 if (bf->bf_comp == NULL) { 4353 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4354 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) { 4355 /* 4356 * XXX assume this isn't an aggregate 4357 * frame. 4358 */ 4359 ath_tx_update_ratectrl(sc, ni, 4360 bf->bf_state.bfs_rc, ts, 4361 bf->bf_state.bfs_pktlen, 1, 4362 (ts->ts_status == 0 ? 0 : 1)); 4363 } 4364 ath_tx_default_comp(sc, bf, 0); 4365 } else 4366 bf->bf_comp(sc, bf, 0); 4367 } 4368 4369 4370 4371 /* 4372 * Process completed xmit descriptors from the specified queue. 4373 * Kick the packet scheduler if needed. This can occur from this 4374 * particular task. 4375 */ 4376 static int 4377 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched) 4378 { 4379 struct ath_hal *ah = sc->sc_ah; 4380 struct ath_buf *bf; 4381 struct ath_desc *ds; 4382 struct ath_tx_status *ts; 4383 struct ieee80211_node *ni; 4384 #ifdef IEEE80211_SUPPORT_SUPERG 4385 struct ieee80211com *ic = &sc->sc_ic; 4386 #endif /* IEEE80211_SUPPORT_SUPERG */ 4387 int nacked; 4388 HAL_STATUS status; 4389 4390 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4391 __func__, txq->axq_qnum, 4392 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4393 txq->axq_link); 4394 4395 ATH_KTR(sc, ATH_KTR_TXCOMP, 4, 4396 "ath_tx_processq: txq=%u head %p link %p depth %p", 4397 txq->axq_qnum, 4398 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4399 txq->axq_link, 4400 txq->axq_depth); 4401 4402 nacked = 0; 4403 for (;;) { 4404 ATH_TXQ_LOCK(txq); 4405 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4406 bf = TAILQ_FIRST(&txq->axq_q); 4407 if (bf == NULL) { 4408 ATH_TXQ_UNLOCK(txq); 4409 break; 4410 } 4411 ds = bf->bf_lastds; /* XXX must be setup correctly! */ 4412 ts = &bf->bf_status.ds_txstat; 4413 4414 status = ath_hal_txprocdesc(ah, ds, ts); 4415 #ifdef ATH_DEBUG 4416 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4417 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4418 status == HAL_OK); 4419 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0)) 4420 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4421 status == HAL_OK); 4422 #endif 4423 #ifdef ATH_DEBUG_ALQ 4424 if (if_ath_alq_checkdebug(&sc->sc_alq, 4425 ATH_ALQ_EDMA_TXSTATUS)) { 4426 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS, 4427 sc->sc_tx_statuslen, 4428 (char *) ds); 4429 } 4430 #endif 4431 4432 if (status == HAL_EINPROGRESS) { 4433 ATH_KTR(sc, ATH_KTR_TXCOMP, 3, 4434 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS", 4435 txq->axq_qnum, bf, ds); 4436 ATH_TXQ_UNLOCK(txq); 4437 break; 4438 } 4439 ATH_TXQ_REMOVE(txq, bf, bf_list); 4440 4441 /* 4442 * Sanity check. 4443 */ 4444 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) { 4445 device_printf(sc->sc_dev, 4446 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n", 4447 __func__, 4448 txq->axq_qnum, 4449 bf, 4450 bf->bf_state.bfs_tx_queue); 4451 } 4452 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) { 4453 device_printf(sc->sc_dev, 4454 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n", 4455 __func__, 4456 txq->axq_qnum, 4457 bf->bf_last, 4458 bf->bf_last->bf_state.bfs_tx_queue); 4459 } 4460 4461 #if 0 4462 if (txq->axq_depth > 0) { 4463 /* 4464 * More frames follow. Mark the buffer busy 4465 * so it's not re-used while the hardware may 4466 * still re-read the link field in the descriptor. 4467 * 4468 * Use the last buffer in an aggregate as that 4469 * is where the hardware may be - intermediate 4470 * descriptors won't be "busy". 4471 */ 4472 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 4473 } else 4474 txq->axq_link = NULL; 4475 #else 4476 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 4477 #endif 4478 if (bf->bf_state.bfs_aggr) 4479 txq->axq_aggr_depth--; 4480 4481 ni = bf->bf_node; 4482 4483 ATH_KTR(sc, ATH_KTR_TXCOMP, 5, 4484 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x", 4485 txq->axq_qnum, bf, ds, ni, ts->ts_status); 4486 /* 4487 * If unicast frame was ack'd update RSSI, 4488 * including the last rx time used to 4489 * workaround phantom bmiss interrupts. 4490 */ 4491 if (ni != NULL && ts->ts_status == 0 && 4492 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 4493 nacked++; 4494 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4495 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4496 ts->ts_rssi); 4497 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgtxrssi, 4498 ts->ts_rssi); 4499 } 4500 ATH_TXQ_UNLOCK(txq); 4501 4502 /* 4503 * Update statistics and call completion 4504 */ 4505 ath_tx_process_buf_completion(sc, txq, ts, bf); 4506 4507 /* XXX at this point, bf and ni may be totally invalid */ 4508 } 4509 #ifdef IEEE80211_SUPPORT_SUPERG 4510 /* 4511 * Flush fast-frame staging queue when traffic slows. 4512 */ 4513 if (txq->axq_depth <= 1) 4514 ieee80211_ff_flush(ic, txq->axq_ac); 4515 #endif 4516 4517 /* Kick the software TXQ scheduler */ 4518 if (dosched) { 4519 ATH_TX_LOCK(sc); 4520 ath_txq_sched(sc, txq); 4521 ATH_TX_UNLOCK(sc); 4522 } 4523 4524 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4525 "ath_tx_processq: txq=%u: done", 4526 txq->axq_qnum); 4527 4528 return nacked; 4529 } 4530 4531 #define TXQACTIVE(t, q) ( (t) & (1 << (q))) 4532 4533 /* 4534 * Deferred processing of transmit interrupt; special-cased 4535 * for a single hardware transmit queue (e.g. 5210 and 5211). 4536 */ 4537 static void 4538 ath_tx_proc_q0(void *arg, int npending) 4539 { 4540 struct ath_softc *sc = arg; 4541 uint32_t txqs; 4542 4543 ATH_PCU_LOCK(sc); 4544 sc->sc_txproc_cnt++; 4545 txqs = sc->sc_txq_active; 4546 sc->sc_txq_active &= ~txqs; 4547 ATH_PCU_UNLOCK(sc); 4548 4549 ATH_LOCK(sc); 4550 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4551 ATH_UNLOCK(sc); 4552 4553 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4554 "ath_tx_proc_q0: txqs=0x%08x", txqs); 4555 4556 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1)) 4557 /* XXX why is lastrx updated in tx code? */ 4558 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4559 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4560 ath_tx_processq(sc, sc->sc_cabq, 1); 4561 sc->sc_wd_timer = 0; 4562 4563 if (sc->sc_softled) 4564 ath_led_event(sc, sc->sc_txrix); 4565 4566 ATH_PCU_LOCK(sc); 4567 sc->sc_txproc_cnt--; 4568 ATH_PCU_UNLOCK(sc); 4569 4570 ATH_LOCK(sc); 4571 ath_power_restore_power_state(sc); 4572 ATH_UNLOCK(sc); 4573 4574 ath_tx_kick(sc); 4575 } 4576 4577 /* 4578 * Deferred processing of transmit interrupt; special-cased 4579 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4580 */ 4581 static void 4582 ath_tx_proc_q0123(void *arg, int npending) 4583 { 4584 struct ath_softc *sc = arg; 4585 int nacked; 4586 uint32_t txqs; 4587 4588 ATH_PCU_LOCK(sc); 4589 sc->sc_txproc_cnt++; 4590 txqs = sc->sc_txq_active; 4591 sc->sc_txq_active &= ~txqs; 4592 ATH_PCU_UNLOCK(sc); 4593 4594 ATH_LOCK(sc); 4595 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4596 ATH_UNLOCK(sc); 4597 4598 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, 4599 "ath_tx_proc_q0123: txqs=0x%08x", txqs); 4600 4601 /* 4602 * Process each active queue. 4603 */ 4604 nacked = 0; 4605 if (TXQACTIVE(txqs, 0)) 4606 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1); 4607 if (TXQACTIVE(txqs, 1)) 4608 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1); 4609 if (TXQACTIVE(txqs, 2)) 4610 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1); 4611 if (TXQACTIVE(txqs, 3)) 4612 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1); 4613 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4614 ath_tx_processq(sc, sc->sc_cabq, 1); 4615 if (nacked) 4616 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4617 4618 sc->sc_wd_timer = 0; 4619 4620 if (sc->sc_softled) 4621 ath_led_event(sc, sc->sc_txrix); 4622 4623 ATH_PCU_LOCK(sc); 4624 sc->sc_txproc_cnt--; 4625 ATH_PCU_UNLOCK(sc); 4626 4627 ATH_LOCK(sc); 4628 ath_power_restore_power_state(sc); 4629 ATH_UNLOCK(sc); 4630 4631 ath_tx_kick(sc); 4632 } 4633 4634 /* 4635 * Deferred processing of transmit interrupt. 4636 */ 4637 static void 4638 ath_tx_proc(void *arg, int npending) 4639 { 4640 struct ath_softc *sc = arg; 4641 int i, nacked; 4642 uint32_t txqs; 4643 4644 ATH_PCU_LOCK(sc); 4645 sc->sc_txproc_cnt++; 4646 txqs = sc->sc_txq_active; 4647 sc->sc_txq_active &= ~txqs; 4648 ATH_PCU_UNLOCK(sc); 4649 4650 ATH_LOCK(sc); 4651 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4652 ATH_UNLOCK(sc); 4653 4654 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs); 4655 4656 /* 4657 * Process each active queue. 4658 */ 4659 nacked = 0; 4660 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4661 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i)) 4662 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1); 4663 if (nacked) 4664 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4665 4666 sc->sc_wd_timer = 0; 4667 4668 if (sc->sc_softled) 4669 ath_led_event(sc, sc->sc_txrix); 4670 4671 ATH_PCU_LOCK(sc); 4672 sc->sc_txproc_cnt--; 4673 ATH_PCU_UNLOCK(sc); 4674 4675 ATH_LOCK(sc); 4676 ath_power_restore_power_state(sc); 4677 ATH_UNLOCK(sc); 4678 4679 ath_tx_kick(sc); 4680 } 4681 #undef TXQACTIVE 4682 4683 /* 4684 * Deferred processing of TXQ rescheduling. 4685 */ 4686 static void 4687 ath_txq_sched_tasklet(void *arg, int npending) 4688 { 4689 struct ath_softc *sc = arg; 4690 int i; 4691 4692 /* XXX is skipping ok? */ 4693 ATH_PCU_LOCK(sc); 4694 #if 0 4695 if (sc->sc_inreset_cnt > 0) { 4696 device_printf(sc->sc_dev, 4697 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 4698 ATH_PCU_UNLOCK(sc); 4699 return; 4700 } 4701 #endif 4702 sc->sc_txproc_cnt++; 4703 ATH_PCU_UNLOCK(sc); 4704 4705 ATH_LOCK(sc); 4706 ath_power_set_power_state(sc, HAL_PM_AWAKE); 4707 ATH_UNLOCK(sc); 4708 4709 ATH_TX_LOCK(sc); 4710 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 4711 if (ATH_TXQ_SETUP(sc, i)) { 4712 ath_txq_sched(sc, &sc->sc_txq[i]); 4713 } 4714 } 4715 ATH_TX_UNLOCK(sc); 4716 4717 ATH_LOCK(sc); 4718 ath_power_restore_power_state(sc); 4719 ATH_UNLOCK(sc); 4720 4721 ATH_PCU_LOCK(sc); 4722 sc->sc_txproc_cnt--; 4723 ATH_PCU_UNLOCK(sc); 4724 } 4725 4726 void 4727 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf) 4728 { 4729 4730 ATH_TXBUF_LOCK_ASSERT(sc); 4731 4732 if (bf->bf_flags & ATH_BUF_MGMT) 4733 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list); 4734 else { 4735 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4736 sc->sc_txbuf_cnt++; 4737 if (sc->sc_txbuf_cnt > ath_txbuf) { 4738 device_printf(sc->sc_dev, 4739 "%s: sc_txbuf_cnt > %d?\n", 4740 __func__, 4741 ath_txbuf); 4742 sc->sc_txbuf_cnt = ath_txbuf; 4743 } 4744 } 4745 } 4746 4747 void 4748 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf) 4749 { 4750 4751 ATH_TXBUF_LOCK_ASSERT(sc); 4752 4753 if (bf->bf_flags & ATH_BUF_MGMT) 4754 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list); 4755 else { 4756 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 4757 sc->sc_txbuf_cnt++; 4758 if (sc->sc_txbuf_cnt > ATH_TXBUF) { 4759 device_printf(sc->sc_dev, 4760 "%s: sc_txbuf_cnt > %d?\n", 4761 __func__, 4762 ATH_TXBUF); 4763 sc->sc_txbuf_cnt = ATH_TXBUF; 4764 } 4765 } 4766 } 4767 4768 /* 4769 * Free the holding buffer if it exists 4770 */ 4771 void 4772 ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq) 4773 { 4774 ATH_TXBUF_UNLOCK_ASSERT(sc); 4775 ATH_TXQ_LOCK_ASSERT(txq); 4776 4777 if (txq->axq_holdingbf == NULL) 4778 return; 4779 4780 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY; 4781 4782 ATH_TXBUF_LOCK(sc); 4783 ath_returnbuf_tail(sc, txq->axq_holdingbf); 4784 ATH_TXBUF_UNLOCK(sc); 4785 4786 txq->axq_holdingbf = NULL; 4787 } 4788 4789 /* 4790 * Add this buffer to the holding queue, freeing the previous 4791 * one if it exists. 4792 */ 4793 static void 4794 ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf) 4795 { 4796 struct ath_txq *txq; 4797 4798 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue]; 4799 4800 ATH_TXBUF_UNLOCK_ASSERT(sc); 4801 ATH_TXQ_LOCK_ASSERT(txq); 4802 4803 /* XXX assert ATH_BUF_BUSY is set */ 4804 4805 /* XXX assert the tx queue is under the max number */ 4806 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) { 4807 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n", 4808 __func__, 4809 bf, 4810 bf->bf_state.bfs_tx_queue); 4811 bf->bf_flags &= ~ATH_BUF_BUSY; 4812 ath_returnbuf_tail(sc, bf); 4813 return; 4814 } 4815 ath_txq_freeholdingbuf(sc, txq); 4816 txq->axq_holdingbf = bf; 4817 } 4818 4819 /* 4820 * Return a buffer to the pool and update the 'busy' flag on the 4821 * previous 'tail' entry. 4822 * 4823 * This _must_ only be called when the buffer is involved in a completed 4824 * TX. The logic is that if it was part of an active TX, the previous 4825 * buffer on the list is now not involved in a halted TX DMA queue, waiting 4826 * for restart (eg for TDMA.) 4827 * 4828 * The caller must free the mbuf and recycle the node reference. 4829 * 4830 * XXX This method of handling busy / holding buffers is insanely stupid. 4831 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would 4832 * be much nicer if buffers in the processq() methods would instead be 4833 * always completed there (pushed onto a txq or ath_bufhead) so we knew 4834 * exactly what hardware queue they came from in the first place. 4835 */ 4836 void 4837 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf) 4838 { 4839 struct ath_txq *txq; 4840 4841 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue]; 4842 4843 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__)); 4844 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__)); 4845 4846 /* 4847 * If this buffer is busy, push it onto the holding queue. 4848 */ 4849 if (bf->bf_flags & ATH_BUF_BUSY) { 4850 ATH_TXQ_LOCK(txq); 4851 ath_txq_addholdingbuf(sc, bf); 4852 ATH_TXQ_UNLOCK(txq); 4853 return; 4854 } 4855 4856 /* 4857 * Not a busy buffer, so free normally 4858 */ 4859 ATH_TXBUF_LOCK(sc); 4860 ath_returnbuf_tail(sc, bf); 4861 ATH_TXBUF_UNLOCK(sc); 4862 } 4863 4864 /* 4865 * This is currently used by ath_tx_draintxq() and 4866 * ath_tx_tid_free_pkts(). 4867 * 4868 * It recycles a single ath_buf. 4869 */ 4870 void 4871 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status) 4872 { 4873 struct ieee80211_node *ni = bf->bf_node; 4874 struct mbuf *m0 = bf->bf_m; 4875 4876 /* 4877 * Make sure that we only sync/unload if there's an mbuf. 4878 * If not (eg we cloned a buffer), the unload will have already 4879 * occurred. 4880 */ 4881 if (bf->bf_m != NULL) { 4882 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4883 BUS_DMASYNC_POSTWRITE); 4884 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4885 } 4886 4887 bf->bf_node = NULL; 4888 bf->bf_m = NULL; 4889 4890 /* Free the buffer, it's not needed any longer */ 4891 ath_freebuf(sc, bf); 4892 4893 /* Pass the buffer back to net80211 - completing it */ 4894 ieee80211_tx_complete(ni, m0, status); 4895 } 4896 4897 static struct ath_buf * 4898 ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq) 4899 { 4900 struct ath_buf *bf; 4901 4902 ATH_TXQ_LOCK_ASSERT(txq); 4903 4904 /* 4905 * Drain the FIFO queue first, then if it's 4906 * empty, move to the normal frame queue. 4907 */ 4908 bf = TAILQ_FIRST(&txq->fifo.axq_q); 4909 if (bf != NULL) { 4910 /* 4911 * Is it the last buffer in this set? 4912 * Decrement the FIFO counter. 4913 */ 4914 if (bf->bf_flags & ATH_BUF_FIFOEND) { 4915 if (txq->axq_fifo_depth == 0) { 4916 device_printf(sc->sc_dev, 4917 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n", 4918 __func__, 4919 txq->axq_qnum, 4920 txq->fifo.axq_depth); 4921 } else 4922 txq->axq_fifo_depth--; 4923 } 4924 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list); 4925 return (bf); 4926 } 4927 4928 /* 4929 * Debugging! 4930 */ 4931 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) { 4932 device_printf(sc->sc_dev, 4933 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n", 4934 __func__, 4935 txq->axq_qnum, 4936 txq->axq_fifo_depth, 4937 txq->fifo.axq_depth); 4938 } 4939 4940 /* 4941 * Now drain the pending queue. 4942 */ 4943 bf = TAILQ_FIRST(&txq->axq_q); 4944 if (bf == NULL) { 4945 txq->axq_link = NULL; 4946 return (NULL); 4947 } 4948 ATH_TXQ_REMOVE(txq, bf, bf_list); 4949 return (bf); 4950 } 4951 4952 void 4953 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4954 { 4955 #ifdef ATH_DEBUG 4956 struct ath_hal *ah = sc->sc_ah; 4957 #endif 4958 struct ath_buf *bf; 4959 u_int ix; 4960 4961 /* 4962 * NB: this assumes output has been stopped and 4963 * we do not need to block ath_tx_proc 4964 */ 4965 for (ix = 0;; ix++) { 4966 ATH_TXQ_LOCK(txq); 4967 bf = ath_tx_draintxq_get_one(sc, txq); 4968 if (bf == NULL) { 4969 ATH_TXQ_UNLOCK(txq); 4970 break; 4971 } 4972 if (bf->bf_state.bfs_aggr) 4973 txq->axq_aggr_depth--; 4974 #ifdef ATH_DEBUG 4975 if (sc->sc_debug & ATH_DEBUG_RESET) { 4976 struct ieee80211com *ic = &sc->sc_ic; 4977 int status = 0; 4978 4979 /* 4980 * EDMA operation has a TX completion FIFO 4981 * separate from the TX descriptor, so this 4982 * method of checking the "completion" status 4983 * is wrong. 4984 */ 4985 if (! sc->sc_isedma) { 4986 status = (ath_hal_txprocdesc(ah, 4987 bf->bf_lastds, 4988 &bf->bf_status.ds_txstat) == HAL_OK); 4989 } 4990 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status); 4991 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 4992 bf->bf_m->m_len, 0, -1); 4993 } 4994 #endif /* ATH_DEBUG */ 4995 /* 4996 * Since we're now doing magic in the completion 4997 * functions, we -must- call it for aggregation 4998 * destinations or BAW tracking will get upset. 4999 */ 5000 /* 5001 * Clear ATH_BUF_BUSY; the completion handler 5002 * will free the buffer. 5003 */ 5004 ATH_TXQ_UNLOCK(txq); 5005 bf->bf_flags &= ~ATH_BUF_BUSY; 5006 if (bf->bf_comp) 5007 bf->bf_comp(sc, bf, 1); 5008 else 5009 ath_tx_default_comp(sc, bf, 1); 5010 } 5011 5012 /* 5013 * Free the holding buffer if it exists 5014 */ 5015 ATH_TXQ_LOCK(txq); 5016 ath_txq_freeholdingbuf(sc, txq); 5017 ATH_TXQ_UNLOCK(txq); 5018 5019 /* 5020 * Drain software queued frames which are on 5021 * active TIDs. 5022 */ 5023 ath_tx_txq_drain(sc, txq); 5024 } 5025 5026 static void 5027 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5028 { 5029 struct ath_hal *ah = sc->sc_ah; 5030 5031 ATH_TXQ_LOCK_ASSERT(txq); 5032 5033 DPRINTF(sc, ATH_DEBUG_RESET, 5034 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, " 5035 "link %p, holdingbf=%p\n", 5036 __func__, 5037 txq->axq_qnum, 5038 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5039 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)), 5040 (int) ath_hal_numtxpending(ah, txq->axq_qnum), 5041 txq->axq_flags, 5042 txq->axq_link, 5043 txq->axq_holdingbf); 5044 5045 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5046 /* We've stopped TX DMA, so mark this as stopped. */ 5047 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING; 5048 5049 #ifdef ATH_DEBUG 5050 if ((sc->sc_debug & ATH_DEBUG_RESET) 5051 && (txq->axq_holdingbf != NULL)) { 5052 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0); 5053 } 5054 #endif 5055 } 5056 5057 int 5058 ath_stoptxdma(struct ath_softc *sc) 5059 { 5060 struct ath_hal *ah = sc->sc_ah; 5061 int i; 5062 5063 /* XXX return value */ 5064 if (sc->sc_invalid) 5065 return 0; 5066 5067 if (!sc->sc_invalid) { 5068 /* don't touch the hardware if marked invalid */ 5069 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5070 __func__, sc->sc_bhalq, 5071 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5072 NULL); 5073 5074 /* stop the beacon queue */ 5075 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5076 5077 /* Stop the data queues */ 5078 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5079 if (ATH_TXQ_SETUP(sc, i)) { 5080 ATH_TXQ_LOCK(&sc->sc_txq[i]); 5081 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5082 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 5083 } 5084 } 5085 } 5086 5087 return 1; 5088 } 5089 5090 #ifdef ATH_DEBUG 5091 void 5092 ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq) 5093 { 5094 struct ath_hal *ah = sc->sc_ah; 5095 struct ath_buf *bf; 5096 int i = 0; 5097 5098 if (! (sc->sc_debug & ATH_DEBUG_RESET)) 5099 return; 5100 5101 device_printf(sc->sc_dev, "%s: Q%d: begin\n", 5102 __func__, txq->axq_qnum); 5103 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) { 5104 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 5105 ath_hal_txprocdesc(ah, bf->bf_lastds, 5106 &bf->bf_status.ds_txstat) == HAL_OK); 5107 i++; 5108 } 5109 device_printf(sc->sc_dev, "%s: Q%d: end\n", 5110 __func__, txq->axq_qnum); 5111 } 5112 #endif /* ATH_DEBUG */ 5113 5114 /* 5115 * Drain the transmit queues and reclaim resources. 5116 */ 5117 void 5118 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 5119 { 5120 struct ath_hal *ah = sc->sc_ah; 5121 struct ath_buf *bf_last; 5122 int i; 5123 5124 (void) ath_stoptxdma(sc); 5125 5126 /* 5127 * Dump the queue contents 5128 */ 5129 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5130 /* 5131 * XXX TODO: should we just handle the completed TX frames 5132 * here, whether or not the reset is a full one or not? 5133 */ 5134 if (ATH_TXQ_SETUP(sc, i)) { 5135 #ifdef ATH_DEBUG 5136 if (sc->sc_debug & ATH_DEBUG_RESET) 5137 ath_tx_dump(sc, &sc->sc_txq[i]); 5138 #endif /* ATH_DEBUG */ 5139 if (reset_type == ATH_RESET_NOLOSS) { 5140 ath_tx_processq(sc, &sc->sc_txq[i], 0); 5141 ATH_TXQ_LOCK(&sc->sc_txq[i]); 5142 /* 5143 * Free the holding buffer; DMA is now 5144 * stopped. 5145 */ 5146 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]); 5147 /* 5148 * Setup the link pointer to be the 5149 * _last_ buffer/descriptor in the list. 5150 * If there's nothing in the list, set it 5151 * to NULL. 5152 */ 5153 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i], 5154 axq_q_s); 5155 if (bf_last != NULL) { 5156 ath_hal_gettxdesclinkptr(ah, 5157 bf_last->bf_lastds, 5158 &sc->sc_txq[i].axq_link); 5159 } else { 5160 sc->sc_txq[i].axq_link = NULL; 5161 } 5162 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 5163 } else 5164 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5165 } 5166 } 5167 #ifdef ATH_DEBUG 5168 if (sc->sc_debug & ATH_DEBUG_RESET) { 5169 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf); 5170 if (bf != NULL && bf->bf_m != NULL) { 5171 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5172 ath_hal_txprocdesc(ah, bf->bf_lastds, 5173 &bf->bf_status.ds_txstat) == HAL_OK); 5174 ieee80211_dump_pkt(&sc->sc_ic, 5175 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 5176 0, -1); 5177 } 5178 } 5179 #endif /* ATH_DEBUG */ 5180 sc->sc_wd_timer = 0; 5181 } 5182 5183 /* 5184 * Update internal state after a channel change. 5185 */ 5186 static void 5187 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5188 { 5189 enum ieee80211_phymode mode; 5190 5191 /* 5192 * Change channels and update the h/w rate map 5193 * if we're switching; e.g. 11a to 11b/g. 5194 */ 5195 mode = ieee80211_chan2mode(chan); 5196 if (mode != sc->sc_curmode) 5197 ath_setcurmode(sc, mode); 5198 sc->sc_curchan = chan; 5199 } 5200 5201 /* 5202 * Set/change channels. If the channel is really being changed, 5203 * it's done by resetting the chip. To accomplish this we must 5204 * first cleanup any pending DMA, then restart stuff after a la 5205 * ath_init. 5206 */ 5207 static int 5208 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5209 { 5210 struct ieee80211com *ic = &sc->sc_ic; 5211 struct ath_hal *ah = sc->sc_ah; 5212 int ret = 0; 5213 5214 /* Treat this as an interface reset */ 5215 ATH_PCU_UNLOCK_ASSERT(sc); 5216 ATH_UNLOCK_ASSERT(sc); 5217 5218 /* (Try to) stop TX/RX from occurring */ 5219 taskqueue_block(sc->sc_tq); 5220 5221 ATH_PCU_LOCK(sc); 5222 5223 /* Disable interrupts */ 5224 ath_hal_intrset(ah, 0); 5225 5226 /* Stop new RX/TX/interrupt completion */ 5227 if (ath_reset_grablock(sc, 1) == 0) { 5228 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n", 5229 __func__); 5230 } 5231 5232 /* Stop pending RX/TX completion */ 5233 ath_txrx_stop_locked(sc); 5234 5235 ATH_PCU_UNLOCK(sc); 5236 5237 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 5238 __func__, ieee80211_chan2ieee(ic, chan), 5239 chan->ic_freq, chan->ic_flags); 5240 if (chan != sc->sc_curchan) { 5241 HAL_STATUS status; 5242 /* 5243 * To switch channels clear any pending DMA operations; 5244 * wait long enough for the RX fifo to drain, reset the 5245 * hardware at the new frequency, and then re-enable 5246 * the relevant bits of the h/w. 5247 */ 5248 #if 0 5249 ath_hal_intrset(ah, 0); /* disable interrupts */ 5250 #endif 5251 ath_stoprecv(sc, 1); /* turn off frame recv */ 5252 /* 5253 * First, handle completed TX/RX frames. 5254 */ 5255 ath_rx_flush(sc); 5256 ath_draintxq(sc, ATH_RESET_NOLOSS); 5257 /* 5258 * Next, flush the non-scheduled frames. 5259 */ 5260 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */ 5261 5262 ath_update_chainmasks(sc, chan); 5263 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask, 5264 sc->sc_cur_rxchainmask); 5265 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, 5266 HAL_RESET_NORMAL, &status)) { 5267 device_printf(sc->sc_dev, "%s: unable to reset " 5268 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 5269 __func__, ieee80211_chan2ieee(ic, chan), 5270 chan->ic_freq, chan->ic_flags, status); 5271 ret = EIO; 5272 goto finish; 5273 } 5274 sc->sc_diversity = ath_hal_getdiversity(ah); 5275 5276 ATH_RX_LOCK(sc); 5277 sc->sc_rx_stopped = 1; 5278 sc->sc_rx_resetted = 1; 5279 ATH_RX_UNLOCK(sc); 5280 5281 /* Quiet time handling - ensure we resync */ 5282 ath_vap_clear_quiet_ie(sc); 5283 5284 /* Let DFS at it in case it's a DFS channel */ 5285 ath_dfs_radar_enable(sc, chan); 5286 5287 /* Let spectral at in case spectral is enabled */ 5288 ath_spectral_enable(sc, chan); 5289 5290 /* 5291 * Let bluetooth coexistence at in case it's needed for this 5292 * channel 5293 */ 5294 ath_btcoex_enable(sc, ic->ic_curchan); 5295 5296 /* 5297 * If we're doing TDMA, enforce the TXOP limitation for chips 5298 * that support it. 5299 */ 5300 if (sc->sc_hasenforcetxop && sc->sc_tdma) 5301 ath_hal_setenforcetxop(sc->sc_ah, 1); 5302 else 5303 ath_hal_setenforcetxop(sc->sc_ah, 0); 5304 5305 /* 5306 * Re-enable rx framework. 5307 */ 5308 if (ath_startrecv(sc) != 0) { 5309 device_printf(sc->sc_dev, 5310 "%s: unable to restart recv logic\n", __func__); 5311 ret = EIO; 5312 goto finish; 5313 } 5314 5315 /* 5316 * Change channels and update the h/w rate map 5317 * if we're switching; e.g. 11a to 11b/g. 5318 */ 5319 ath_chan_change(sc, chan); 5320 5321 /* 5322 * Reset clears the beacon timers; reset them 5323 * here if needed. 5324 */ 5325 if (sc->sc_beacons) { /* restart beacons */ 5326 #ifdef IEEE80211_SUPPORT_TDMA 5327 if (sc->sc_tdma) 5328 ath_tdma_config(sc, NULL); 5329 else 5330 #endif 5331 ath_beacon_config(sc, NULL); 5332 } 5333 5334 /* 5335 * Re-enable interrupts. 5336 */ 5337 #if 0 5338 ath_hal_intrset(ah, sc->sc_imask); 5339 #endif 5340 } 5341 5342 finish: 5343 ATH_PCU_LOCK(sc); 5344 sc->sc_inreset_cnt--; 5345 /* XXX only do this if sc_inreset_cnt == 0? */ 5346 ath_hal_intrset(ah, sc->sc_imask); 5347 ATH_PCU_UNLOCK(sc); 5348 5349 ath_txrx_start(sc); 5350 /* XXX ath_start? */ 5351 5352 return ret; 5353 } 5354 5355 /* 5356 * Periodically recalibrate the PHY to account 5357 * for temperature/environment changes. 5358 */ 5359 static void 5360 ath_calibrate(void *arg) 5361 { 5362 struct ath_softc *sc = arg; 5363 struct ath_hal *ah = sc->sc_ah; 5364 struct ieee80211com *ic = &sc->sc_ic; 5365 HAL_BOOL longCal, isCalDone = AH_TRUE; 5366 HAL_BOOL aniCal, shortCal = AH_FALSE; 5367 int nextcal; 5368 5369 ATH_LOCK_ASSERT(sc); 5370 5371 /* 5372 * Force the hardware awake for ANI work. 5373 */ 5374 ath_power_set_power_state(sc, HAL_PM_AWAKE); 5375 5376 /* Skip trying to do this if we're in reset */ 5377 if (sc->sc_inreset_cnt) 5378 goto restart; 5379 5380 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 5381 goto restart; 5382 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5383 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000); 5384 if (sc->sc_doresetcal) 5385 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000); 5386 5387 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal); 5388 if (aniCal) { 5389 sc->sc_stats.ast_ani_cal++; 5390 sc->sc_lastani = ticks; 5391 ath_hal_ani_poll(ah, sc->sc_curchan); 5392 } 5393 5394 if (longCal) { 5395 sc->sc_stats.ast_per_cal++; 5396 sc->sc_lastlongcal = ticks; 5397 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5398 /* 5399 * Rfgain is out of bounds, reset the chip 5400 * to load new gain values. 5401 */ 5402 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5403 "%s: rfgain change\n", __func__); 5404 sc->sc_stats.ast_per_rfgain++; 5405 sc->sc_resetcal = 0; 5406 sc->sc_doresetcal = AH_TRUE; 5407 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 5408 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 5409 ath_power_restore_power_state(sc); 5410 return; 5411 } 5412 /* 5413 * If this long cal is after an idle period, then 5414 * reset the data collection state so we start fresh. 5415 */ 5416 if (sc->sc_resetcal) { 5417 (void) ath_hal_calreset(ah, sc->sc_curchan); 5418 sc->sc_lastcalreset = ticks; 5419 sc->sc_lastshortcal = ticks; 5420 sc->sc_resetcal = 0; 5421 sc->sc_doresetcal = AH_TRUE; 5422 } 5423 } 5424 5425 /* Only call if we're doing a short/long cal, not for ANI calibration */ 5426 if (shortCal || longCal) { 5427 isCalDone = AH_FALSE; 5428 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 5429 if (longCal) { 5430 /* 5431 * Calibrate noise floor data again in case of change. 5432 */ 5433 ath_hal_process_noisefloor(ah); 5434 } 5435 } else { 5436 DPRINTF(sc, ATH_DEBUG_ANY, 5437 "%s: calibration of channel %u failed\n", 5438 __func__, sc->sc_curchan->ic_freq); 5439 sc->sc_stats.ast_per_calfail++; 5440 } 5441 /* 5442 * XXX TODO: get the NF calibration results from the HAL. 5443 * If we failed NF cal then schedule a hard reset to potentially 5444 * un-freeze the PHY. 5445 * 5446 * Note we have to be careful here to not get stuck in an 5447 * infinite NIC restart. Ideally we'd not restart if we 5448 * failed the first NF cal - that /can/ fail sometimes in 5449 * a noisy environment. 5450 */ 5451 if (shortCal) 5452 sc->sc_lastshortcal = ticks; 5453 } 5454 if (!isCalDone) { 5455 restart: 5456 /* 5457 * Use a shorter interval to potentially collect multiple 5458 * data samples required to complete calibration. Once 5459 * we're told the work is done we drop back to a longer 5460 * interval between requests. We're more aggressive doing 5461 * work when operating as an AP to improve operation right 5462 * after startup. 5463 */ 5464 sc->sc_lastshortcal = ticks; 5465 nextcal = ath_shortcalinterval*hz/1000; 5466 if (sc->sc_opmode != HAL_M_HOSTAP) 5467 nextcal *= 10; 5468 sc->sc_doresetcal = AH_TRUE; 5469 } else { 5470 /* nextcal should be the shortest time for next event */ 5471 nextcal = ath_longcalinterval*hz; 5472 if (sc->sc_lastcalreset == 0) 5473 sc->sc_lastcalreset = sc->sc_lastlongcal; 5474 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 5475 sc->sc_resetcal = 1; /* setup reset next trip */ 5476 sc->sc_doresetcal = AH_FALSE; 5477 } 5478 /* ANI calibration may occur more often than short/long/resetcal */ 5479 if (ath_anicalinterval > 0) 5480 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000); 5481 5482 if (nextcal != 0) { 5483 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 5484 __func__, nextcal, isCalDone ? "" : "!"); 5485 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 5486 } else { 5487 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 5488 __func__); 5489 /* NB: don't rearm timer */ 5490 } 5491 /* 5492 * Restore power state now that we're done. 5493 */ 5494 ath_power_restore_power_state(sc); 5495 } 5496 5497 static void 5498 ath_scan_start(struct ieee80211com *ic) 5499 { 5500 struct ath_softc *sc = ic->ic_softc; 5501 struct ath_hal *ah = sc->sc_ah; 5502 u_int32_t rfilt; 5503 5504 /* XXX calibration timer? */ 5505 /* XXXGL: is constant ieee80211broadcastaddr a correct choice? */ 5506 5507 ATH_LOCK(sc); 5508 sc->sc_scanning = 1; 5509 sc->sc_syncbeacon = 0; 5510 rfilt = ath_calcrxfilter(sc); 5511 ATH_UNLOCK(sc); 5512 5513 ATH_PCU_LOCK(sc); 5514 ath_hal_setrxfilter(ah, rfilt); 5515 ath_hal_setassocid(ah, ieee80211broadcastaddr, 0); 5516 ATH_PCU_UNLOCK(sc); 5517 5518 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5519 __func__, rfilt, ether_sprintf(ieee80211broadcastaddr)); 5520 } 5521 5522 static void 5523 ath_scan_end(struct ieee80211com *ic) 5524 { 5525 struct ath_softc *sc = ic->ic_softc; 5526 struct ath_hal *ah = sc->sc_ah; 5527 u_int32_t rfilt; 5528 5529 ATH_LOCK(sc); 5530 sc->sc_scanning = 0; 5531 rfilt = ath_calcrxfilter(sc); 5532 ATH_UNLOCK(sc); 5533 5534 ATH_PCU_LOCK(sc); 5535 ath_hal_setrxfilter(ah, rfilt); 5536 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5537 5538 ath_hal_process_noisefloor(ah); 5539 ATH_PCU_UNLOCK(sc); 5540 5541 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5542 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5543 sc->sc_curaid); 5544 } 5545 5546 #ifdef ATH_ENABLE_11N 5547 /* 5548 * For now, just do a channel change. 5549 * 5550 * Later, we'll go through the hard slog of suspending tx/rx, changing rate 5551 * control state and resetting the hardware without dropping frames out 5552 * of the queue. 5553 * 5554 * The unfortunate trouble here is making absolutely sure that the 5555 * channel width change has propagated enough so the hardware 5556 * absolutely isn't handed bogus frames for it's current operating 5557 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and 5558 * does occur in parallel, we need to make certain we've blocked 5559 * any further ongoing TX (and RX, that can cause raw TX) 5560 * before we do this. 5561 */ 5562 static void 5563 ath_update_chw(struct ieee80211com *ic) 5564 { 5565 struct ath_softc *sc = ic->ic_softc; 5566 5567 //DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__); 5568 device_printf(sc->sc_dev, "%s: called\n", __func__); 5569 5570 /* 5571 * XXX TODO: schedule a tasklet that stops things without freeing, 5572 * walks the now stopped TX queue(s) looking for frames to retry 5573 * as if we TX filtered them (whch may mean dropping non-ampdu frames!) 5574 * but okay) then place them back on the software queue so they 5575 * can have the rate control lookup done again. 5576 */ 5577 ath_set_channel(ic); 5578 } 5579 #endif /* ATH_ENABLE_11N */ 5580 5581 /* 5582 * This is called by the beacon parsing routine in the receive 5583 * path to update the current quiet time information provided by 5584 * an AP. 5585 * 5586 * This is STA specific, it doesn't take the AP TBTT/beacon slot 5587 * offset into account. 5588 * 5589 * The quiet IE doesn't control the /now/ beacon interval - it 5590 * controls the upcoming beacon interval. So, when tbtt=1, 5591 * the quiet element programming shall be for the next beacon 5592 * interval. There's no tbtt=0 behaviour defined, so don't. 5593 * 5594 * Since we're programming the next quiet interval, we have 5595 * to keep in mind what we will see when the next beacon 5596 * is received with potentially a quiet IE. For example, if 5597 * quiet_period is 1, then we are always getting a quiet interval 5598 * each TBTT - so if we just program it in upon each beacon received, 5599 * it will constantly reflect the "next" TBTT and we will never 5600 * let the counter stay programmed correctly. 5601 * 5602 * So: 5603 * + the first time we see the quiet IE, program it and store 5604 * the details somewhere; 5605 * + if the quiet parameters don't change (ie, period/duration/offset) 5606 * then just leave the programming enabled; 5607 * + (we can "skip" beacons, so don't try to enforce tbttcount unless 5608 * you're willing to also do the skipped beacon math); 5609 * + if the quiet IE is removed, then halt quiet time. 5610 */ 5611 static int 5612 ath_set_quiet_ie(struct ieee80211_node *ni, uint8_t *ie) 5613 { 5614 struct ieee80211_quiet_ie *q; 5615 struct ieee80211vap *vap = ni->ni_vap; 5616 struct ath_vap *avp = ATH_VAP(vap); 5617 struct ieee80211com *ic = vap->iv_ic; 5618 struct ath_softc *sc = ic->ic_softc; 5619 5620 if (vap->iv_opmode != IEEE80211_M_STA) 5621 return (0); 5622 5623 /* Verify we have a quiet time IE */ 5624 if (ie == NULL) { 5625 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5626 "%s: called; NULL IE, disabling\n", __func__); 5627 5628 ath_hal_set_quiet(sc->sc_ah, 0, 0, 0, HAL_QUIET_DISABLE); 5629 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 5630 return (0); 5631 } 5632 5633 /* If we do, verify it's actually legit */ 5634 if (ie[0] != IEEE80211_ELEMID_QUIET) 5635 return 0; 5636 if (ie[1] != 6) 5637 return 0; 5638 5639 /* Note: this belongs in net80211, parsed out and everything */ 5640 q = (void *) ie; 5641 5642 /* 5643 * Compare what we have stored to what we last saw. 5644 * If they're the same then don't program in anything. 5645 */ 5646 if ((q->period == avp->quiet_ie.period) && 5647 (le16dec(&q->duration) == le16dec(&avp->quiet_ie.duration)) && 5648 (le16dec(&q->offset) == le16dec(&avp->quiet_ie.offset))) 5649 return (0); 5650 5651 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5652 "%s: called; tbttcount=%d, period=%d, duration=%d, offset=%d\n", 5653 __func__, 5654 (int) q->tbttcount, 5655 (int) q->period, 5656 (int) le16dec(&q->duration), 5657 (int) le16dec(&q->offset)); 5658 5659 /* 5660 * Don't program in garbage values. 5661 */ 5662 if ((le16dec(&q->duration) == 0) || 5663 (le16dec(&q->duration) >= ni->ni_intval)) { 5664 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5665 "%s: invalid duration (%d)\n", __func__, 5666 le16dec(&q->duration)); 5667 return (0); 5668 } 5669 /* 5670 * Can have a 0 offset, but not a duration - so just check 5671 * they don't exceed the intval. 5672 */ 5673 if (le16dec(&q->duration) + le16dec(&q->offset) >= ni->ni_intval) { 5674 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5675 "%s: invalid duration + offset (%d+%d)\n", __func__, 5676 le16dec(&q->duration), 5677 le16dec(&q->offset)); 5678 return (0); 5679 } 5680 if (q->tbttcount == 0) { 5681 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5682 "%s: invalid tbttcount (0)\n", __func__); 5683 return (0); 5684 } 5685 if (q->period == 0) { 5686 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5687 "%s: invalid period (0)\n", __func__); 5688 return (0); 5689 } 5690 5691 /* 5692 * This is a new quiet time IE config, so wait until tbttcount 5693 * is equal to 1, and program it in. 5694 */ 5695 if (q->tbttcount == 1) { 5696 DPRINTF(sc, ATH_DEBUG_QUIETIE, 5697 "%s: programming\n", __func__); 5698 ath_hal_set_quiet(sc->sc_ah, 5699 q->period * ni->ni_intval, /* convert to TU */ 5700 le16dec(&q->duration), /* already in TU */ 5701 le16dec(&q->offset) + ni->ni_intval, 5702 HAL_QUIET_ENABLE | HAL_QUIET_ADD_CURRENT_TSF); 5703 /* 5704 * Note: no HAL_QUIET_ADD_SWBA_RESP_TIME; as this is for 5705 * STA mode 5706 */ 5707 5708 /* Update local state */ 5709 memcpy(&avp->quiet_ie, ie, sizeof(struct ieee80211_quiet_ie)); 5710 } 5711 5712 return (0); 5713 } 5714 5715 static void 5716 ath_set_channel(struct ieee80211com *ic) 5717 { 5718 struct ath_softc *sc = ic->ic_softc; 5719 5720 ATH_LOCK(sc); 5721 ath_power_set_power_state(sc, HAL_PM_AWAKE); 5722 ATH_UNLOCK(sc); 5723 5724 (void) ath_chan_set(sc, ic->ic_curchan); 5725 /* 5726 * If we are returning to our bss channel then mark state 5727 * so the next recv'd beacon's tsf will be used to sync the 5728 * beacon timers. Note that since we only hear beacons in 5729 * sta/ibss mode this has no effect in other operating modes. 5730 */ 5731 ATH_LOCK(sc); 5732 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5733 sc->sc_syncbeacon = 1; 5734 ath_power_restore_power_state(sc); 5735 ATH_UNLOCK(sc); 5736 } 5737 5738 /* 5739 * Walk the vap list and check if there any vap's in RUN state. 5740 */ 5741 static int 5742 ath_isanyrunningvaps(struct ieee80211vap *this) 5743 { 5744 struct ieee80211com *ic = this->iv_ic; 5745 struct ieee80211vap *vap; 5746 5747 IEEE80211_LOCK_ASSERT(ic); 5748 5749 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5750 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 5751 return 1; 5752 } 5753 return 0; 5754 } 5755 5756 static int 5757 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5758 { 5759 struct ieee80211com *ic = vap->iv_ic; 5760 struct ath_softc *sc = ic->ic_softc; 5761 struct ath_vap *avp = ATH_VAP(vap); 5762 struct ath_hal *ah = sc->sc_ah; 5763 struct ieee80211_node *ni = NULL; 5764 int i, error, stamode; 5765 u_int32_t rfilt; 5766 int csa_run_transition = 0; 5767 enum ieee80211_state ostate = vap->iv_state; 5768 5769 static const HAL_LED_STATE leds[] = { 5770 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5771 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5772 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5773 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5774 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5775 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5776 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5777 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5778 }; 5779 5780 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5781 ieee80211_state_name[ostate], 5782 ieee80211_state_name[nstate]); 5783 5784 /* 5785 * net80211 _should_ have the comlock asserted at this point. 5786 * There are some comments around the calls to vap->iv_newstate 5787 * which indicate that it (newstate) may end up dropping the 5788 * lock. This and the subsequent lock assert check after newstate 5789 * are an attempt to catch these and figure out how/why. 5790 */ 5791 IEEE80211_LOCK_ASSERT(ic); 5792 5793 /* Before we touch the hardware - wake it up */ 5794 ATH_LOCK(sc); 5795 /* 5796 * If the NIC is in anything other than SLEEP state, 5797 * we need to ensure that self-generated frames are 5798 * set for PWRMGT=0. Otherwise we may end up with 5799 * strange situations. 5800 * 5801 * XXX TODO: is this actually the case? :-) 5802 */ 5803 if (nstate != IEEE80211_S_SLEEP) 5804 ath_power_setselfgen(sc, HAL_PM_AWAKE); 5805 5806 /* 5807 * Now, wake the thing up. 5808 */ 5809 ath_power_set_power_state(sc, HAL_PM_AWAKE); 5810 5811 /* 5812 * And stop the calibration callout whilst we have 5813 * ATH_LOCK held. 5814 */ 5815 callout_stop(&sc->sc_cal_ch); 5816 ATH_UNLOCK(sc); 5817 5818 if (ostate == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN) 5819 csa_run_transition = 1; 5820 5821 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5822 5823 if (nstate == IEEE80211_S_SCAN) { 5824 /* 5825 * Scanning: turn off beacon miss and don't beacon. 5826 * Mark beacon state so when we reach RUN state we'll 5827 * [re]setup beacons. Unblock the task q thread so 5828 * deferred interrupt processing is done. 5829 */ 5830 5831 /* Ensure we stay awake during scan */ 5832 ATH_LOCK(sc); 5833 ath_power_setselfgen(sc, HAL_PM_AWAKE); 5834 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 5835 ATH_UNLOCK(sc); 5836 5837 ath_hal_intrset(ah, 5838 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5839 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5840 sc->sc_beacons = 0; 5841 taskqueue_unblock(sc->sc_tq); 5842 } 5843 5844 ni = ieee80211_ref_node(vap->iv_bss); 5845 rfilt = ath_calcrxfilter(sc); 5846 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5847 vap->iv_opmode == IEEE80211_M_AHDEMO || 5848 vap->iv_opmode == IEEE80211_M_IBSS); 5849 5850 /* 5851 * XXX Dont need to do this (and others) if we've transitioned 5852 * from SLEEP->RUN. 5853 */ 5854 if (stamode && nstate == IEEE80211_S_RUN) { 5855 sc->sc_curaid = ni->ni_associd; 5856 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5857 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5858 } 5859 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5860 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5861 ath_hal_setrxfilter(ah, rfilt); 5862 5863 /* XXX is this to restore keycache on resume? */ 5864 if (vap->iv_opmode != IEEE80211_M_STA && 5865 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5866 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5867 if (ath_hal_keyisvalid(ah, i)) 5868 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5869 } 5870 5871 /* 5872 * Invoke the parent method to do net80211 work. 5873 */ 5874 error = avp->av_newstate(vap, nstate, arg); 5875 if (error != 0) 5876 goto bad; 5877 5878 /* 5879 * See above: ensure av_newstate() doesn't drop the lock 5880 * on us. 5881 */ 5882 IEEE80211_LOCK_ASSERT(ic); 5883 5884 /* 5885 * XXX TODO: if nstate is _S_CAC, then we should disable 5886 * ACK processing until CAC is completed. 5887 */ 5888 5889 /* 5890 * XXX TODO: if we're on a passive channel, then we should 5891 * not allow any ACKs or self-generated frames until we hear 5892 * a beacon. Unfortunately there isn't a notification from 5893 * net80211 so perhaps we could slot that particular check 5894 * into the mgmt receive path and just ensure that we clear 5895 * it on RX of beacons in passive mode (and only clear it 5896 * once, obviously.) 5897 */ 5898 5899 /* 5900 * XXX TODO: net80211 should be tracking whether channels 5901 * have heard beacons and are thus considered "OK" for 5902 * transmitting - and then inform the driver about this 5903 * state change. That way if we hear an AP go quiet 5904 * (and nothing else is beaconing on a channel) the 5905 * channel can go back to being passive until another 5906 * beacon is heard. 5907 */ 5908 5909 /* 5910 * XXX TODO: if nstate is _S_CAC, then we should disable 5911 * ACK processing until CAC is completed. 5912 */ 5913 5914 /* 5915 * XXX TODO: if we're on a passive channel, then we should 5916 * not allow any ACKs or self-generated frames until we hear 5917 * a beacon. Unfortunately there isn't a notification from 5918 * net80211 so perhaps we could slot that particular check 5919 * into the mgmt receive path and just ensure that we clear 5920 * it on RX of beacons in passive mode (and only clear it 5921 * once, obviously.) 5922 */ 5923 5924 /* 5925 * XXX TODO: net80211 should be tracking whether channels 5926 * have heard beacons and are thus considered "OK" for 5927 * transmitting - and then inform the driver about this 5928 * state change. That way if we hear an AP go quiet 5929 * (and nothing else is beaconing on a channel) the 5930 * channel can go back to being passive until another 5931 * beacon is heard. 5932 */ 5933 5934 if (nstate == IEEE80211_S_RUN) { 5935 /* NB: collect bss node again, it may have changed */ 5936 ieee80211_free_node(ni); 5937 ni = ieee80211_ref_node(vap->iv_bss); 5938 5939 DPRINTF(sc, ATH_DEBUG_STATE, 5940 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5941 "capinfo 0x%04x chan %d\n", __func__, 5942 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5943 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5944 5945 switch (vap->iv_opmode) { 5946 #ifdef IEEE80211_SUPPORT_TDMA 5947 case IEEE80211_M_AHDEMO: 5948 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5949 break; 5950 /* fall thru... */ 5951 #endif 5952 case IEEE80211_M_HOSTAP: 5953 case IEEE80211_M_IBSS: 5954 case IEEE80211_M_MBSS: 5955 5956 /* 5957 * TODO: Enable ACK processing (ie, clear AR_DIAG_ACK_DIS.) 5958 * For channels that are in CAC, we may have disabled 5959 * this during CAC to ensure we don't ACK frames 5960 * sent to us. 5961 */ 5962 5963 /* 5964 * Allocate and setup the beacon frame. 5965 * 5966 * Stop any previous beacon DMA. This may be 5967 * necessary, for example, when an ibss merge 5968 * causes reconfiguration; there will be a state 5969 * transition from RUN->RUN that means we may 5970 * be called with beacon transmission active. 5971 */ 5972 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5973 5974 error = ath_beacon_alloc(sc, ni); 5975 if (error != 0) 5976 goto bad; 5977 /* 5978 * If joining an adhoc network defer beacon timer 5979 * configuration to the next beacon frame so we 5980 * have a current TSF to use. Otherwise we're 5981 * starting an ibss/bss so there's no need to delay; 5982 * if this is the first vap moving to RUN state, then 5983 * beacon state needs to be [re]configured. 5984 */ 5985 if (vap->iv_opmode == IEEE80211_M_IBSS && 5986 ni->ni_tstamp.tsf != 0) { 5987 sc->sc_syncbeacon = 1; 5988 } else if (!sc->sc_beacons) { 5989 #ifdef IEEE80211_SUPPORT_TDMA 5990 if (vap->iv_caps & IEEE80211_C_TDMA) 5991 ath_tdma_config(sc, vap); 5992 else 5993 #endif 5994 ath_beacon_config(sc, vap); 5995 sc->sc_beacons = 1; 5996 } 5997 break; 5998 case IEEE80211_M_STA: 5999 /* 6000 * Defer beacon timer configuration to the next 6001 * beacon frame so we have a current TSF to use 6002 * (any TSF collected when scanning is likely old). 6003 * However if it's due to a CSA -> RUN transition, 6004 * force a beacon update so we pick up a lack of 6005 * beacons from an AP in CAC and thus force a 6006 * scan. 6007 * 6008 * And, there's also corner cases here where 6009 * after a scan, the AP may have disappeared. 6010 * In that case, we may not receive an actual 6011 * beacon to update the beacon timer and thus we 6012 * won't get notified of the missing beacons. 6013 */ 6014 if (ostate != IEEE80211_S_RUN && 6015 ostate != IEEE80211_S_SLEEP) { 6016 DPRINTF(sc, ATH_DEBUG_BEACON, 6017 "%s: STA; syncbeacon=1\n", __func__); 6018 sc->sc_syncbeacon = 1; 6019 6020 /* Quiet time handling - ensure we resync */ 6021 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 6022 6023 if (csa_run_transition) 6024 ath_beacon_config(sc, vap); 6025 6026 /* 6027 * PR: kern/175227 6028 * 6029 * Reconfigure beacons during reset; as otherwise 6030 * we won't get the beacon timers reprogrammed 6031 * after a reset and thus we won't pick up a 6032 * beacon miss interrupt. 6033 * 6034 * Hopefully we'll see a beacon before the BMISS 6035 * timer fires (too often), leading to a STA 6036 * disassociation. 6037 */ 6038 sc->sc_beacons = 1; 6039 } 6040 break; 6041 case IEEE80211_M_MONITOR: 6042 /* 6043 * Monitor mode vaps have only INIT->RUN and RUN->RUN 6044 * transitions so we must re-enable interrupts here to 6045 * handle the case of a single monitor mode vap. 6046 */ 6047 ath_hal_intrset(ah, sc->sc_imask); 6048 break; 6049 case IEEE80211_M_WDS: 6050 break; 6051 default: 6052 break; 6053 } 6054 /* 6055 * Let the hal process statistics collected during a 6056 * scan so it can provide calibrated noise floor data. 6057 */ 6058 ath_hal_process_noisefloor(ah); 6059 /* 6060 * Reset rssi stats; maybe not the best place... 6061 */ 6062 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 6063 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 6064 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 6065 6066 /* 6067 * Force awake for RUN mode. 6068 */ 6069 ATH_LOCK(sc); 6070 ath_power_setselfgen(sc, HAL_PM_AWAKE); 6071 ath_power_setpower(sc, HAL_PM_AWAKE, 1); 6072 6073 /* 6074 * Finally, start any timers and the task q thread 6075 * (in case we didn't go through SCAN state). 6076 */ 6077 if (ath_longcalinterval != 0) { 6078 /* start periodic recalibration timer */ 6079 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 6080 } else { 6081 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 6082 "%s: calibration disabled\n", __func__); 6083 } 6084 ATH_UNLOCK(sc); 6085 6086 taskqueue_unblock(sc->sc_tq); 6087 } else if (nstate == IEEE80211_S_INIT) { 6088 6089 /* Quiet time handling - ensure we resync */ 6090 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 6091 6092 /* 6093 * If there are no vaps left in RUN state then 6094 * shutdown host/driver operation: 6095 * o disable interrupts 6096 * o disable the task queue thread 6097 * o mark beacon processing as stopped 6098 */ 6099 if (!ath_isanyrunningvaps(vap)) { 6100 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 6101 /* disable interrupts */ 6102 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 6103 taskqueue_block(sc->sc_tq); 6104 sc->sc_beacons = 0; 6105 } 6106 6107 /* 6108 * For at least STA mode we likely should clear the ANI 6109 * and NF calibration state and allow the NIC/HAL to figure 6110 * out optimal parameters at runtime. Otherwise if we 6111 * disassociate due to interference / deafness it may persist 6112 * when we reconnect. 6113 * 6114 * Note: may need to do this for other states too, not just 6115 * _S_INIT. 6116 */ 6117 #ifdef IEEE80211_SUPPORT_TDMA 6118 ath_hal_setcca(ah, AH_TRUE); 6119 #endif 6120 } else if (nstate == IEEE80211_S_SLEEP) { 6121 /* We're going to sleep, so transition appropriately */ 6122 /* For now, only do this if we're a single STA vap */ 6123 if (sc->sc_nvaps == 1 && 6124 vap->iv_opmode == IEEE80211_M_STA) { 6125 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: syncbeacon=%d\n", __func__, sc->sc_syncbeacon); 6126 ATH_LOCK(sc); 6127 /* 6128 * Always at least set the self-generated 6129 * frame config to set PWRMGT=1. 6130 */ 6131 ath_power_setselfgen(sc, HAL_PM_NETWORK_SLEEP); 6132 6133 /* 6134 * If we're not syncing beacons, transition 6135 * to NETWORK_SLEEP. 6136 * 6137 * We stay awake if syncbeacon > 0 in case 6138 * we need to listen for some beacons otherwise 6139 * our beacon timer config may be wrong. 6140 */ 6141 if (sc->sc_syncbeacon == 0) { 6142 ath_power_setpower(sc, HAL_PM_NETWORK_SLEEP, 1); 6143 } 6144 ATH_UNLOCK(sc); 6145 } 6146 6147 /* 6148 * Note - the ANI/calibration timer isn't re-enabled during 6149 * network sleep for now. One unfortunate side-effect is that 6150 * the PHY/airtime statistics aren't gathered on the channel 6151 * but I haven't yet tested to see if reading those registers 6152 * CAN occur during network sleep. 6153 * 6154 * This should be revisited in a future commit, even if it's 6155 * just to split out the airtime polling from ANI/calibration. 6156 */ 6157 } else if (nstate == IEEE80211_S_SCAN) { 6158 /* Quiet time handling - ensure we resync */ 6159 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie)); 6160 6161 /* 6162 * If we're in scan mode then startpcureceive() is 6163 * hopefully being called with "reset ANI" for this channel; 6164 * but once we attempt to reassociate we program in the previous 6165 * ANI values and.. not do any calibration until we're running. 6166 * This may mean we stay deaf unless we can associate successfully. 6167 * 6168 * So do kick off the cal timer to get NF/ANI going. 6169 */ 6170 ATH_LOCK(sc); 6171 if (ath_longcalinterval != 0) { 6172 /* start periodic recalibration timer */ 6173 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 6174 } else { 6175 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 6176 "%s: calibration disabled\n", __func__); 6177 } 6178 ATH_UNLOCK(sc); 6179 } 6180 bad: 6181 ieee80211_free_node(ni); 6182 6183 /* 6184 * Restore the power state - either to what it was, or 6185 * to network_sleep if it's alright. 6186 */ 6187 ATH_LOCK(sc); 6188 ath_power_restore_power_state(sc); 6189 ATH_UNLOCK(sc); 6190 return error; 6191 } 6192 6193 /* 6194 * Allocate a key cache slot to the station so we can 6195 * setup a mapping from key index to node. The key cache 6196 * slot is needed for managing antenna state and for 6197 * compression when stations do not use crypto. We do 6198 * it uniliaterally here; if crypto is employed this slot 6199 * will be reassigned. 6200 */ 6201 static void 6202 ath_setup_stationkey(struct ieee80211_node *ni) 6203 { 6204 struct ieee80211vap *vap = ni->ni_vap; 6205 struct ath_softc *sc = vap->iv_ic->ic_softc; 6206 ieee80211_keyix keyix, rxkeyix; 6207 6208 /* XXX should take a locked ref to vap->iv_bss */ 6209 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 6210 /* 6211 * Key cache is full; we'll fall back to doing 6212 * the more expensive lookup in software. Note 6213 * this also means no h/w compression. 6214 */ 6215 /* XXX msg+statistic */ 6216 } else { 6217 /* XXX locking? */ 6218 ni->ni_ucastkey.wk_keyix = keyix; 6219 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 6220 /* NB: must mark device key to get called back on delete */ 6221 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 6222 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 6223 /* NB: this will create a pass-thru key entry */ 6224 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss); 6225 } 6226 } 6227 6228 /* 6229 * Setup driver-specific state for a newly associated node. 6230 * Note that we're called also on a re-associate, the isnew 6231 * param tells us if this is the first time or not. 6232 */ 6233 static void 6234 ath_newassoc(struct ieee80211_node *ni, int isnew) 6235 { 6236 struct ath_node *an = ATH_NODE(ni); 6237 struct ieee80211vap *vap = ni->ni_vap; 6238 struct ath_softc *sc = vap->iv_ic->ic_softc; 6239 const struct ieee80211_txparam *tp = ni->ni_txparms; 6240 6241 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 6242 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 6243 6244 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: reassoc; isnew=%d, is_powersave=%d\n", 6245 __func__, 6246 ni->ni_macaddr, 6247 ":", 6248 isnew, 6249 an->an_is_powersave); 6250 6251 ATH_NODE_LOCK(an); 6252 ath_rate_newassoc(sc, an, isnew); 6253 ATH_NODE_UNLOCK(an); 6254 6255 if (isnew && 6256 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 6257 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 6258 ath_setup_stationkey(ni); 6259 6260 /* 6261 * If we're reassociating, make sure that any paused queues 6262 * get unpaused. 6263 * 6264 * Now, we may have frames in the hardware queue for this node. 6265 * So if we are reassociating and there are frames in the queue, 6266 * we need to go through the cleanup path to ensure that they're 6267 * marked as non-aggregate. 6268 */ 6269 if (! isnew) { 6270 DPRINTF(sc, ATH_DEBUG_NODE, 6271 "%s: %6D: reassoc; is_powersave=%d\n", 6272 __func__, 6273 ni->ni_macaddr, 6274 ":", 6275 an->an_is_powersave); 6276 6277 /* XXX for now, we can't hold the lock across assoc */ 6278 ath_tx_node_reassoc(sc, an); 6279 6280 /* XXX for now, we can't hold the lock across wakeup */ 6281 if (an->an_is_powersave) 6282 ath_tx_node_wakeup(sc, an); 6283 } 6284 } 6285 6286 static int 6287 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 6288 int nchans, struct ieee80211_channel chans[]) 6289 { 6290 struct ath_softc *sc = ic->ic_softc; 6291 struct ath_hal *ah = sc->sc_ah; 6292 HAL_STATUS status; 6293 6294 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 6295 "%s: rd %u cc %u location %c%s\n", 6296 __func__, reg->regdomain, reg->country, reg->location, 6297 reg->ecm ? " ecm" : ""); 6298 6299 status = ath_hal_set_channels(ah, chans, nchans, 6300 reg->country, reg->regdomain); 6301 if (status != HAL_OK) { 6302 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 6303 __func__, status); 6304 return EINVAL; /* XXX */ 6305 } 6306 6307 return 0; 6308 } 6309 6310 static void 6311 ath_getradiocaps(struct ieee80211com *ic, 6312 int maxchans, int *nchans, struct ieee80211_channel chans[]) 6313 { 6314 struct ath_softc *sc = ic->ic_softc; 6315 struct ath_hal *ah = sc->sc_ah; 6316 6317 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 6318 __func__, SKU_DEBUG, CTRY_DEFAULT); 6319 6320 /* XXX check return */ 6321 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 6322 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 6323 6324 } 6325 6326 static int 6327 ath_getchannels(struct ath_softc *sc) 6328 { 6329 struct ieee80211com *ic = &sc->sc_ic; 6330 struct ath_hal *ah = sc->sc_ah; 6331 HAL_STATUS status; 6332 6333 /* 6334 * Collect channel set based on EEPROM contents. 6335 */ 6336 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 6337 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 6338 if (status != HAL_OK) { 6339 device_printf(sc->sc_dev, 6340 "%s: unable to collect channel list from hal, status %d\n", 6341 __func__, status); 6342 return EINVAL; 6343 } 6344 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 6345 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 6346 /* XXX map Atheros sku's to net80211 SKU's */ 6347 /* XXX net80211 types too small */ 6348 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 6349 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 6350 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 6351 ic->ic_regdomain.isocc[1] = ' '; 6352 6353 ic->ic_regdomain.ecm = 1; 6354 ic->ic_regdomain.location = 'I'; 6355 6356 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 6357 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 6358 __func__, sc->sc_eerd, sc->sc_eecc, 6359 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 6360 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 6361 return 0; 6362 } 6363 6364 static int 6365 ath_rate_setup(struct ath_softc *sc, u_int mode) 6366 { 6367 struct ath_hal *ah = sc->sc_ah; 6368 const HAL_RATE_TABLE *rt; 6369 6370 switch (mode) { 6371 case IEEE80211_MODE_11A: 6372 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 6373 break; 6374 case IEEE80211_MODE_HALF: 6375 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 6376 break; 6377 case IEEE80211_MODE_QUARTER: 6378 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 6379 break; 6380 case IEEE80211_MODE_11B: 6381 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 6382 break; 6383 case IEEE80211_MODE_11G: 6384 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 6385 break; 6386 case IEEE80211_MODE_TURBO_A: 6387 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 6388 break; 6389 case IEEE80211_MODE_TURBO_G: 6390 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 6391 break; 6392 case IEEE80211_MODE_STURBO_A: 6393 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 6394 break; 6395 case IEEE80211_MODE_11NA: 6396 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 6397 break; 6398 case IEEE80211_MODE_11NG: 6399 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 6400 break; 6401 default: 6402 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 6403 __func__, mode); 6404 return 0; 6405 } 6406 sc->sc_rates[mode] = rt; 6407 return (rt != NULL); 6408 } 6409 6410 static void 6411 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 6412 { 6413 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 6414 static const struct { 6415 u_int rate; /* tx/rx 802.11 rate */ 6416 u_int16_t timeOn; /* LED on time (ms) */ 6417 u_int16_t timeOff; /* LED off time (ms) */ 6418 } blinkrates[] = { 6419 { 108, 40, 10 }, 6420 { 96, 44, 11 }, 6421 { 72, 50, 13 }, 6422 { 48, 57, 14 }, 6423 { 36, 67, 16 }, 6424 { 24, 80, 20 }, 6425 { 22, 100, 25 }, 6426 { 18, 133, 34 }, 6427 { 12, 160, 40 }, 6428 { 10, 200, 50 }, 6429 { 6, 240, 58 }, 6430 { 4, 267, 66 }, 6431 { 2, 400, 100 }, 6432 { 0, 500, 130 }, 6433 /* XXX half/quarter rates */ 6434 }; 6435 const HAL_RATE_TABLE *rt; 6436 int i, j; 6437 6438 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 6439 rt = sc->sc_rates[mode]; 6440 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 6441 for (i = 0; i < rt->rateCount; i++) { 6442 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6443 if (rt->info[i].phy != IEEE80211_T_HT) 6444 sc->sc_rixmap[ieeerate] = i; 6445 else 6446 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 6447 } 6448 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6449 for (i = 0; i < nitems(sc->sc_hwmap); i++) { 6450 if (i >= rt->rateCount) { 6451 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6452 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6453 continue; 6454 } 6455 sc->sc_hwmap[i].ieeerate = 6456 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6457 if (rt->info[i].phy == IEEE80211_T_HT) 6458 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 6459 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6460 if (rt->info[i].shortPreamble || 6461 rt->info[i].phy == IEEE80211_T_OFDM) 6462 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6463 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 6464 for (j = 0; j < nitems(blinkrates)-1; j++) 6465 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6466 break; 6467 /* NB: this uses the last entry if the rate isn't found */ 6468 /* XXX beware of overlow */ 6469 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6470 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6471 } 6472 sc->sc_currates = rt; 6473 sc->sc_curmode = mode; 6474 /* 6475 * All protection frames are transmitted at 2Mb/s for 6476 * 11g, otherwise at 1Mb/s. 6477 */ 6478 if (mode == IEEE80211_MODE_11G) 6479 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 6480 else 6481 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 6482 /* NB: caller is responsible for resetting rate control state */ 6483 } 6484 6485 static void 6486 ath_watchdog(void *arg) 6487 { 6488 struct ath_softc *sc = arg; 6489 struct ieee80211com *ic = &sc->sc_ic; 6490 int do_reset = 0; 6491 6492 ATH_LOCK_ASSERT(sc); 6493 6494 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 6495 uint32_t hangs; 6496 6497 ath_power_set_power_state(sc, HAL_PM_AWAKE); 6498 6499 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 6500 hangs != 0) { 6501 device_printf(sc->sc_dev, "%s hang detected (0x%x)\n", 6502 hangs & 0xff ? "bb" : "mac", hangs); 6503 } else 6504 device_printf(sc->sc_dev, "device timeout\n"); 6505 do_reset = 1; 6506 counter_u64_add(ic->ic_oerrors, 1); 6507 sc->sc_stats.ast_watchdog++; 6508 6509 ath_power_restore_power_state(sc); 6510 } 6511 6512 /* 6513 * We can't hold the lock across the ath_reset() call. 6514 * 6515 * And since this routine can't hold a lock and sleep, 6516 * do the reset deferred. 6517 */ 6518 if (do_reset) { 6519 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask); 6520 } 6521 6522 callout_schedule(&sc->sc_wd_ch, hz); 6523 } 6524 6525 static void 6526 ath_parent(struct ieee80211com *ic) 6527 { 6528 struct ath_softc *sc = ic->ic_softc; 6529 int error = EDOOFUS; 6530 6531 ATH_LOCK(sc); 6532 if (ic->ic_nrunning > 0) { 6533 /* 6534 * To avoid rescanning another access point, 6535 * do not call ath_init() here. Instead, 6536 * only reflect promisc mode settings. 6537 */ 6538 if (sc->sc_running) { 6539 ath_power_set_power_state(sc, HAL_PM_AWAKE); 6540 ath_mode_init(sc); 6541 ath_power_restore_power_state(sc); 6542 } else if (!sc->sc_invalid) { 6543 /* 6544 * Beware of being called during attach/detach 6545 * to reset promiscuous mode. In that case we 6546 * will still be marked UP but not RUNNING. 6547 * However trying to re-init the interface 6548 * is the wrong thing to do as we've already 6549 * torn down much of our state. There's 6550 * probably a better way to deal with this. 6551 */ 6552 error = ath_init(sc); 6553 } 6554 } else { 6555 ath_stop(sc); 6556 if (!sc->sc_invalid) 6557 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1); 6558 } 6559 ATH_UNLOCK(sc); 6560 6561 if (error == 0) { 6562 #ifdef ATH_TX99_DIAG 6563 if (sc->sc_tx99 != NULL) 6564 sc->sc_tx99->start(sc->sc_tx99); 6565 else 6566 #endif 6567 ieee80211_start_all(ic); 6568 } 6569 } 6570 6571 /* 6572 * Announce various information on device/driver attach. 6573 */ 6574 static void 6575 ath_announce(struct ath_softc *sc) 6576 { 6577 struct ath_hal *ah = sc->sc_ah; 6578 6579 device_printf(sc->sc_dev, "%s mac %d.%d RF%s phy %d.%d\n", 6580 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 6581 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 6582 device_printf(sc->sc_dev, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n", 6583 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev); 6584 if (bootverbose) { 6585 int i; 6586 for (i = 0; i <= WME_AC_VO; i++) { 6587 struct ath_txq *txq = sc->sc_ac2q[i]; 6588 device_printf(sc->sc_dev, 6589 "Use hw queue %u for %s traffic\n", 6590 txq->axq_qnum, ieee80211_wme_acnames[i]); 6591 } 6592 device_printf(sc->sc_dev, "Use hw queue %u for CAB traffic\n", 6593 sc->sc_cabq->axq_qnum); 6594 device_printf(sc->sc_dev, "Use hw queue %u for beacons\n", 6595 sc->sc_bhalq); 6596 } 6597 if (ath_rxbuf != ATH_RXBUF) 6598 device_printf(sc->sc_dev, "using %u rx buffers\n", ath_rxbuf); 6599 if (ath_txbuf != ATH_TXBUF) 6600 device_printf(sc->sc_dev, "using %u tx buffers\n", ath_txbuf); 6601 if (sc->sc_mcastkey && bootverbose) 6602 device_printf(sc->sc_dev, "using multicast key search\n"); 6603 } 6604 6605 static void 6606 ath_dfs_tasklet(void *p, int npending) 6607 { 6608 struct ath_softc *sc = (struct ath_softc *) p; 6609 struct ieee80211com *ic = &sc->sc_ic; 6610 6611 /* 6612 * If previous processing has found a radar event, 6613 * signal this to the net80211 layer to begin DFS 6614 * processing. 6615 */ 6616 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) { 6617 /* DFS event found, initiate channel change */ 6618 6619 /* 6620 * XXX TODO: immediately disable ACK processing 6621 * on the current channel. This would be done 6622 * by setting AR_DIAG_ACK_DIS (AR5212; may be 6623 * different for others) until we are out of 6624 * CAC. 6625 */ 6626 6627 /* 6628 * XXX doesn't currently tell us whether the event 6629 * XXX was found in the primary or extension 6630 * XXX channel! 6631 */ 6632 IEEE80211_LOCK(ic); 6633 ieee80211_dfs_notify_radar(ic, sc->sc_curchan); 6634 IEEE80211_UNLOCK(ic); 6635 } 6636 } 6637 6638 /* 6639 * Enable/disable power save. This must be called with 6640 * no TX driver locks currently held, so it should only 6641 * be called from the RX path (which doesn't hold any 6642 * TX driver locks.) 6643 */ 6644 static void 6645 ath_node_powersave(struct ieee80211_node *ni, int enable) 6646 { 6647 #ifdef ATH_SW_PSQ 6648 struct ath_node *an = ATH_NODE(ni); 6649 struct ieee80211com *ic = ni->ni_ic; 6650 struct ath_softc *sc = ic->ic_softc; 6651 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6652 6653 /* XXX and no TXQ locks should be held here */ 6654 6655 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n", 6656 __func__, 6657 ni->ni_macaddr, 6658 ":", 6659 !! enable); 6660 6661 /* Suspend or resume software queue handling */ 6662 if (enable) 6663 ath_tx_node_sleep(sc, an); 6664 else 6665 ath_tx_node_wakeup(sc, an); 6666 6667 /* Update net80211 state */ 6668 avp->av_node_ps(ni, enable); 6669 #else 6670 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6671 6672 /* Update net80211 state */ 6673 avp->av_node_ps(ni, enable); 6674 #endif/* ATH_SW_PSQ */ 6675 } 6676 6677 /* 6678 * Notification from net80211 that the powersave queue state has 6679 * changed. 6680 * 6681 * Since the software queue also may have some frames: 6682 * 6683 * + if the node software queue has frames and the TID state 6684 * is 0, we set the TIM; 6685 * + if the node and the stack are both empty, we clear the TIM bit. 6686 * + If the stack tries to set the bit, always set it. 6687 * + If the stack tries to clear the bit, only clear it if the 6688 * software queue in question is also cleared. 6689 * 6690 * TODO: this is called during node teardown; so let's ensure this 6691 * is all correctly handled and that the TIM bit is cleared. 6692 * It may be that the node flush is called _AFTER_ the net80211 6693 * stack clears the TIM. 6694 * 6695 * Here is the racy part. Since it's possible >1 concurrent, 6696 * overlapping TXes will appear complete with a TX completion in 6697 * another thread, it's possible that the concurrent TIM calls will 6698 * clash. We can't hold the node lock here because setting the 6699 * TIM grabs the net80211 comlock and this may cause a LOR. 6700 * The solution is either to totally serialise _everything_ at 6701 * this point (ie, all TX, completion and any reset/flush go into 6702 * one taskqueue) or a new "ath TIM lock" needs to be created that 6703 * just wraps the driver state change and this call to avp->av_set_tim(). 6704 * 6705 * The same race exists in the net80211 power save queue handling 6706 * as well. Since multiple transmitting threads may queue frames 6707 * into the driver, as well as ps-poll and the driver transmitting 6708 * frames (and thus clearing the psq), it's quite possible that 6709 * a packet entering the PSQ and a ps-poll being handled will 6710 * race, causing the TIM to be cleared and not re-set. 6711 */ 6712 static int 6713 ath_node_set_tim(struct ieee80211_node *ni, int enable) 6714 { 6715 #ifdef ATH_SW_PSQ 6716 struct ieee80211com *ic = ni->ni_ic; 6717 struct ath_softc *sc = ic->ic_softc; 6718 struct ath_node *an = ATH_NODE(ni); 6719 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6720 int changed = 0; 6721 6722 ATH_TX_LOCK(sc); 6723 an->an_stack_psq = enable; 6724 6725 /* 6726 * This will get called for all operating modes, 6727 * even if avp->av_set_tim is unset. 6728 * It's currently set for hostap/ibss modes; but 6729 * the same infrastructure is used for both STA 6730 * and AP/IBSS node power save. 6731 */ 6732 if (avp->av_set_tim == NULL) { 6733 ATH_TX_UNLOCK(sc); 6734 return (0); 6735 } 6736 6737 /* 6738 * If setting the bit, always set it here. 6739 * If clearing the bit, only clear it if the 6740 * software queue is also empty. 6741 * 6742 * If the node has left power save, just clear the TIM 6743 * bit regardless of the state of the power save queue. 6744 * 6745 * XXX TODO: although atomics are used, it's quite possible 6746 * that a race will occur between this and setting/clearing 6747 * in another thread. TX completion will occur always in 6748 * one thread, however setting/clearing the TIM bit can come 6749 * from a variety of different process contexts! 6750 */ 6751 if (enable && an->an_tim_set == 1) { 6752 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6753 "%s: %6D: enable=%d, tim_set=1, ignoring\n", 6754 __func__, 6755 ni->ni_macaddr, 6756 ":", 6757 enable); 6758 ATH_TX_UNLOCK(sc); 6759 } else if (enable) { 6760 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6761 "%s: %6D: enable=%d, enabling TIM\n", 6762 __func__, 6763 ni->ni_macaddr, 6764 ":", 6765 enable); 6766 an->an_tim_set = 1; 6767 ATH_TX_UNLOCK(sc); 6768 changed = avp->av_set_tim(ni, enable); 6769 } else if (an->an_swq_depth == 0) { 6770 /* disable */ 6771 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6772 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n", 6773 __func__, 6774 ni->ni_macaddr, 6775 ":", 6776 enable); 6777 an->an_tim_set = 0; 6778 ATH_TX_UNLOCK(sc); 6779 changed = avp->av_set_tim(ni, enable); 6780 } else if (! an->an_is_powersave) { 6781 /* 6782 * disable regardless; the node isn't in powersave now 6783 */ 6784 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6785 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n", 6786 __func__, 6787 ni->ni_macaddr, 6788 ":", 6789 enable); 6790 an->an_tim_set = 0; 6791 ATH_TX_UNLOCK(sc); 6792 changed = avp->av_set_tim(ni, enable); 6793 } else { 6794 /* 6795 * psq disable, node is currently in powersave, node 6796 * software queue isn't empty, so don't clear the TIM bit 6797 * for now. 6798 */ 6799 ATH_TX_UNLOCK(sc); 6800 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6801 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n", 6802 __func__, 6803 ni->ni_macaddr, 6804 ":", 6805 enable); 6806 changed = 0; 6807 } 6808 6809 return (changed); 6810 #else 6811 struct ath_vap *avp = ATH_VAP(ni->ni_vap); 6812 6813 /* 6814 * Some operating modes don't set av_set_tim(), so don't 6815 * update it here. 6816 */ 6817 if (avp->av_set_tim == NULL) 6818 return (0); 6819 6820 return (avp->av_set_tim(ni, enable)); 6821 #endif /* ATH_SW_PSQ */ 6822 } 6823 6824 /* 6825 * Set or update the TIM from the software queue. 6826 * 6827 * Check the software queue depth before attempting to do lock 6828 * anything; that avoids trying to obtain the lock. Then, 6829 * re-check afterwards to ensure nothing has changed in the 6830 * meantime. 6831 * 6832 * set: This is designed to be called from the TX path, after 6833 * a frame has been queued; to see if the swq > 0. 6834 * 6835 * clear: This is designed to be called from the buffer completion point 6836 * (right now it's ath_tx_default_comp()) where the state of 6837 * a software queue has changed. 6838 * 6839 * It makes sense to place it at buffer free / completion rather 6840 * than after each software queue operation, as there's no real 6841 * point in churning the TIM bit as the last frames in the software 6842 * queue are transmitted. If they fail and we retry them, we'd 6843 * just be setting the TIM bit again anyway. 6844 */ 6845 void 6846 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni, 6847 int enable) 6848 { 6849 #ifdef ATH_SW_PSQ 6850 struct ath_node *an; 6851 struct ath_vap *avp; 6852 6853 /* Don't do this for broadcast/etc frames */ 6854 if (ni == NULL) 6855 return; 6856 6857 an = ATH_NODE(ni); 6858 avp = ATH_VAP(ni->ni_vap); 6859 6860 /* 6861 * And for operating modes without the TIM handler set, let's 6862 * just skip those. 6863 */ 6864 if (avp->av_set_tim == NULL) 6865 return; 6866 6867 ATH_TX_LOCK_ASSERT(sc); 6868 6869 if (enable) { 6870 if (an->an_is_powersave && 6871 an->an_tim_set == 0 && 6872 an->an_swq_depth != 0) { 6873 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6874 "%s: %6D: swq_depth>0, tim_set=0, set!\n", 6875 __func__, 6876 ni->ni_macaddr, 6877 ":"); 6878 an->an_tim_set = 1; 6879 (void) avp->av_set_tim(ni, 1); 6880 } 6881 } else { 6882 /* 6883 * Don't bother grabbing the lock unless the queue is empty. 6884 */ 6885 if (an->an_swq_depth != 0) 6886 return; 6887 6888 if (an->an_is_powersave && 6889 an->an_stack_psq == 0 && 6890 an->an_tim_set == 1 && 6891 an->an_swq_depth == 0) { 6892 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6893 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0," 6894 " clear!\n", 6895 __func__, 6896 ni->ni_macaddr, 6897 ":"); 6898 an->an_tim_set = 0; 6899 (void) avp->av_set_tim(ni, 0); 6900 } 6901 } 6902 #else 6903 return; 6904 #endif /* ATH_SW_PSQ */ 6905 } 6906 6907 /* 6908 * Received a ps-poll frame from net80211. 6909 * 6910 * Here we get a chance to serve out a software-queued frame ourselves 6911 * before we punt it to net80211 to transmit us one itself - either 6912 * because there's traffic in the net80211 psq, or a NULL frame to 6913 * indicate there's nothing else. 6914 */ 6915 static void 6916 ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m) 6917 { 6918 #ifdef ATH_SW_PSQ 6919 struct ath_node *an; 6920 struct ath_vap *avp; 6921 struct ieee80211com *ic = ni->ni_ic; 6922 struct ath_softc *sc = ic->ic_softc; 6923 int tid; 6924 6925 /* Just paranoia */ 6926 if (ni == NULL) 6927 return; 6928 6929 /* 6930 * Unassociated (temporary node) station. 6931 */ 6932 if (ni->ni_associd == 0) 6933 return; 6934 6935 /* 6936 * We do have an active node, so let's begin looking into it. 6937 */ 6938 an = ATH_NODE(ni); 6939 avp = ATH_VAP(ni->ni_vap); 6940 6941 /* 6942 * For now, we just call the original ps-poll method. 6943 * Once we're ready to flip this on: 6944 * 6945 * + Set leak to 1, as no matter what we're going to have 6946 * to send a frame; 6947 * + Check the software queue and if there's something in it, 6948 * schedule the highest TID thas has traffic from this node. 6949 * Then make sure we schedule the software scheduler to 6950 * run so it picks up said frame. 6951 * 6952 * That way whatever happens, we'll at least send _a_ frame 6953 * to the given node. 6954 * 6955 * Again, yes, it's crappy QoS if the node has multiple 6956 * TIDs worth of traffic - but let's get it working first 6957 * before we optimise it. 6958 * 6959 * Also yes, there's definitely latency here - we're not 6960 * direct dispatching to the hardware in this path (and 6961 * we're likely being called from the packet receive path, 6962 * so going back into TX may be a little hairy!) but again 6963 * I'd like to get this working first before optimising 6964 * turn-around time. 6965 */ 6966 6967 ATH_TX_LOCK(sc); 6968 6969 /* 6970 * Legacy - we're called and the node isn't asleep. 6971 * Immediately punt. 6972 */ 6973 if (! an->an_is_powersave) { 6974 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 6975 "%s: %6D: not in powersave?\n", 6976 __func__, 6977 ni->ni_macaddr, 6978 ":"); 6979 ATH_TX_UNLOCK(sc); 6980 avp->av_recv_pspoll(ni, m); 6981 return; 6982 } 6983 6984 /* 6985 * We're in powersave. 6986 * 6987 * Leak a frame. 6988 */ 6989 an->an_leak_count = 1; 6990 6991 /* 6992 * Now, if there's no frames in the node, just punt to 6993 * recv_pspoll. 6994 * 6995 * Don't bother checking if the TIM bit is set, we really 6996 * only care if there are any frames here! 6997 */ 6998 if (an->an_swq_depth == 0) { 6999 ATH_TX_UNLOCK(sc); 7000 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 7001 "%s: %6D: SWQ empty; punting to net80211\n", 7002 __func__, 7003 ni->ni_macaddr, 7004 ":"); 7005 avp->av_recv_pspoll(ni, m); 7006 return; 7007 } 7008 7009 /* 7010 * Ok, let's schedule the highest TID that has traffic 7011 * and then schedule something. 7012 */ 7013 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) { 7014 struct ath_tid *atid = &an->an_tid[tid]; 7015 /* 7016 * No frames? Skip. 7017 */ 7018 if (atid->axq_depth == 0) 7019 continue; 7020 ath_tx_tid_sched(sc, atid); 7021 /* 7022 * XXX we could do a direct call to the TXQ 7023 * scheduler code here to optimise latency 7024 * at the expense of a REALLY deep callstack. 7025 */ 7026 ATH_TX_UNLOCK(sc); 7027 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 7028 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 7029 "%s: %6D: leaking frame to TID %d\n", 7030 __func__, 7031 ni->ni_macaddr, 7032 ":", 7033 tid); 7034 return; 7035 } 7036 7037 ATH_TX_UNLOCK(sc); 7038 7039 /* 7040 * XXX nothing in the TIDs at this point? Eek. 7041 */ 7042 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, 7043 "%s: %6D: TIDs empty, but ath_node showed traffic?!\n", 7044 __func__, 7045 ni->ni_macaddr, 7046 ":"); 7047 avp->av_recv_pspoll(ni, m); 7048 #else 7049 avp->av_recv_pspoll(ni, m); 7050 #endif /* ATH_SW_PSQ */ 7051 } 7052 7053 MODULE_VERSION(ath_main, 1); 7054 MODULE_DEPEND(ath_main, wlan, 1, 1, 1); /* 802.11 media layer */ 7055 MODULE_DEPEND(ath_main, ath_rate, 1, 1, 1); 7056 MODULE_DEPEND(ath_main, ath_dfs, 1, 1, 1); 7057 MODULE_DEPEND(ath_main, ath_hal, 1, 1, 1); 7058 #if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) || defined(ATH_DEBUG_ALQ) 7059 MODULE_DEPEND(ath_main, alq, 1, 1, 1); 7060 #endif 7061