1 /*- 2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 /* 41 * Driver for the Atheros Wireless LAN controller. 42 * 43 * This software is derived from work of Atsushi Onoe; his contribution 44 * is greatly appreciated. 45 */ 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/lock.h> 55 #include <sys/mutex.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/errno.h> 60 #include <sys/callout.h> 61 #include <sys/bus.h> 62 #include <sys/endian.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_arp.h> 70 #include <net/ethernet.h> 71 #include <net/if_llc.h> 72 73 #include <net80211/ieee80211_var.h> 74 75 #include <net/bpf.h> 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/if_ether.h> 80 #endif 81 82 #define AR_DEBUG 83 #include <dev/ath/if_athvar.h> 84 #include <contrib/dev/ath/ah_desc.h> 85 86 /* unalligned little endian access */ 87 #define LE_READ_2(p) \ 88 ((u_int16_t) \ 89 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 90 #define LE_READ_4(p) \ 91 ((u_int32_t) \ 92 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 93 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 94 95 static void ath_init(void *); 96 static void ath_stop(struct ifnet *); 97 static void ath_start(struct ifnet *); 98 static void ath_reset(struct ath_softc *); 99 static int ath_media_change(struct ifnet *); 100 static void ath_watchdog(struct ifnet *); 101 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 102 static void ath_fatal_proc(void *, int); 103 static void ath_rxorn_proc(void *, int); 104 static void ath_bmiss_proc(void *, int); 105 static void ath_initkeytable(struct ath_softc *); 106 static void ath_mode_init(struct ath_softc *); 107 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 108 static void ath_beacon_proc(void *, int); 109 static void ath_beacon_free(struct ath_softc *); 110 static void ath_beacon_config(struct ath_softc *); 111 static int ath_desc_alloc(struct ath_softc *); 112 static void ath_desc_free(struct ath_softc *); 113 static struct ieee80211_node *ath_node_alloc(struct ieee80211com *); 114 static void ath_node_free(struct ieee80211com *, struct ieee80211_node *); 115 static void ath_node_copy(struct ieee80211com *, 116 struct ieee80211_node *, const struct ieee80211_node *); 117 static u_int8_t ath_node_getrssi(struct ieee80211com *, 118 struct ieee80211_node *); 119 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 120 static void ath_rx_proc(void *, int); 121 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 122 struct ath_buf *, struct mbuf *); 123 static void ath_tx_proc(void *, int); 124 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 125 static void ath_draintxq(struct ath_softc *); 126 static void ath_stoprecv(struct ath_softc *); 127 static int ath_startrecv(struct ath_softc *); 128 static void ath_next_scan(void *); 129 static void ath_calibrate(void *); 130 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 131 static void ath_newassoc(struct ieee80211com *, 132 struct ieee80211_node *, int); 133 static int ath_getchannels(struct ath_softc *, u_int cc, HAL_BOOL outdoor); 134 135 static int ath_rate_setup(struct ath_softc *sc, u_int mode); 136 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 137 static void ath_rate_ctl_reset(struct ath_softc *, enum ieee80211_state); 138 static void ath_rate_ctl(void *, struct ieee80211_node *); 139 140 SYSCTL_DECL(_hw_ath); 141 142 /* XXX validate sysctl values */ 143 static int ath_dwelltime = 200; /* 5 channels/second */ 144 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 145 0, "channel dwell time (ms) for AP/station scanning"); 146 static int ath_calinterval = 30; /* calibrate every 30 secs */ 147 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 148 0, "chip calibration interval (secs)"); 149 static int ath_outdoor = AH_TRUE; /* outdoor operation */ 150 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 151 0, "enable/disable outdoor operation"); 152 static int ath_countrycode = CTRY_DEFAULT; /* country code */ 153 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 154 0, "country code"); 155 static int ath_regdomain = 0; /* regulatory domain */ 156 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 157 0, "regulatory domain"); 158 159 #ifdef AR_DEBUG 160 int ath_debug = 0; 161 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 162 0, "control debugging printfs"); 163 #define IFF_DUMPPKTS(_ifp) \ 164 (ath_debug || \ 165 ((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 166 static void ath_printrxbuf(struct ath_buf *bf, int); 167 static void ath_printtxbuf(struct ath_buf *bf, int); 168 #define DPRINTF(X) if (ath_debug) printf X 169 #define DPRINTF2(X) if (ath_debug > 1) printf X 170 #else 171 #define IFF_DUMPPKTS(_ifp) \ 172 (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 173 #define DPRINTF(X) 174 #define DPRINTF2(X) 175 #endif 176 177 int 178 ath_attach(u_int16_t devid, struct ath_softc *sc) 179 { 180 struct ieee80211com *ic = &sc->sc_ic; 181 struct ifnet *ifp = &ic->ic_if; 182 struct ath_hal *ah; 183 HAL_STATUS status; 184 int error = 0; 185 186 DPRINTF(("ath_attach: devid 0x%x\n", devid)); 187 188 /* set these up early for if_printf use */ 189 ifp->if_unit = device_get_unit(sc->sc_dev); 190 ifp->if_name = "ath"; 191 192 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 193 if (ah == NULL) { 194 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 195 status); 196 error = ENXIO; 197 goto bad; 198 } 199 sc->sc_ah = ah; 200 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 201 202 /* 203 * Collect the channel list using the default country 204 * code and including outdoor channels. The 802.11 layer 205 * is resposible for filtering this list based on settings 206 * like the phy mode. 207 */ 208 error = ath_getchannels(sc, ath_countrycode, ath_outdoor); 209 if (error != 0) 210 goto bad; 211 /* 212 * Copy these back; they are set as a side effect 213 * of constructing the channel list. 214 */ 215 ath_regdomain = ath_hal_getregdomain(ah); 216 ath_countrycode = ath_hal_getcountrycode(ah); 217 218 /* 219 * Setup rate tables for all potential media types. 220 */ 221 ath_rate_setup(sc, IEEE80211_MODE_11A); 222 ath_rate_setup(sc, IEEE80211_MODE_11B); 223 ath_rate_setup(sc, IEEE80211_MODE_11G); 224 ath_rate_setup(sc, IEEE80211_MODE_TURBO); 225 226 error = ath_desc_alloc(sc); 227 if (error != 0) { 228 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 229 goto bad; 230 } 231 callout_init(&sc->sc_scan_ch, CALLOUT_MPSAFE); 232 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 233 234 mtx_init(&sc->sc_txbuflock, 235 device_get_nameunit(sc->sc_dev), "xmit buf q", MTX_DEF); 236 mtx_init(&sc->sc_txqlock, 237 device_get_nameunit(sc->sc_dev), "xmit q", MTX_DEF); 238 239 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 240 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 241 TASK_INIT(&sc->sc_swbatask, 0, ath_beacon_proc, sc); 242 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 243 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 244 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 245 246 /* 247 * For now just pre-allocate one data queue and one 248 * beacon queue. Note that the HAL handles resetting 249 * them at the needed time. Eventually we'll want to 250 * allocate more tx queues for splitting management 251 * frames and for QOS support. 252 */ 253 sc->sc_txhalq = ath_hal_setuptxqueue(ah, 254 HAL_TX_QUEUE_DATA, 255 AH_TRUE /* enable interrupts */ 256 ); 257 if (sc->sc_txhalq == (u_int) -1) { 258 if_printf(ifp, "unable to setup a data xmit queue!\n"); 259 goto bad; 260 } 261 sc->sc_bhalq = ath_hal_setuptxqueue(ah, 262 HAL_TX_QUEUE_BEACON, 263 AH_TRUE /* enable interrupts */ 264 ); 265 if (sc->sc_bhalq == (u_int) -1) { 266 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 267 goto bad; 268 } 269 270 ifp->if_softc = sc; 271 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 272 ifp->if_start = ath_start; 273 ifp->if_watchdog = ath_watchdog; 274 ifp->if_ioctl = ath_ioctl; 275 ifp->if_init = ath_init; 276 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 277 278 ic->ic_softc = sc; 279 ic->ic_newassoc = ath_newassoc; 280 /* XXX not right but it's not used anywhere important */ 281 ic->ic_phytype = IEEE80211_T_OFDM; 282 ic->ic_opmode = IEEE80211_M_STA; 283 ic->ic_caps = IEEE80211_C_WEP | IEEE80211_C_IBSS | IEEE80211_C_HOSTAP 284 | IEEE80211_C_MONITOR | IEEE80211_C_SHPREAMBLE; 285 286 /* get mac address from hardware */ 287 ath_hal_getmac(ah, ic->ic_myaddr); 288 289 /* call MI attach routine. */ 290 ieee80211_ifattach(ifp); 291 /* override default methods */ 292 ic->ic_node_alloc = ath_node_alloc; 293 ic->ic_node_free = ath_node_free; 294 ic->ic_node_copy = ath_node_copy; 295 ic->ic_node_getrssi = ath_node_getrssi; 296 sc->sc_newstate = ic->ic_newstate; 297 ic->ic_newstate = ath_newstate; 298 /* complete initialization */ 299 ieee80211_media_init(ifp, ath_media_change, ieee80211_media_status); 300 301 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 302 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 303 &sc->sc_drvbpf); 304 /* 305 * Initialize constant fields. 306 * 307 * NB: the channel is setup each time we transition to the 308 * RUN state to avoid filling it in for each frame. 309 */ 310 sc->sc_tx_th.wt_ihdr.it_len = sizeof(sc->sc_tx_th); 311 sc->sc_tx_th.wt_ihdr.it_present = ATH_TX_RADIOTAP_PRESENT; 312 313 sc->sc_rx_th.wr_ihdr.it_len = sizeof(sc->sc_rx_th); 314 sc->sc_rx_th.wr_ihdr.it_present = ATH_RX_RADIOTAP_PRESENT; 315 316 if_printf(ifp, "802.11 address: %s\n", ether_sprintf(ic->ic_myaddr)); 317 318 return 0; 319 bad: 320 if (ah) 321 ath_hal_detach(ah); 322 sc->sc_invalid = 1; 323 return error; 324 } 325 326 int 327 ath_detach(struct ath_softc *sc) 328 { 329 struct ifnet *ifp = &sc->sc_ic.ic_if; 330 331 DPRINTF(("ath_detach: if_flags %x\n", ifp->if_flags)); 332 333 mtx_lock(&sc->sc_mtx); 334 ath_stop(ifp); 335 bpfdetach(ifp); 336 ath_desc_free(sc); 337 ath_hal_detach(sc->sc_ah); 338 ieee80211_ifdetach(ifp); 339 mtx_unlock(&sc->sc_mtx); 340 return 0; 341 } 342 343 void 344 ath_suspend(struct ath_softc *sc) 345 { 346 struct ifnet *ifp = &sc->sc_ic.ic_if; 347 348 DPRINTF(("ath_suspend: if_flags %x\n", ifp->if_flags)); 349 350 ath_stop(ifp); 351 } 352 353 void 354 ath_resume(struct ath_softc *sc) 355 { 356 struct ifnet *ifp = &sc->sc_ic.ic_if; 357 358 DPRINTF(("ath_resume: if_flags %x\n", ifp->if_flags)); 359 360 if (ifp->if_flags & IFF_UP) { 361 ath_init(ifp); 362 if (ifp->if_flags & IFF_RUNNING) 363 ath_start(ifp); 364 } 365 } 366 367 void 368 ath_shutdown(struct ath_softc *sc) 369 { 370 struct ifnet *ifp = &sc->sc_ic.ic_if; 371 372 DPRINTF(("ath_shutdown: if_flags %x\n", ifp->if_flags)); 373 374 ath_stop(ifp); 375 } 376 377 void 378 ath_intr(void *arg) 379 { 380 struct ath_softc *sc = arg; 381 struct ieee80211com *ic = &sc->sc_ic; 382 struct ifnet *ifp = &ic->ic_if; 383 struct ath_hal *ah = sc->sc_ah; 384 HAL_INT status; 385 386 if (sc->sc_invalid) { 387 /* 388 * The hardware is not ready/present, don't touch anything. 389 * Note this can happen early on if the IRQ is shared. 390 */ 391 DPRINTF(("ath_intr: invalid; ignored\n")); 392 return; 393 } 394 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) { 395 DPRINTF(("ath_intr: if_flags 0x%x\n", ifp->if_flags)); 396 ath_hal_getisr(ah, &status); /* clear ISR */ 397 ath_hal_intrset(ah, 0); /* disable further intr's */ 398 return; 399 } 400 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 401 DPRINTF2(("ath_intr: status 0x%x\n", status)); 402 #ifdef AR_DEBUG 403 if (ath_debug && 404 (status & (HAL_INT_FATAL|HAL_INT_RXORN|HAL_INT_BMISS))) { 405 if_printf(ifp, "ath_intr: status 0x%x\n", status); 406 ath_hal_dumpstate(ah); 407 } 408 #endif /* AR_DEBUG */ 409 status &= sc->sc_imask; /* discard unasked for bits */ 410 if (status & HAL_INT_FATAL) { 411 sc->sc_stats.ast_hardware++; 412 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 413 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask); 414 } else if (status & HAL_INT_RXORN) { 415 sc->sc_stats.ast_rxorn++; 416 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 417 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask); 418 } else { 419 if (status & HAL_INT_RXEOL) { 420 /* 421 * NB: the hardware should re-read the link when 422 * RXE bit is written, but it doesn't work at 423 * least on older hardware revs. 424 */ 425 sc->sc_stats.ast_rxeol++; 426 sc->sc_rxlink = NULL; 427 } 428 if (status & HAL_INT_TXURN) { 429 sc->sc_stats.ast_txurn++; 430 /* bump tx trigger level */ 431 ath_hal_updatetxtriglevel(ah, AH_TRUE); 432 } 433 if (status & HAL_INT_RX) 434 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask); 435 if (status & HAL_INT_TX) 436 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask); 437 if (status & HAL_INT_SWBA) 438 taskqueue_enqueue(taskqueue_swi, &sc->sc_swbatask); 439 if (status & HAL_INT_BMISS) { 440 sc->sc_stats.ast_bmiss++; 441 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask); 442 } 443 } 444 } 445 446 static void 447 ath_fatal_proc(void *arg, int pending) 448 { 449 struct ath_softc *sc = arg; 450 451 device_printf(sc->sc_dev, "hardware error; resetting\n"); 452 ath_reset(sc); 453 } 454 455 static void 456 ath_rxorn_proc(void *arg, int pending) 457 { 458 struct ath_softc *sc = arg; 459 460 device_printf(sc->sc_dev, "rx FIFO overrun; resetting\n"); 461 ath_reset(sc); 462 } 463 464 static void 465 ath_bmiss_proc(void *arg, int pending) 466 { 467 struct ath_softc *sc = arg; 468 struct ieee80211com *ic = &sc->sc_ic; 469 470 DPRINTF(("ath_bmiss_proc: pending %u\n", pending)); 471 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 472 ("unexpect operating mode %u", ic->ic_opmode)); 473 if (ic->ic_state == IEEE80211_S_RUN) 474 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 475 } 476 477 static u_int 478 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 479 { 480 static const u_int modeflags[] = { 481 0, /* IEEE80211_MODE_AUTO */ 482 CHANNEL_A, /* IEEE80211_MODE_11A */ 483 CHANNEL_B, /* IEEE80211_MODE_11B */ 484 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 485 CHANNEL_T /* IEEE80211_MODE_TURBO */ 486 }; 487 return modeflags[ieee80211_chan2mode(ic, chan)]; 488 } 489 490 static void 491 ath_init(void *arg) 492 { 493 struct ath_softc *sc = (struct ath_softc *) arg; 494 struct ieee80211com *ic = &sc->sc_ic; 495 struct ifnet *ifp = &ic->ic_if; 496 struct ieee80211_node *ni; 497 enum ieee80211_phymode mode; 498 struct ath_hal *ah = sc->sc_ah; 499 HAL_STATUS status; 500 HAL_CHANNEL hchan; 501 502 DPRINTF(("ath_init: if_flags 0x%x\n", ifp->if_flags)); 503 504 mtx_lock(&sc->sc_mtx); 505 /* 506 * Stop anything previously setup. This is safe 507 * whether this is the first time through or not. 508 */ 509 ath_stop(ifp); 510 511 /* 512 * The basic interface to setting the hardware in a good 513 * state is ``reset''. On return the hardware is known to 514 * be powered up and with interrupts disabled. This must 515 * be followed by initialization of the appropriate bits 516 * and then setup of the interrupt mask. 517 */ 518 hchan.channel = ic->ic_ibss_chan->ic_freq; 519 hchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan); 520 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_FALSE, &status)) { 521 if_printf(ifp, "unable to reset hardware; hal status %u\n", 522 status); 523 goto done; 524 } 525 526 /* 527 * Setup the hardware after reset: the key cache 528 * is filled as needed and the receive engine is 529 * set going. Frame transmit is handled entirely 530 * in the frame output path; there's nothing to do 531 * here except setup the interrupt mask. 532 */ 533 if (ic->ic_flags & IEEE80211_F_WEPON) 534 ath_initkeytable(sc); 535 if (ath_startrecv(sc) != 0) { 536 if_printf(ifp, "unable to start recv logic\n"); 537 goto done; 538 } 539 540 /* 541 * Enable interrupts. 542 */ 543 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 544 | HAL_INT_RXEOL | HAL_INT_RXORN 545 | HAL_INT_FATAL | HAL_INT_GLOBAL; 546 ath_hal_intrset(ah, sc->sc_imask); 547 548 ifp->if_flags |= IFF_RUNNING; 549 ic->ic_state = IEEE80211_S_INIT; 550 551 /* 552 * The hardware should be ready to go now so it's safe 553 * to kick the 802.11 state machine as it's likely to 554 * immediately call back to us to send mgmt frames. 555 */ 556 ni = ic->ic_bss; 557 ni->ni_chan = ic->ic_ibss_chan; 558 mode = ieee80211_chan2mode(ic, ni->ni_chan); 559 if (mode != sc->sc_curmode) 560 ath_setcurmode(sc, mode); 561 if (ic->ic_opmode != IEEE80211_M_MONITOR) 562 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 563 else 564 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 565 done: 566 mtx_unlock(&sc->sc_mtx); 567 } 568 569 static void 570 ath_stop(struct ifnet *ifp) 571 { 572 struct ieee80211com *ic = (struct ieee80211com *) ifp; 573 struct ath_softc *sc = ifp->if_softc; 574 struct ath_hal *ah = sc->sc_ah; 575 576 DPRINTF(("ath_stop: invalid %u if_flags 0x%x\n", 577 sc->sc_invalid, ifp->if_flags)); 578 579 mtx_lock(&sc->sc_mtx); 580 if (ifp->if_flags & IFF_RUNNING) { 581 /* 582 * Shutdown the hardware and driver: 583 * disable interrupts 584 * turn off timers 585 * clear transmit machinery 586 * clear receive machinery 587 * drain and release tx queues 588 * reclaim beacon resources 589 * reset 802.11 state machine 590 * power down hardware 591 * 592 * Note that some of this work is not possible if the 593 * hardware is gone (invalid). 594 */ 595 ifp->if_flags &= ~IFF_RUNNING; 596 ifp->if_timer = 0; 597 if (!sc->sc_invalid) 598 ath_hal_intrset(ah, 0); 599 ath_draintxq(sc); 600 if (!sc->sc_invalid) 601 ath_stoprecv(sc); 602 else 603 sc->sc_rxlink = NULL; 604 IF_DRAIN(&ifp->if_snd); 605 ath_beacon_free(sc); 606 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 607 if (!sc->sc_invalid) 608 ath_hal_setpower(ah, HAL_PM_FULL_SLEEP, 0); 609 } 610 mtx_unlock(&sc->sc_mtx); 611 } 612 613 /* 614 * Reset the hardware w/o losing operational state. This is 615 * basically a more efficient way of doing ath_stop, ath_init, 616 * followed by state transitions to the current 802.11 617 * operational state. Used to recover from errors rx overrun 618 * and to reset the hardware when rf gain settings must be reset. 619 */ 620 static void 621 ath_reset(struct ath_softc *sc) 622 { 623 struct ieee80211com *ic = &sc->sc_ic; 624 struct ifnet *ifp = &ic->ic_if; 625 struct ath_hal *ah = sc->sc_ah; 626 struct ieee80211_channel *c; 627 HAL_STATUS status; 628 HAL_CHANNEL hchan; 629 630 /* 631 * Convert to a HAL channel description with the flags 632 * constrained to reflect the current operating mode. 633 */ 634 c = ic->ic_ibss_chan; 635 hchan.channel = c->ic_freq; 636 hchan.channelFlags = ath_chan2flags(ic, c); 637 638 ath_hal_intrset(ah, 0); /* disable interrupts */ 639 ath_draintxq(sc); /* stop xmit side */ 640 ath_stoprecv(sc); /* stop recv side */ 641 /* NB: indicate channel change so we do a full reset */ 642 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) 643 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 644 __func__, status); 645 ath_hal_intrset(ah, sc->sc_imask); 646 if (ath_startrecv(sc) != 0) /* restart recv */ 647 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 648 ath_start(ifp); /* restart xmit */ 649 if (ic->ic_state == IEEE80211_S_RUN) 650 ath_beacon_config(sc); /* restart beacons */ 651 } 652 653 static void 654 ath_start(struct ifnet *ifp) 655 { 656 struct ath_softc *sc = ifp->if_softc; 657 struct ath_hal *ah = sc->sc_ah; 658 struct ieee80211com *ic = &sc->sc_ic; 659 struct ieee80211_node *ni; 660 struct ath_buf *bf; 661 struct mbuf *m; 662 struct ieee80211_frame *wh; 663 664 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 665 return; 666 for (;;) { 667 /* 668 * Grab a TX buffer and associated resources. 669 */ 670 mtx_lock(&sc->sc_txbuflock); 671 bf = TAILQ_FIRST(&sc->sc_txbuf); 672 if (bf != NULL) 673 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 674 mtx_unlock(&sc->sc_txbuflock); 675 if (bf == NULL) { 676 DPRINTF(("ath_start: out of xmit buffers\n")); 677 sc->sc_stats.ast_tx_qstop++; 678 ifp->if_flags |= IFF_OACTIVE; 679 break; 680 } 681 /* 682 * Poll the management queue for frames; they 683 * have priority over normal data frames. 684 */ 685 IF_DEQUEUE(&ic->ic_mgtq, m); 686 if (m == NULL) { 687 /* 688 * No data frames go out unless we're associated. 689 */ 690 if (ic->ic_state != IEEE80211_S_RUN) { 691 DPRINTF(("ath_start: ignore data packet, " 692 "state %u\n", ic->ic_state)); 693 sc->sc_stats.ast_tx_discard++; 694 mtx_lock(&sc->sc_txbuflock); 695 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 696 mtx_unlock(&sc->sc_txbuflock); 697 break; 698 } 699 IF_DEQUEUE(&ifp->if_snd, m); 700 if (m == NULL) { 701 mtx_lock(&sc->sc_txbuflock); 702 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 703 mtx_unlock(&sc->sc_txbuflock); 704 break; 705 } 706 ifp->if_opackets++; 707 BPF_MTAP(ifp, m); 708 /* 709 * Encapsulate the packet in prep for transmission. 710 */ 711 m = ieee80211_encap(ifp, m, &ni); 712 if (m == NULL) { 713 DPRINTF(("ath_start: encapsulation failure\n")); 714 sc->sc_stats.ast_tx_encap++; 715 goto bad; 716 } 717 wh = mtod(m, struct ieee80211_frame *); 718 if (ic->ic_flags & IEEE80211_F_WEPON) 719 wh->i_fc[1] |= IEEE80211_FC1_WEP; 720 } else { 721 /* 722 * Hack! The referenced node pointer is in the 723 * rcvif field of the packet header. This is 724 * placed there by ieee80211_mgmt_output because 725 * we need to hold the reference with the frame 726 * and there's no other way (other than packet 727 * tags which we consider too expensive to use) 728 * to pass it along. 729 */ 730 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 731 m->m_pkthdr.rcvif = NULL; 732 733 wh = mtod(m, struct ieee80211_frame *); 734 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 735 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 736 /* fill time stamp */ 737 u_int64_t tsf; 738 u_int32_t *tstamp; 739 740 tsf = ath_hal_gettsf64(ah); 741 /* XXX: adjust 100us delay to xmit */ 742 tsf += 100; 743 tstamp = (u_int32_t *)&wh[1]; 744 tstamp[0] = htole32(tsf & 0xffffffff); 745 tstamp[1] = htole32(tsf >> 32); 746 } 747 sc->sc_stats.ast_tx_mgmt++; 748 } 749 if (ic->ic_rawbpf) 750 bpf_mtap(ic->ic_rawbpf, m); 751 752 if (sc->sc_drvbpf) { 753 struct mbuf *mb; 754 755 MGETHDR(mb, M_DONTWAIT, m->m_type); 756 if (mb != NULL) { 757 sc->sc_tx_th.wt_rate = 758 ni->ni_rates.rs_rates[ni->ni_txrate]; 759 760 mb->m_next = m; 761 mb->m_data = (caddr_t)&sc->sc_tx_th; 762 mb->m_len = sizeof(sc->sc_tx_th); 763 mb->m_pkthdr.len += mb->m_len; 764 bpf_mtap(sc->sc_drvbpf, mb); 765 m_free(mb); 766 } 767 } 768 769 if (ath_tx_start(sc, ni, bf, m)) { 770 bad: 771 mtx_lock(&sc->sc_txbuflock); 772 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 773 mtx_unlock(&sc->sc_txbuflock); 774 ifp->if_oerrors++; 775 if (ni && ni != ic->ic_bss) 776 ieee80211_free_node(ic, ni); 777 continue; 778 } 779 780 sc->sc_tx_timer = 5; 781 ifp->if_timer = 1; 782 } 783 } 784 785 static int 786 ath_media_change(struct ifnet *ifp) 787 { 788 int error; 789 790 error = ieee80211_media_change(ifp); 791 if (error == ENETRESET) { 792 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 793 (IFF_RUNNING|IFF_UP)) 794 ath_init(ifp); /* XXX lose error */ 795 error = 0; 796 } 797 return error; 798 } 799 800 static void 801 ath_watchdog(struct ifnet *ifp) 802 { 803 struct ath_softc *sc = ifp->if_softc; 804 struct ieee80211com *ic = &sc->sc_ic; 805 806 ifp->if_timer = 0; 807 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) 808 return; 809 if (sc->sc_tx_timer) { 810 if (--sc->sc_tx_timer == 0) { 811 if_printf(ifp, "device timeout\n"); 812 #ifdef AR_DEBUG 813 if (ath_debug) 814 ath_hal_dumpstate(sc->sc_ah); 815 #endif /* AR_DEBUG */ 816 ath_init(ifp); /* XXX ath_reset??? */ 817 ifp->if_oerrors++; 818 sc->sc_stats.ast_watchdog++; 819 return; 820 } 821 ifp->if_timer = 1; 822 } 823 if (ic->ic_fixed_rate == -1) { 824 /* 825 * Run the rate control algorithm if we're not 826 * locked at a fixed rate. 827 */ 828 if (ic->ic_opmode == IEEE80211_M_STA) 829 ath_rate_ctl(sc, ic->ic_bss); 830 else 831 ieee80211_iterate_nodes(ic, ath_rate_ctl, sc); 832 } 833 ieee80211_watchdog(ifp); 834 } 835 836 static int 837 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 838 { 839 struct ath_softc *sc = ifp->if_softc; 840 struct ifreq *ifr = (struct ifreq *)data; 841 int error = 0; 842 843 mtx_lock(&sc->sc_mtx); 844 switch (cmd) { 845 case SIOCSIFFLAGS: 846 if (ifp->if_flags & IFF_UP) { 847 if (ifp->if_flags & IFF_RUNNING) { 848 /* 849 * To avoid rescanning another access point, 850 * do not call ath_init() here. Instead, 851 * only reflect promisc mode settings. 852 */ 853 ath_mode_init(sc); 854 } else 855 ath_init(ifp); /* XXX lose error */ 856 } else 857 ath_stop(ifp); 858 break; 859 case SIOCADDMULTI: 860 case SIOCDELMULTI: 861 /* 862 * The upper layer has already installed/removed 863 * the multicast address(es), just recalculate the 864 * multicast filter for the card. 865 */ 866 if (ifp->if_flags & IFF_RUNNING) 867 ath_mode_init(sc); 868 break; 869 case SIOCGATHSTATS: 870 copyout(&sc->sc_stats, ifr->ifr_data, sizeof (sc->sc_stats)); 871 break; 872 default: 873 error = ieee80211_ioctl(ifp, cmd, data); 874 if (error == ENETRESET) { 875 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 876 (IFF_RUNNING|IFF_UP)) 877 ath_init(ifp); /* XXX lose error */ 878 error = 0; 879 } 880 break; 881 } 882 mtx_unlock(&sc->sc_mtx); 883 return error; 884 } 885 886 /* 887 * Fill the hardware key cache with key entries. 888 */ 889 static void 890 ath_initkeytable(struct ath_softc *sc) 891 { 892 struct ieee80211com *ic = &sc->sc_ic; 893 struct ath_hal *ah = sc->sc_ah; 894 int i; 895 896 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 897 struct ieee80211_wepkey *k = &ic->ic_nw_keys[i]; 898 if (k->wk_len == 0) 899 ath_hal_keyreset(ah, i); 900 else 901 /* XXX return value */ 902 /* NB: this uses HAL_KEYVAL == ieee80211_wepkey */ 903 ath_hal_keyset(ah, i, (const HAL_KEYVAL *) k); 904 } 905 } 906 907 static void 908 ath_mode_init(struct ath_softc *sc) 909 { 910 struct ieee80211com *ic = &sc->sc_ic; 911 struct ath_hal *ah = sc->sc_ah; 912 struct ifnet *ifp = &ic->ic_if; 913 u_int32_t rfilt, mfilt[2], val; 914 u_int8_t pos; 915 struct ifmultiaddr *ifma; 916 917 /* configure operational mode */ 918 ath_hal_setopmode(ah, ic->ic_opmode); 919 920 /* receive filter */ 921 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 922 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 923 if (ic->ic_opmode != IEEE80211_M_STA) 924 rfilt |= HAL_RX_FILTER_PROBEREQ; 925 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 926 (ifp->if_flags & IFF_PROMISC)) 927 rfilt |= HAL_RX_FILTER_PROM; 928 if (ic->ic_opmode == IEEE80211_M_STA || 929 ic->ic_state == IEEE80211_S_SCAN) 930 rfilt |= HAL_RX_FILTER_BEACON; 931 ath_hal_setrxfilter(ah, rfilt); 932 933 /* calculate and install multicast filter */ 934 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 935 mfilt[0] = mfilt[1] = 0; 936 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 937 caddr_t dl; 938 939 /* calculate XOR of eight 6bit values */ 940 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 941 val = LE_READ_4(dl + 0); 942 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 943 val = LE_READ_4(dl + 3); 944 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 945 pos &= 0x3f; 946 mfilt[pos / 32] |= (1 << (pos % 32)); 947 } 948 } else { 949 mfilt[0] = mfilt[1] = ~0; 950 } 951 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 952 DPRINTF(("ath_mode_init: RX filter 0x%x, MC filter %08x:%08x\n", 953 rfilt, mfilt[0], mfilt[1])); 954 } 955 956 static void 957 ath_mbuf_load_cb(void *arg, bus_dma_segment_t *seg, int nseg, bus_size_t mapsize, int error) 958 { 959 struct ath_buf *bf = arg; 960 961 KASSERT(nseg <= ATH_MAX_SCATTER, 962 ("ath_mbuf_load_cb: too many DMA segments %u", nseg)); 963 bf->bf_mapsize = mapsize; 964 bf->bf_nseg = nseg; 965 bcopy(seg, bf->bf_segs, nseg * sizeof (seg[0])); 966 } 967 968 static int 969 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 970 { 971 struct ieee80211com *ic = &sc->sc_ic; 972 struct ifnet *ifp = &ic->ic_if; 973 struct ath_hal *ah = sc->sc_ah; 974 struct ieee80211_frame *wh; 975 struct ath_buf *bf; 976 struct ath_desc *ds; 977 struct mbuf *m; 978 int error, pktlen; 979 u_int8_t *frm, rate; 980 u_int16_t capinfo; 981 struct ieee80211_rateset *rs; 982 const HAL_RATE_TABLE *rt; 983 984 bf = sc->sc_bcbuf; 985 if (bf->bf_m != NULL) { 986 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 987 m_freem(bf->bf_m); 988 bf->bf_m = NULL; 989 bf->bf_node = NULL; 990 } 991 /* 992 * NB: the beacon data buffer must be 32-bit aligned; 993 * we assume the mbuf routines will return us something 994 * with this alignment (perhaps should assert). 995 */ 996 rs = &ni->ni_rates; 997 pktlen = sizeof (struct ieee80211_frame) 998 + 8 + 2 + 2 + 2+ni->ni_esslen + 2+rs->rs_nrates + 3 + 6; 999 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 1000 pktlen += 2; 1001 if (pktlen <= MHLEN) 1002 MGETHDR(m, M_DONTWAIT, MT_DATA); 1003 else 1004 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1005 if (m == NULL) { 1006 DPRINTF(("ath_beacon_alloc: cannot get mbuf/cluster; size %u\n", 1007 pktlen)); 1008 sc->sc_stats.ast_be_nombuf++; 1009 return ENOMEM; 1010 } 1011 1012 wh = mtod(m, struct ieee80211_frame *); 1013 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1014 IEEE80211_FC0_SUBTYPE_BEACON; 1015 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1016 *(u_int16_t *)wh->i_dur = 0; 1017 memcpy(wh->i_addr1, ifp->if_broadcastaddr, IEEE80211_ADDR_LEN); 1018 memcpy(wh->i_addr2, ic->ic_myaddr, IEEE80211_ADDR_LEN); 1019 memcpy(wh->i_addr3, ni->ni_bssid, IEEE80211_ADDR_LEN); 1020 *(u_int16_t *)wh->i_seq = 0; 1021 1022 /* 1023 * beacon frame format 1024 * [8] time stamp 1025 * [2] beacon interval 1026 * [2] cabability information 1027 * [tlv] ssid 1028 * [tlv] supported rates 1029 * [tlv] parameter set (IBSS) 1030 * [tlv] extended supported rates 1031 */ 1032 frm = (u_int8_t *)&wh[1]; 1033 memset(frm, 0, 8); /* timestamp is set by hardware */ 1034 frm += 8; 1035 *(u_int16_t *)frm = htole16(ni->ni_intval); 1036 frm += 2; 1037 if (ic->ic_opmode == IEEE80211_M_IBSS) 1038 capinfo = IEEE80211_CAPINFO_IBSS; 1039 else 1040 capinfo = IEEE80211_CAPINFO_ESS; 1041 if (ic->ic_flags & IEEE80211_F_WEPON) 1042 capinfo |= IEEE80211_CAPINFO_PRIVACY; 1043 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1044 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 1045 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 1046 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1047 capinfo |= IEEE80211_CAPINFO_SHORT_SLOTTIME; 1048 *(u_int16_t *)frm = htole16(capinfo); 1049 frm += 2; 1050 *frm++ = IEEE80211_ELEMID_SSID; 1051 *frm++ = ni->ni_esslen; 1052 memcpy(frm, ni->ni_essid, ni->ni_esslen); 1053 frm += ni->ni_esslen; 1054 frm = ieee80211_add_rates(frm, rs); 1055 *frm++ = IEEE80211_ELEMID_DSPARMS; 1056 *frm++ = 1; 1057 *frm++ = ieee80211_chan2ieee(ic, ni->ni_chan); 1058 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1059 *frm++ = IEEE80211_ELEMID_IBSSPARMS; 1060 *frm++ = 2; 1061 *frm++ = 0; *frm++ = 0; /* TODO: ATIM window */ 1062 } else { 1063 /* TODO: TIM */ 1064 *frm++ = IEEE80211_ELEMID_TIM; 1065 *frm++ = 4; /* length */ 1066 *frm++ = 0; /* DTIM count */ 1067 *frm++ = 1; /* DTIM period */ 1068 *frm++ = 0; /* bitmap control */ 1069 *frm++ = 0; /* Partial Virtual Bitmap (variable length) */ 1070 } 1071 frm = ieee80211_add_xrates(frm, rs); 1072 m->m_pkthdr.len = m->m_len = frm - mtod(m, u_int8_t *); 1073 KASSERT(m->m_pkthdr.len <= pktlen, 1074 ("beacon bigger than expected, len %u calculated %u", 1075 m->m_pkthdr.len, pktlen)); 1076 1077 DPRINTF2(("ath_beacon_alloc: m %p len %u\n", m, m->m_len)); 1078 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1079 ath_mbuf_load_cb, bf, 1080 BUS_DMA_NOWAIT); 1081 if (error != 0) { 1082 m_freem(m); 1083 return error; 1084 } 1085 KASSERT(bf->bf_nseg == 1, 1086 ("ath_beacon_alloc: multi-segment packet; nseg %u", 1087 bf->bf_nseg)); 1088 bf->bf_m = m; 1089 1090 /* setup descriptors */ 1091 ds = bf->bf_desc; 1092 1093 ds->ds_link = 0; 1094 ds->ds_data = bf->bf_segs[0].ds_addr; 1095 /* 1096 * Calculate rate code. 1097 * XXX everything at min xmit rate 1098 */ 1099 rt = sc->sc_currates; 1100 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1101 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1102 rate = rt->info[0].rateCode | rt->info[0].shortPreamble; 1103 else 1104 rate = rt->info[0].rateCode; 1105 ath_hal_setuptxdesc(ah, ds 1106 , m->m_pkthdr.len + IEEE80211_CRC_LEN /* packet length */ 1107 , sizeof(struct ieee80211_frame) /* header length */ 1108 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1109 , 0x20 /* txpower XXX */ 1110 , rate, 1 /* series 0 rate/tries */ 1111 , HAL_TXKEYIX_INVALID /* no encryption */ 1112 , 0 /* antenna mode */ 1113 , HAL_TXDESC_NOACK /* no ack for beacons */ 1114 , 0 /* rts/cts rate */ 1115 , 0 /* rts/cts duration */ 1116 ); 1117 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1118 /* XXX verify mbuf data area covers this roundup */ 1119 ath_hal_filltxdesc(ah, ds 1120 , roundup(bf->bf_segs[0].ds_len, 4) /* buffer length */ 1121 , AH_TRUE /* first segment */ 1122 , AH_TRUE /* last segment */ 1123 ); 1124 1125 return 0; 1126 } 1127 1128 static void 1129 ath_beacon_proc(void *arg, int pending) 1130 { 1131 struct ath_softc *sc = arg; 1132 struct ieee80211com *ic = &sc->sc_ic; 1133 struct ath_buf *bf = sc->sc_bcbuf; 1134 struct ath_hal *ah = sc->sc_ah; 1135 1136 DPRINTF2(("%s: pending %u\n", __func__, pending)); 1137 if (ic->ic_opmode == IEEE80211_M_STA || 1138 bf == NULL || bf->bf_m == NULL) { 1139 DPRINTF(("%s: ic_flags=%x bf=%p bf_m=%p\n", 1140 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL)); 1141 return; 1142 } 1143 /* TODO: update beacon to reflect PS poll state */ 1144 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1145 DPRINTF(("%s: beacon queue %u did not stop?", 1146 __func__, sc->sc_bhalq)); 1147 return; /* busy, XXX is this right? */ 1148 } 1149 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1150 1151 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 1152 ath_hal_txstart(ah, sc->sc_bhalq); 1153 DPRINTF2(("%s: TXDP%u = %p (%p)\n", __func__, 1154 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1155 } 1156 1157 static void 1158 ath_beacon_free(struct ath_softc *sc) 1159 { 1160 struct ath_buf *bf = sc->sc_bcbuf; 1161 1162 if (bf->bf_m != NULL) { 1163 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1164 m_freem(bf->bf_m); 1165 bf->bf_m = NULL; 1166 bf->bf_node = NULL; 1167 } 1168 } 1169 1170 /* 1171 * Configure the beacon and sleep timers. 1172 * 1173 * When operating as an AP this resets the TSF and sets 1174 * up the hardware to notify us when we need to issue beacons. 1175 * 1176 * When operating in station mode this sets up the beacon 1177 * timers according to the timestamp of the last received 1178 * beacon and the current TSF, configures PCF and DTIM 1179 * handling, programs the sleep registers so the hardware 1180 * will wakeup in time to receive beacons, and configures 1181 * the beacon miss handling so we'll receive a BMISS 1182 * interrupt when we stop seeing beacons from the AP 1183 * we've associated with. 1184 */ 1185 static void 1186 ath_beacon_config(struct ath_softc *sc) 1187 { 1188 struct ath_hal *ah = sc->sc_ah; 1189 struct ieee80211com *ic = &sc->sc_ic; 1190 struct ieee80211_node *ni = ic->ic_bss; 1191 u_int32_t nexttbtt; 1192 1193 nexttbtt = (LE_READ_4(ni->ni_tstamp + 4) << 22) | 1194 (LE_READ_4(ni->ni_tstamp) >> 10); 1195 DPRINTF(("%s: nexttbtt=%u\n", __func__, nexttbtt)); 1196 nexttbtt += ni->ni_intval; 1197 if (ic->ic_opmode == IEEE80211_M_STA) { 1198 HAL_BEACON_STATE bs; 1199 u_int32_t bmisstime; 1200 1201 /* NB: no PCF support right now */ 1202 memset(&bs, 0, sizeof(bs)); 1203 bs.bs_intval = ni->ni_intval; 1204 bs.bs_nexttbtt = nexttbtt; 1205 bs.bs_dtimperiod = bs.bs_intval; 1206 bs.bs_nextdtim = nexttbtt; 1207 /* 1208 * Calculate the number of consecutive beacons to miss 1209 * before taking a BMISS interrupt. The configuration 1210 * is specified in ms, so we need to convert that to 1211 * TU's and then calculate based on the beacon interval. 1212 * Note that we clamp the result to at most 10 beacons. 1213 */ 1214 bmisstime = (ic->ic_bmisstimeout * 1000) / 1024; 1215 bs.bs_bmissthreshold = howmany(bmisstime,ni->ni_intval); 1216 if (bs.bs_bmissthreshold > 10) 1217 bs.bs_bmissthreshold = 10; 1218 else if (bs.bs_bmissthreshold <= 0) 1219 bs.bs_bmissthreshold = 1; 1220 1221 /* 1222 * Calculate sleep duration. The configuration is 1223 * given in ms. We insure a multiple of the beacon 1224 * period is used. Also, if the sleep duration is 1225 * greater than the DTIM period then it makes senses 1226 * to make it a multiple of that. 1227 * 1228 * XXX fixed at 100ms 1229 */ 1230 bs.bs_sleepduration = 1231 roundup((100 * 1000) / 1024, bs.bs_intval); 1232 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1233 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1234 1235 DPRINTF(("%s: intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u\n" 1236 , __func__ 1237 , bs.bs_intval 1238 , bs.bs_nexttbtt 1239 , bs.bs_dtimperiod 1240 , bs.bs_nextdtim 1241 , bs.bs_bmissthreshold 1242 , bs.bs_sleepduration 1243 )); 1244 ath_hal_intrset(ah, 0); 1245 /* 1246 * Reset our tsf so the hardware will update the 1247 * tsf register to reflect timestamps found in 1248 * received beacons. 1249 */ 1250 ath_hal_resettsf(ah); 1251 ath_hal_beacontimers(ah, &bs, 0/*XXX*/, 0, 0); 1252 sc->sc_imask |= HAL_INT_BMISS; 1253 ath_hal_intrset(ah, sc->sc_imask); 1254 } else { 1255 DPRINTF(("%s: intval %u nexttbtt %u\n", 1256 __func__, ni->ni_intval, nexttbtt)); 1257 ath_hal_intrset(ah, 0); 1258 ath_hal_beaconinit(ah, ic->ic_opmode, 1259 nexttbtt, ni->ni_intval); 1260 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1261 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1262 ath_hal_intrset(ah, sc->sc_imask); 1263 } 1264 } 1265 1266 static void 1267 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1268 { 1269 bus_addr_t *paddr = (bus_addr_t*) arg; 1270 *paddr = segs->ds_addr; 1271 } 1272 1273 static int 1274 ath_desc_alloc(struct ath_softc *sc) 1275 { 1276 int i, bsize, error; 1277 struct ath_desc *ds; 1278 struct ath_buf *bf; 1279 1280 /* allocate descriptors */ 1281 sc->sc_desc_len = sizeof(struct ath_desc) * 1282 (ATH_TXBUF * ATH_TXDESC + ATH_RXBUF + 1); 1283 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1284 if (error != 0) 1285 return error; 1286 1287 error = bus_dmamem_alloc(sc->sc_dmat, (void**) &sc->sc_desc, 1288 BUS_DMA_NOWAIT, &sc->sc_ddmamap); 1289 if (error != 0) 1290 goto fail0; 1291 1292 error = bus_dmamap_load(sc->sc_dmat, sc->sc_ddmamap, 1293 sc->sc_desc, sc->sc_desc_len, 1294 ath_load_cb, &sc->sc_desc_paddr, 1295 BUS_DMA_NOWAIT); 1296 if (error != 0) 1297 goto fail1; 1298 1299 ds = sc->sc_desc; 1300 DPRINTF(("ath_desc_alloc: DMA map: %p (%d) -> %p (%lu)\n", 1301 ds, sc->sc_desc_len, 1302 (caddr_t) sc->sc_desc_paddr, /*XXX*/ (u_long) sc->sc_desc_len)); 1303 1304 /* allocate buffers */ 1305 bsize = sizeof(struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 1); 1306 bf = malloc(bsize, M_DEVBUF, M_NOWAIT | M_ZERO); 1307 if (bf == NULL) 1308 goto fail2; 1309 sc->sc_bufptr = bf; 1310 1311 TAILQ_INIT(&sc->sc_rxbuf); 1312 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 1313 bf->bf_desc = ds; 1314 bf->bf_daddr = sc->sc_desc_paddr + 1315 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1316 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1317 &bf->bf_dmamap); 1318 if (error != 0) 1319 break; 1320 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1321 } 1322 1323 TAILQ_INIT(&sc->sc_txbuf); 1324 for (i = 0; i < ATH_TXBUF; i++, bf++, ds += ATH_TXDESC) { 1325 bf->bf_desc = ds; 1326 bf->bf_daddr = sc->sc_desc_paddr + 1327 ((caddr_t)ds - (caddr_t)sc->sc_desc); 1328 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1329 &bf->bf_dmamap); 1330 if (error != 0) 1331 break; 1332 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1333 } 1334 TAILQ_INIT(&sc->sc_txq); 1335 1336 /* beacon buffer */ 1337 bf->bf_desc = ds; 1338 bf->bf_daddr = sc->sc_desc_paddr + ((caddr_t)ds - (caddr_t)sc->sc_desc); 1339 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &bf->bf_dmamap); 1340 if (error != 0) 1341 return error; 1342 sc->sc_bcbuf = bf; 1343 return 0; 1344 1345 fail2: 1346 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1347 fail1: 1348 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1349 fail0: 1350 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1351 sc->sc_ddmamap = NULL; 1352 return error; 1353 } 1354 1355 static void 1356 ath_desc_free(struct ath_softc *sc) 1357 { 1358 struct ath_buf *bf; 1359 1360 bus_dmamap_unload(sc->sc_dmat, sc->sc_ddmamap); 1361 bus_dmamem_free(sc->sc_dmat, sc->sc_desc, sc->sc_ddmamap); 1362 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ddmamap); 1363 1364 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1365 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1366 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1367 m_freem(bf->bf_m); 1368 } 1369 TAILQ_FOREACH(bf, &sc->sc_txbuf, bf_list) 1370 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1371 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1372 if (bf->bf_m) { 1373 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1374 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 1375 m_freem(bf->bf_m); 1376 bf->bf_m = NULL; 1377 } 1378 } 1379 if (sc->sc_bcbuf != NULL) { 1380 bus_dmamap_unload(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1381 bus_dmamap_destroy(sc->sc_dmat, sc->sc_bcbuf->bf_dmamap); 1382 sc->sc_bcbuf = NULL; 1383 } 1384 1385 TAILQ_INIT(&sc->sc_rxbuf); 1386 TAILQ_INIT(&sc->sc_txbuf); 1387 TAILQ_INIT(&sc->sc_txq); 1388 free(sc->sc_bufptr, M_DEVBUF); 1389 sc->sc_bufptr = NULL; 1390 } 1391 1392 static struct ieee80211_node * 1393 ath_node_alloc(struct ieee80211com *ic) 1394 { 1395 struct ath_node *an = 1396 malloc(sizeof(struct ath_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1397 if (an) { 1398 int i; 1399 for (i = 0; i < ATH_RHIST_SIZE; i++) 1400 an->an_rx_hist[i].arh_ticks = ATH_RHIST_NOTIME; 1401 an->an_rx_hist_next = ATH_RHIST_SIZE-1; 1402 return &an->an_node; 1403 } else 1404 return NULL; 1405 } 1406 1407 static void 1408 ath_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 1409 { 1410 struct ath_softc *sc = ic->ic_if.if_softc; 1411 struct ath_buf *bf; 1412 1413 TAILQ_FOREACH(bf, &sc->sc_txq, bf_list) { 1414 if (bf->bf_node == ni) 1415 bf->bf_node = NULL; 1416 } 1417 free(ni, M_DEVBUF); 1418 } 1419 1420 static void 1421 ath_node_copy(struct ieee80211com *ic, 1422 struct ieee80211_node *dst, const struct ieee80211_node *src) 1423 { 1424 *(struct ath_node *)dst = *(const struct ath_node *)src; 1425 } 1426 1427 1428 static u_int8_t 1429 ath_node_getrssi(struct ieee80211com *ic, struct ieee80211_node *ni) 1430 { 1431 struct ath_node *an = ATH_NODE(ni); 1432 int i, now, nsamples, rssi; 1433 1434 /* 1435 * Calculate the average over the last second of sampled data. 1436 */ 1437 now = ticks; 1438 nsamples = 0; 1439 rssi = 0; 1440 i = an->an_rx_hist_next; 1441 do { 1442 struct ath_recv_hist *rh = &an->an_rx_hist[i]; 1443 if (rh->arh_ticks == ATH_RHIST_NOTIME) 1444 goto done; 1445 if (now - rh->arh_ticks > hz) 1446 goto done; 1447 rssi += rh->arh_rssi; 1448 nsamples++; 1449 if (i == 0) 1450 i = ATH_RHIST_SIZE-1; 1451 else 1452 i--; 1453 } while (i != an->an_rx_hist_next); 1454 done: 1455 /* 1456 * Return either the average or the last known 1457 * value if there is no recent data. 1458 */ 1459 return (nsamples ? rssi / nsamples : an->an_rx_hist[i].arh_rssi); 1460 } 1461 1462 static int 1463 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 1464 { 1465 struct ath_hal *ah = sc->sc_ah; 1466 int error; 1467 struct mbuf *m; 1468 struct ath_desc *ds; 1469 1470 m = bf->bf_m; 1471 if (m == NULL) { 1472 /* 1473 * NB: by assigning a page to the rx dma buffer we 1474 * implicitly satisfy the Atheros requirement that 1475 * this buffer be cache-line-aligned and sized to be 1476 * multiple of the cache line size. Not doing this 1477 * causes weird stuff to happen (for the 5210 at least). 1478 */ 1479 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1480 if (m == NULL) { 1481 DPRINTF(("ath_rxbuf_init: no mbuf/cluster\n")); 1482 sc->sc_stats.ast_rx_nombuf++; 1483 return ENOMEM; 1484 } 1485 bf->bf_m = m; 1486 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 1487 1488 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m, 1489 ath_mbuf_load_cb, bf, 1490 BUS_DMA_NOWAIT); 1491 if (error != 0) { 1492 DPRINTF(("ath_rxbuf_init: bus_dmamap_load_mbuf failed;" 1493 " error %d\n", error)); 1494 sc->sc_stats.ast_rx_busdma++; 1495 return error; 1496 } 1497 KASSERT(bf->bf_nseg == 1, 1498 ("ath_rxbuf_init: multi-segment packet; nseg %u", 1499 bf->bf_nseg)); 1500 } 1501 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 1502 1503 /* setup descriptors */ 1504 ds = bf->bf_desc; 1505 ds->ds_link = 0; 1506 ds->ds_data = bf->bf_segs[0].ds_addr; 1507 ath_hal_setuprxdesc(ah, ds 1508 , m->m_len /* buffer size */ 1509 , 0 1510 ); 1511 1512 if (sc->sc_rxlink != NULL) 1513 *sc->sc_rxlink = bf->bf_daddr; 1514 sc->sc_rxlink = &ds->ds_link; 1515 return 0; 1516 } 1517 1518 static void 1519 ath_rx_proc(void *arg, int npending) 1520 { 1521 struct ath_softc *sc = arg; 1522 struct ath_buf *bf; 1523 struct ieee80211com *ic = &sc->sc_ic; 1524 struct ifnet *ifp = &ic->ic_if; 1525 struct ath_hal *ah = sc->sc_ah; 1526 struct ath_desc *ds; 1527 struct mbuf *m; 1528 struct ieee80211_frame *wh, whbuf; 1529 struct ieee80211_node *ni; 1530 struct ath_node *an; 1531 struct ath_recv_hist *rh; 1532 int len; 1533 u_int phyerr; 1534 HAL_STATUS status; 1535 1536 DPRINTF2(("ath_rx_proc: pending %u\n", npending)); 1537 do { 1538 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1539 if (bf == NULL) { /* NB: shouldn't happen */ 1540 if_printf(ifp, "ath_rx_proc: no buffer!\n"); 1541 break; 1542 } 1543 m = bf->bf_m; 1544 if (m == NULL) { /* NB: shouldn't happen */ 1545 if_printf(ifp, "ath_rx_proc: no mbuf!\n"); 1546 continue; 1547 } 1548 ds = bf->bf_desc; 1549 status = ath_hal_rxprocdesc(ah, ds); 1550 #ifdef AR_DEBUG 1551 if (ath_debug > 1) 1552 ath_printrxbuf(bf, status == HAL_OK); 1553 #endif 1554 if (status == HAL_EINPROGRESS) 1555 break; 1556 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1557 if (ds->ds_rxstat.rs_status != 0) { 1558 ifp->if_ierrors++; 1559 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 1560 sc->sc_stats.ast_rx_crcerr++; 1561 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 1562 sc->sc_stats.ast_rx_fifoerr++; 1563 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) 1564 sc->sc_stats.ast_rx_badcrypt++; 1565 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 1566 sc->sc_stats.ast_rx_phyerr++; 1567 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 1568 sc->sc_stats.ast_rx_phy[phyerr]++; 1569 } 1570 goto rx_next; 1571 } 1572 1573 len = ds->ds_rxstat.rs_datalen; 1574 if (len < IEEE80211_MIN_LEN) { 1575 DPRINTF(("ath_rx_proc: short packet %d\n", len)); 1576 sc->sc_stats.ast_rx_tooshort++; 1577 goto rx_next; 1578 } 1579 1580 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 1581 BUS_DMASYNC_POSTREAD); 1582 1583 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1584 bf->bf_m = NULL; 1585 m->m_pkthdr.rcvif = ifp; 1586 m->m_pkthdr.len = m->m_len = len; 1587 1588 if (sc->sc_drvbpf) { 1589 struct mbuf *mb; 1590 1591 /* XXX pre-allocate space when setting up recv's */ 1592 MGETHDR(mb, M_DONTWAIT, m->m_type); 1593 if (mb != NULL) { 1594 sc->sc_rx_th.wr_rate = 1595 sc->sc_hwmap[ds->ds_rxstat.rs_rate]; 1596 sc->sc_rx_th.wr_antsignal = 1597 ds->ds_rxstat.rs_rssi; 1598 sc->sc_rx_th.wr_antenna = 1599 ds->ds_rxstat.rs_antenna; 1600 /* XXX TSF */ 1601 1602 (void) m_dup_pkthdr(mb, m, M_DONTWAIT); 1603 mb->m_next = m; 1604 mb->m_data = (caddr_t)&sc->sc_rx_th; 1605 mb->m_len = sizeof(sc->sc_rx_th); 1606 mb->m_pkthdr.len += mb->m_len; 1607 bpf_mtap(sc->sc_drvbpf, mb); 1608 m_free(mb); 1609 } 1610 } 1611 1612 m_adj(m, -IEEE80211_CRC_LEN); 1613 wh = mtod(m, struct ieee80211_frame *); 1614 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1615 /* 1616 * WEP is decrypted by hardware. Clear WEP bit 1617 * and trim WEP header for ieee80211_input(). 1618 */ 1619 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 1620 memcpy(&whbuf, wh, sizeof(whbuf)); 1621 m_adj(m, IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN); 1622 memcpy(mtod(m, caddr_t), &whbuf, sizeof(whbuf)); 1623 /* 1624 * Also trim WEP ICV from the tail. 1625 */ 1626 m_adj(m, -IEEE80211_WEP_CRCLEN); 1627 } 1628 1629 /* 1630 * Locate the node for sender, track state, and 1631 * then pass this node (referenced) up to the 802.11 1632 * layer for its use. We are required to pass 1633 * something so we fall back to ic_bss when this frame 1634 * is from an unknown sender. 1635 */ 1636 if (ic->ic_opmode != IEEE80211_M_STA) { 1637 ni = ieee80211_find_node(ic, wh->i_addr2); 1638 if (ni == NULL) 1639 ni = ieee80211_ref_node(ic->ic_bss); 1640 } else 1641 ni = ieee80211_ref_node(ic->ic_bss); 1642 1643 /* 1644 * Record driver-specific state. 1645 */ 1646 an = ATH_NODE(ni); 1647 if (++(an->an_rx_hist_next) == ATH_RHIST_SIZE) 1648 an->an_rx_hist_next = 0; 1649 rh = &an->an_rx_hist[an->an_rx_hist_next]; 1650 rh->arh_ticks = ticks; 1651 rh->arh_rssi = ds->ds_rxstat.rs_rssi; 1652 rh->arh_antenna = ds->ds_rxstat.rs_antenna; 1653 1654 /* 1655 * Send frame up for processing. 1656 */ 1657 ieee80211_input(ifp, m, ni, 1658 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 1659 1660 /* 1661 * The frame may have caused the node to be marked for 1662 * reclamation (e.g. in response to a DEAUTH message) 1663 * so use free_node here instead of unref_node. 1664 */ 1665 if (ni == ic->ic_bss) 1666 ieee80211_unref_node(&ni); 1667 else 1668 ieee80211_free_node(ic, ni); 1669 rx_next: 1670 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1671 } while (ath_rxbuf_init(sc, bf) == 0); 1672 1673 ath_hal_rxmonitor(ah); /* rx signal state monitoring */ 1674 ath_hal_rxena(ah); /* in case of RXEOL */ 1675 } 1676 1677 /* 1678 * XXX Size of an ACK control frame in bytes. 1679 */ 1680 #define IEEE80211_ACK_SIZE (2+2+IEEE80211_ADDR_LEN+4) 1681 1682 static int 1683 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 1684 struct mbuf *m0) 1685 { 1686 struct ieee80211com *ic = &sc->sc_ic; 1687 struct ath_hal *ah = sc->sc_ah; 1688 struct ifnet *ifp = &sc->sc_ic.ic_if; 1689 int i, error, iswep, hdrlen, pktlen; 1690 u_int8_t rix, cix, txrate, ctsrate; 1691 struct ath_desc *ds; 1692 struct mbuf *m; 1693 struct ieee80211_frame *wh; 1694 u_int32_t iv; 1695 u_int8_t *ivp; 1696 u_int8_t hdrbuf[sizeof(struct ieee80211_frame) + 1697 IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN]; 1698 u_int subtype, flags, ctsduration, antenna; 1699 HAL_PKT_TYPE atype; 1700 const HAL_RATE_TABLE *rt; 1701 HAL_BOOL shortPreamble; 1702 struct ath_node *an; 1703 1704 wh = mtod(m0, struct ieee80211_frame *); 1705 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1706 hdrlen = sizeof(struct ieee80211_frame); 1707 pktlen = m0->m_pkthdr.len; 1708 1709 if (iswep) { 1710 memcpy(hdrbuf, mtod(m0, caddr_t), hdrlen); 1711 m_adj(m0, hdrlen); 1712 M_PREPEND(m0, sizeof(hdrbuf), M_DONTWAIT); 1713 if (m0 == NULL) { 1714 sc->sc_stats.ast_tx_nombuf++; 1715 return ENOMEM; 1716 } 1717 ivp = hdrbuf + hdrlen; 1718 /* 1719 * XXX 1720 * IV must not duplicate during the lifetime of the key. 1721 * But no mechanism to renew keys is defined in IEEE 802.11 1722 * WEP. And IV may be duplicated between other stations 1723 * because of the session key itself is shared. 1724 * So we use pseudo random IV for now, though it is not the 1725 * right way. 1726 */ 1727 iv = arc4random(); 1728 for (i = 0; i < IEEE80211_WEP_IVLEN; i++) { 1729 ivp[i] = iv; 1730 iv >>= 8; 1731 } 1732 ivp[i] = sc->sc_ic.ic_wep_txkey << 6; /* Key ID and pad */ 1733 memcpy(mtod(m0, caddr_t), hdrbuf, sizeof(hdrbuf)); 1734 /* 1735 * The ICV length must be included into hdrlen and pktlen. 1736 */ 1737 hdrlen = sizeof(hdrbuf) + IEEE80211_WEP_CRCLEN; 1738 pktlen = m0->m_pkthdr.len + IEEE80211_WEP_CRCLEN; 1739 } 1740 pktlen += IEEE80211_CRC_LEN; 1741 1742 /* 1743 * Load the DMA map so any coalescing is done. This 1744 * also calculates the number of descriptors we need. 1745 */ 1746 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1747 ath_mbuf_load_cb, bf, 1748 BUS_DMA_NOWAIT); 1749 if (error != 0) { 1750 sc->sc_stats.ast_tx_busdma++; 1751 m_freem(m0); 1752 return error; 1753 } 1754 /* 1755 * Discard null packets and check for packets that 1756 * require too many TX descriptors. We try to convert 1757 * the latter to a cluster. 1758 */ 1759 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 1760 sc->sc_stats.ast_tx_linear++; 1761 MGETHDR(m, M_DONTWAIT, MT_DATA); 1762 if (m == NULL) { 1763 sc->sc_stats.ast_tx_nombuf++; 1764 m_freem(m0); 1765 return ENOMEM; 1766 } 1767 M_MOVE_PKTHDR(m, m0); 1768 MCLGET(m, M_DONTWAIT); 1769 if ((m->m_flags & M_EXT) == 0) { 1770 sc->sc_stats.ast_tx_nomcl++; 1771 m_freem(m0); 1772 m_free(m); 1773 return ENOMEM; 1774 } 1775 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1776 m_freem(m0); 1777 m->m_len = m->m_pkthdr.len; 1778 m0 = m; 1779 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0, 1780 ath_mbuf_load_cb, bf, 1781 BUS_DMA_NOWAIT); 1782 if (error != 0) { 1783 sc->sc_stats.ast_tx_busdma++; 1784 m_freem(m0); 1785 return error; 1786 } 1787 KASSERT(bf->bf_nseg == 1, 1788 ("ath_tx_start: packet not one segment; nseg %u", 1789 bf->bf_nseg)); 1790 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 1791 sc->sc_stats.ast_tx_nodata++; 1792 m_freem(m0); 1793 return EIO; 1794 } 1795 DPRINTF2(("ath_tx_start: m %p len %u\n", m0, pktlen)); 1796 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1797 bf->bf_m = m0; 1798 bf->bf_node = ni; /* NB: held reference */ 1799 1800 /* setup descriptors */ 1801 ds = bf->bf_desc; 1802 rt = sc->sc_currates; 1803 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1804 1805 /* 1806 * Calculate Atheros packet type from IEEE80211 packet header 1807 * and setup for rate calculations. 1808 */ 1809 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1810 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1811 case IEEE80211_FC0_TYPE_MGT: 1812 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1813 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1814 atype = HAL_PKT_TYPE_BEACON; 1815 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1816 atype = HAL_PKT_TYPE_PROBE_RESP; 1817 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1818 atype = HAL_PKT_TYPE_ATIM; 1819 rix = 0; /* XXX lowest rate */ 1820 break; 1821 case IEEE80211_FC0_TYPE_CTL: 1822 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1823 if (subtype == IEEE80211_FC0_SUBTYPE_PS_POLL) 1824 atype = HAL_PKT_TYPE_PSPOLL; 1825 rix = 0; /* XXX lowest rate */ 1826 break; 1827 default: 1828 rix = sc->sc_rixmap[ni->ni_rates.rs_rates[ni->ni_txrate] & 1829 IEEE80211_RATE_VAL]; 1830 if (rix == 0xff) { 1831 if_printf(ifp, "bogus xmit rate 0x%x\n", 1832 ni->ni_rates.rs_rates[ni->ni_txrate]); 1833 sc->sc_stats.ast_tx_badrate++; 1834 m_freem(m0); 1835 return EIO; 1836 } 1837 break; 1838 } 1839 /* 1840 * NB: the 802.11 layer marks whether or not we should 1841 * use short preamble based on the current mode and 1842 * negotiated parameters. 1843 */ 1844 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1845 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1846 txrate = rt->info[rix].rateCode | rt->info[rix].shortPreamble; 1847 shortPreamble = AH_TRUE; 1848 sc->sc_stats.ast_tx_shortpre++; 1849 } else { 1850 txrate = rt->info[rix].rateCode; 1851 shortPreamble = AH_FALSE; 1852 } 1853 1854 /* 1855 * Calculate miscellaneous flags. 1856 */ 1857 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for wep errors */ 1858 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1859 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1860 sc->sc_stats.ast_tx_noack++; 1861 } else if (pktlen > ic->ic_rtsthreshold) { 1862 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1863 sc->sc_stats.ast_tx_rts++; 1864 } 1865 1866 /* 1867 * Calculate duration. This logically belongs in the 802.11 1868 * layer but it lacks sufficient information to calculate it. 1869 */ 1870 if ((flags & HAL_TXDESC_NOACK) == 0 && 1871 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 1872 u_int16_t dur; 1873 /* 1874 * XXX not right with fragmentation. 1875 */ 1876 dur = ath_hal_computetxtime(ah, rt, IEEE80211_ACK_SIZE, 1877 rix, shortPreamble); 1878 *((u_int16_t*) wh->i_dur) = htole16(dur); 1879 } 1880 1881 /* 1882 * Calculate RTS/CTS rate and duration if needed. 1883 */ 1884 ctsduration = 0; 1885 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 1886 /* 1887 * CTS transmit rate is derived from the transmit rate 1888 * by looking in the h/w rate table. We must also factor 1889 * in whether or not a short preamble is to be used. 1890 */ 1891 cix = rt->info[rix].controlRate; 1892 ctsrate = rt->info[cix].rateCode; 1893 if (shortPreamble) 1894 ctsrate |= rt->info[cix].shortPreamble; 1895 /* 1896 * Compute the transmit duration based on the size 1897 * of an ACK frame. We call into the HAL to do the 1898 * computation since it depends on the characteristics 1899 * of the actual PHY being used. 1900 */ 1901 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 1902 ctsduration += ath_hal_computetxtime(ah, 1903 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 1904 } 1905 /* SIFS + data */ 1906 ctsduration += ath_hal_computetxtime(ah, 1907 rt, pktlen, rix, shortPreamble); 1908 if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 1909 ctsduration += ath_hal_computetxtime(ah, 1910 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 1911 } 1912 } else 1913 ctsrate = 0; 1914 1915 /* 1916 * For now use the antenna on which the last good 1917 * frame was received on. We assume this field is 1918 * initialized to 0 which gives us ``auto'' or the 1919 * ``default'' antenna. 1920 */ 1921 an = (struct ath_node *) ni; 1922 if (an->an_tx_antenna) 1923 antenna = an->an_tx_antenna; 1924 else 1925 antenna = an->an_rx_hist[an->an_rx_hist_next].arh_antenna; 1926 1927 /* 1928 * Formulate first tx descriptor with tx controls. 1929 */ 1930 /* XXX check return value? */ 1931 ath_hal_setuptxdesc(ah, ds 1932 , pktlen /* packet length */ 1933 , hdrlen /* header length */ 1934 , atype /* Atheros packet type */ 1935 , 60 /* txpower XXX */ 1936 , txrate, 1+10 /* series 0 rate/tries */ 1937 , iswep ? sc->sc_ic.ic_wep_txkey : HAL_TXKEYIX_INVALID 1938 , antenna /* antenna mode */ 1939 , flags /* flags */ 1940 , ctsrate /* rts/cts rate */ 1941 , ctsduration /* rts/cts duration */ 1942 ); 1943 #ifdef notyet 1944 ath_hal_setupxtxdesc(ah, ds 1945 , AH_FALSE /* short preamble */ 1946 , 0, 0 /* series 1 rate/tries */ 1947 , 0, 0 /* series 2 rate/tries */ 1948 , 0, 0 /* series 3 rate/tries */ 1949 ); 1950 #endif 1951 /* 1952 * Fillin the remainder of the descriptor info. 1953 */ 1954 for (i = 0; i < bf->bf_nseg; i++, ds++) { 1955 ds->ds_data = bf->bf_segs[i].ds_addr; 1956 if (i == bf->bf_nseg - 1) 1957 ds->ds_link = 0; 1958 else 1959 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 1960 ath_hal_filltxdesc(ah, ds 1961 , bf->bf_segs[i].ds_len /* segment length */ 1962 , i == 0 /* first segment */ 1963 , i == bf->bf_nseg - 1 /* last segment */ 1964 ); 1965 DPRINTF2(("ath_tx_start: %d: %08x %08x %08x %08x %08x %08x\n", 1966 i, ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1, 1967 ds->ds_hw[0], ds->ds_hw[1])); 1968 } 1969 1970 /* 1971 * Insert the frame on the outbound list and 1972 * pass it on to the hardware. 1973 */ 1974 mtx_lock(&sc->sc_txqlock); 1975 TAILQ_INSERT_TAIL(&sc->sc_txq, bf, bf_list); 1976 if (sc->sc_txlink == NULL) { 1977 ath_hal_puttxbuf(ah, sc->sc_txhalq, bf->bf_daddr); 1978 DPRINTF2(("ath_tx_start: TXDP0 = %p (%p)\n", 1979 (caddr_t)bf->bf_daddr, bf->bf_desc)); 1980 } else { 1981 *sc->sc_txlink = bf->bf_daddr; 1982 DPRINTF2(("ath_tx_start: link(%p)=%p (%p)\n", 1983 sc->sc_txlink, (caddr_t)bf->bf_daddr, bf->bf_desc)); 1984 } 1985 sc->sc_txlink = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 1986 mtx_unlock(&sc->sc_txqlock); 1987 1988 ath_hal_txstart(ah, sc->sc_txhalq); 1989 return 0; 1990 } 1991 1992 static void 1993 ath_tx_proc(void *arg, int npending) 1994 { 1995 struct ath_softc *sc = arg; 1996 struct ath_hal *ah = sc->sc_ah; 1997 struct ath_buf *bf; 1998 struct ieee80211com *ic = &sc->sc_ic; 1999 struct ifnet *ifp = &ic->ic_if; 2000 struct ath_desc *ds; 2001 struct ieee80211_node *ni; 2002 struct ath_node *an; 2003 int sr, lr; 2004 HAL_STATUS status; 2005 2006 DPRINTF2(("ath_tx_proc: pending %u tx queue %p, link %p\n", 2007 npending, (caddr_t) ath_hal_gettxbuf(sc->sc_ah, sc->sc_txhalq), 2008 sc->sc_txlink)); 2009 for (;;) { 2010 mtx_lock(&sc->sc_txqlock); 2011 bf = TAILQ_FIRST(&sc->sc_txq); 2012 if (bf == NULL) { 2013 sc->sc_txlink = NULL; 2014 mtx_unlock(&sc->sc_txqlock); 2015 break; 2016 } 2017 /* only the last descriptor is needed */ 2018 ds = &bf->bf_desc[bf->bf_nseg - 1]; 2019 status = ath_hal_txprocdesc(ah, ds); 2020 #ifdef AR_DEBUG 2021 if (ath_debug > 1) 2022 ath_printtxbuf(bf, status == HAL_OK); 2023 #endif 2024 if (status == HAL_EINPROGRESS) { 2025 mtx_unlock(&sc->sc_txqlock); 2026 break; 2027 } 2028 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2029 mtx_unlock(&sc->sc_txqlock); 2030 2031 ni = bf->bf_node; 2032 if (ni != NULL) { 2033 an = (struct ath_node *) ni; 2034 if (ds->ds_txstat.ts_status == 0) { 2035 an->an_tx_ok++; 2036 an->an_tx_antenna = ds->ds_txstat.ts_antenna; 2037 } else { 2038 an->an_tx_err++; 2039 ifp->if_oerrors++; 2040 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 2041 sc->sc_stats.ast_tx_xretries++; 2042 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 2043 sc->sc_stats.ast_tx_fifoerr++; 2044 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 2045 sc->sc_stats.ast_tx_filtered++; 2046 an->an_tx_antenna = 0; /* invalidate */ 2047 } 2048 sr = ds->ds_txstat.ts_shortretry; 2049 lr = ds->ds_txstat.ts_longretry; 2050 sc->sc_stats.ast_tx_shortretry += sr; 2051 sc->sc_stats.ast_tx_longretry += lr; 2052 if (sr + lr) 2053 an->an_tx_retr++; 2054 /* 2055 * Reclaim reference to node. 2056 * 2057 * NB: the node may be reclaimed here if, for example 2058 * this is a DEAUTH message that was sent and the 2059 * node was timed out due to inactivity. 2060 */ 2061 if (ni != ic->ic_bss) 2062 ieee80211_free_node(ic, ni); 2063 } 2064 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2065 BUS_DMASYNC_POSTWRITE); 2066 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2067 m_freem(bf->bf_m); 2068 bf->bf_m = NULL; 2069 bf->bf_node = NULL; 2070 2071 mtx_lock(&sc->sc_txbuflock); 2072 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2073 mtx_unlock(&sc->sc_txbuflock); 2074 } 2075 ifp->if_flags &= ~IFF_OACTIVE; 2076 sc->sc_tx_timer = 0; 2077 2078 ath_start(ifp); 2079 } 2080 2081 /* 2082 * Drain the transmit queue and reclaim resources. 2083 */ 2084 static void 2085 ath_draintxq(struct ath_softc *sc) 2086 { 2087 struct ath_hal *ah = sc->sc_ah; 2088 struct ifnet *ifp = &sc->sc_ic.ic_if; 2089 struct ath_buf *bf; 2090 2091 /* XXX return value */ 2092 if (!sc->sc_invalid) { 2093 /* don't touch the hardware if marked invalid */ 2094 (void) ath_hal_stoptxdma(ah, sc->sc_txhalq); 2095 DPRINTF(("ath_draintxq: tx queue %p, link %p\n", 2096 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_txhalq), 2097 sc->sc_txlink)); 2098 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 2099 DPRINTF(("ath_draintxq: beacon queue %p\n", 2100 (caddr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq))); 2101 } 2102 for (;;) { 2103 mtx_lock(&sc->sc_txqlock); 2104 bf = TAILQ_FIRST(&sc->sc_txq); 2105 if (bf == NULL) { 2106 sc->sc_txlink = NULL; 2107 mtx_unlock(&sc->sc_txqlock); 2108 break; 2109 } 2110 TAILQ_REMOVE(&sc->sc_txq, bf, bf_list); 2111 mtx_unlock(&sc->sc_txqlock); 2112 #ifdef AR_DEBUG 2113 if (ath_debug) 2114 ath_printtxbuf(bf, 2115 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 2116 #endif /* AR_DEBUG */ 2117 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2118 m_freem(bf->bf_m); 2119 bf->bf_m = NULL; 2120 bf->bf_node = NULL; 2121 mtx_lock(&sc->sc_txbuflock); 2122 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2123 mtx_unlock(&sc->sc_txbuflock); 2124 } 2125 ifp->if_flags &= ~IFF_OACTIVE; 2126 sc->sc_tx_timer = 0; 2127 } 2128 2129 /* 2130 * Disable the receive h/w in preparation for a reset. 2131 */ 2132 static void 2133 ath_stoprecv(struct ath_softc *sc) 2134 { 2135 struct ath_hal *ah = sc->sc_ah; 2136 2137 ath_hal_stoppcurecv(ah); /* disable PCU */ 2138 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 2139 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 2140 DELAY(3000); /* long enough for 1 frame */ 2141 #ifdef AR_DEBUG 2142 if (ath_debug) { 2143 struct ath_buf *bf; 2144 2145 DPRINTF(("ath_stoprecv: rx queue %p, link %p\n", 2146 (caddr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink)); 2147 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2148 if (ath_hal_rxprocdesc(ah, bf->bf_desc) == HAL_OK) 2149 ath_printrxbuf(bf, 1); 2150 } 2151 } 2152 #endif 2153 sc->sc_rxlink = NULL; /* just in case */ 2154 } 2155 2156 /* 2157 * Enable the receive h/w following a reset. 2158 */ 2159 static int 2160 ath_startrecv(struct ath_softc *sc) 2161 { 2162 struct ath_hal *ah = sc->sc_ah; 2163 struct ath_buf *bf; 2164 2165 sc->sc_rxlink = NULL; 2166 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 2167 int error = ath_rxbuf_init(sc, bf); 2168 if (error != 0) { 2169 DPRINTF(("ath_startrecv: ath_rxbuf_init failed %d\n", 2170 error)); 2171 return error; 2172 } 2173 } 2174 2175 bf = TAILQ_FIRST(&sc->sc_rxbuf); 2176 ath_hal_putrxbuf(ah, bf->bf_daddr); 2177 ath_hal_rxena(ah); /* enable recv descriptors */ 2178 ath_mode_init(sc); /* set filters, etc. */ 2179 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 2180 return 0; 2181 } 2182 2183 /* 2184 * Set/change channels. If the channel is really being changed, 2185 * it's done by resetting the chip. To accomplish this we must 2186 * first cleanup any pending DMA, then restart stuff after a la 2187 * ath_init. 2188 */ 2189 static int 2190 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 2191 { 2192 struct ath_hal *ah = sc->sc_ah; 2193 struct ieee80211com *ic = &sc->sc_ic; 2194 2195 DPRINTF(("ath_chan_set: %u (%u MHz) -> %u (%u MHz)\n", 2196 ieee80211_chan2ieee(ic, ic->ic_ibss_chan), 2197 ic->ic_ibss_chan->ic_freq, 2198 ieee80211_chan2ieee(ic, chan), chan->ic_freq)); 2199 if (chan != ic->ic_ibss_chan) { 2200 HAL_STATUS status; 2201 HAL_CHANNEL hchan; 2202 enum ieee80211_phymode mode; 2203 2204 /* 2205 * To switch channels clear any pending DMA operations; 2206 * wait long enough for the RX fifo to drain, reset the 2207 * hardware at the new frequency, and then re-enable 2208 * the relevant bits of the h/w. 2209 */ 2210 ath_hal_intrset(ah, 0); /* disable interrupts */ 2211 ath_draintxq(sc); /* clear pending tx frames */ 2212 ath_stoprecv(sc); /* turn off frame recv */ 2213 /* 2214 * Convert to a HAL channel description with 2215 * the flags constrained to reflect the current 2216 * operating mode. 2217 */ 2218 hchan.channel = chan->ic_freq; 2219 hchan.channelFlags = ath_chan2flags(ic, chan); 2220 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 2221 if_printf(&ic->ic_if, "ath_chan_set: unable to reset " 2222 "channel %u (%u Mhz)\n", 2223 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 2224 return EIO; 2225 } 2226 /* 2227 * Re-enable rx framework. 2228 */ 2229 if (ath_startrecv(sc) != 0) { 2230 if_printf(&ic->ic_if, 2231 "ath_chan_set: unable to restart recv logic\n"); 2232 return EIO; 2233 } 2234 2235 /* 2236 * Update BPF state. 2237 */ 2238 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 2239 htole16(chan->ic_freq); 2240 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 2241 htole16(chan->ic_flags); 2242 2243 /* 2244 * Change channels and update the h/w rate map 2245 * if we're switching; e.g. 11a to 11b/g. 2246 */ 2247 ic->ic_ibss_chan = chan; 2248 mode = ieee80211_chan2mode(ic, chan); 2249 if (mode != sc->sc_curmode) 2250 ath_setcurmode(sc, mode); 2251 2252 /* 2253 * Re-enable interrupts. 2254 */ 2255 ath_hal_intrset(ah, sc->sc_imask); 2256 } 2257 return 0; 2258 } 2259 2260 static void 2261 ath_next_scan(void *arg) 2262 { 2263 struct ath_softc *sc = arg; 2264 struct ieee80211com *ic = &sc->sc_ic; 2265 struct ifnet *ifp = &ic->ic_if; 2266 2267 if (ic->ic_state == IEEE80211_S_SCAN) 2268 ieee80211_next_scan(ifp); 2269 } 2270 2271 /* 2272 * Periodically recalibrate the PHY to account 2273 * for temperature/environment changes. 2274 */ 2275 static void 2276 ath_calibrate(void *arg) 2277 { 2278 struct ath_softc *sc = arg; 2279 struct ath_hal *ah = sc->sc_ah; 2280 struct ieee80211com *ic = &sc->sc_ic; 2281 struct ieee80211_channel *c; 2282 HAL_CHANNEL hchan; 2283 2284 sc->sc_stats.ast_per_cal++; 2285 2286 /* 2287 * Convert to a HAL channel description with the flags 2288 * constrained to reflect the current operating mode. 2289 */ 2290 c = ic->ic_ibss_chan; 2291 hchan.channel = c->ic_freq; 2292 hchan.channelFlags = ath_chan2flags(ic, c); 2293 2294 DPRINTF(("%s: channel %u/%x\n", __func__, c->ic_freq, c->ic_flags)); 2295 2296 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 2297 /* 2298 * Rfgain is out of bounds, reset the chip 2299 * to load new gain values. 2300 */ 2301 sc->sc_stats.ast_per_rfgain++; 2302 ath_reset(sc); 2303 } 2304 if (!ath_hal_calibrate(ah, &hchan)) { 2305 DPRINTF(("%s: calibration of channel %u failed\n", 2306 __func__, c->ic_freq)); 2307 sc->sc_stats.ast_per_calfail++; 2308 } 2309 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, ath_calibrate, sc); 2310 } 2311 2312 static int 2313 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2314 { 2315 struct ifnet *ifp = &ic->ic_if; 2316 struct ath_softc *sc = ifp->if_softc; 2317 struct ath_hal *ah = sc->sc_ah; 2318 struct ieee80211_node *ni; 2319 int i, error; 2320 u_int8_t *bssid; 2321 u_int32_t rfilt; 2322 static const HAL_LED_STATE leds[] = { 2323 HAL_LED_INIT, /* IEEE80211_S_INIT */ 2324 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 2325 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 2326 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 2327 HAL_LED_RUN, /* IEEE80211_S_RUN */ 2328 }; 2329 2330 DPRINTF(("%s: %s -> %s\n", __func__, 2331 ieee80211_state_name[ic->ic_state], 2332 ieee80211_state_name[nstate])); 2333 2334 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 2335 2336 if (nstate == IEEE80211_S_INIT) { 2337 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2338 ath_hal_intrset(ah, sc->sc_imask); 2339 callout_stop(&sc->sc_scan_ch); 2340 callout_stop(&sc->sc_cal_ch); 2341 return (*sc->sc_newstate)(ic, nstate, arg); 2342 } 2343 ni = ic->ic_bss; 2344 error = ath_chan_set(sc, ni->ni_chan); 2345 if (error != 0) 2346 goto bad; 2347 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 2348 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2349 if (ic->ic_opmode != IEEE80211_M_STA) 2350 rfilt |= HAL_RX_FILTER_PROBEREQ; 2351 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2352 (ifp->if_flags & IFF_PROMISC)) 2353 rfilt |= HAL_RX_FILTER_PROM; 2354 if (ic->ic_opmode == IEEE80211_M_STA || 2355 ic->ic_state == IEEE80211_S_SCAN) 2356 rfilt |= HAL_RX_FILTER_BEACON; 2357 if (nstate == IEEE80211_S_SCAN) { 2358 callout_reset(&sc->sc_scan_ch, (hz * ath_dwelltime) / 1000, 2359 ath_next_scan, sc); 2360 bssid = ifp->if_broadcastaddr; 2361 } else { 2362 callout_stop(&sc->sc_scan_ch); 2363 bssid = ni->ni_bssid; 2364 } 2365 ath_hal_setrxfilter(ah, rfilt); 2366 DPRINTF(("%s: RX filter 0x%x bssid %s\n", 2367 __func__, rfilt, ether_sprintf(bssid))); 2368 2369 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 2370 ath_hal_setassocid(ah, bssid, ni->ni_associd); 2371 else 2372 ath_hal_setassocid(ah, bssid, 0); 2373 if (ic->ic_flags & IEEE80211_F_WEPON) { 2374 for (i = 0; i < IEEE80211_WEP_NKID; i++) 2375 if (ath_hal_keyisvalid(ah, i)) 2376 ath_hal_keysetmac(ah, i, bssid); 2377 } 2378 2379 if (nstate == IEEE80211_S_RUN) { 2380 DPRINTF(("%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 2381 "capinfo=0x%04x chan=%d\n" 2382 , __func__ 2383 , ic->ic_flags 2384 , ni->ni_intval 2385 , ether_sprintf(ni->ni_bssid) 2386 , ni->ni_capinfo 2387 , ieee80211_chan2ieee(ic, ni->ni_chan))); 2388 2389 /* 2390 * Allocate and setup the beacon frame for AP or adhoc mode. 2391 */ 2392 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2393 ic->ic_opmode == IEEE80211_M_IBSS) { 2394 error = ath_beacon_alloc(sc, ni); 2395 if (error != 0) 2396 goto bad; 2397 } 2398 2399 /* 2400 * Configure the beacon and sleep timers. 2401 */ 2402 ath_beacon_config(sc); 2403 2404 /* start periodic recalibration timer */ 2405 callout_reset(&sc->sc_cal_ch, hz * ath_calinterval, 2406 ath_calibrate, sc); 2407 } else { 2408 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 2409 ath_hal_intrset(ah, sc->sc_imask); 2410 callout_stop(&sc->sc_cal_ch); /* no calibration */ 2411 } 2412 /* 2413 * Reset the rate control state. 2414 */ 2415 ath_rate_ctl_reset(sc, nstate); 2416 /* 2417 * Invoke the parent method to complete the work. 2418 */ 2419 return (*sc->sc_newstate)(ic, nstate, arg); 2420 bad: 2421 callout_stop(&sc->sc_scan_ch); 2422 callout_stop(&sc->sc_cal_ch); 2423 /* NB: do not invoke the parent */ 2424 return error; 2425 } 2426 2427 /* 2428 * Setup driver-specific state for a newly associated node. 2429 * Note that we're called also on a re-associate, the isnew 2430 * param tells us if this is the first time or not. 2431 */ 2432 static void 2433 ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2434 { 2435 if (isnew) { 2436 struct ath_node *an = (struct ath_node *) ni; 2437 2438 an->an_tx_ok = an->an_tx_err = 2439 an->an_tx_retr = an->an_tx_upper = 0; 2440 /* start with highest negotiated rate */ 2441 /* 2442 * XXX should do otherwise but only when 2443 * the rate control algorithm is better. 2444 */ 2445 KASSERT(ni->ni_rates.rs_nrates > 0, 2446 ("new association w/ no rates!")); 2447 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2448 } 2449 } 2450 2451 static int 2452 ath_getchannels(struct ath_softc *sc, u_int cc, HAL_BOOL outdoor) 2453 { 2454 struct ieee80211com *ic = &sc->sc_ic; 2455 struct ifnet *ifp = &ic->ic_if; 2456 struct ath_hal *ah = sc->sc_ah; 2457 HAL_CHANNEL *chans; 2458 int i, ix, nchan; 2459 2460 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 2461 M_TEMP, M_NOWAIT); 2462 if (chans == NULL) { 2463 if_printf(ifp, "unable to allocate channel table\n"); 2464 return ENOMEM; 2465 } 2466 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 2467 cc, HAL_MODE_ALL, outdoor)) { 2468 if_printf(ifp, "unable to collect channel list from hal\n"); 2469 free(chans, M_TEMP); 2470 return EINVAL; 2471 } 2472 2473 /* 2474 * Convert HAL channels to ieee80211 ones and insert 2475 * them in the table according to their channel number. 2476 */ 2477 for (i = 0; i < nchan; i++) { 2478 HAL_CHANNEL *c = &chans[i]; 2479 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 2480 if (ix > IEEE80211_CHAN_MAX) { 2481 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 2482 ix, c->channel, c->channelFlags); 2483 continue; 2484 } 2485 /* NB: flags are known to be compatible */ 2486 if (ic->ic_channels[ix].ic_freq == 0) { 2487 ic->ic_channels[ix].ic_freq = c->channel; 2488 ic->ic_channels[ix].ic_flags = c->channelFlags; 2489 } else { 2490 /* channels overlap; e.g. 11g and 11b */ 2491 ic->ic_channels[ix].ic_flags |= c->channelFlags; 2492 } 2493 } 2494 free(chans, M_TEMP); 2495 return 0; 2496 } 2497 2498 static int 2499 ath_rate_setup(struct ath_softc *sc, u_int mode) 2500 { 2501 struct ath_hal *ah = sc->sc_ah; 2502 struct ieee80211com *ic = &sc->sc_ic; 2503 const HAL_RATE_TABLE *rt; 2504 struct ieee80211_rateset *rs; 2505 int i, maxrates; 2506 2507 switch (mode) { 2508 case IEEE80211_MODE_11A: 2509 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 2510 break; 2511 case IEEE80211_MODE_11B: 2512 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 2513 break; 2514 case IEEE80211_MODE_11G: 2515 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 2516 break; 2517 case IEEE80211_MODE_TURBO: 2518 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 2519 break; 2520 default: 2521 DPRINTF(("%s: invalid mode %u\n", __func__, mode)); 2522 return 0; 2523 } 2524 rt = sc->sc_rates[mode]; 2525 if (rt == NULL) 2526 return 0; 2527 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 2528 DPRINTF(("%s: rate table too small (%u > %u)\n", 2529 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE)); 2530 maxrates = IEEE80211_RATE_MAXSIZE; 2531 } else 2532 maxrates = rt->rateCount; 2533 rs = &ic->ic_sup_rates[mode]; 2534 for (i = 0; i < maxrates; i++) 2535 rs->rs_rates[i] = rt->info[i].dot11Rate; 2536 rs->rs_nrates = maxrates; 2537 return 1; 2538 } 2539 2540 static void 2541 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 2542 { 2543 const HAL_RATE_TABLE *rt; 2544 int i; 2545 2546 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 2547 rt = sc->sc_rates[mode]; 2548 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 2549 for (i = 0; i < rt->rateCount; i++) 2550 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 2551 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 2552 for (i = 0; i < 32; i++) 2553 sc->sc_hwmap[i] = rt->info[rt->rateCodeToIndex[i]].dot11Rate; 2554 sc->sc_currates = rt; 2555 sc->sc_curmode = mode; 2556 } 2557 2558 /* 2559 * Reset the rate control state for each 802.11 state transition. 2560 */ 2561 static void 2562 ath_rate_ctl_reset(struct ath_softc *sc, enum ieee80211_state state) 2563 { 2564 struct ieee80211com *ic = &sc->sc_ic; 2565 struct ieee80211_node *ni; 2566 struct ath_node *an; 2567 2568 if (ic->ic_opmode != IEEE80211_M_STA) { 2569 /* 2570 * When operating as a station the node table holds 2571 * the AP's that were discovered during scanning. 2572 * For any other operating mode we want to reset the 2573 * tx rate state of each node. 2574 */ 2575 TAILQ_FOREACH(ni, &ic->ic_node, ni_list) { 2576 ni->ni_txrate = 0; /* use lowest rate */ 2577 an = (struct ath_node *) ni; 2578 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 2579 an->an_tx_upper = 0; 2580 } 2581 } 2582 /* 2583 * Reset local xmit state; this is really only meaningful 2584 * when operating in station or adhoc mode. 2585 */ 2586 ni = ic->ic_bss; 2587 an = (struct ath_node *) ni; 2588 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = an->an_tx_upper = 0; 2589 if (state == IEEE80211_S_RUN) { 2590 /* start with highest negotiated rate */ 2591 KASSERT(ni->ni_rates.rs_nrates > 0, 2592 ("transition to RUN state w/ no rates!")); 2593 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2594 } else { 2595 /* use lowest rate */ 2596 ni->ni_txrate = 0; 2597 } 2598 } 2599 2600 /* 2601 * Examine and potentially adjust the transmit rate. 2602 */ 2603 static void 2604 ath_rate_ctl(void *arg, struct ieee80211_node *ni) 2605 { 2606 struct ath_softc *sc = arg; 2607 struct ath_node *an = (struct ath_node *) ni; 2608 struct ieee80211_rateset *rs = &ni->ni_rates; 2609 int mod = 0, orate, enough; 2610 2611 /* 2612 * Rate control 2613 * XXX: very primitive version. 2614 */ 2615 sc->sc_stats.ast_rate_calls++; 2616 2617 enough = (an->an_tx_ok + an->an_tx_err >= 10); 2618 2619 /* no packet reached -> down */ 2620 if (an->an_tx_err > 0 && an->an_tx_ok == 0) 2621 mod = -1; 2622 2623 /* all packets needs retry in average -> down */ 2624 if (enough && an->an_tx_ok < an->an_tx_retr) 2625 mod = -1; 2626 2627 /* no error and less than 10% of packets needs retry -> up */ 2628 if (enough && an->an_tx_err == 0 && an->an_tx_ok > an->an_tx_retr * 10) 2629 mod = 1; 2630 2631 orate = ni->ni_txrate; 2632 switch (mod) { 2633 case 0: 2634 if (enough && an->an_tx_upper > 0) 2635 an->an_tx_upper--; 2636 break; 2637 case -1: 2638 if (ni->ni_txrate > 0) { 2639 ni->ni_txrate--; 2640 sc->sc_stats.ast_rate_drop++; 2641 } 2642 an->an_tx_upper = 0; 2643 break; 2644 case 1: 2645 if (++an->an_tx_upper < 2) 2646 break; 2647 an->an_tx_upper = 0; 2648 if (ni->ni_txrate + 1 < rs->rs_nrates) { 2649 ni->ni_txrate++; 2650 sc->sc_stats.ast_rate_raise++; 2651 } 2652 break; 2653 } 2654 2655 if (ni->ni_txrate != orate) { 2656 printf("%s: %dM -> %dM (%d ok, %d err, %d retr)\n", 2657 __func__, 2658 (rs->rs_rates[orate] & IEEE80211_RATE_VAL) / 2, 2659 (rs->rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL) / 2, 2660 an->an_tx_ok, an->an_tx_err, an->an_tx_retr); 2661 } 2662 if (ni->ni_txrate != orate || enough) 2663 an->an_tx_ok = an->an_tx_err = an->an_tx_retr = 0; 2664 } 2665 2666 #ifdef AR_DEBUG 2667 static int 2668 sysctl_hw_ath_dump(SYSCTL_HANDLER_ARGS) 2669 { 2670 char dmode[64]; 2671 int error; 2672 2673 strncpy(dmode, "", sizeof(dmode) - 1); 2674 dmode[sizeof(dmode) - 1] = '\0'; 2675 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2676 2677 if (error == 0 && req->newptr != NULL) { 2678 struct ifnet *ifp; 2679 struct ath_softc *sc; 2680 2681 ifp = ifunit("ath0"); /* XXX */ 2682 if (!ifp) 2683 return EINVAL; 2684 sc = ifp->if_softc; 2685 if (strcmp(dmode, "hal") == 0) 2686 ath_hal_dumpstate(sc->sc_ah); 2687 else if (strcmp(dmode, "eeprom") == 0) 2688 ath_hal_dumpeeprom(sc->sc_ah); 2689 else if (strcmp(dmode, "rfgain") == 0) 2690 ath_hal_dumprfgain(sc->sc_ah); 2691 else if (strcmp(dmode, "ani") == 0) 2692 ath_hal_dumpani(sc->sc_ah); 2693 else 2694 return EINVAL; 2695 } 2696 return error; 2697 } 2698 SYSCTL_PROC(_hw_ath, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2699 0, 0, sysctl_hw_ath_dump, "A", "Dump driver state"); 2700 2701 static void 2702 ath_printrxbuf(struct ath_buf *bf, int done) 2703 { 2704 struct ath_desc *ds; 2705 int i; 2706 2707 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2708 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 2709 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2710 ds->ds_link, ds->ds_data, 2711 ds->ds_ctl0, ds->ds_ctl1, 2712 ds->ds_hw[0], ds->ds_hw[1], 2713 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 2714 } 2715 } 2716 2717 static void 2718 ath_printtxbuf(struct ath_buf *bf, int done) 2719 { 2720 struct ath_desc *ds; 2721 int i; 2722 2723 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 2724 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 2725 i, ds, (struct ath_desc *)bf->bf_daddr + i, 2726 ds->ds_link, ds->ds_data, 2727 ds->ds_ctl0, ds->ds_ctl1, 2728 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 2729 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 2730 } 2731 } 2732 #endif /* AR_DEBUG */ 2733