1 /*- 2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sysctl.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/errno.h> 54 #include <sys/callout.h> 55 #include <sys/bus.h> 56 #include <sys/endian.h> 57 #include <sys/kthread.h> 58 #include <sys/taskqueue.h> 59 60 #include <machine/bus.h> 61 62 #include <net/if.h> 63 #include <net/if_dl.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 #include <net/if_arp.h> 67 #include <net/ethernet.h> 68 #include <net/if_llc.h> 69 70 #include <net80211/ieee80211_var.h> 71 72 #include <net/bpf.h> 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/if_ether.h> 77 #endif 78 79 #include <dev/ath/if_athvar.h> 80 #include <contrib/dev/ath/ah_desc.h> 81 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 82 83 #ifdef ATH_TX99_DIAG 84 #include <dev/ath/ath_tx99/ath_tx99.h> 85 #endif 86 87 /* unaligned little endian access */ 88 #define LE_READ_2(p) \ 89 ((u_int16_t) \ 90 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 91 #define LE_READ_4(p) \ 92 ((u_int32_t) \ 93 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 94 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 95 96 enum { 97 ATH_LED_TX, 98 ATH_LED_RX, 99 ATH_LED_POLL, 100 }; 101 102 static void ath_init(void *); 103 static void ath_stop_locked(struct ifnet *); 104 static void ath_stop(struct ifnet *); 105 static void ath_start(struct ifnet *); 106 static int ath_reset(struct ifnet *); 107 static int ath_media_change(struct ifnet *); 108 static void ath_watchdog(struct ifnet *); 109 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 110 static void ath_fatal_proc(void *, int); 111 static void ath_rxorn_proc(void *, int); 112 static void ath_bmiss_proc(void *, int); 113 static int ath_key_alloc(struct ieee80211com *, 114 const struct ieee80211_key *, 115 ieee80211_keyix *, ieee80211_keyix *); 116 static int ath_key_delete(struct ieee80211com *, 117 const struct ieee80211_key *); 118 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 119 const u_int8_t mac[IEEE80211_ADDR_LEN]); 120 static void ath_key_update_begin(struct ieee80211com *); 121 static void ath_key_update_end(struct ieee80211com *); 122 static void ath_mode_init(struct ath_softc *); 123 static void ath_setslottime(struct ath_softc *); 124 static void ath_updateslot(struct ifnet *); 125 static int ath_beaconq_setup(struct ath_hal *); 126 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 127 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 128 static void ath_beacon_proc(void *, int); 129 static void ath_bstuck_proc(void *, int); 130 static void ath_beacon_free(struct ath_softc *); 131 static void ath_beacon_config(struct ath_softc *); 132 static void ath_descdma_cleanup(struct ath_softc *sc, 133 struct ath_descdma *, ath_bufhead *); 134 static int ath_desc_alloc(struct ath_softc *); 135 static void ath_desc_free(struct ath_softc *); 136 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 137 static void ath_node_free(struct ieee80211_node *); 138 static int8_t ath_node_getrssi(const struct ieee80211_node *); 139 static void ath_node_getsignal(const struct ieee80211_node *, 140 int8_t *, int8_t *); 141 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 142 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 143 struct ieee80211_node *ni, 144 int subtype, int rssi, int noise, u_int32_t rstamp); 145 static void ath_setdefantenna(struct ath_softc *, u_int); 146 static void ath_rx_proc(void *, int); 147 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 148 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 149 static int ath_tx_setup(struct ath_softc *, int, int); 150 static int ath_wme_update(struct ieee80211com *); 151 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 152 static void ath_tx_cleanup(struct ath_softc *); 153 static void ath_freetx(struct mbuf *); 154 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 155 struct ath_buf *, struct mbuf *); 156 static void ath_tx_proc_q0(void *, int); 157 static void ath_tx_proc_q0123(void *, int); 158 static void ath_tx_proc(void *, int); 159 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 160 static void ath_draintxq(struct ath_softc *); 161 static void ath_stoprecv(struct ath_softc *); 162 static int ath_startrecv(struct ath_softc *); 163 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 164 static void ath_scan_start(struct ieee80211com *); 165 static void ath_scan_end(struct ieee80211com *); 166 static void ath_set_channel(struct ieee80211com *); 167 static void ath_calibrate(void *); 168 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 169 static void ath_setup_stationkey(struct ieee80211_node *); 170 static void ath_newassoc(struct ieee80211_node *, int); 171 static int ath_getchannels(struct ath_softc *, 172 HAL_REG_DOMAIN, HAL_CTRY_CODE, HAL_BOOL, HAL_BOOL); 173 static void ath_led_event(struct ath_softc *, int); 174 static void ath_update_txpow(struct ath_softc *); 175 176 static int ath_rate_setup(struct ath_softc *, u_int mode); 177 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 178 179 static void ath_sysctlattach(struct ath_softc *); 180 static int ath_raw_xmit(struct ieee80211_node *, 181 struct mbuf *, const struct ieee80211_bpf_params *); 182 static void ath_bpfattach(struct ath_softc *); 183 static void ath_announce(struct ath_softc *); 184 185 SYSCTL_DECL(_hw_ath); 186 187 /* XXX validate sysctl values */ 188 static int ath_calinterval = 30; /* calibrate every 30 secs */ 189 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 190 0, "chip calibration interval (secs)"); 191 static int ath_outdoor = AH_TRUE; /* outdoor operation */ 192 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RW, &ath_outdoor, 193 0, "outdoor operation"); 194 TUNABLE_INT("hw.ath.outdoor", &ath_outdoor); 195 static int ath_xchanmode = AH_TRUE; /* extended channel use */ 196 SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RW, &ath_xchanmode, 197 0, "extended channel mode"); 198 TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode); 199 static int ath_countrycode = CTRY_DEFAULT; /* country code */ 200 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RW, &ath_countrycode, 201 0, "country code"); 202 TUNABLE_INT("hw.ath.countrycode", &ath_countrycode); 203 static int ath_regdomain = 0; /* regulatory domain */ 204 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 205 0, "regulatory domain"); 206 207 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 208 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 209 0, "rx buffers allocated"); 210 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 211 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 212 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 213 0, "tx buffers allocated"); 214 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 215 216 #ifdef ATH_DEBUG 217 static int ath_debug = 0; 218 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 219 0, "control debugging printfs"); 220 TUNABLE_INT("hw.ath.debug", &ath_debug); 221 enum { 222 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 223 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 224 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 225 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 226 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 227 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 228 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 229 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 230 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 231 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 232 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 233 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 234 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 235 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 236 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 237 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 238 ATH_DEBUG_NODE = 0x00080000, /* node management */ 239 ATH_DEBUG_LED = 0x00100000, /* led management */ 240 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 241 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 242 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 243 ATH_DEBUG_ANY = 0xffffffff 244 }; 245 #define IFF_DUMPPKTS(sc, m) \ 246 ((sc->sc_debug & (m)) || \ 247 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 248 #define DPRINTF(sc, m, fmt, ...) do { \ 249 if (sc->sc_debug & (m)) \ 250 printf(fmt, __VA_ARGS__); \ 251 } while (0) 252 #define KEYPRINTF(sc, ix, hk, mac) do { \ 253 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 254 ath_keyprint(sc, __func__, ix, hk, mac); \ 255 } while (0) 256 static void ath_printrxbuf(const struct ath_buf *bf, u_int ix, int); 257 static void ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done); 258 #else 259 #define IFF_DUMPPKTS(sc, m) \ 260 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 261 #define DPRINTF(sc, m, fmt, ...) do { \ 262 (void) sc; \ 263 } while (0) 264 #define KEYPRINTF(sc, k, ix, mac) do { \ 265 (void) sc; \ 266 } while (0) 267 #endif 268 269 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 270 271 int 272 ath_attach(u_int16_t devid, struct ath_softc *sc) 273 { 274 struct ifnet *ifp; 275 struct ieee80211com *ic = &sc->sc_ic; 276 struct ath_hal *ah = NULL; 277 HAL_STATUS status; 278 int error = 0, i; 279 280 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 281 282 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 283 if (ifp == NULL) { 284 device_printf(sc->sc_dev, "can not if_alloc()\n"); 285 error = ENOSPC; 286 goto bad; 287 } 288 289 /* set these up early for if_printf use */ 290 if_initname(ifp, device_get_name(sc->sc_dev), 291 device_get_unit(sc->sc_dev)); 292 293 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 294 if (ah == NULL) { 295 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 296 status); 297 error = ENXIO; 298 goto bad; 299 } 300 if (ah->ah_abi != HAL_ABI_VERSION) { 301 if_printf(ifp, "HAL ABI mismatch detected " 302 "(HAL:0x%x != driver:0x%x)\n", 303 ah->ah_abi, HAL_ABI_VERSION); 304 error = ENXIO; 305 goto bad; 306 } 307 sc->sc_ah = ah; 308 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 309 310 /* 311 * Check if the MAC has multi-rate retry support. 312 * We do this by trying to setup a fake extended 313 * descriptor. MAC's that don't have support will 314 * return false w/o doing anything. MAC's that do 315 * support it will return true w/o doing anything. 316 */ 317 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 318 319 /* 320 * Check if the device has hardware counters for PHY 321 * errors. If so we need to enable the MIB interrupt 322 * so we can act on stat triggers. 323 */ 324 if (ath_hal_hwphycounters(ah)) 325 sc->sc_needmib = 1; 326 327 /* 328 * Get the hardware key cache size. 329 */ 330 sc->sc_keymax = ath_hal_keycachesize(ah); 331 if (sc->sc_keymax > ATH_KEYMAX) { 332 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 333 ATH_KEYMAX, sc->sc_keymax); 334 sc->sc_keymax = ATH_KEYMAX; 335 } 336 /* 337 * Reset the key cache since some parts do not 338 * reset the contents on initial power up. 339 */ 340 for (i = 0; i < sc->sc_keymax; i++) 341 ath_hal_keyreset(ah, i); 342 343 /* 344 * Collect the channel list using the default country 345 * code and including outdoor channels. The 802.11 layer 346 * is resposible for filtering this list based on settings 347 * like the phy mode. 348 */ 349 error = ath_getchannels(sc, ath_regdomain, ath_countrycode, 350 ath_outdoor != 0, ath_xchanmode != 0); 351 if (error != 0) 352 goto bad; 353 354 /* 355 * Setup rate tables for all potential media types. 356 */ 357 ath_rate_setup(sc, IEEE80211_MODE_11A); 358 ath_rate_setup(sc, IEEE80211_MODE_11B); 359 ath_rate_setup(sc, IEEE80211_MODE_11G); 360 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 361 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 362 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 363 ath_rate_setup(sc, IEEE80211_MODE_11NA); 364 ath_rate_setup(sc, IEEE80211_MODE_11NG); 365 ath_rate_setup(sc, IEEE80211_MODE_HALF); 366 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 367 368 /* NB: setup here so ath_rate_update is happy */ 369 ath_setcurmode(sc, IEEE80211_MODE_11A); 370 371 /* 372 * Allocate tx+rx descriptors and populate the lists. 373 */ 374 error = ath_desc_alloc(sc); 375 if (error != 0) { 376 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 377 goto bad; 378 } 379 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 380 callout_init(&sc->sc_dfs_ch, CALLOUT_MPSAFE); 381 382 ATH_TXBUF_LOCK_INIT(sc); 383 384 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 385 taskqueue_thread_enqueue, &sc->sc_tq); 386 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 387 "%s taskq", ifp->if_xname); 388 389 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 390 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 391 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 392 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 393 394 /* 395 * Allocate hardware transmit queues: one queue for 396 * beacon frames and one data queue for each QoS 397 * priority. Note that the hal handles reseting 398 * these queues at the needed time. 399 * 400 * XXX PS-Poll 401 */ 402 sc->sc_bhalq = ath_beaconq_setup(ah); 403 if (sc->sc_bhalq == (u_int) -1) { 404 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 405 error = EIO; 406 goto bad2; 407 } 408 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 409 if (sc->sc_cabq == NULL) { 410 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 411 error = EIO; 412 goto bad2; 413 } 414 /* NB: s/w q, qnum used only by WITNESS */ 415 ath_txq_init(sc, &sc->sc_mcastq, HAL_NUM_TX_QUEUES+1); 416 /* NB: insure BK queue is the lowest priority h/w queue */ 417 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 418 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 419 ieee80211_wme_acnames[WME_AC_BK]); 420 error = EIO; 421 goto bad2; 422 } 423 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 424 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 425 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 426 /* 427 * Not enough hardware tx queues to properly do WME; 428 * just punt and assign them all to the same h/w queue. 429 * We could do a better job of this if, for example, 430 * we allocate queues when we switch from station to 431 * AP mode. 432 */ 433 if (sc->sc_ac2q[WME_AC_VI] != NULL) 434 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 435 if (sc->sc_ac2q[WME_AC_BE] != NULL) 436 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 437 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 438 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 439 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 440 } 441 442 /* 443 * Special case certain configurations. Note the 444 * CAB queue is handled by these specially so don't 445 * include them when checking the txq setup mask. 446 */ 447 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 448 case 0x01: 449 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 450 break; 451 case 0x0f: 452 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 453 break; 454 default: 455 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 456 break; 457 } 458 459 /* 460 * Setup rate control. Some rate control modules 461 * call back to change the anntena state so expose 462 * the necessary entry points. 463 * XXX maybe belongs in struct ath_ratectrl? 464 */ 465 sc->sc_setdefantenna = ath_setdefantenna; 466 sc->sc_rc = ath_rate_attach(sc); 467 if (sc->sc_rc == NULL) { 468 error = EIO; 469 goto bad2; 470 } 471 472 sc->sc_blinking = 0; 473 sc->sc_ledstate = 1; 474 sc->sc_ledon = 0; /* low true */ 475 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 476 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 477 /* 478 * Auto-enable soft led processing for IBM cards and for 479 * 5211 minipci cards. Users can also manually enable/disable 480 * support with a sysctl. 481 */ 482 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 483 if (sc->sc_softled) { 484 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 485 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 486 } 487 488 ifp->if_softc = sc; 489 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 490 ifp->if_start = ath_start; 491 ifp->if_watchdog = ath_watchdog; 492 ifp->if_ioctl = ath_ioctl; 493 ifp->if_init = ath_init; 494 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 495 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 496 IFQ_SET_READY(&ifp->if_snd); 497 498 ic->ic_ifp = ifp; 499 ic->ic_reset = ath_reset; 500 ic->ic_newassoc = ath_newassoc; 501 ic->ic_updateslot = ath_updateslot; 502 ic->ic_wme.wme_update = ath_wme_update; 503 /* XXX not right but it's not used anywhere important */ 504 ic->ic_phytype = IEEE80211_T_OFDM; 505 ic->ic_opmode = IEEE80211_M_STA; 506 ic->ic_caps = 507 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 508 | IEEE80211_C_HOSTAP /* hostap mode */ 509 | IEEE80211_C_MONITOR /* monitor mode */ 510 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 511 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 512 | IEEE80211_C_SHSLOT /* short slot time supported */ 513 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 514 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 515 | IEEE80211_C_TXFRAG /* handle tx frags */ 516 ; 517 /* 518 * Query the hal to figure out h/w crypto support. 519 */ 520 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 521 ic->ic_caps |= IEEE80211_C_WEP; 522 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 523 ic->ic_caps |= IEEE80211_C_AES; 524 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 525 ic->ic_caps |= IEEE80211_C_AES_CCM; 526 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 527 ic->ic_caps |= IEEE80211_C_CKIP; 528 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 529 ic->ic_caps |= IEEE80211_C_TKIP; 530 /* 531 * Check if h/w does the MIC and/or whether the 532 * separate key cache entries are required to 533 * handle both tx+rx MIC keys. 534 */ 535 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 536 ic->ic_caps |= IEEE80211_C_TKIPMIC; 537 /* 538 * If the h/w supports storing tx+rx MIC keys 539 * in one cache slot automatically enable use. 540 */ 541 if (ath_hal_hastkipsplit(ah) || 542 !ath_hal_settkipsplit(ah, AH_FALSE)) 543 sc->sc_splitmic = 1; 544 } 545 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 546 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 547 /* 548 * Mark key cache slots associated with global keys 549 * as in use. If we knew TKIP was not to be used we 550 * could leave the +32, +64, and +32+64 slots free. 551 */ 552 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 553 setbit(sc->sc_keymap, i); 554 setbit(sc->sc_keymap, i+64); 555 if (sc->sc_splitmic) { 556 setbit(sc->sc_keymap, i+32); 557 setbit(sc->sc_keymap, i+32+64); 558 } 559 } 560 /* 561 * TPC support can be done either with a global cap or 562 * per-packet support. The latter is not available on 563 * all parts. We're a bit pedantic here as all parts 564 * support a global cap. 565 */ 566 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 567 ic->ic_caps |= IEEE80211_C_TXPMGT; 568 569 /* 570 * Mark WME capability only if we have sufficient 571 * hardware queues to do proper priority scheduling. 572 */ 573 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 574 ic->ic_caps |= IEEE80211_C_WME; 575 /* 576 * Check for misc other capabilities. 577 */ 578 if (ath_hal_hasbursting(ah)) 579 ic->ic_caps |= IEEE80211_C_BURST; 580 if (ath_hal_hasfastframes(ah)) 581 ic->ic_caps |= IEEE80211_C_FF; 582 if (ath_hal_getwirelessmodes(ah, ath_countrycode) & (HAL_MODE_108G|HAL_MODE_TURBO)) 583 ic->ic_caps |= IEEE80211_C_TURBOP; 584 585 /* 586 * Indicate we need the 802.11 header padded to a 587 * 32-bit boundary for 4-address and QoS frames. 588 */ 589 ic->ic_flags |= IEEE80211_F_DATAPAD; 590 591 /* 592 * Query the hal about antenna support. 593 */ 594 sc->sc_defant = ath_hal_getdefantenna(ah); 595 596 /* 597 * Not all chips have the VEOL support we want to 598 * use with IBSS beacons; check here for it. 599 */ 600 sc->sc_hasveol = ath_hal_hasveol(ah); 601 602 /* get mac address from hardware */ 603 ath_hal_getmac(ah, ic->ic_myaddr); 604 605 /* call MI attach routine. */ 606 ieee80211_ifattach(ic); 607 sc->sc_opmode = ic->ic_opmode; 608 /* override default methods */ 609 ic->ic_node_alloc = ath_node_alloc; 610 sc->sc_node_free = ic->ic_node_free; 611 ic->ic_node_free = ath_node_free; 612 ic->ic_node_getrssi = ath_node_getrssi; 613 ic->ic_node_getsignal = ath_node_getsignal; 614 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 615 ic->ic_recv_mgmt = ath_recv_mgmt; 616 sc->sc_newstate = ic->ic_newstate; 617 ic->ic_newstate = ath_newstate; 618 ic->ic_scan_start = ath_scan_start; 619 ic->ic_scan_end = ath_scan_end; 620 ic->ic_set_channel = ath_set_channel; 621 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 622 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 623 ic->ic_crypto.cs_key_delete = ath_key_delete; 624 ic->ic_crypto.cs_key_set = ath_key_set; 625 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 626 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 627 ic->ic_raw_xmit = ath_raw_xmit; 628 /* complete initialization */ 629 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 630 631 ath_bpfattach(sc); 632 /* 633 * Setup dynamic sysctl's now that country code and 634 * regdomain are available from the hal. 635 */ 636 ath_sysctlattach(sc); 637 638 if (bootverbose) 639 ieee80211_announce(ic); 640 ath_announce(sc); 641 return 0; 642 bad2: 643 ath_tx_cleanup(sc); 644 ath_desc_free(sc); 645 bad: 646 if (ah) 647 ath_hal_detach(ah); 648 if (ifp != NULL) 649 if_free(ifp); 650 sc->sc_invalid = 1; 651 return error; 652 } 653 654 int 655 ath_detach(struct ath_softc *sc) 656 { 657 struct ifnet *ifp = sc->sc_ifp; 658 659 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 660 __func__, ifp->if_flags); 661 662 ath_stop(ifp); 663 bpfdetach(ifp); 664 /* 665 * NB: the order of these is important: 666 * o call the 802.11 layer before detaching the hal to 667 * insure callbacks into the driver to delete global 668 * key cache entries can be handled 669 * o reclaim the tx queue data structures after calling 670 * the 802.11 layer as we'll get called back to reclaim 671 * node state and potentially want to use them 672 * o to cleanup the tx queues the hal is called, so detach 673 * it last 674 * Other than that, it's straightforward... 675 */ 676 ieee80211_ifdetach(&sc->sc_ic); 677 #ifdef ATH_TX99_DIAG 678 if (sc->sc_tx99 != NULL) 679 sc->sc_tx99->detach(sc->sc_tx99); 680 #endif 681 taskqueue_free(sc->sc_tq); 682 ath_rate_detach(sc->sc_rc); 683 ath_desc_free(sc); 684 ath_tx_cleanup(sc); 685 ath_hal_detach(sc->sc_ah); 686 if_free(ifp); 687 688 return 0; 689 } 690 691 void 692 ath_suspend(struct ath_softc *sc) 693 { 694 struct ifnet *ifp = sc->sc_ifp; 695 696 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 697 __func__, ifp->if_flags); 698 699 ath_stop(ifp); 700 } 701 702 void 703 ath_resume(struct ath_softc *sc) 704 { 705 struct ifnet *ifp = sc->sc_ifp; 706 707 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 708 __func__, ifp->if_flags); 709 710 if (ifp->if_flags & IFF_UP) { 711 ath_init(sc); 712 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 713 ath_start(ifp); 714 } 715 if (sc->sc_softled) { 716 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 717 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 718 } 719 } 720 721 void 722 ath_shutdown(struct ath_softc *sc) 723 { 724 struct ifnet *ifp = sc->sc_ifp; 725 726 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 727 __func__, ifp->if_flags); 728 729 ath_stop(ifp); 730 } 731 732 /* 733 * Interrupt handler. Most of the actual processing is deferred. 734 */ 735 void 736 ath_intr(void *arg) 737 { 738 struct ath_softc *sc = arg; 739 struct ifnet *ifp = sc->sc_ifp; 740 struct ath_hal *ah = sc->sc_ah; 741 HAL_INT status; 742 743 if (sc->sc_invalid) { 744 /* 745 * The hardware is not ready/present, don't touch anything. 746 * Note this can happen early on if the IRQ is shared. 747 */ 748 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 749 return; 750 } 751 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 752 return; 753 if ((ifp->if_flags & IFF_UP) == 0 || 754 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 755 HAL_INT status; 756 757 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 758 __func__, ifp->if_flags); 759 ath_hal_getisr(ah, &status); /* clear ISR */ 760 ath_hal_intrset(ah, 0); /* disable further intr's */ 761 return; 762 } 763 /* 764 * Figure out the reason(s) for the interrupt. Note 765 * that the hal returns a pseudo-ISR that may include 766 * bits we haven't explicitly enabled so we mask the 767 * value to insure we only process bits we requested. 768 */ 769 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 770 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 771 status &= sc->sc_imask; /* discard unasked for bits */ 772 if (status & HAL_INT_FATAL) { 773 sc->sc_stats.ast_hardware++; 774 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 775 ath_fatal_proc(sc, 0); 776 } else if (status & HAL_INT_RXORN) { 777 sc->sc_stats.ast_rxorn++; 778 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 779 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxorntask); 780 } else { 781 if (status & HAL_INT_SWBA) { 782 /* 783 * Software beacon alert--time to send a beacon. 784 * Handle beacon transmission directly; deferring 785 * this is too slow to meet timing constraints 786 * under load. 787 */ 788 ath_beacon_proc(sc, 0); 789 } 790 if (status & HAL_INT_RXEOL) { 791 /* 792 * NB: the hardware should re-read the link when 793 * RXE bit is written, but it doesn't work at 794 * least on older hardware revs. 795 */ 796 sc->sc_stats.ast_rxeol++; 797 sc->sc_rxlink = NULL; 798 } 799 if (status & HAL_INT_TXURN) { 800 sc->sc_stats.ast_txurn++; 801 /* bump tx trigger level */ 802 ath_hal_updatetxtriglevel(ah, AH_TRUE); 803 } 804 if (status & HAL_INT_RX) 805 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 806 if (status & HAL_INT_TX) 807 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 808 if (status & HAL_INT_BMISS) { 809 sc->sc_stats.ast_bmiss++; 810 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 811 } 812 if (status & HAL_INT_MIB) { 813 sc->sc_stats.ast_mib++; 814 /* 815 * Disable interrupts until we service the MIB 816 * interrupt; otherwise it will continue to fire. 817 */ 818 ath_hal_intrset(ah, 0); 819 /* 820 * Let the hal handle the event. We assume it will 821 * clear whatever condition caused the interrupt. 822 */ 823 ath_hal_mibevent(ah, &sc->sc_halstats); 824 ath_hal_intrset(ah, sc->sc_imask); 825 } 826 } 827 } 828 829 static void 830 ath_fatal_proc(void *arg, int pending) 831 { 832 struct ath_softc *sc = arg; 833 struct ifnet *ifp = sc->sc_ifp; 834 u_int32_t *state; 835 u_int32_t len; 836 void *sp; 837 838 if_printf(ifp, "hardware error; resetting\n"); 839 /* 840 * Fatal errors are unrecoverable. Typically these 841 * are caused by DMA errors. Collect h/w state from 842 * the hal so we can diagnose what's going on. 843 */ 844 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 845 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 846 state = sp; 847 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 848 state[0], state[1] , state[2], state[3], 849 state[4], state[5]); 850 } 851 ath_reset(ifp); 852 } 853 854 static void 855 ath_rxorn_proc(void *arg, int pending) 856 { 857 struct ath_softc *sc = arg; 858 struct ifnet *ifp = sc->sc_ifp; 859 860 if_printf(ifp, "rx FIFO overrun; resetting\n"); 861 ath_reset(ifp); 862 } 863 864 static void 865 ath_bmiss_proc(void *arg, int pending) 866 { 867 struct ath_softc *sc = arg; 868 struct ieee80211com *ic = &sc->sc_ic; 869 870 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 871 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 872 ("unexpect operating mode %u", ic->ic_opmode)); 873 if (ic->ic_state == IEEE80211_S_RUN) { 874 u_int64_t lastrx = sc->sc_lastrx; 875 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 876 u_int bmisstimeout = 877 ic->ic_bmissthreshold * ic->ic_bss->ni_intval * 1024; 878 879 DPRINTF(sc, ATH_DEBUG_BEACON, 880 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 881 __func__, (unsigned long long) tsf, 882 (unsigned long long)(tsf - lastrx), 883 (unsigned long long) lastrx, bmisstimeout); 884 /* 885 * Workaround phantom bmiss interrupts by sanity-checking 886 * the time of our last rx'd frame. If it is within the 887 * beacon miss interval then ignore the interrupt. If it's 888 * truly a bmiss we'll get another interrupt soon and that'll 889 * be dispatched up for processing. 890 */ 891 if (tsf - lastrx > bmisstimeout) { 892 NET_LOCK_GIANT(); 893 ieee80211_beacon_miss(ic); 894 NET_UNLOCK_GIANT(); 895 } else 896 sc->sc_stats.ast_bmiss_phantom++; 897 } 898 } 899 900 /* 901 * Convert net80211 channel to a HAL channel with the flags 902 * constrained to reflect the current operating mode and 903 * the frequency possibly mapped for GSM channels. 904 */ 905 static void 906 ath_mapchan(HAL_CHANNEL *hc, const struct ieee80211_channel *chan) 907 { 908 #define N(a) (sizeof(a) / sizeof(a[0])) 909 static const u_int modeflags[IEEE80211_MODE_MAX] = { 910 0, /* IEEE80211_MODE_AUTO */ 911 CHANNEL_A, /* IEEE80211_MODE_11A */ 912 CHANNEL_B, /* IEEE80211_MODE_11B */ 913 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 914 0, /* IEEE80211_MODE_FH */ 915 CHANNEL_108A, /* IEEE80211_MODE_TURBO_A */ 916 CHANNEL_108G, /* IEEE80211_MODE_TURBO_G */ 917 CHANNEL_ST, /* IEEE80211_MODE_STURBO_A */ 918 CHANNEL_A, /* IEEE80211_MODE_11NA */ 919 CHANNEL_PUREG, /* IEEE80211_MODE_11NG */ 920 }; 921 enum ieee80211_phymode mode = ieee80211_chan2mode(chan); 922 923 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 924 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 925 hc->channelFlags = modeflags[mode]; 926 if (IEEE80211_IS_CHAN_HALF(chan)) 927 hc->channelFlags |= CHANNEL_HALF; 928 if (IEEE80211_IS_CHAN_QUARTER(chan)) 929 hc->channelFlags |= CHANNEL_QUARTER; 930 if (IEEE80211_IS_CHAN_HT20(chan)) 931 hc->channelFlags |= CHANNEL_HT20; 932 if (IEEE80211_IS_CHAN_HT40D(chan)) 933 hc->channelFlags |= CHANNEL_HT40MINUS; 934 if (IEEE80211_IS_CHAN_HT40U(chan)) 935 hc->channelFlags |= CHANNEL_HT40PLUS; 936 937 hc->channel = IEEE80211_IS_CHAN_GSM(chan) ? 938 2422 + (922 - chan->ic_freq) : chan->ic_freq; 939 #undef N 940 } 941 942 static void 943 ath_init(void *arg) 944 { 945 struct ath_softc *sc = (struct ath_softc *) arg; 946 struct ieee80211com *ic = &sc->sc_ic; 947 struct ifnet *ifp = sc->sc_ifp; 948 struct ath_hal *ah = sc->sc_ah; 949 HAL_STATUS status; 950 951 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 952 __func__, ifp->if_flags); 953 954 ATH_LOCK(sc); 955 /* 956 * Stop anything previously setup. This is safe 957 * whether this is the first time through or not. 958 */ 959 ath_stop_locked(ifp); 960 961 /* 962 * The basic interface to setting the hardware in a good 963 * state is ``reset''. On return the hardware is known to 964 * be powered up and with interrupts disabled. This must 965 * be followed by initialization of the appropriate bits 966 * and then setup of the interrupt mask. 967 */ 968 ath_mapchan(&sc->sc_curchan, ic->ic_curchan); 969 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 970 if_printf(ifp, "unable to reset hardware; hal status %u\n", 971 status); 972 goto done; 973 } 974 975 /* 976 * This is needed only to setup initial state 977 * but it's best done after a reset. 978 */ 979 ath_update_txpow(sc); 980 /* 981 * Likewise this is set during reset so update 982 * state cached in the driver. 983 */ 984 sc->sc_diversity = ath_hal_getdiversity(ah); 985 sc->sc_calinterval = 1; 986 sc->sc_caltries = 0; 987 988 /* 989 * Setup the hardware after reset: the key cache 990 * is filled as needed and the receive engine is 991 * set going. Frame transmit is handled entirely 992 * in the frame output path; there's nothing to do 993 * here except setup the interrupt mask. 994 */ 995 if (ath_startrecv(sc) != 0) { 996 if_printf(ifp, "unable to start recv logic\n"); 997 goto done; 998 } 999 1000 /* 1001 * Enable interrupts. 1002 */ 1003 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1004 | HAL_INT_RXEOL | HAL_INT_RXORN 1005 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1006 /* 1007 * Enable MIB interrupts when there are hardware phy counters. 1008 * Note we only do this (at the moment) for station mode. 1009 */ 1010 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1011 sc->sc_imask |= HAL_INT_MIB; 1012 ath_hal_intrset(ah, sc->sc_imask); 1013 1014 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1015 ic->ic_state = IEEE80211_S_INIT; 1016 1017 /* 1018 * The hardware should be ready to go now so it's safe 1019 * to kick the 802.11 state machine as it's likely to 1020 * immediately call back to us to send mgmt frames. 1021 */ 1022 ath_chan_change(sc, ic->ic_curchan); 1023 #ifdef ATH_TX99_DIAG 1024 if (sc->sc_tx99 != NULL) 1025 sc->sc_tx99->start(sc->sc_tx99); 1026 else 1027 #endif 1028 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1029 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 1030 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1031 } else 1032 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1033 done: 1034 ATH_UNLOCK(sc); 1035 } 1036 1037 static void 1038 ath_stop_locked(struct ifnet *ifp) 1039 { 1040 struct ath_softc *sc = ifp->if_softc; 1041 struct ieee80211com *ic = &sc->sc_ic; 1042 struct ath_hal *ah = sc->sc_ah; 1043 1044 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1045 __func__, sc->sc_invalid, ifp->if_flags); 1046 1047 ATH_LOCK_ASSERT(sc); 1048 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1049 /* 1050 * Shutdown the hardware and driver: 1051 * reset 802.11 state machine 1052 * turn off timers 1053 * disable interrupts 1054 * turn off the radio 1055 * clear transmit machinery 1056 * clear receive machinery 1057 * drain and release tx queues 1058 * reclaim beacon resources 1059 * power down hardware 1060 * 1061 * Note that some of this work is not possible if the 1062 * hardware is gone (invalid). 1063 */ 1064 #ifdef ATH_TX99_DIAG 1065 if (sc->sc_tx99 != NULL) 1066 sc->sc_tx99->stop(sc->sc_tx99); 1067 #endif 1068 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1069 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1070 ifp->if_timer = 0; 1071 if (!sc->sc_invalid) { 1072 if (sc->sc_softled) { 1073 callout_stop(&sc->sc_ledtimer); 1074 ath_hal_gpioset(ah, sc->sc_ledpin, 1075 !sc->sc_ledon); 1076 sc->sc_blinking = 0; 1077 } 1078 ath_hal_intrset(ah, 0); 1079 } 1080 ath_draintxq(sc); 1081 if (!sc->sc_invalid) { 1082 ath_stoprecv(sc); 1083 ath_hal_phydisable(ah); 1084 } else 1085 sc->sc_rxlink = NULL; 1086 IFQ_DRV_PURGE(&ifp->if_snd); 1087 ath_beacon_free(sc); 1088 } 1089 } 1090 1091 static void 1092 ath_stop(struct ifnet *ifp) 1093 { 1094 struct ath_softc *sc = ifp->if_softc; 1095 1096 ATH_LOCK(sc); 1097 ath_stop_locked(ifp); 1098 if (!sc->sc_invalid) { 1099 /* 1100 * Set the chip in full sleep mode. Note that we are 1101 * careful to do this only when bringing the interface 1102 * completely to a stop. When the chip is in this state 1103 * it must be carefully woken up or references to 1104 * registers in the PCI clock domain may freeze the bus 1105 * (and system). This varies by chip and is mostly an 1106 * issue with newer parts that go to sleep more quickly. 1107 */ 1108 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 1109 } 1110 ATH_UNLOCK(sc); 1111 } 1112 1113 /* 1114 * Reset the hardware w/o losing operational state. This is 1115 * basically a more efficient way of doing ath_stop, ath_init, 1116 * followed by state transitions to the current 802.11 1117 * operational state. Used to recover from various errors and 1118 * to reset or reload hardware state. 1119 */ 1120 static int 1121 ath_reset(struct ifnet *ifp) 1122 { 1123 struct ath_softc *sc = ifp->if_softc; 1124 struct ieee80211com *ic = &sc->sc_ic; 1125 struct ath_hal *ah = sc->sc_ah; 1126 HAL_STATUS status; 1127 1128 /* 1129 * Convert to a HAL channel description with the flags 1130 * constrained to reflect the current operating mode. 1131 */ 1132 ath_mapchan(&sc->sc_curchan, ic->ic_curchan); 1133 1134 ath_hal_intrset(ah, 0); /* disable interrupts */ 1135 ath_draintxq(sc); /* stop xmit side */ 1136 ath_stoprecv(sc); /* stop recv side */ 1137 /* NB: indicate channel change so we do a full reset */ 1138 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1139 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1140 __func__, status); 1141 ath_update_txpow(sc); /* update tx power state */ 1142 sc->sc_diversity = ath_hal_getdiversity(ah); 1143 sc->sc_calinterval = 1; 1144 sc->sc_caltries = 0; 1145 if (ath_startrecv(sc) != 0) /* restart recv */ 1146 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1147 /* 1148 * We may be doing a reset in response to an ioctl 1149 * that changes the channel so update any state that 1150 * might change as a result. 1151 */ 1152 ath_chan_change(sc, ic->ic_curchan); 1153 if (ic->ic_state == IEEE80211_S_RUN) 1154 ath_beacon_config(sc); /* restart beacons */ 1155 ath_hal_intrset(ah, sc->sc_imask); 1156 1157 ath_start(ifp); /* restart xmit */ 1158 return 0; 1159 } 1160 1161 static int 1162 ath_ff_always(struct ath_txq *txq, struct ath_buf *bf) 1163 { 1164 return 0; 1165 } 1166 1167 #if 0 1168 static int 1169 ath_ff_ageflushtestdone(struct ath_txq *txq, struct ath_buf *bf) 1170 { 1171 return (txq->axq_curage - bf->bf_age) < ATH_FF_STAGEMAX; 1172 } 1173 #endif 1174 1175 /* 1176 * Flush FF staging queue. 1177 */ 1178 static void 1179 ath_ff_stageq_flush(struct ath_softc *sc, struct ath_txq *txq, 1180 int (*ath_ff_flushdonetest)(struct ath_txq *txq, struct ath_buf *bf)) 1181 { 1182 struct ath_buf *bf; 1183 struct ieee80211_node *ni; 1184 int pktlen, pri; 1185 1186 for (;;) { 1187 ATH_TXQ_LOCK(txq); 1188 /* 1189 * Go from the back (oldest) to front so we can 1190 * stop early based on the age of the entry. 1191 */ 1192 bf = TAILQ_LAST(&txq->axq_stageq, axq_headtype); 1193 if (bf == NULL || ath_ff_flushdonetest(txq, bf)) { 1194 ATH_TXQ_UNLOCK(txq); 1195 break; 1196 } 1197 1198 ni = bf->bf_node; 1199 pri = M_WME_GETAC(bf->bf_m); 1200 KASSERT(ATH_NODE(ni)->an_ff_buf[pri], 1201 ("no bf on staging queue %p", bf)); 1202 ATH_NODE(ni)->an_ff_buf[pri] = NULL; 1203 TAILQ_REMOVE(&txq->axq_stageq, bf, bf_stagelist); 1204 1205 ATH_TXQ_UNLOCK(txq); 1206 1207 DPRINTF(sc, ATH_DEBUG_FF, "%s: flush frame, age %u\n", 1208 __func__, bf->bf_age); 1209 1210 sc->sc_stats.ast_ff_flush++; 1211 1212 /* encap and xmit */ 1213 bf->bf_m = ieee80211_encap(&sc->sc_ic, bf->bf_m, ni); 1214 if (bf->bf_m == NULL) { 1215 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1216 "%s: discard, encapsulation failure\n", 1217 __func__); 1218 sc->sc_stats.ast_tx_encap++; 1219 goto bad; 1220 } 1221 pktlen = bf->bf_m->m_pkthdr.len; /* NB: don't reference below */ 1222 if (ath_tx_start(sc, ni, bf, bf->bf_m) == 0) { 1223 #if 0 /*XXX*/ 1224 ifp->if_opackets++; 1225 #endif 1226 continue; 1227 } 1228 bad: 1229 if (ni != NULL) 1230 ieee80211_free_node(ni); 1231 bf->bf_node = NULL; 1232 if (bf->bf_m != NULL) { 1233 m_freem(bf->bf_m); 1234 bf->bf_m = NULL; 1235 } 1236 1237 ATH_TXBUF_LOCK(sc); 1238 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1239 ATH_TXBUF_UNLOCK(sc); 1240 } 1241 } 1242 1243 static __inline u_int32_t 1244 ath_ff_approx_txtime(struct ath_softc *sc, struct ath_node *an, struct mbuf *m) 1245 { 1246 u_int32_t framelen; 1247 struct ath_buf *bf; 1248 1249 /* 1250 * Approximate the frame length to be transmitted. A swag to add 1251 * the following maximal values to the skb payload: 1252 * - 32: 802.11 encap + CRC 1253 * - 24: encryption overhead (if wep bit) 1254 * - 4 + 6: fast-frame header and padding 1255 * - 16: 2 LLC FF tunnel headers 1256 * - 14: 1 802.3 FF tunnel header (skb already accounts for 2nd) 1257 */ 1258 framelen = m->m_pkthdr.len + 32 + 4 + 6 + 16 + 14; 1259 if (sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) 1260 framelen += 24; 1261 bf = an->an_ff_buf[M_WME_GETAC(m)]; 1262 if (bf != NULL) 1263 framelen += bf->bf_m->m_pkthdr.len; 1264 return ath_hal_computetxtime(sc->sc_ah, sc->sc_currates, framelen, 1265 sc->sc_lastdatarix, AH_FALSE); 1266 } 1267 1268 /* 1269 * Determine if a data frame may be aggregated via ff tunnelling. 1270 * Note the caller is responsible for checking if the destination 1271 * supports fast frames. 1272 * 1273 * NB: allowing EAPOL frames to be aggregated with other unicast traffic. 1274 * Do 802.1x EAPOL frames proceed in the clear? Then they couldn't 1275 * be aggregated with other types of frames when encryption is on? 1276 * 1277 * NB: assumes lock on an_ff_buf effectively held by txq lock mechanism. 1278 */ 1279 static __inline int 1280 ath_ff_can_aggregate(struct ath_softc *sc, 1281 struct ath_node *an, struct mbuf *m, int *flushq) 1282 { 1283 struct ieee80211com *ic = &sc->sc_ic; 1284 struct ath_txq *txq; 1285 u_int32_t txoplimit; 1286 u_int pri; 1287 1288 *flushq = 0; 1289 1290 /* 1291 * If there is no frame to combine with and the txq has 1292 * fewer frames than the minimum required; then do not 1293 * attempt to aggregate this frame. 1294 */ 1295 pri = M_WME_GETAC(m); 1296 txq = sc->sc_ac2q[pri]; 1297 if (an->an_ff_buf[pri] == NULL && txq->axq_depth < sc->sc_fftxqmin) 1298 return 0; 1299 /* 1300 * When not in station mode never aggregate a multicast 1301 * frame; this insures, for example, that a combined frame 1302 * does not require multiple encryption keys when using 1303 * 802.1x/WPA. 1304 */ 1305 if (ic->ic_opmode != IEEE80211_M_STA && 1306 ETHER_IS_MULTICAST(mtod(m, struct ether_header *)->ether_dhost)) 1307 return 0; 1308 /* 1309 * Consult the max bursting interval to insure a combined 1310 * frame fits within the TxOp window. 1311 */ 1312 txoplimit = IEEE80211_TXOP_TO_US( 1313 ic->ic_wme.wme_chanParams.cap_wmeParams[pri].wmep_txopLimit); 1314 if (txoplimit != 0 && ath_ff_approx_txtime(sc, an, m) > txoplimit) { 1315 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1316 "%s: FF TxOp violation\n", __func__); 1317 if (an->an_ff_buf[pri] != NULL) 1318 *flushq = 1; 1319 return 0; 1320 } 1321 return 1; /* try to aggregate */ 1322 } 1323 1324 /* 1325 * Check if the supplied frame can be partnered with an existing 1326 * or pending frame. Return a reference to any frame that should be 1327 * sent on return; otherwise return NULL. 1328 */ 1329 static struct mbuf * 1330 ath_ff_check(struct ath_softc *sc, struct ath_txq *txq, 1331 struct ath_buf *bf, struct mbuf *m, struct ieee80211_node *ni) 1332 { 1333 struct ieee80211com *ic = ni->ni_ic; 1334 struct ath_node *an = ATH_NODE(ni); 1335 struct ath_buf *bfstaged; 1336 int ff_flush, pri; 1337 1338 /* 1339 * Check if the supplied frame can be aggregated. 1340 * 1341 * NB: we use the txq lock to protect references to 1342 * an->an_ff_txbuf in ath_ff_can_aggregate(). 1343 */ 1344 ATH_TXQ_LOCK(txq); 1345 pri = M_WME_GETAC(m); 1346 if (ath_ff_can_aggregate(sc, an, m, &ff_flush)) { 1347 struct ath_buf *bfstaged = an->an_ff_buf[pri]; 1348 if (bfstaged != NULL) { 1349 /* 1350 * A frame is available for partnering; remove 1351 * it, chain it to this one, and encapsulate. 1352 */ 1353 an->an_ff_buf[pri] = NULL; 1354 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist); 1355 ATH_TXQ_UNLOCK(txq); 1356 1357 /* 1358 * Chain mbufs and add FF magic. 1359 */ 1360 DPRINTF(sc, ATH_DEBUG_FF, 1361 "[%s] aggregate fast-frame, age %u\n", 1362 ether_sprintf(ni->ni_macaddr), txq->axq_curage); 1363 m->m_nextpkt = NULL; 1364 bfstaged->bf_m->m_nextpkt = m; 1365 m = bfstaged->bf_m; 1366 bfstaged->bf_m = NULL; 1367 m->m_flags |= M_FF; 1368 /* 1369 * Release the node reference held while 1370 * the packet sat on an_ff_buf[] 1371 */ 1372 bfstaged->bf_node = NULL; 1373 ieee80211_free_node(ni); 1374 1375 /* 1376 * Return bfstaged to the free list. 1377 */ 1378 ATH_TXBUF_LOCK(sc); 1379 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bfstaged, bf_list); 1380 ATH_TXBUF_UNLOCK(sc); 1381 1382 return m; /* ready to go */ 1383 } else { 1384 /* 1385 * No frame available, queue this frame to wait 1386 * for a partner. Note that we hold the buffer 1387 * and a reference to the node; we need the 1388 * buffer in particular so we're certain we 1389 * can flush the frame at a later time. 1390 */ 1391 DPRINTF(sc, ATH_DEBUG_FF, 1392 "[%s] stage fast-frame, age %u\n", 1393 ether_sprintf(ni->ni_macaddr), txq->axq_curage); 1394 1395 bf->bf_m = m; 1396 bf->bf_node = ni; /* NB: held reference */ 1397 bf->bf_age = txq->axq_curage; 1398 an->an_ff_buf[pri] = bf; 1399 TAILQ_INSERT_HEAD(&txq->axq_stageq, bf, bf_stagelist); 1400 ATH_TXQ_UNLOCK(txq); 1401 1402 return NULL; /* consumed */ 1403 } 1404 } 1405 /* 1406 * Frame could not be aggregated, it needs to be returned 1407 * to the caller for immediate transmission. In addition 1408 * we check if we should first flush a frame from the 1409 * staging queue before sending this one. 1410 * 1411 * NB: ath_ff_can_aggregate only marks ff_flush if a frame 1412 * is present to flush. 1413 */ 1414 if (ff_flush) { 1415 int pktlen; 1416 1417 bfstaged = an->an_ff_buf[pri]; 1418 an->an_ff_buf[pri] = NULL; 1419 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist); 1420 ATH_TXQ_UNLOCK(txq); 1421 1422 DPRINTF(sc, ATH_DEBUG_FF, "[%s] flush staged frame\n", 1423 ether_sprintf(an->an_node.ni_macaddr)); 1424 1425 /* encap and xmit */ 1426 bfstaged->bf_m = ieee80211_encap(ic, bfstaged->bf_m, ni); 1427 if (bfstaged->bf_m == NULL) { 1428 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1429 "%s: discard, encap failure\n", __func__); 1430 sc->sc_stats.ast_tx_encap++; 1431 goto ff_flushbad; 1432 } 1433 pktlen = bfstaged->bf_m->m_pkthdr.len; 1434 if (ath_tx_start(sc, ni, bfstaged, bfstaged->bf_m)) { 1435 DPRINTF(sc, ATH_DEBUG_XMIT, 1436 "%s: discard, xmit failure\n", __func__); 1437 ff_flushbad: 1438 /* 1439 * Unable to transmit frame that was on the staging 1440 * queue. Reclaim the node reference and other 1441 * resources. 1442 */ 1443 if (ni != NULL) 1444 ieee80211_free_node(ni); 1445 bfstaged->bf_node = NULL; 1446 if (bfstaged->bf_m != NULL) { 1447 m_freem(bfstaged->bf_m); 1448 bfstaged->bf_m = NULL; 1449 } 1450 1451 ATH_TXBUF_LOCK(sc); 1452 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bfstaged, bf_list); 1453 ATH_TXBUF_UNLOCK(sc); 1454 } else { 1455 #if 0 1456 ifp->if_opackets++; 1457 #endif 1458 } 1459 } else { 1460 if (an->an_ff_buf[pri] != NULL) { 1461 /* 1462 * XXX: out-of-order condition only occurs for AP 1463 * mode and multicast. There may be no valid way 1464 * to get this condition. 1465 */ 1466 DPRINTF(sc, ATH_DEBUG_FF, "[%s] out-of-order frame\n", 1467 ether_sprintf(an->an_node.ni_macaddr)); 1468 /* XXX stat */ 1469 } 1470 ATH_TXQ_UNLOCK(txq); 1471 } 1472 return m; 1473 } 1474 1475 /* 1476 * Cleanup driver resources when we run out of buffers 1477 * while processing fragments; return the tx buffers 1478 * allocated and drop node references. 1479 */ 1480 static void 1481 ath_txfrag_cleanup(struct ath_softc *sc, 1482 ath_bufhead *frags, struct ieee80211_node *ni) 1483 { 1484 struct ath_buf *bf, *next; 1485 1486 ATH_TXBUF_LOCK_ASSERT(sc); 1487 1488 STAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 1489 /* NB: bf assumed clean */ 1490 STAILQ_REMOVE_HEAD(frags, bf_list); 1491 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1492 ieee80211_node_decref(ni); 1493 } 1494 } 1495 1496 /* 1497 * Setup xmit of a fragmented frame. Allocate a buffer 1498 * for each frag and bump the node reference count to 1499 * reflect the held reference to be setup by ath_tx_start. 1500 */ 1501 static int 1502 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1503 struct mbuf *m0, struct ieee80211_node *ni) 1504 { 1505 struct mbuf *m; 1506 struct ath_buf *bf; 1507 1508 ATH_TXBUF_LOCK(sc); 1509 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1510 bf = STAILQ_FIRST(&sc->sc_txbuf); 1511 if (bf == NULL) { /* out of buffers, cleanup */ 1512 ath_txfrag_cleanup(sc, frags, ni); 1513 break; 1514 } 1515 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1516 ieee80211_node_incref(ni); 1517 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1518 } 1519 ATH_TXBUF_UNLOCK(sc); 1520 1521 return !STAILQ_EMPTY(frags); 1522 } 1523 1524 static void 1525 ath_start(struct ifnet *ifp) 1526 { 1527 struct ath_softc *sc = ifp->if_softc; 1528 struct ath_hal *ah = sc->sc_ah; 1529 struct ieee80211com *ic = &sc->sc_ic; 1530 struct ieee80211_node *ni; 1531 struct ath_buf *bf; 1532 struct mbuf *m, *next; 1533 struct ieee80211_frame *wh; 1534 struct ether_header *eh; 1535 struct ath_txq *txq; 1536 ath_bufhead frags; 1537 int pri; 1538 1539 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 1540 return; 1541 for (;;) { 1542 /* 1543 * Grab a TX buffer and associated resources. 1544 */ 1545 ATH_TXBUF_LOCK(sc); 1546 bf = STAILQ_FIRST(&sc->sc_txbuf); 1547 if (bf != NULL) 1548 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1549 ATH_TXBUF_UNLOCK(sc); 1550 if (bf == NULL) { 1551 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1552 __func__); 1553 sc->sc_stats.ast_tx_qstop++; 1554 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1555 break; 1556 } 1557 /* 1558 * Poll the management queue for frames; they 1559 * have priority over normal data frames. 1560 */ 1561 IF_DEQUEUE(&ic->ic_mgtq, m); 1562 if (m == NULL) { 1563 /* 1564 * No data frames go out unless we're associated. 1565 */ 1566 if (ic->ic_state != IEEE80211_S_RUN) { 1567 DPRINTF(sc, ATH_DEBUG_XMIT, 1568 "%s: discard data packet, state %s\n", 1569 __func__, 1570 ieee80211_state_name[ic->ic_state]); 1571 sc->sc_stats.ast_tx_discard++; 1572 ATH_TXBUF_LOCK(sc); 1573 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1574 ATH_TXBUF_UNLOCK(sc); 1575 break; 1576 } 1577 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1578 if (m == NULL) { 1579 ATH_TXBUF_LOCK(sc); 1580 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1581 ATH_TXBUF_UNLOCK(sc); 1582 break; 1583 } 1584 STAILQ_INIT(&frags); 1585 /* 1586 * Find the node for the destination so we can do 1587 * things like power save and fast frames aggregation. 1588 */ 1589 if (m->m_len < sizeof(struct ether_header) && 1590 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1591 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1592 ni = NULL; 1593 goto bad; 1594 } 1595 eh = mtod(m, struct ether_header *); 1596 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1597 if (ni == NULL) { 1598 /* NB: ieee80211_find_txnode does stat+msg */ 1599 m_freem(m); 1600 goto bad; 1601 } 1602 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1603 (m->m_flags & M_PWR_SAV) == 0) { 1604 /* 1605 * Station in power save mode; pass the frame 1606 * to the 802.11 layer and continue. We'll get 1607 * the frame back when the time is right. 1608 */ 1609 ieee80211_pwrsave(ni, m); 1610 /* 1611 * If we're in power save mode 'cuz of a bg 1612 * scan cancel it so the traffic can flow. 1613 * The packet we just queued will automatically 1614 * get sent when we drop out of power save. 1615 * XXX locking 1616 */ 1617 if (ic->ic_flags & IEEE80211_F_SCAN) 1618 ieee80211_cancel_scan(ic); 1619 goto reclaim; 1620 } 1621 /* calculate priority so we can find the tx queue */ 1622 if (ieee80211_classify(ic, m, ni)) { 1623 DPRINTF(sc, ATH_DEBUG_XMIT, 1624 "%s: discard, classification failure\n", 1625 __func__); 1626 m_freem(m); 1627 goto bad; 1628 } 1629 pri = M_WME_GETAC(m); 1630 txq = sc->sc_ac2q[pri]; 1631 if (ni->ni_ath_flags & IEEE80211_NODE_FF) { 1632 /* 1633 * Check queue length; if too deep drop this 1634 * frame (tail drop considered good). 1635 */ 1636 if (txq->axq_depth >= sc->sc_fftxqmax) { 1637 DPRINTF(sc, ATH_DEBUG_FF, 1638 "[%s] tail drop on q %u depth %u\n", 1639 ether_sprintf(ni->ni_macaddr), 1640 txq->axq_qnum, txq->axq_depth); 1641 sc->sc_stats.ast_tx_qfull++; 1642 m_freem(m); 1643 goto reclaim; 1644 } 1645 m = ath_ff_check(sc, txq, bf, m, ni); 1646 if (m == NULL) { 1647 /* NB: ni ref & bf held on stageq */ 1648 continue; 1649 } 1650 } 1651 ifp->if_opackets++; 1652 BPF_MTAP(ifp, m); 1653 /* 1654 * Encapsulate the packet in prep for transmission. 1655 */ 1656 m = ieee80211_encap(ic, m, ni); 1657 if (m == NULL) { 1658 DPRINTF(sc, ATH_DEBUG_XMIT, 1659 "%s: encapsulation failure\n", 1660 __func__); 1661 sc->sc_stats.ast_tx_encap++; 1662 goto bad; 1663 } 1664 /* 1665 * Check for fragmentation. If this frame 1666 * has been broken up verify we have enough 1667 * buffers to send all the fragments so all 1668 * go out or none... 1669 */ 1670 if ((m->m_flags & M_FRAG) && 1671 !ath_txfrag_setup(sc, &frags, m, ni)) { 1672 DPRINTF(sc, ATH_DEBUG_XMIT, 1673 "%s: out of txfrag buffers\n", __func__); 1674 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1675 ath_freetx(m); 1676 goto bad; 1677 } 1678 } else { 1679 /* 1680 * Hack! The referenced node pointer is in the 1681 * rcvif field of the packet header. This is 1682 * placed there by ieee80211_mgmt_output because 1683 * we need to hold the reference with the frame 1684 * and there's no other way (other than packet 1685 * tags which we consider too expensive to use) 1686 * to pass it along. 1687 */ 1688 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1689 m->m_pkthdr.rcvif = NULL; 1690 1691 wh = mtod(m, struct ieee80211_frame *); 1692 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1693 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1694 /* fill time stamp */ 1695 u_int64_t tsf; 1696 u_int32_t *tstamp; 1697 1698 tsf = ath_hal_gettsf64(ah); 1699 /* XXX: adjust 100us delay to xmit */ 1700 tsf += 100; 1701 tstamp = (u_int32_t *)&wh[1]; 1702 tstamp[0] = htole32(tsf & 0xffffffff); 1703 tstamp[1] = htole32(tsf >> 32); 1704 } 1705 sc->sc_stats.ast_tx_mgmt++; 1706 } 1707 1708 nextfrag: 1709 /* 1710 * Pass the frame to the h/w for transmission. 1711 * Fragmented frames have each frag chained together 1712 * with m_nextpkt. We know there are sufficient ath_buf's 1713 * to send all the frags because of work done by 1714 * ath_txfrag_setup. We leave m_nextpkt set while 1715 * calling ath_tx_start so it can use it to extend the 1716 * the tx duration to cover the subsequent frag and 1717 * so it can reclaim all the mbufs in case of an error; 1718 * ath_tx_start clears m_nextpkt once it commits to 1719 * handing the frame to the hardware. 1720 */ 1721 next = m->m_nextpkt; 1722 if (ath_tx_start(sc, ni, bf, m)) { 1723 bad: 1724 ifp->if_oerrors++; 1725 reclaim: 1726 bf->bf_m = NULL; 1727 bf->bf_node = NULL; 1728 ATH_TXBUF_LOCK(sc); 1729 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1730 ath_txfrag_cleanup(sc, &frags, ni); 1731 ATH_TXBUF_UNLOCK(sc); 1732 if (ni != NULL) 1733 ieee80211_free_node(ni); 1734 continue; 1735 } 1736 if (next != NULL) { 1737 /* 1738 * Beware of state changing between frags. 1739 * XXX check sta power-save state? 1740 */ 1741 if (ic->ic_state != IEEE80211_S_RUN) { 1742 DPRINTF(sc, ATH_DEBUG_XMIT, 1743 "%s: flush fragmented packet, state %s\n", 1744 __func__, 1745 ieee80211_state_name[ic->ic_state]); 1746 ath_freetx(next); 1747 goto reclaim; 1748 } 1749 m = next; 1750 bf = STAILQ_FIRST(&frags); 1751 KASSERT(bf != NULL, ("no buf for txfrag")); 1752 STAILQ_REMOVE_HEAD(&frags, bf_list); 1753 goto nextfrag; 1754 } 1755 1756 ifp->if_timer = 5; 1757 #if 0 1758 /* 1759 * Flush stale frames from the fast-frame staging queue. 1760 */ 1761 if (ic->ic_opmode != IEEE80211_M_STA) 1762 ath_ff_stageq_flush(sc, txq, ath_ff_ageflushtestdone); 1763 #endif 1764 } 1765 } 1766 1767 static int 1768 ath_media_change(struct ifnet *ifp) 1769 { 1770 #define IS_UP(ifp) \ 1771 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1772 int error; 1773 1774 error = ieee80211_media_change(ifp); 1775 if (error == ENETRESET) { 1776 struct ath_softc *sc = ifp->if_softc; 1777 struct ieee80211com *ic = &sc->sc_ic; 1778 1779 if (ic->ic_opmode == IEEE80211_M_AHDEMO) { 1780 /* 1781 * Adhoc demo mode is just ibss mode w/o beacons 1782 * (mostly). The hal knows nothing about it; 1783 * tell it we're operating in ibss mode. 1784 */ 1785 sc->sc_opmode = HAL_M_IBSS; 1786 } else 1787 sc->sc_opmode = ic->ic_opmode; 1788 if (IS_UP(ifp)) 1789 ath_init(sc); /* XXX lose error */ 1790 error = 0; 1791 } 1792 return error; 1793 #undef IS_UP 1794 } 1795 1796 #ifdef ATH_DEBUG 1797 static void 1798 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 1799 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1800 { 1801 static const char *ciphers[] = { 1802 "WEP", 1803 "AES-OCB", 1804 "AES-CCM", 1805 "CKIP", 1806 "TKIP", 1807 "CLR", 1808 }; 1809 int i, n; 1810 1811 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1812 for (i = 0, n = hk->kv_len; i < n; i++) 1813 printf("%02x", hk->kv_val[i]); 1814 printf(" mac %s", ether_sprintf(mac)); 1815 if (hk->kv_type == HAL_CIPHER_TKIP) { 1816 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 1817 for (i = 0; i < sizeof(hk->kv_mic); i++) 1818 printf("%02x", hk->kv_mic[i]); 1819 #if HAL_ABI_VERSION > 0x06052200 1820 if (!sc->sc_splitmic) { 1821 printf(" txmic "); 1822 for (i = 0; i < sizeof(hk->kv_txmic); i++) 1823 printf("%02x", hk->kv_txmic[i]); 1824 } 1825 #endif 1826 } 1827 printf("\n"); 1828 } 1829 #endif 1830 1831 /* 1832 * Set a TKIP key into the hardware. This handles the 1833 * potential distribution of key state to multiple key 1834 * cache slots for TKIP. 1835 */ 1836 static int 1837 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1838 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1839 { 1840 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1841 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1842 struct ath_hal *ah = sc->sc_ah; 1843 1844 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1845 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1846 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1847 if (sc->sc_splitmic) { 1848 /* 1849 * TX key goes at first index, RX key at the rx index. 1850 * The hal handles the MIC keys at index+64. 1851 */ 1852 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1853 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1854 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1855 return 0; 1856 1857 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1858 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1859 /* XXX delete tx key on failure? */ 1860 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1861 } else { 1862 /* 1863 * Room for both TX+RX MIC keys in one key cache 1864 * slot, just set key at the first index; the hal 1865 * will handle the reset. 1866 */ 1867 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1868 #if HAL_ABI_VERSION > 0x06052200 1869 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1870 #endif 1871 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1872 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1873 } 1874 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1875 /* 1876 * TX/RX key goes at first index. 1877 * The hal handles the MIC keys are index+64. 1878 */ 1879 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1880 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1881 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1882 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1883 } 1884 return 0; 1885 #undef IEEE80211_KEY_XR 1886 } 1887 1888 /* 1889 * Set a net80211 key into the hardware. This handles the 1890 * potential distribution of key state to multiple key 1891 * cache slots for TKIP with hardware MIC support. 1892 */ 1893 static int 1894 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1895 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1896 struct ieee80211_node *bss) 1897 { 1898 #define N(a) (sizeof(a)/sizeof(a[0])) 1899 static const u_int8_t ciphermap[] = { 1900 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1901 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1902 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1903 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1904 (u_int8_t) -1, /* 4 is not allocated */ 1905 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1906 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1907 }; 1908 struct ath_hal *ah = sc->sc_ah; 1909 const struct ieee80211_cipher *cip = k->wk_cipher; 1910 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1911 const u_int8_t *mac; 1912 HAL_KEYVAL hk; 1913 1914 memset(&hk, 0, sizeof(hk)); 1915 /* 1916 * Software crypto uses a "clear key" so non-crypto 1917 * state kept in the key cache are maintained and 1918 * so that rx frames have an entry to match. 1919 */ 1920 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1921 KASSERT(cip->ic_cipher < N(ciphermap), 1922 ("invalid cipher type %u", cip->ic_cipher)); 1923 hk.kv_type = ciphermap[cip->ic_cipher]; 1924 hk.kv_len = k->wk_keylen; 1925 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1926 } else 1927 hk.kv_type = HAL_CIPHER_CLR; 1928 1929 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1930 /* 1931 * Group keys on hardware that supports multicast frame 1932 * key search use a mac that is the sender's address with 1933 * the high bit set instead of the app-specified address. 1934 */ 1935 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1936 gmac[0] |= 0x80; 1937 mac = gmac; 1938 } else 1939 mac = mac0; 1940 1941 if (hk.kv_type == HAL_CIPHER_TKIP && 1942 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1943 return ath_keyset_tkip(sc, k, &hk, mac); 1944 } else { 1945 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1946 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1947 } 1948 #undef N 1949 } 1950 1951 /* 1952 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1953 * each key, one for decrypt/encrypt and the other for the MIC. 1954 */ 1955 static u_int16_t 1956 key_alloc_2pair(struct ath_softc *sc, 1957 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1958 { 1959 #define N(a) (sizeof(a)/sizeof(a[0])) 1960 u_int i, keyix; 1961 1962 KASSERT(sc->sc_splitmic, ("key cache !split")); 1963 /* XXX could optimize */ 1964 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1965 u_int8_t b = sc->sc_keymap[i]; 1966 if (b != 0xff) { 1967 /* 1968 * One or more slots in this byte are free. 1969 */ 1970 keyix = i*NBBY; 1971 while (b & 1) { 1972 again: 1973 keyix++; 1974 b >>= 1; 1975 } 1976 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1977 if (isset(sc->sc_keymap, keyix+32) || 1978 isset(sc->sc_keymap, keyix+64) || 1979 isset(sc->sc_keymap, keyix+32+64)) { 1980 /* full pair unavailable */ 1981 /* XXX statistic */ 1982 if (keyix == (i+1)*NBBY) { 1983 /* no slots were appropriate, advance */ 1984 continue; 1985 } 1986 goto again; 1987 } 1988 setbit(sc->sc_keymap, keyix); 1989 setbit(sc->sc_keymap, keyix+64); 1990 setbit(sc->sc_keymap, keyix+32); 1991 setbit(sc->sc_keymap, keyix+32+64); 1992 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1993 "%s: key pair %u,%u %u,%u\n", 1994 __func__, keyix, keyix+64, 1995 keyix+32, keyix+32+64); 1996 *txkeyix = keyix; 1997 *rxkeyix = keyix+32; 1998 return 1; 1999 } 2000 } 2001 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2002 return 0; 2003 #undef N 2004 } 2005 2006 /* 2007 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2008 * each key, one for decrypt/encrypt and the other for the MIC. 2009 */ 2010 static u_int16_t 2011 key_alloc_pair(struct ath_softc *sc, 2012 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2013 { 2014 #define N(a) (sizeof(a)/sizeof(a[0])) 2015 u_int i, keyix; 2016 2017 KASSERT(!sc->sc_splitmic, ("key cache split")); 2018 /* XXX could optimize */ 2019 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2020 u_int8_t b = sc->sc_keymap[i]; 2021 if (b != 0xff) { 2022 /* 2023 * One or more slots in this byte are free. 2024 */ 2025 keyix = i*NBBY; 2026 while (b & 1) { 2027 again: 2028 keyix++; 2029 b >>= 1; 2030 } 2031 if (isset(sc->sc_keymap, keyix+64)) { 2032 /* full pair unavailable */ 2033 /* XXX statistic */ 2034 if (keyix == (i+1)*NBBY) { 2035 /* no slots were appropriate, advance */ 2036 continue; 2037 } 2038 goto again; 2039 } 2040 setbit(sc->sc_keymap, keyix); 2041 setbit(sc->sc_keymap, keyix+64); 2042 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2043 "%s: key pair %u,%u\n", 2044 __func__, keyix, keyix+64); 2045 *txkeyix = *rxkeyix = keyix; 2046 return 1; 2047 } 2048 } 2049 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2050 return 0; 2051 #undef N 2052 } 2053 2054 /* 2055 * Allocate a single key cache slot. 2056 */ 2057 static int 2058 key_alloc_single(struct ath_softc *sc, 2059 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2060 { 2061 #define N(a) (sizeof(a)/sizeof(a[0])) 2062 u_int i, keyix; 2063 2064 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 2065 for (i = 0; i < N(sc->sc_keymap); i++) { 2066 u_int8_t b = sc->sc_keymap[i]; 2067 if (b != 0xff) { 2068 /* 2069 * One or more slots are free. 2070 */ 2071 keyix = i*NBBY; 2072 while (b & 1) 2073 keyix++, b >>= 1; 2074 setbit(sc->sc_keymap, keyix); 2075 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 2076 __func__, keyix); 2077 *txkeyix = *rxkeyix = keyix; 2078 return 1; 2079 } 2080 } 2081 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 2082 return 0; 2083 #undef N 2084 } 2085 2086 /* 2087 * Allocate one or more key cache slots for a uniacst key. The 2088 * key itself is needed only to identify the cipher. For hardware 2089 * TKIP with split cipher+MIC keys we allocate two key cache slot 2090 * pairs so that we can setup separate TX and RX MIC keys. Note 2091 * that the MIC key for a TKIP key at slot i is assumed by the 2092 * hardware to be at slot i+64. This limits TKIP keys to the first 2093 * 64 entries. 2094 */ 2095 static int 2096 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 2097 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2098 { 2099 struct ath_softc *sc = ic->ic_ifp->if_softc; 2100 2101 /* 2102 * Group key allocation must be handled specially for 2103 * parts that do not support multicast key cache search 2104 * functionality. For those parts the key id must match 2105 * the h/w key index so lookups find the right key. On 2106 * parts w/ the key search facility we install the sender's 2107 * mac address (with the high bit set) and let the hardware 2108 * find the key w/o using the key id. This is preferred as 2109 * it permits us to support multiple users for adhoc and/or 2110 * multi-station operation. 2111 */ 2112 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 2113 if (!(&ic->ic_nw_keys[0] <= k && 2114 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 2115 /* should not happen */ 2116 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2117 "%s: bogus group key\n", __func__); 2118 return 0; 2119 } 2120 /* 2121 * XXX we pre-allocate the global keys so 2122 * have no way to check if they've already been allocated. 2123 */ 2124 *keyix = *rxkeyix = k - ic->ic_nw_keys; 2125 return 1; 2126 } 2127 2128 /* 2129 * We allocate two pair for TKIP when using the h/w to do 2130 * the MIC. For everything else, including software crypto, 2131 * we allocate a single entry. Note that s/w crypto requires 2132 * a pass-through slot on the 5211 and 5212. The 5210 does 2133 * not support pass-through cache entries and we map all 2134 * those requests to slot 0. 2135 */ 2136 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2137 return key_alloc_single(sc, keyix, rxkeyix); 2138 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 2139 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2140 if (sc->sc_splitmic) 2141 return key_alloc_2pair(sc, keyix, rxkeyix); 2142 else 2143 return key_alloc_pair(sc, keyix, rxkeyix); 2144 } else { 2145 return key_alloc_single(sc, keyix, rxkeyix); 2146 } 2147 } 2148 2149 /* 2150 * Delete an entry in the key cache allocated by ath_key_alloc. 2151 */ 2152 static int 2153 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 2154 { 2155 struct ath_softc *sc = ic->ic_ifp->if_softc; 2156 struct ath_hal *ah = sc->sc_ah; 2157 const struct ieee80211_cipher *cip = k->wk_cipher; 2158 u_int keyix = k->wk_keyix; 2159 2160 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 2161 2162 ath_hal_keyreset(ah, keyix); 2163 /* 2164 * Handle split tx/rx keying required for TKIP with h/w MIC. 2165 */ 2166 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2167 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 2168 ath_hal_keyreset(ah, keyix+32); /* RX key */ 2169 if (keyix >= IEEE80211_WEP_NKID) { 2170 /* 2171 * Don't touch keymap entries for global keys so 2172 * they are never considered for dynamic allocation. 2173 */ 2174 clrbit(sc->sc_keymap, keyix); 2175 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2176 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2177 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 2178 if (sc->sc_splitmic) { 2179 /* +32 for RX key, +32+64 for RX key MIC */ 2180 clrbit(sc->sc_keymap, keyix+32); 2181 clrbit(sc->sc_keymap, keyix+32+64); 2182 } 2183 } 2184 } 2185 return 1; 2186 } 2187 2188 /* 2189 * Set the key cache contents for the specified key. Key cache 2190 * slot(s) must already have been allocated by ath_key_alloc. 2191 */ 2192 static int 2193 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 2194 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2195 { 2196 struct ath_softc *sc = ic->ic_ifp->if_softc; 2197 2198 return ath_keyset(sc, k, mac, ic->ic_bss); 2199 } 2200 2201 /* 2202 * Block/unblock tx+rx processing while a key change is done. 2203 * We assume the caller serializes key management operations 2204 * so we only need to worry about synchronization with other 2205 * uses that originate in the driver. 2206 */ 2207 static void 2208 ath_key_update_begin(struct ieee80211com *ic) 2209 { 2210 struct ifnet *ifp = ic->ic_ifp; 2211 struct ath_softc *sc = ifp->if_softc; 2212 2213 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2214 #if 0 2215 tasklet_disable(&sc->sc_rxtq); 2216 #endif 2217 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2218 } 2219 2220 static void 2221 ath_key_update_end(struct ieee80211com *ic) 2222 { 2223 struct ifnet *ifp = ic->ic_ifp; 2224 struct ath_softc *sc = ifp->if_softc; 2225 2226 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2227 IF_UNLOCK(&ifp->if_snd); 2228 #if 0 2229 tasklet_enable(&sc->sc_rxtq); 2230 #endif 2231 } 2232 2233 /* 2234 * Calculate the receive filter according to the 2235 * operating mode and state: 2236 * 2237 * o always accept unicast, broadcast, and multicast traffic 2238 * o maintain current state of phy error reception (the hal 2239 * may enable phy error frames for noise immunity work) 2240 * o probe request frames are accepted only when operating in 2241 * hostap, adhoc, or monitor modes 2242 * o enable promiscuous mode according to the interface state 2243 * o accept beacons: 2244 * - when operating in adhoc mode so the 802.11 layer creates 2245 * node table entries for peers, 2246 * - when operating in station mode for collecting rssi data when 2247 * the station is otherwise quiet, or 2248 * - when scanning 2249 * o accept control frames: 2250 * - when in monitor mode 2251 */ 2252 static u_int32_t 2253 ath_calcrxfilter(struct ath_softc *sc) 2254 { 2255 #define RX_FILTER_PRESERVE (HAL_RX_FILTER_PHYERR | HAL_RX_FILTER_PHYRADAR) 2256 struct ieee80211com *ic = &sc->sc_ic; 2257 struct ath_hal *ah = sc->sc_ah; 2258 struct ifnet *ifp = sc->sc_ifp; 2259 u_int32_t rfilt; 2260 2261 rfilt = (ath_hal_getrxfilter(ah) & RX_FILTER_PRESERVE) 2262 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2263 if (ic->ic_opmode != IEEE80211_M_STA) 2264 rfilt |= HAL_RX_FILTER_PROBEREQ; 2265 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2266 (ifp->if_flags & IFF_PROMISC)) 2267 rfilt |= HAL_RX_FILTER_PROM; 2268 if (ic->ic_opmode == IEEE80211_M_STA || 2269 ic->ic_opmode == IEEE80211_M_IBSS || 2270 sc->sc_scanning) 2271 rfilt |= HAL_RX_FILTER_BEACON; 2272 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2273 rfilt |= HAL_RX_FILTER_CONTROL; 2274 return rfilt; 2275 #undef RX_FILTER_PRESERVE 2276 } 2277 2278 static void 2279 ath_mode_init(struct ath_softc *sc) 2280 { 2281 struct ieee80211com *ic = &sc->sc_ic; 2282 struct ath_hal *ah = sc->sc_ah; 2283 struct ifnet *ifp = sc->sc_ifp; 2284 u_int32_t rfilt, mfilt[2], val; 2285 u_int8_t pos; 2286 struct ifmultiaddr *ifma; 2287 2288 /* configure rx filter */ 2289 rfilt = ath_calcrxfilter(sc); 2290 ath_hal_setrxfilter(ah, rfilt); 2291 2292 /* configure operational mode */ 2293 ath_hal_setopmode(ah); 2294 2295 /* 2296 * Handle any link-level address change. Note that we only 2297 * need to force ic_myaddr; any other addresses are handled 2298 * as a byproduct of the ifnet code marking the interface 2299 * down then up. 2300 * 2301 * XXX should get from lladdr instead of arpcom but that's more work 2302 */ 2303 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2304 ath_hal_setmac(ah, ic->ic_myaddr); 2305 2306 /* calculate and install multicast filter */ 2307 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2308 mfilt[0] = mfilt[1] = 0; 2309 IF_ADDR_LOCK(ifp); 2310 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2311 caddr_t dl; 2312 2313 /* calculate XOR of eight 6bit values */ 2314 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2315 val = LE_READ_4(dl + 0); 2316 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2317 val = LE_READ_4(dl + 3); 2318 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2319 pos &= 0x3f; 2320 mfilt[pos / 32] |= (1 << (pos % 32)); 2321 } 2322 IF_ADDR_UNLOCK(ifp); 2323 } else { 2324 mfilt[0] = mfilt[1] = ~0; 2325 } 2326 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 2327 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 2328 __func__, rfilt, mfilt[0], mfilt[1]); 2329 } 2330 2331 /* 2332 * Set the slot time based on the current setting. 2333 */ 2334 static void 2335 ath_setslottime(struct ath_softc *sc) 2336 { 2337 struct ieee80211com *ic = &sc->sc_ic; 2338 struct ath_hal *ah = sc->sc_ah; 2339 u_int usec; 2340 2341 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2342 usec = 13; 2343 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2344 usec = 21; 2345 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2346 /* honor short/long slot time only in 11g */ 2347 /* XXX shouldn't honor on pure g or turbo g channel */ 2348 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2349 usec = HAL_SLOT_TIME_9; 2350 else 2351 usec = HAL_SLOT_TIME_20; 2352 } else 2353 usec = HAL_SLOT_TIME_9; 2354 2355 DPRINTF(sc, ATH_DEBUG_RESET, 2356 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2357 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2358 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2359 2360 ath_hal_setslottime(ah, usec); 2361 sc->sc_updateslot = OK; 2362 } 2363 2364 /* 2365 * Callback from the 802.11 layer to update the 2366 * slot time based on the current setting. 2367 */ 2368 static void 2369 ath_updateslot(struct ifnet *ifp) 2370 { 2371 struct ath_softc *sc = ifp->if_softc; 2372 struct ieee80211com *ic = &sc->sc_ic; 2373 2374 /* 2375 * When not coordinating the BSS, change the hardware 2376 * immediately. For other operation we defer the change 2377 * until beacon updates have propagated to the stations. 2378 */ 2379 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2380 sc->sc_updateslot = UPDATE; 2381 else 2382 ath_setslottime(sc); 2383 } 2384 2385 /* 2386 * Setup a h/w transmit queue for beacons. 2387 */ 2388 static int 2389 ath_beaconq_setup(struct ath_hal *ah) 2390 { 2391 HAL_TXQ_INFO qi; 2392 2393 memset(&qi, 0, sizeof(qi)); 2394 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2395 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2396 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2397 /* NB: for dynamic turbo, don't enable any other interrupts */ 2398 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2399 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2400 } 2401 2402 /* 2403 * Setup the transmit queue parameters for the beacon queue. 2404 */ 2405 static int 2406 ath_beaconq_config(struct ath_softc *sc) 2407 { 2408 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2409 struct ieee80211com *ic = &sc->sc_ic; 2410 struct ath_hal *ah = sc->sc_ah; 2411 HAL_TXQ_INFO qi; 2412 2413 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2414 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2415 /* 2416 * Always burst out beacon and CAB traffic. 2417 */ 2418 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2419 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2420 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2421 } else { 2422 struct wmeParams *wmep = 2423 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2424 /* 2425 * Adhoc mode; important thing is to use 2x cwmin. 2426 */ 2427 qi.tqi_aifs = wmep->wmep_aifsn; 2428 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2429 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2430 } 2431 2432 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2433 device_printf(sc->sc_dev, "unable to update parameters for " 2434 "beacon hardware queue!\n"); 2435 return 0; 2436 } else { 2437 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2438 return 1; 2439 } 2440 #undef ATH_EXPONENT_TO_VALUE 2441 } 2442 2443 /* 2444 * Allocate and setup an initial beacon frame. 2445 */ 2446 static int 2447 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2448 { 2449 struct ieee80211com *ic = ni->ni_ic; 2450 struct ath_buf *bf; 2451 struct mbuf *m; 2452 int error; 2453 2454 bf = STAILQ_FIRST(&sc->sc_bbuf); 2455 if (bf == NULL) { 2456 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 2457 sc->sc_stats.ast_be_nombuf++; /* XXX */ 2458 return ENOMEM; /* XXX */ 2459 } 2460 /* 2461 * NB: the beacon data buffer must be 32-bit aligned; 2462 * we assume the mbuf routines will return us something 2463 * with this alignment (perhaps should assert). 2464 */ 2465 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 2466 if (m == NULL) { 2467 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 2468 __func__); 2469 sc->sc_stats.ast_be_nombuf++; 2470 return ENOMEM; 2471 } 2472 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2473 bf->bf_segs, &bf->bf_nseg, 2474 BUS_DMA_NOWAIT); 2475 if (error == 0) { 2476 bf->bf_m = m; 2477 bf->bf_node = ieee80211_ref_node(ni); 2478 } else { 2479 m_freem(m); 2480 } 2481 return error; 2482 } 2483 2484 /* 2485 * Setup the beacon frame for transmit. 2486 */ 2487 static void 2488 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2489 { 2490 #define USE_SHPREAMBLE(_ic) \ 2491 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2492 == IEEE80211_F_SHPREAMBLE) 2493 struct ieee80211_node *ni = bf->bf_node; 2494 struct ieee80211com *ic = ni->ni_ic; 2495 struct mbuf *m = bf->bf_m; 2496 struct ath_hal *ah = sc->sc_ah; 2497 struct ath_desc *ds; 2498 int flags, antenna; 2499 const HAL_RATE_TABLE *rt; 2500 u_int8_t rix, rate; 2501 2502 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2503 __func__, m, m->m_len); 2504 2505 /* setup descriptors */ 2506 ds = bf->bf_desc; 2507 2508 flags = HAL_TXDESC_NOACK; 2509 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2510 ds->ds_link = bf->bf_daddr; /* self-linked */ 2511 flags |= HAL_TXDESC_VEOL; 2512 /* 2513 * Let hardware handle antenna switching. 2514 */ 2515 antenna = sc->sc_txantenna; 2516 } else { 2517 ds->ds_link = 0; 2518 /* 2519 * Switch antenna every 4 beacons. 2520 * XXX assumes two antenna 2521 */ 2522 antenna = sc->sc_txantenna != 0 ? sc->sc_txantenna 2523 : (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2524 } 2525 2526 KASSERT(bf->bf_nseg == 1, 2527 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2528 ds->ds_data = bf->bf_segs[0].ds_addr; 2529 /* 2530 * Calculate rate code. 2531 * XXX everything at min xmit rate 2532 */ 2533 rix = sc->sc_minrateix; 2534 rt = sc->sc_currates; 2535 rate = rt->info[rix].rateCode; 2536 if (USE_SHPREAMBLE(ic)) 2537 rate |= rt->info[rix].shortPreamble; 2538 ath_hal_setuptxdesc(ah, ds 2539 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2540 , sizeof(struct ieee80211_frame)/* header length */ 2541 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2542 , ni->ni_txpower /* txpower XXX */ 2543 , rate, 1 /* series 0 rate/tries */ 2544 , HAL_TXKEYIX_INVALID /* no encryption */ 2545 , antenna /* antenna mode */ 2546 , flags /* no ack, veol for beacons */ 2547 , 0 /* rts/cts rate */ 2548 , 0 /* rts/cts duration */ 2549 ); 2550 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2551 ath_hal_filltxdesc(ah, ds 2552 , roundup(m->m_len, 4) /* buffer length */ 2553 , AH_TRUE /* first segment */ 2554 , AH_TRUE /* last segment */ 2555 , ds /* first descriptor */ 2556 ); 2557 #undef USE_SHPREAMBLE 2558 } 2559 2560 /* 2561 * Append the contents of src to dst; both queues 2562 * are assumed to be locked. 2563 */ 2564 static void 2565 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2566 { 2567 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 2568 dst->axq_link = src->axq_link; 2569 src->axq_link = NULL; 2570 dst->axq_depth += src->axq_depth; 2571 src->axq_depth = 0; 2572 } 2573 2574 /* 2575 * Transmit a beacon frame at SWBA. Dynamic updates to the 2576 * frame contents are done as needed and the slot time is 2577 * also adjusted based on current state. 2578 */ 2579 static void 2580 ath_beacon_proc(void *arg, int pending) 2581 { 2582 struct ath_softc *sc = arg; 2583 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 2584 struct ieee80211_node *ni = bf->bf_node; 2585 struct ieee80211com *ic = ni->ni_ic; 2586 struct ath_hal *ah = sc->sc_ah; 2587 struct ath_txq *cabq = sc->sc_cabq; 2588 struct mbuf *m; 2589 int ncabq, nmcastq, error, otherant; 2590 2591 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2592 __func__, pending); 2593 2594 if (ic->ic_opmode == IEEE80211_M_STA || 2595 ic->ic_opmode == IEEE80211_M_MONITOR || 2596 bf == NULL || bf->bf_m == NULL) { 2597 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 2598 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 2599 return; 2600 } 2601 /* 2602 * Check if the previous beacon has gone out. If 2603 * not don't try to post another, skip this period 2604 * and wait for the next. Missed beacons indicate 2605 * a problem and should not occur. If we miss too 2606 * many consecutive beacons reset the device. 2607 */ 2608 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2609 sc->sc_bmisscount++; 2610 DPRINTF(sc, ATH_DEBUG_BEACON, 2611 "%s: missed %u consecutive beacons\n", 2612 __func__, sc->sc_bmisscount); 2613 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2614 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2615 return; 2616 } 2617 if (sc->sc_bmisscount != 0) { 2618 DPRINTF(sc, ATH_DEBUG_BEACON, 2619 "%s: resume beacon xmit after %u misses\n", 2620 __func__, sc->sc_bmisscount); 2621 sc->sc_bmisscount = 0; 2622 } 2623 2624 /* 2625 * Update dynamic beacon contents. If this returns 2626 * non-zero then we need to remap the memory because 2627 * the beacon frame changed size (probably because 2628 * of the TIM bitmap). 2629 */ 2630 m = bf->bf_m; 2631 nmcastq = sc->sc_mcastq.axq_depth; 2632 ncabq = ath_hal_numtxpending(ah, cabq->axq_qnum); 2633 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq+nmcastq)) { 2634 /* XXX too conservative? */ 2635 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2636 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2637 bf->bf_segs, &bf->bf_nseg, 2638 BUS_DMA_NOWAIT); 2639 if (error != 0) { 2640 if_printf(ic->ic_ifp, 2641 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 2642 __func__, error); 2643 return; 2644 } 2645 } 2646 if (ncabq && (sc->sc_boff.bo_tim[4] & 1)) { 2647 /* 2648 * CABQ traffic from the previous DTIM is still pending. 2649 * This is ok for now but when there are multiple vap's 2650 * and we are using staggered beacons we'll want to drain 2651 * the cabq before loading frames for the different vap. 2652 */ 2653 DPRINTF(sc, ATH_DEBUG_BEACON, 2654 "%s: cabq did not drain, mcastq %u cabq %u/%u\n", 2655 __func__, nmcastq, ncabq, cabq->axq_depth); 2656 sc->sc_stats.ast_cabq_busy++; 2657 } 2658 2659 /* 2660 * Handle slot time change when a non-ERP station joins/leaves 2661 * an 11g network. The 802.11 layer notifies us via callback, 2662 * we mark updateslot, then wait one beacon before effecting 2663 * the change. This gives associated stations at least one 2664 * beacon interval to note the state change. 2665 */ 2666 /* XXX locking */ 2667 if (sc->sc_updateslot == UPDATE) 2668 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2669 else if (sc->sc_updateslot == COMMIT) 2670 ath_setslottime(sc); /* commit change to h/w */ 2671 2672 /* 2673 * Check recent per-antenna transmit statistics and flip 2674 * the default antenna if noticeably more frames went out 2675 * on the non-default antenna. 2676 * XXX assumes 2 anntenae 2677 */ 2678 otherant = sc->sc_defant & 1 ? 2 : 1; 2679 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2680 ath_setdefantenna(sc, otherant); 2681 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2682 2683 /* 2684 * Construct tx descriptor. 2685 */ 2686 ath_beacon_setup(sc, bf); 2687 2688 /* 2689 * Stop any current dma and put the new frame on the queue. 2690 * This should never fail since we check above that no frames 2691 * are still pending on the queue. 2692 */ 2693 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2694 DPRINTF(sc, ATH_DEBUG_ANY, 2695 "%s: beacon queue %u did not stop?\n", 2696 __func__, sc->sc_bhalq); 2697 } 2698 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2699 2700 /* 2701 * Enable the CAB queue before the beacon queue to 2702 * insure cab frames are triggered by this beacon. 2703 */ 2704 if (sc->sc_boff.bo_tim_len && (sc->sc_boff.bo_tim[4] & 1)) { 2705 /* NB: only at DTIM */ 2706 ATH_TXQ_LOCK(cabq); 2707 ATH_TXQ_LOCK(&sc->sc_mcastq); 2708 if (nmcastq) { 2709 struct ath_buf *bfm; 2710 2711 /* 2712 * Move frames from the s/w mcast q to the h/w cab q. 2713 */ 2714 bfm = STAILQ_FIRST(&sc->sc_mcastq.axq_q); 2715 if (cabq->axq_link != NULL) { 2716 *cabq->axq_link = bfm->bf_daddr; 2717 } else 2718 ath_hal_puttxbuf(ah, cabq->axq_qnum, 2719 bfm->bf_daddr); 2720 ath_txqmove(cabq, &sc->sc_mcastq); 2721 2722 sc->sc_stats.ast_cabq_xmit += nmcastq; 2723 } 2724 /* NB: gated by beacon so safe to start here */ 2725 ath_hal_txstart(ah, cabq->axq_qnum); 2726 ATH_TXQ_UNLOCK(cabq); 2727 ATH_TXQ_UNLOCK(&sc->sc_mcastq); 2728 } 2729 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2730 ath_hal_txstart(ah, sc->sc_bhalq); 2731 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2732 "%s: TXDP[%u] = %p (%p)\n", __func__, 2733 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 2734 2735 sc->sc_stats.ast_be_xmit++; 2736 } 2737 2738 /* 2739 * Reset the hardware after detecting beacons have stopped. 2740 */ 2741 static void 2742 ath_bstuck_proc(void *arg, int pending) 2743 { 2744 struct ath_softc *sc = arg; 2745 struct ifnet *ifp = sc->sc_ifp; 2746 2747 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2748 sc->sc_bmisscount); 2749 ath_reset(ifp); 2750 } 2751 2752 /* 2753 * Reclaim beacon resources. 2754 */ 2755 static void 2756 ath_beacon_free(struct ath_softc *sc) 2757 { 2758 struct ath_buf *bf; 2759 2760 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2761 if (bf->bf_m != NULL) { 2762 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2763 m_freem(bf->bf_m); 2764 bf->bf_m = NULL; 2765 } 2766 if (bf->bf_node != NULL) { 2767 ieee80211_free_node(bf->bf_node); 2768 bf->bf_node = NULL; 2769 } 2770 } 2771 } 2772 2773 /* 2774 * Configure the beacon and sleep timers. 2775 * 2776 * When operating as an AP this resets the TSF and sets 2777 * up the hardware to notify us when we need to issue beacons. 2778 * 2779 * When operating in station mode this sets up the beacon 2780 * timers according to the timestamp of the last received 2781 * beacon and the current TSF, configures PCF and DTIM 2782 * handling, programs the sleep registers so the hardware 2783 * will wakeup in time to receive beacons, and configures 2784 * the beacon miss handling so we'll receive a BMISS 2785 * interrupt when we stop seeing beacons from the AP 2786 * we've associated with. 2787 */ 2788 static void 2789 ath_beacon_config(struct ath_softc *sc) 2790 { 2791 #define TSF_TO_TU(_h,_l) \ 2792 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 2793 #define FUDGE 2 2794 struct ath_hal *ah = sc->sc_ah; 2795 struct ieee80211com *ic = &sc->sc_ic; 2796 struct ieee80211_node *ni = ic->ic_bss; 2797 u_int32_t nexttbtt, intval, tsftu; 2798 u_int64_t tsf; 2799 2800 /* extract tstamp from last beacon and convert to TU */ 2801 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2802 LE_READ_4(ni->ni_tstamp.data)); 2803 /* NB: the beacon interval is kept internally in TU's */ 2804 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2805 if (nexttbtt == 0) /* e.g. for ap mode */ 2806 nexttbtt = intval; 2807 else if (intval) /* NB: can be 0 for monitor mode */ 2808 nexttbtt = roundup(nexttbtt, intval); 2809 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2810 __func__, nexttbtt, intval, ni->ni_intval); 2811 if (ic->ic_opmode == IEEE80211_M_STA) { 2812 HAL_BEACON_STATE bs; 2813 int dtimperiod, dtimcount; 2814 int cfpperiod, cfpcount; 2815 2816 /* 2817 * Setup dtim and cfp parameters according to 2818 * last beacon we received (which may be none). 2819 */ 2820 dtimperiod = ni->ni_dtim_period; 2821 if (dtimperiod <= 0) /* NB: 0 if not known */ 2822 dtimperiod = 1; 2823 dtimcount = ni->ni_dtim_count; 2824 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2825 dtimcount = 0; /* XXX? */ 2826 cfpperiod = 1; /* NB: no PCF support yet */ 2827 cfpcount = 0; 2828 /* 2829 * Pull nexttbtt forward to reflect the current 2830 * TSF and calculate dtim+cfp state for the result. 2831 */ 2832 tsf = ath_hal_gettsf64(ah); 2833 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2834 do { 2835 nexttbtt += intval; 2836 if (--dtimcount < 0) { 2837 dtimcount = dtimperiod - 1; 2838 if (--cfpcount < 0) 2839 cfpcount = cfpperiod - 1; 2840 } 2841 } while (nexttbtt < tsftu); 2842 memset(&bs, 0, sizeof(bs)); 2843 bs.bs_intval = intval; 2844 bs.bs_nexttbtt = nexttbtt; 2845 bs.bs_dtimperiod = dtimperiod*intval; 2846 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2847 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2848 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2849 bs.bs_cfpmaxduration = 0; 2850 #if 0 2851 /* 2852 * The 802.11 layer records the offset to the DTIM 2853 * bitmap while receiving beacons; use it here to 2854 * enable h/w detection of our AID being marked in 2855 * the bitmap vector (to indicate frames for us are 2856 * pending at the AP). 2857 * XXX do DTIM handling in s/w to WAR old h/w bugs 2858 * XXX enable based on h/w rev for newer chips 2859 */ 2860 bs.bs_timoffset = ni->ni_timoff; 2861 #endif 2862 /* 2863 * Calculate the number of consecutive beacons to miss 2864 * before taking a BMISS interrupt. 2865 * Note that we clamp the result to at most 10 beacons. 2866 */ 2867 bs.bs_bmissthreshold = ic->ic_bmissthreshold; 2868 if (bs.bs_bmissthreshold > 10) 2869 bs.bs_bmissthreshold = 10; 2870 else if (bs.bs_bmissthreshold <= 0) 2871 bs.bs_bmissthreshold = 1; 2872 2873 /* 2874 * Calculate sleep duration. The configuration is 2875 * given in ms. We insure a multiple of the beacon 2876 * period is used. Also, if the sleep duration is 2877 * greater than the DTIM period then it makes senses 2878 * to make it a multiple of that. 2879 * 2880 * XXX fixed at 100ms 2881 */ 2882 bs.bs_sleepduration = 2883 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2884 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2885 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2886 2887 DPRINTF(sc, ATH_DEBUG_BEACON, 2888 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2889 , __func__ 2890 , tsf, tsftu 2891 , bs.bs_intval 2892 , bs.bs_nexttbtt 2893 , bs.bs_dtimperiod 2894 , bs.bs_nextdtim 2895 , bs.bs_bmissthreshold 2896 , bs.bs_sleepduration 2897 , bs.bs_cfpperiod 2898 , bs.bs_cfpmaxduration 2899 , bs.bs_cfpnext 2900 , bs.bs_timoffset 2901 ); 2902 ath_hal_intrset(ah, 0); 2903 ath_hal_beacontimers(ah, &bs); 2904 sc->sc_imask |= HAL_INT_BMISS; 2905 ath_hal_intrset(ah, sc->sc_imask); 2906 } else { 2907 ath_hal_intrset(ah, 0); 2908 if (nexttbtt == intval) 2909 intval |= HAL_BEACON_RESET_TSF; 2910 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2911 /* 2912 * In IBSS mode enable the beacon timers but only 2913 * enable SWBA interrupts if we need to manually 2914 * prepare beacon frames. Otherwise we use a 2915 * self-linked tx descriptor and let the hardware 2916 * deal with things. 2917 */ 2918 intval |= HAL_BEACON_ENA; 2919 if (!sc->sc_hasveol) 2920 sc->sc_imask |= HAL_INT_SWBA; 2921 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 2922 /* 2923 * Pull nexttbtt forward to reflect 2924 * the current TSF. 2925 */ 2926 tsf = ath_hal_gettsf64(ah); 2927 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 2928 do { 2929 nexttbtt += intval; 2930 } while (nexttbtt < tsftu); 2931 } 2932 ath_beaconq_config(sc); 2933 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2934 /* 2935 * In AP mode we enable the beacon timers and 2936 * SWBA interrupts to prepare beacon frames. 2937 */ 2938 intval |= HAL_BEACON_ENA; 2939 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2940 ath_beaconq_config(sc); 2941 } 2942 ath_hal_beaconinit(ah, nexttbtt, intval); 2943 sc->sc_bmisscount = 0; 2944 ath_hal_intrset(ah, sc->sc_imask); 2945 /* 2946 * When using a self-linked beacon descriptor in 2947 * ibss mode load it once here. 2948 */ 2949 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2950 ath_beacon_proc(sc, 0); 2951 } 2952 sc->sc_syncbeacon = 0; 2953 #undef FUDGE 2954 #undef TSF_TO_TU 2955 } 2956 2957 static void 2958 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2959 { 2960 bus_addr_t *paddr = (bus_addr_t*) arg; 2961 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 2962 *paddr = segs->ds_addr; 2963 } 2964 2965 static int 2966 ath_descdma_setup(struct ath_softc *sc, 2967 struct ath_descdma *dd, ath_bufhead *head, 2968 const char *name, int nbuf, int ndesc) 2969 { 2970 #define DS2PHYS(_dd, _ds) \ 2971 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2972 struct ifnet *ifp = sc->sc_ifp; 2973 struct ath_desc *ds; 2974 struct ath_buf *bf; 2975 int i, bsize, error; 2976 2977 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2978 __func__, name, nbuf, ndesc); 2979 2980 dd->dd_name = name; 2981 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2982 2983 /* 2984 * Setup DMA descriptor area. 2985 */ 2986 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 2987 PAGE_SIZE, 0, /* alignment, bounds */ 2988 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2989 BUS_SPACE_MAXADDR, /* highaddr */ 2990 NULL, NULL, /* filter, filterarg */ 2991 dd->dd_desc_len, /* maxsize */ 2992 1, /* nsegments */ 2993 dd->dd_desc_len, /* maxsegsize */ 2994 BUS_DMA_ALLOCNOW, /* flags */ 2995 NULL, /* lockfunc */ 2996 NULL, /* lockarg */ 2997 &dd->dd_dmat); 2998 if (error != 0) { 2999 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3000 return error; 3001 } 3002 3003 /* allocate descriptors */ 3004 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3005 if (error != 0) { 3006 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3007 "error %u\n", dd->dd_name, error); 3008 goto fail0; 3009 } 3010 3011 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3012 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3013 &dd->dd_dmamap); 3014 if (error != 0) { 3015 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3016 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3017 goto fail1; 3018 } 3019 3020 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3021 dd->dd_desc, dd->dd_desc_len, 3022 ath_load_cb, &dd->dd_desc_paddr, 3023 BUS_DMA_NOWAIT); 3024 if (error != 0) { 3025 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3026 dd->dd_name, error); 3027 goto fail2; 3028 } 3029 3030 ds = dd->dd_desc; 3031 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3032 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3033 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3034 3035 /* allocate rx buffers */ 3036 bsize = sizeof(struct ath_buf) * nbuf; 3037 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3038 if (bf == NULL) { 3039 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3040 dd->dd_name, bsize); 3041 goto fail3; 3042 } 3043 dd->dd_bufptr = bf; 3044 3045 STAILQ_INIT(head); 3046 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 3047 bf->bf_desc = ds; 3048 bf->bf_daddr = DS2PHYS(dd, ds); 3049 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3050 &bf->bf_dmamap); 3051 if (error != 0) { 3052 if_printf(ifp, "unable to create dmamap for %s " 3053 "buffer %u, error %u\n", dd->dd_name, i, error); 3054 ath_descdma_cleanup(sc, dd, head); 3055 return error; 3056 } 3057 STAILQ_INSERT_TAIL(head, bf, bf_list); 3058 } 3059 return 0; 3060 fail3: 3061 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3062 fail2: 3063 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3064 fail1: 3065 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3066 fail0: 3067 bus_dma_tag_destroy(dd->dd_dmat); 3068 memset(dd, 0, sizeof(*dd)); 3069 return error; 3070 #undef DS2PHYS 3071 } 3072 3073 static void 3074 ath_descdma_cleanup(struct ath_softc *sc, 3075 struct ath_descdma *dd, ath_bufhead *head) 3076 { 3077 struct ath_buf *bf; 3078 struct ieee80211_node *ni; 3079 3080 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3081 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3082 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3083 bus_dma_tag_destroy(dd->dd_dmat); 3084 3085 STAILQ_FOREACH(bf, head, bf_list) { 3086 if (bf->bf_m) { 3087 m_freem(bf->bf_m); 3088 bf->bf_m = NULL; 3089 } 3090 if (bf->bf_dmamap != NULL) { 3091 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3092 bf->bf_dmamap = NULL; 3093 } 3094 ni = bf->bf_node; 3095 bf->bf_node = NULL; 3096 if (ni != NULL) { 3097 /* 3098 * Reclaim node reference. 3099 */ 3100 ieee80211_free_node(ni); 3101 } 3102 } 3103 3104 STAILQ_INIT(head); 3105 free(dd->dd_bufptr, M_ATHDEV); 3106 memset(dd, 0, sizeof(*dd)); 3107 } 3108 3109 static int 3110 ath_desc_alloc(struct ath_softc *sc) 3111 { 3112 int error; 3113 3114 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3115 "rx", ath_rxbuf, 1); 3116 if (error != 0) 3117 return error; 3118 3119 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3120 "tx", ath_txbuf, ATH_TXDESC); 3121 if (error != 0) { 3122 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3123 return error; 3124 } 3125 3126 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3127 "beacon", 1, 1); 3128 if (error != 0) { 3129 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3130 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3131 return error; 3132 } 3133 return 0; 3134 } 3135 3136 static void 3137 ath_desc_free(struct ath_softc *sc) 3138 { 3139 3140 if (sc->sc_bdma.dd_desc_len != 0) 3141 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3142 if (sc->sc_txdma.dd_desc_len != 0) 3143 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3144 if (sc->sc_rxdma.dd_desc_len != 0) 3145 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3146 } 3147 3148 static struct ieee80211_node * 3149 ath_node_alloc(struct ieee80211_node_table *nt) 3150 { 3151 struct ieee80211com *ic = nt->nt_ic; 3152 struct ath_softc *sc = ic->ic_ifp->if_softc; 3153 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3154 struct ath_node *an; 3155 3156 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3157 if (an == NULL) { 3158 /* XXX stat+msg */ 3159 return NULL; 3160 } 3161 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 3162 ath_rate_node_init(sc, an); 3163 3164 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3165 return &an->an_node; 3166 } 3167 3168 static void 3169 ath_node_free(struct ieee80211_node *ni) 3170 { 3171 struct ieee80211com *ic = ni->ni_ic; 3172 struct ath_softc *sc = ic->ic_ifp->if_softc; 3173 3174 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3175 3176 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3177 sc->sc_node_free(ni); 3178 } 3179 3180 static int8_t 3181 ath_node_getrssi(const struct ieee80211_node *ni) 3182 { 3183 #define HAL_EP_RND(x, mul) \ 3184 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 3185 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 3186 int32_t rssi; 3187 3188 /* 3189 * When only one frame is received there will be no state in 3190 * avgrssi so fallback on the value recorded by the 802.11 layer. 3191 */ 3192 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 3193 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 3194 else 3195 rssi = ni->ni_rssi; 3196 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 3197 #undef HAL_EP_RND 3198 } 3199 3200 static void 3201 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3202 { 3203 struct ieee80211com *ic = ni->ni_ic; 3204 struct ath_softc *sc = ic->ic_ifp->if_softc; 3205 struct ath_hal *ah = sc->sc_ah; 3206 HAL_CHANNEL hchan; 3207 3208 *rssi = ath_node_getrssi(ni); 3209 if (ni->ni_chan != IEEE80211_CHAN_ANYC) { 3210 ath_mapchan(&hchan, ni->ni_chan); 3211 *noise = ath_hal_getchannoise(ah, &hchan); 3212 } else 3213 *noise = -95; /* nominally correct */ 3214 } 3215 3216 static int 3217 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3218 { 3219 struct ath_hal *ah = sc->sc_ah; 3220 int error; 3221 struct mbuf *m; 3222 struct ath_desc *ds; 3223 3224 m = bf->bf_m; 3225 if (m == NULL) { 3226 /* 3227 * NB: by assigning a page to the rx dma buffer we 3228 * implicitly satisfy the Atheros requirement that 3229 * this buffer be cache-line-aligned and sized to be 3230 * multiple of the cache line size. Not doing this 3231 * causes weird stuff to happen (for the 5210 at least). 3232 */ 3233 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3234 if (m == NULL) { 3235 DPRINTF(sc, ATH_DEBUG_ANY, 3236 "%s: no mbuf/cluster\n", __func__); 3237 sc->sc_stats.ast_rx_nombuf++; 3238 return ENOMEM; 3239 } 3240 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3241 3242 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 3243 bf->bf_dmamap, m, 3244 bf->bf_segs, &bf->bf_nseg, 3245 BUS_DMA_NOWAIT); 3246 if (error != 0) { 3247 DPRINTF(sc, ATH_DEBUG_ANY, 3248 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 3249 __func__, error); 3250 sc->sc_stats.ast_rx_busdma++; 3251 m_freem(m); 3252 return error; 3253 } 3254 KASSERT(bf->bf_nseg == 1, 3255 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3256 bf->bf_m = m; 3257 } 3258 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3259 3260 /* 3261 * Setup descriptors. For receive we always terminate 3262 * the descriptor list with a self-linked entry so we'll 3263 * not get overrun under high load (as can happen with a 3264 * 5212 when ANI processing enables PHY error frames). 3265 * 3266 * To insure the last descriptor is self-linked we create 3267 * each descriptor as self-linked and add it to the end. As 3268 * each additional descriptor is added the previous self-linked 3269 * entry is ``fixed'' naturally. This should be safe even 3270 * if DMA is happening. When processing RX interrupts we 3271 * never remove/process the last, self-linked, entry on the 3272 * descriptor list. This insures the hardware always has 3273 * someplace to write a new frame. 3274 */ 3275 ds = bf->bf_desc; 3276 ds->ds_link = bf->bf_daddr; /* link to self */ 3277 ds->ds_data = bf->bf_segs[0].ds_addr; 3278 ath_hal_setuprxdesc(ah, ds 3279 , m->m_len /* buffer size */ 3280 , 0 3281 ); 3282 3283 if (sc->sc_rxlink != NULL) 3284 *sc->sc_rxlink = bf->bf_daddr; 3285 sc->sc_rxlink = &ds->ds_link; 3286 return 0; 3287 } 3288 3289 /* 3290 * Extend 15-bit time stamp from rx descriptor to 3291 * a full 64-bit TSF using the specified TSF. 3292 */ 3293 static __inline u_int64_t 3294 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 3295 { 3296 if ((tsf & 0x7fff) < rstamp) 3297 tsf -= 0x8000; 3298 return ((tsf &~ 0x7fff) | rstamp); 3299 } 3300 3301 /* 3302 * Intercept management frames to collect beacon rssi data 3303 * and to do ibss merges. 3304 */ 3305 static void 3306 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 3307 struct ieee80211_node *ni, 3308 int subtype, int rssi, int noise, u_int32_t rstamp) 3309 { 3310 struct ath_softc *sc = ic->ic_ifp->if_softc; 3311 3312 /* 3313 * Call up first so subsequent work can use information 3314 * potentially stored in the node (e.g. for ibss merge). 3315 */ 3316 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, noise, rstamp); 3317 switch (subtype) { 3318 case IEEE80211_FC0_SUBTYPE_BEACON: 3319 /* update rssi statistics for use by the hal */ 3320 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3321 if (sc->sc_syncbeacon && 3322 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) { 3323 /* 3324 * Resync beacon timers using the tsf of the beacon 3325 * frame we just received. 3326 */ 3327 ath_beacon_config(sc); 3328 } 3329 /* fall thru... */ 3330 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3331 if (ic->ic_opmode == IEEE80211_M_IBSS && 3332 ic->ic_state == IEEE80211_S_RUN) { 3333 u_int64_t tsf = ath_extend_tsf(rstamp, 3334 ath_hal_gettsf64(sc->sc_ah)); 3335 /* 3336 * Handle ibss merge as needed; check the tsf on the 3337 * frame before attempting the merge. The 802.11 spec 3338 * says the station should change it's bssid to match 3339 * the oldest station with the same ssid, where oldest 3340 * is determined by the tsf. Note that hardware 3341 * reconfiguration happens through callback to 3342 * ath_newstate as the state machine will go from 3343 * RUN -> RUN when this happens. 3344 */ 3345 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3346 DPRINTF(sc, ATH_DEBUG_STATE, 3347 "ibss merge, rstamp %u tsf %ju " 3348 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3349 (uintmax_t)ni->ni_tstamp.tsf); 3350 (void) ieee80211_ibss_merge(ni); 3351 } 3352 } 3353 break; 3354 } 3355 } 3356 3357 /* 3358 * Set the default antenna. 3359 */ 3360 static void 3361 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3362 { 3363 struct ath_hal *ah = sc->sc_ah; 3364 3365 /* XXX block beacon interrupts */ 3366 ath_hal_setdefantenna(ah, antenna); 3367 if (sc->sc_defant != antenna) 3368 sc->sc_stats.ast_ant_defswitch++; 3369 sc->sc_defant = antenna; 3370 sc->sc_rxotherant = 0; 3371 } 3372 3373 static int 3374 ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 3375 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 3376 { 3377 #define CHANNEL_HT (CHANNEL_HT20|CHANNEL_HT40PLUS|CHANNEL_HT40MINUS) 3378 u_int8_t rix; 3379 3380 KASSERT(sc->sc_drvbpf != NULL, ("no tap")); 3381 3382 /* 3383 * Discard anything shorter than an ack or cts. 3384 */ 3385 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) { 3386 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n", 3387 __func__, m->m_pkthdr.len); 3388 sc->sc_stats.ast_rx_tooshort++; 3389 return 0; 3390 } 3391 rix = rs->rs_rate; 3392 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3393 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3394 #if HAL_ABI_VERSION >= 0x07050400 3395 if (sc->sc_curchan.channelFlags & CHANNEL_HT) { 3396 /* 3397 * For HT operation we must specify the channel 3398 * attributes for each packet since they vary. 3399 * We deduce this by from HT40 bit in the rx 3400 * status and the MCS/legacy rate bit. 3401 */ 3402 sc->sc_rx_th.wr_chan_flags &= ~IEEE80211_CHAN_HT; 3403 if (sc->sc_rx_th.wr_rate & 0x80) { /* HT rate */ 3404 /* XXX 40U/40D */ 3405 sc->sc_rx_th.wr_chan_flags |= 3406 (rs->rs_flags & HAL_RX_2040) ? 3407 IEEE80211_CHAN_HT40U : IEEE80211_CHAN_HT20; 3408 if ((rs->rs_flags & HAL_RX_GI) == 0) 3409 sc->sc_rx_th.wr_flags |= 3410 IEEE80211_RADIOTAP_F_SHORTGI; 3411 } 3412 } 3413 #endif 3414 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 3415 if (rs->rs_status & HAL_RXERR_CRC) 3416 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3417 /* XXX propagate other error flags from descriptor */ 3418 sc->sc_rx_th.wr_antsignal = rs->rs_rssi + nf; 3419 sc->sc_rx_th.wr_antnoise = nf; 3420 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 3421 3422 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, sc->sc_rx_th_len, m); 3423 3424 return 1; 3425 #undef CHANNEL_HT 3426 } 3427 3428 static void 3429 ath_rx_proc(void *arg, int npending) 3430 { 3431 #define PA2DESC(_sc, _pa) \ 3432 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3433 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3434 struct ath_softc *sc = arg; 3435 struct ath_buf *bf; 3436 struct ieee80211com *ic = &sc->sc_ic; 3437 struct ifnet *ifp = sc->sc_ifp; 3438 struct ath_hal *ah = sc->sc_ah; 3439 struct ath_desc *ds; 3440 struct ath_rx_status *rs; 3441 struct mbuf *m; 3442 struct ieee80211_node *ni; 3443 struct ath_node *an; 3444 int len, type, ngood; 3445 u_int phyerr; 3446 HAL_STATUS status; 3447 int16_t nf; 3448 u_int64_t tsf; 3449 3450 NET_LOCK_GIANT(); /* XXX */ 3451 3452 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3453 ngood = 0; 3454 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 3455 tsf = ath_hal_gettsf64(ah); 3456 do { 3457 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3458 if (bf == NULL) { /* NB: shouldn't happen */ 3459 if_printf(ifp, "%s: no buffer!\n", __func__); 3460 break; 3461 } 3462 m = bf->bf_m; 3463 if (m == NULL) { /* NB: shouldn't happen */ 3464 /* 3465 * If mbuf allocation failed previously there 3466 * will be no mbuf; try again to re-populate it. 3467 */ 3468 /* XXX make debug msg */ 3469 if_printf(ifp, "%s: no mbuf!\n", __func__); 3470 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3471 goto rx_next; 3472 } 3473 ds = bf->bf_desc; 3474 if (ds->ds_link == bf->bf_daddr) { 3475 /* NB: never process the self-linked entry at the end */ 3476 break; 3477 } 3478 /* XXX sync descriptor memory */ 3479 /* 3480 * Must provide the virtual address of the current 3481 * descriptor, the physical address, and the virtual 3482 * address of the next descriptor in the h/w chain. 3483 * This allows the HAL to look ahead to see if the 3484 * hardware is done with a descriptor by checking the 3485 * done bit in the following descriptor and the address 3486 * of the current descriptor the DMA engine is working 3487 * on. All this is necessary because of our use of 3488 * a self-linked list to avoid rx overruns. 3489 */ 3490 rs = &bf->bf_status.ds_rxstat; 3491 status = ath_hal_rxprocdesc(ah, ds, 3492 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 3493 #ifdef ATH_DEBUG 3494 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3495 ath_printrxbuf(bf, 0, status == HAL_OK); 3496 #endif 3497 if (status == HAL_EINPROGRESS) 3498 break; 3499 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3500 if (rs->rs_status != 0) { 3501 if (rs->rs_status & HAL_RXERR_CRC) 3502 sc->sc_stats.ast_rx_crcerr++; 3503 if (rs->rs_status & HAL_RXERR_FIFO) 3504 sc->sc_stats.ast_rx_fifoerr++; 3505 if (rs->rs_status & HAL_RXERR_PHY) { 3506 sc->sc_stats.ast_rx_phyerr++; 3507 phyerr = rs->rs_phyerr & 0x1f; 3508 sc->sc_stats.ast_rx_phy[phyerr]++; 3509 goto rx_error; /* NB: don't count in ierrors */ 3510 } 3511 if (rs->rs_status & HAL_RXERR_DECRYPT) { 3512 /* 3513 * Decrypt error. If the error occurred 3514 * because there was no hardware key, then 3515 * let the frame through so the upper layers 3516 * can process it. This is necessary for 5210 3517 * parts which have no way to setup a ``clear'' 3518 * key cache entry. 3519 * 3520 * XXX do key cache faulting 3521 */ 3522 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 3523 goto rx_accept; 3524 sc->sc_stats.ast_rx_badcrypt++; 3525 } 3526 if (rs->rs_status & HAL_RXERR_MIC) { 3527 sc->sc_stats.ast_rx_badmic++; 3528 /* 3529 * Do minimal work required to hand off 3530 * the 802.11 header for notifcation. 3531 */ 3532 /* XXX frag's and qos frames */ 3533 len = rs->rs_datalen; 3534 if (len >= sizeof (struct ieee80211_frame)) { 3535 bus_dmamap_sync(sc->sc_dmat, 3536 bf->bf_dmamap, 3537 BUS_DMASYNC_POSTREAD); 3538 ieee80211_notify_michael_failure(ic, 3539 mtod(m, struct ieee80211_frame *), 3540 sc->sc_splitmic ? 3541 rs->rs_keyix-32 : rs->rs_keyix 3542 ); 3543 } 3544 } 3545 ifp->if_ierrors++; 3546 rx_error: 3547 /* 3548 * Cleanup any pending partial frame. 3549 */ 3550 if (sc->sc_rxpending != NULL) { 3551 m_freem(sc->sc_rxpending); 3552 sc->sc_rxpending = NULL; 3553 } 3554 /* 3555 * When a tap is present pass error frames 3556 * that have been requested. By default we 3557 * pass decrypt+mic errors but others may be 3558 * interesting (e.g. crc). 3559 */ 3560 if (bpf_peers_present(sc->sc_drvbpf) && 3561 (rs->rs_status & sc->sc_monpass)) { 3562 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3563 BUS_DMASYNC_POSTREAD); 3564 /* NB: bpf needs the mbuf length setup */ 3565 len = rs->rs_datalen; 3566 m->m_pkthdr.len = m->m_len = len; 3567 (void) ath_rx_tap(sc, m, rs, tsf, nf); 3568 } 3569 /* XXX pass MIC errors up for s/w reclaculation */ 3570 goto rx_next; 3571 } 3572 rx_accept: 3573 /* 3574 * Sync and unmap the frame. At this point we're 3575 * committed to passing the mbuf somewhere so clear 3576 * bf_m; this means a new mbuf must be allocated 3577 * when the rx descriptor is setup again to receive 3578 * another frame. 3579 */ 3580 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3581 BUS_DMASYNC_POSTREAD); 3582 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3583 bf->bf_m = NULL; 3584 3585 len = rs->rs_datalen; 3586 m->m_len = len; 3587 3588 if (rs->rs_more) { 3589 /* 3590 * Frame spans multiple descriptors; save 3591 * it for the next completed descriptor, it 3592 * will be used to construct a jumbogram. 3593 */ 3594 if (sc->sc_rxpending != NULL) { 3595 /* NB: max frame size is currently 2 clusters */ 3596 sc->sc_stats.ast_rx_toobig++; 3597 m_freem(sc->sc_rxpending); 3598 } 3599 m->m_pkthdr.rcvif = ifp; 3600 m->m_pkthdr.len = len; 3601 sc->sc_rxpending = m; 3602 goto rx_next; 3603 } else if (sc->sc_rxpending != NULL) { 3604 /* 3605 * This is the second part of a jumbogram, 3606 * chain it to the first mbuf, adjust the 3607 * frame length, and clear the rxpending state. 3608 */ 3609 sc->sc_rxpending->m_next = m; 3610 sc->sc_rxpending->m_pkthdr.len += len; 3611 m = sc->sc_rxpending; 3612 sc->sc_rxpending = NULL; 3613 } else { 3614 /* 3615 * Normal single-descriptor receive; setup 3616 * the rcvif and packet length. 3617 */ 3618 m->m_pkthdr.rcvif = ifp; 3619 m->m_pkthdr.len = len; 3620 } 3621 3622 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 3623 3624 if (bpf_peers_present(sc->sc_drvbpf) && 3625 !ath_rx_tap(sc, m, rs, tsf, nf)) { 3626 m_freem(m); /* XXX reclaim */ 3627 goto rx_next; 3628 } 3629 3630 /* 3631 * From this point on we assume the frame is at least 3632 * as large as ieee80211_frame_min; verify that. 3633 */ 3634 if (len < IEEE80211_MIN_LEN) { 3635 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 3636 __func__, len); 3637 sc->sc_stats.ast_rx_tooshort++; 3638 m_freem(m); 3639 goto rx_next; 3640 } 3641 3642 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3643 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 3644 sc->sc_hwmap[rs->rs_rate].ieeerate, 3645 rs->rs_rssi); 3646 } 3647 3648 m_adj(m, -IEEE80211_CRC_LEN); 3649 3650 /* 3651 * Locate the node for sender, track state, and then 3652 * pass the (referenced) node up to the 802.11 layer 3653 * for its use. 3654 */ 3655 ni = ieee80211_find_rxnode_withkey(ic, 3656 mtod(m, const struct ieee80211_frame_min *), 3657 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 3658 IEEE80211_KEYIX_NONE : rs->rs_keyix); 3659 /* 3660 * Track rx rssi and do any rx antenna management. 3661 */ 3662 an = ATH_NODE(ni); 3663 ATH_RSSI_LPF(an->an_avgrssi, rs->rs_rssi); 3664 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 3665 /* 3666 * Send frame up for processing. 3667 */ 3668 type = ieee80211_input(ic, m, ni, 3669 rs->rs_rssi, nf, rs->rs_tstamp); 3670 ieee80211_free_node(ni); 3671 if (sc->sc_diversity) { 3672 /* 3673 * When using fast diversity, change the default rx 3674 * antenna if diversity chooses the other antenna 3 3675 * times in a row. 3676 */ 3677 if (sc->sc_defant != rs->rs_antenna) { 3678 if (++sc->sc_rxotherant >= 3) 3679 ath_setdefantenna(sc, rs->rs_antenna); 3680 } else 3681 sc->sc_rxotherant = 0; 3682 } 3683 if (sc->sc_softled) { 3684 /* 3685 * Blink for any data frame. Otherwise do a 3686 * heartbeat-style blink when idle. The latter 3687 * is mainly for station mode where we depend on 3688 * periodic beacon frames to trigger the poll event. 3689 */ 3690 if (type == IEEE80211_FC0_TYPE_DATA) { 3691 sc->sc_rxrate = rs->rs_rate; 3692 ath_led_event(sc, ATH_LED_RX); 3693 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 3694 ath_led_event(sc, ATH_LED_POLL); 3695 } 3696 /* 3697 * Arrange to update the last rx timestamp only for 3698 * frames from our ap when operating in station mode. 3699 * This assumes the rx key is always setup when associated. 3700 */ 3701 if (ic->ic_opmode == IEEE80211_M_STA && 3702 rs->rs_keyix != HAL_RXKEYIX_INVALID) 3703 ngood++; 3704 rx_next: 3705 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 3706 } while (ath_rxbuf_init(sc, bf) == 0); 3707 3708 /* rx signal state monitoring */ 3709 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 3710 if (ngood) 3711 sc->sc_lastrx = tsf; 3712 3713 /* NB: may want to check mgtq too */ 3714 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 && 3715 !IFQ_IS_EMPTY(&ifp->if_snd)) 3716 ath_start(ifp); 3717 3718 NET_UNLOCK_GIANT(); /* XXX */ 3719 #undef PA2DESC 3720 } 3721 3722 static void 3723 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 3724 { 3725 txq->axq_qnum = qnum; 3726 txq->axq_depth = 0; 3727 txq->axq_intrcnt = 0; 3728 txq->axq_link = NULL; 3729 STAILQ_INIT(&txq->axq_q); 3730 ATH_TXQ_LOCK_INIT(sc, txq); 3731 TAILQ_INIT(&txq->axq_stageq); 3732 txq->axq_curage = 0; 3733 } 3734 3735 /* 3736 * Setup a h/w transmit queue. 3737 */ 3738 static struct ath_txq * 3739 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 3740 { 3741 #define N(a) (sizeof(a)/sizeof(a[0])) 3742 struct ath_hal *ah = sc->sc_ah; 3743 HAL_TXQ_INFO qi; 3744 int qnum; 3745 3746 memset(&qi, 0, sizeof(qi)); 3747 qi.tqi_subtype = subtype; 3748 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 3749 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 3750 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 3751 /* 3752 * Enable interrupts only for EOL and DESC conditions. 3753 * We mark tx descriptors to receive a DESC interrupt 3754 * when a tx queue gets deep; otherwise waiting for the 3755 * EOL to reap descriptors. Note that this is done to 3756 * reduce interrupt load and this only defers reaping 3757 * descriptors, never transmitting frames. Aside from 3758 * reducing interrupts this also permits more concurrency. 3759 * The only potential downside is if the tx queue backs 3760 * up in which case the top half of the kernel may backup 3761 * due to a lack of tx descriptors. 3762 */ 3763 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 3764 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 3765 if (qnum == -1) { 3766 /* 3767 * NB: don't print a message, this happens 3768 * normally on parts with too few tx queues 3769 */ 3770 return NULL; 3771 } 3772 if (qnum >= N(sc->sc_txq)) { 3773 device_printf(sc->sc_dev, 3774 "hal qnum %u out of range, max %zu!\n", 3775 qnum, N(sc->sc_txq)); 3776 ath_hal_releasetxqueue(ah, qnum); 3777 return NULL; 3778 } 3779 if (!ATH_TXQ_SETUP(sc, qnum)) { 3780 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 3781 sc->sc_txqsetup |= 1<<qnum; 3782 } 3783 return &sc->sc_txq[qnum]; 3784 #undef N 3785 } 3786 3787 /* 3788 * Setup a hardware data transmit queue for the specified 3789 * access control. The hal may not support all requested 3790 * queues in which case it will return a reference to a 3791 * previously setup queue. We record the mapping from ac's 3792 * to h/w queues for use by ath_tx_start and also track 3793 * the set of h/w queues being used to optimize work in the 3794 * transmit interrupt handler and related routines. 3795 */ 3796 static int 3797 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 3798 { 3799 #define N(a) (sizeof(a)/sizeof(a[0])) 3800 struct ath_txq *txq; 3801 3802 if (ac >= N(sc->sc_ac2q)) { 3803 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 3804 ac, N(sc->sc_ac2q)); 3805 return 0; 3806 } 3807 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 3808 if (txq != NULL) { 3809 sc->sc_ac2q[ac] = txq; 3810 return 1; 3811 } else 3812 return 0; 3813 #undef N 3814 } 3815 3816 /* 3817 * Update WME parameters for a transmit queue. 3818 */ 3819 static int 3820 ath_txq_update(struct ath_softc *sc, int ac) 3821 { 3822 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 3823 #define ATH_TXOP_TO_US(v) (v<<5) 3824 struct ieee80211com *ic = &sc->sc_ic; 3825 struct ath_txq *txq = sc->sc_ac2q[ac]; 3826 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 3827 struct ath_hal *ah = sc->sc_ah; 3828 HAL_TXQ_INFO qi; 3829 3830 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 3831 qi.tqi_aifs = wmep->wmep_aifsn; 3832 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 3833 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 3834 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 3835 3836 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3837 device_printf(sc->sc_dev, "unable to update hardware queue " 3838 "parameters for %s traffic!\n", 3839 ieee80211_wme_acnames[ac]); 3840 return 0; 3841 } else { 3842 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3843 return 1; 3844 } 3845 #undef ATH_TXOP_TO_US 3846 #undef ATH_EXPONENT_TO_VALUE 3847 } 3848 3849 /* 3850 * Callback from the 802.11 layer to update WME parameters. 3851 */ 3852 static int 3853 ath_wme_update(struct ieee80211com *ic) 3854 { 3855 struct ath_softc *sc = ic->ic_ifp->if_softc; 3856 3857 return !ath_txq_update(sc, WME_AC_BE) || 3858 !ath_txq_update(sc, WME_AC_BK) || 3859 !ath_txq_update(sc, WME_AC_VI) || 3860 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3861 } 3862 3863 /* 3864 * Reclaim resources for a setup queue. 3865 */ 3866 static void 3867 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3868 { 3869 3870 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3871 ATH_TXQ_LOCK_DESTROY(txq); 3872 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3873 } 3874 3875 /* 3876 * Reclaim all tx queue resources. 3877 */ 3878 static void 3879 ath_tx_cleanup(struct ath_softc *sc) 3880 { 3881 int i; 3882 3883 ATH_TXBUF_LOCK_DESTROY(sc); 3884 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3885 if (ATH_TXQ_SETUP(sc, i)) 3886 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3887 ATH_TXQ_LOCK_DESTROY(&sc->sc_mcastq); 3888 } 3889 3890 /* 3891 * Defragment an mbuf chain, returning at most maxfrags separate 3892 * mbufs+clusters. If this is not possible NULL is returned and 3893 * the original mbuf chain is left in it's present (potentially 3894 * modified) state. We use two techniques: collapsing consecutive 3895 * mbufs and replacing consecutive mbufs by a cluster. 3896 */ 3897 static struct mbuf * 3898 ath_defrag(struct mbuf *m0, int how, int maxfrags) 3899 { 3900 struct mbuf *m, *n, *n2, **prev; 3901 u_int curfrags; 3902 3903 /* 3904 * Calculate the current number of frags. 3905 */ 3906 curfrags = 0; 3907 for (m = m0; m != NULL; m = m->m_next) 3908 curfrags++; 3909 /* 3910 * First, try to collapse mbufs. Note that we always collapse 3911 * towards the front so we don't need to deal with moving the 3912 * pkthdr. This may be suboptimal if the first mbuf has much 3913 * less data than the following. 3914 */ 3915 m = m0; 3916 again: 3917 for (;;) { 3918 n = m->m_next; 3919 if (n == NULL) 3920 break; 3921 if ((m->m_flags & M_RDONLY) == 0 && 3922 n->m_len < M_TRAILINGSPACE(m)) { 3923 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3924 n->m_len); 3925 m->m_len += n->m_len; 3926 m->m_next = n->m_next; 3927 m_free(n); 3928 if (--curfrags <= maxfrags) 3929 return m0; 3930 } else 3931 m = n; 3932 } 3933 KASSERT(maxfrags > 1, 3934 ("maxfrags %u, but normal collapse failed", maxfrags)); 3935 /* 3936 * Collapse consecutive mbufs to a cluster. 3937 */ 3938 prev = &m0->m_next; /* NB: not the first mbuf */ 3939 while ((n = *prev) != NULL) { 3940 if ((n2 = n->m_next) != NULL && 3941 n->m_len + n2->m_len < MCLBYTES) { 3942 m = m_getcl(how, MT_DATA, 0); 3943 if (m == NULL) 3944 goto bad; 3945 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3946 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3947 n2->m_len); 3948 m->m_len = n->m_len + n2->m_len; 3949 m->m_next = n2->m_next; 3950 *prev = m; 3951 m_free(n); 3952 m_free(n2); 3953 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3954 return m0; 3955 /* 3956 * Still not there, try the normal collapse 3957 * again before we allocate another cluster. 3958 */ 3959 goto again; 3960 } 3961 prev = &n->m_next; 3962 } 3963 /* 3964 * No place where we can collapse to a cluster; punt. 3965 * This can occur if, for example, you request 2 frags 3966 * but the packet requires that both be clusters (we 3967 * never reallocate the first mbuf to avoid moving the 3968 * packet header). 3969 */ 3970 bad: 3971 return NULL; 3972 } 3973 3974 /* 3975 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 3976 */ 3977 static int 3978 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 3979 { 3980 int i; 3981 3982 for (i = 0; i < rt->rateCount; i++) 3983 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 3984 return i; 3985 return 0; /* NB: lowest rate */ 3986 } 3987 3988 /* 3989 * Reclaim mbuf resources. For fragmented frames we 3990 * need to claim each frag chained with m_nextpkt. 3991 */ 3992 static void 3993 ath_freetx(struct mbuf *m) 3994 { 3995 struct mbuf *next; 3996 3997 do { 3998 next = m->m_nextpkt; 3999 m->m_nextpkt = NULL; 4000 m_freem(m); 4001 } while ((m = next) != NULL); 4002 } 4003 4004 static int 4005 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 4006 { 4007 struct mbuf *m; 4008 int error; 4009 4010 /* 4011 * Load the DMA map so any coalescing is done. This 4012 * also calculates the number of descriptors we need. 4013 */ 4014 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4015 bf->bf_segs, &bf->bf_nseg, 4016 BUS_DMA_NOWAIT); 4017 if (error == EFBIG) { 4018 /* XXX packet requires too many descriptors */ 4019 bf->bf_nseg = ATH_TXDESC+1; 4020 } else if (error != 0) { 4021 sc->sc_stats.ast_tx_busdma++; 4022 ath_freetx(m0); 4023 return error; 4024 } 4025 /* 4026 * Discard null packets and check for packets that 4027 * require too many TX descriptors. We try to convert 4028 * the latter to a cluster. 4029 */ 4030 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 4031 sc->sc_stats.ast_tx_linear++; 4032 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 4033 if (m == NULL) { 4034 ath_freetx(m0); 4035 sc->sc_stats.ast_tx_nombuf++; 4036 return ENOMEM; 4037 } 4038 m0 = m; 4039 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4040 bf->bf_segs, &bf->bf_nseg, 4041 BUS_DMA_NOWAIT); 4042 if (error != 0) { 4043 sc->sc_stats.ast_tx_busdma++; 4044 ath_freetx(m0); 4045 return error; 4046 } 4047 KASSERT(bf->bf_nseg <= ATH_TXDESC, 4048 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 4049 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 4050 sc->sc_stats.ast_tx_nodata++; 4051 ath_freetx(m0); 4052 return EIO; 4053 } 4054 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 4055 __func__, m0, m0->m_pkthdr.len); 4056 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 4057 bf->bf_m = m0; 4058 4059 return 0; 4060 } 4061 4062 static void 4063 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 4064 { 4065 struct ath_hal *ah = sc->sc_ah; 4066 struct ath_desc *ds, *ds0; 4067 int i; 4068 4069 /* 4070 * Fillin the remainder of the descriptor info. 4071 */ 4072 ds0 = ds = bf->bf_desc; 4073 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4074 ds->ds_data = bf->bf_segs[i].ds_addr; 4075 if (i == bf->bf_nseg - 1) 4076 ds->ds_link = 0; 4077 else 4078 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4079 ath_hal_filltxdesc(ah, ds 4080 , bf->bf_segs[i].ds_len /* segment length */ 4081 , i == 0 /* first segment */ 4082 , i == bf->bf_nseg - 1 /* last segment */ 4083 , ds0 /* first descriptor */ 4084 ); 4085 DPRINTF(sc, ATH_DEBUG_XMIT, 4086 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4087 __func__, i, ds->ds_link, ds->ds_data, 4088 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4089 } 4090 /* 4091 * Insert the frame on the outbound list and pass it on 4092 * to the hardware. Multicast frames buffered for power 4093 * save stations and transmit from the CAB queue are stored 4094 * on a s/w only queue and loaded on to the CAB queue in 4095 * the SWBA handler since frames only go out on DTIM and 4096 * to avoid possible races. 4097 */ 4098 ATH_TXQ_LOCK(txq); 4099 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4100 if (txq != &sc->sc_mcastq) { 4101 if (txq->axq_link == NULL) { 4102 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4103 DPRINTF(sc, ATH_DEBUG_XMIT, 4104 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 4105 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 4106 txq->axq_depth); 4107 } else { 4108 *txq->axq_link = bf->bf_daddr; 4109 DPRINTF(sc, ATH_DEBUG_XMIT, 4110 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4111 txq->axq_qnum, txq->axq_link, 4112 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4113 } 4114 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4115 ath_hal_txstart(ah, txq->axq_qnum); 4116 } else { 4117 if (txq->axq_link != NULL) 4118 *txq->axq_link = bf->bf_daddr; 4119 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4120 } 4121 ATH_TXQ_UNLOCK(txq); 4122 } 4123 4124 static int 4125 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 4126 struct mbuf *m0) 4127 { 4128 struct ieee80211com *ic = &sc->sc_ic; 4129 struct ath_hal *ah = sc->sc_ah; 4130 struct ifnet *ifp = sc->sc_ifp; 4131 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 4132 int error, iswep, ismcast, isfrag, ismrr; 4133 int keyix, hdrlen, pktlen, try0; 4134 u_int8_t rix, txrate, ctsrate; 4135 u_int8_t cix = 0xff; /* NB: silence compiler */ 4136 struct ath_desc *ds; 4137 struct ath_txq *txq; 4138 struct ieee80211_frame *wh; 4139 u_int subtype, flags, ctsduration; 4140 HAL_PKT_TYPE atype; 4141 const HAL_RATE_TABLE *rt; 4142 HAL_BOOL shortPreamble; 4143 struct ath_node *an; 4144 u_int pri; 4145 4146 wh = mtod(m0, struct ieee80211_frame *); 4147 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 4148 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 4149 isfrag = m0->m_flags & M_FRAG; 4150 hdrlen = ieee80211_anyhdrsize(wh); 4151 /* 4152 * Packet length must not include any 4153 * pad bytes; deduct them here. 4154 */ 4155 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 4156 4157 if (iswep) { 4158 const struct ieee80211_cipher *cip; 4159 struct ieee80211_key *k; 4160 4161 /* 4162 * Construct the 802.11 header+trailer for an encrypted 4163 * frame. The only reason this can fail is because of an 4164 * unknown or unsupported cipher/key type. 4165 */ 4166 k = ieee80211_crypto_encap(ic, ni, m0); 4167 if (k == NULL) { 4168 /* 4169 * This can happen when the key is yanked after the 4170 * frame was queued. Just discard the frame; the 4171 * 802.11 layer counts failures and provides 4172 * debugging/diagnostics. 4173 */ 4174 ath_freetx(m0); 4175 return EIO; 4176 } 4177 /* 4178 * Adjust the packet + header lengths for the crypto 4179 * additions and calculate the h/w key index. When 4180 * a s/w mic is done the frame will have had any mic 4181 * added to it prior to entry so m0->m_pkthdr.len will 4182 * account for it. Otherwise we need to add it to the 4183 * packet length. 4184 */ 4185 cip = k->wk_cipher; 4186 hdrlen += cip->ic_header; 4187 pktlen += cip->ic_header + cip->ic_trailer; 4188 /* NB: frags always have any TKIP MIC done in s/w */ 4189 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 4190 pktlen += cip->ic_miclen; 4191 keyix = k->wk_keyix; 4192 4193 /* packet header may have moved, reset our local pointer */ 4194 wh = mtod(m0, struct ieee80211_frame *); 4195 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 4196 /* 4197 * Use station key cache slot, if assigned. 4198 */ 4199 keyix = ni->ni_ucastkey.wk_keyix; 4200 if (keyix == IEEE80211_KEYIX_NONE) 4201 keyix = HAL_TXKEYIX_INVALID; 4202 } else 4203 keyix = HAL_TXKEYIX_INVALID; 4204 4205 pktlen += IEEE80211_CRC_LEN; 4206 4207 /* 4208 * Load the DMA map so any coalescing is done. This 4209 * also calculates the number of descriptors we need. 4210 */ 4211 error = ath_tx_dmasetup(sc, bf, m0); 4212 if (error != 0) 4213 return error; 4214 bf->bf_node = ni; /* NB: held reference */ 4215 m0 = bf->bf_m; /* NB: may have changed */ 4216 wh = mtod(m0, struct ieee80211_frame *); 4217 4218 /* setup descriptors */ 4219 ds = bf->bf_desc; 4220 rt = sc->sc_currates; 4221 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 4222 4223 /* 4224 * NB: the 802.11 layer marks whether or not we should 4225 * use short preamble based on the current mode and 4226 * negotiated parameters. 4227 */ 4228 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 4229 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 4230 shortPreamble = AH_TRUE; 4231 sc->sc_stats.ast_tx_shortpre++; 4232 } else { 4233 shortPreamble = AH_FALSE; 4234 } 4235 4236 an = ATH_NODE(ni); 4237 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 4238 ismrr = 0; /* default no multi-rate retry*/ 4239 /* 4240 * Calculate Atheros packet type from IEEE80211 packet header, 4241 * setup for rate calculations, and select h/w transmit queue. 4242 */ 4243 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 4244 case IEEE80211_FC0_TYPE_MGT: 4245 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4246 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 4247 atype = HAL_PKT_TYPE_BEACON; 4248 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4249 atype = HAL_PKT_TYPE_PROBE_RESP; 4250 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 4251 atype = HAL_PKT_TYPE_ATIM; 4252 else 4253 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 4254 rix = sc->sc_minrateix; 4255 txrate = rt->info[rix].rateCode; 4256 if (shortPreamble) 4257 txrate |= rt->info[rix].shortPreamble; 4258 try0 = ATH_TXMGTTRY; 4259 /* NB: force all management frames to highest queue */ 4260 if (ni->ni_flags & IEEE80211_NODE_QOS) { 4261 /* NB: force all management frames to highest queue */ 4262 pri = WME_AC_VO; 4263 } else 4264 pri = WME_AC_BE; 4265 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4266 break; 4267 case IEEE80211_FC0_TYPE_CTL: 4268 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 4269 rix = sc->sc_minrateix; 4270 txrate = rt->info[rix].rateCode; 4271 if (shortPreamble) 4272 txrate |= rt->info[rix].shortPreamble; 4273 try0 = ATH_TXMGTTRY; 4274 /* NB: force all ctl frames to highest queue */ 4275 if (ni->ni_flags & IEEE80211_NODE_QOS) { 4276 /* NB: force all ctl frames to highest queue */ 4277 pri = WME_AC_VO; 4278 } else 4279 pri = WME_AC_BE; 4280 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4281 break; 4282 case IEEE80211_FC0_TYPE_DATA: 4283 atype = HAL_PKT_TYPE_NORMAL; /* default */ 4284 /* 4285 * Data frames: multicast frames go out at a fixed rate, 4286 * otherwise consult the rate control module for the 4287 * rate to use. 4288 */ 4289 if (ismcast) { 4290 /* 4291 * Check mcast rate setting in case it's changed. 4292 * XXX move out of fastpath 4293 */ 4294 if (ic->ic_mcast_rate != sc->sc_mcastrate) { 4295 sc->sc_mcastrix = 4296 ath_tx_findrix(rt, ic->ic_mcast_rate); 4297 sc->sc_mcastrate = ic->ic_mcast_rate; 4298 } 4299 rix = sc->sc_mcastrix; 4300 txrate = rt->info[rix].rateCode; 4301 if (shortPreamble) 4302 txrate |= rt->info[rix].shortPreamble; 4303 try0 = 1; 4304 } else { 4305 ath_rate_findrate(sc, an, shortPreamble, pktlen, 4306 &rix, &try0, &txrate); 4307 sc->sc_txrate = txrate; /* for LED blinking */ 4308 sc->sc_lastdatarix = rix; /* for fast frames */ 4309 if (try0 != ATH_TXMAXTRY) 4310 ismrr = 1; 4311 } 4312 pri = M_WME_GETAC(m0); 4313 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 4314 flags |= HAL_TXDESC_NOACK; 4315 break; 4316 default: 4317 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 4318 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 4319 /* XXX statistic */ 4320 ath_freetx(m0); 4321 return EIO; 4322 } 4323 txq = sc->sc_ac2q[pri]; 4324 4325 /* 4326 * When servicing one or more stations in power-save mode 4327 * (or) if there is some mcast data waiting on the mcast 4328 * queue (to prevent out of order delivery) multicast 4329 * frames must be buffered until after the beacon. 4330 */ 4331 if (ismcast && (ic->ic_ps_sta || sc->sc_mcastq.axq_depth)) { 4332 txq = &sc->sc_mcastq; 4333 /* XXX? more bit in 802.11 frame header */ 4334 } 4335 4336 /* 4337 * Calculate miscellaneous flags. 4338 */ 4339 if (ismcast) { 4340 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 4341 } else if (pktlen > ic->ic_rtsthreshold && 4342 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 4343 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 4344 cix = rt->info[rix].controlRate; 4345 sc->sc_stats.ast_tx_rts++; 4346 } 4347 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 4348 sc->sc_stats.ast_tx_noack++; 4349 4350 /* 4351 * If 802.11g protection is enabled, determine whether 4352 * to use RTS/CTS or just CTS. Note that this is only 4353 * done for OFDM unicast frames. 4354 */ 4355 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 4356 rt->info[rix].phy == IEEE80211_T_OFDM && 4357 (flags & HAL_TXDESC_NOACK) == 0) { 4358 /* XXX fragments must use CCK rates w/ protection */ 4359 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4360 flags |= HAL_TXDESC_RTSENA; 4361 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4362 flags |= HAL_TXDESC_CTSENA; 4363 if (isfrag) { 4364 /* 4365 * For frags it would be desirable to use the 4366 * highest CCK rate for RTS/CTS. But stations 4367 * farther away may detect it at a lower CCK rate 4368 * so use the configured protection rate instead 4369 * (for now). 4370 */ 4371 cix = rt->info[sc->sc_protrix].controlRate; 4372 } else 4373 cix = rt->info[sc->sc_protrix].controlRate; 4374 sc->sc_stats.ast_tx_protect++; 4375 } 4376 4377 /* 4378 * Calculate duration. This logically belongs in the 802.11 4379 * layer but it lacks sufficient information to calculate it. 4380 */ 4381 if ((flags & HAL_TXDESC_NOACK) == 0 && 4382 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 4383 u_int16_t dur; 4384 if (shortPreamble) 4385 dur = rt->info[rix].spAckDuration; 4386 else 4387 dur = rt->info[rix].lpAckDuration; 4388 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 4389 dur += dur; /* additional SIFS+ACK */ 4390 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 4391 /* 4392 * Include the size of next fragment so NAV is 4393 * updated properly. The last fragment uses only 4394 * the ACK duration 4395 */ 4396 dur += ath_hal_computetxtime(ah, rt, 4397 m0->m_nextpkt->m_pkthdr.len, 4398 rix, shortPreamble); 4399 } 4400 if (isfrag) { 4401 /* 4402 * Force hardware to use computed duration for next 4403 * fragment by disabling multi-rate retry which updates 4404 * duration based on the multi-rate duration table. 4405 */ 4406 ismrr = 0; 4407 try0 = ATH_TXMGTTRY; /* XXX? */ 4408 } 4409 *(u_int16_t *)wh->i_dur = htole16(dur); 4410 } 4411 4412 /* 4413 * Calculate RTS/CTS rate and duration if needed. 4414 */ 4415 ctsduration = 0; 4416 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 4417 /* 4418 * CTS transmit rate is derived from the transmit rate 4419 * by looking in the h/w rate table. We must also factor 4420 * in whether or not a short preamble is to be used. 4421 */ 4422 /* NB: cix is set above where RTS/CTS is enabled */ 4423 KASSERT(cix != 0xff, ("cix not setup")); 4424 ctsrate = rt->info[cix].rateCode; 4425 /* 4426 * Compute the transmit duration based on the frame 4427 * size and the size of an ACK frame. We call into the 4428 * HAL to do the computation since it depends on the 4429 * characteristics of the actual PHY being used. 4430 * 4431 * NB: CTS is assumed the same size as an ACK so we can 4432 * use the precalculated ACK durations. 4433 */ 4434 if (shortPreamble) { 4435 ctsrate |= rt->info[cix].shortPreamble; 4436 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4437 ctsduration += rt->info[cix].spAckDuration; 4438 ctsduration += ath_hal_computetxtime(ah, 4439 rt, pktlen, rix, AH_TRUE); 4440 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4441 ctsduration += rt->info[rix].spAckDuration; 4442 } else { 4443 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4444 ctsduration += rt->info[cix].lpAckDuration; 4445 ctsduration += ath_hal_computetxtime(ah, 4446 rt, pktlen, rix, AH_FALSE); 4447 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4448 ctsduration += rt->info[rix].lpAckDuration; 4449 } 4450 /* 4451 * Must disable multi-rate retry when using RTS/CTS. 4452 */ 4453 ismrr = 0; 4454 try0 = ATH_TXMGTTRY; /* XXX */ 4455 } else 4456 ctsrate = 0; 4457 4458 /* 4459 * At this point we are committed to sending the frame 4460 * and we don't need to look at m_nextpkt; clear it in 4461 * case this frame is part of frag chain. 4462 */ 4463 m0->m_nextpkt = NULL; 4464 4465 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 4466 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 4467 sc->sc_hwmap[txrate].ieeerate, -1); 4468 4469 if (bpf_peers_present(ic->ic_rawbpf)) 4470 bpf_mtap(ic->ic_rawbpf, m0); 4471 if (bpf_peers_present(sc->sc_drvbpf)) { 4472 u_int64_t tsf = ath_hal_gettsf64(ah); 4473 4474 sc->sc_tx_th.wt_tsf = htole64(tsf); 4475 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 4476 if (iswep) 4477 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4478 if (isfrag) 4479 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 4480 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 4481 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 4482 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 4483 4484 bpf_mtap2(sc->sc_drvbpf, 4485 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 4486 } 4487 4488 /* 4489 * Determine if a tx interrupt should be generated for 4490 * this descriptor. We take a tx interrupt to reap 4491 * descriptors when the h/w hits an EOL condition or 4492 * when the descriptor is specifically marked to generate 4493 * an interrupt. We periodically mark descriptors in this 4494 * way to insure timely replenishing of the supply needed 4495 * for sending frames. Defering interrupts reduces system 4496 * load and potentially allows more concurrent work to be 4497 * done but if done to aggressively can cause senders to 4498 * backup. 4499 * 4500 * NB: use >= to deal with sc_txintrperiod changing 4501 * dynamically through sysctl. 4502 */ 4503 if (flags & HAL_TXDESC_INTREQ) { 4504 txq->axq_intrcnt = 0; 4505 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 4506 flags |= HAL_TXDESC_INTREQ; 4507 txq->axq_intrcnt = 0; 4508 } 4509 4510 /* 4511 * Formulate first tx descriptor with tx controls. 4512 */ 4513 /* XXX check return value? */ 4514 ath_hal_setuptxdesc(ah, ds 4515 , pktlen /* packet length */ 4516 , hdrlen /* header length */ 4517 , atype /* Atheros packet type */ 4518 , ni->ni_txpower /* txpower */ 4519 , txrate, try0 /* series 0 rate/tries */ 4520 , keyix /* key cache index */ 4521 , sc->sc_txantenna /* antenna mode */ 4522 , flags /* flags */ 4523 , ctsrate /* rts/cts rate */ 4524 , ctsduration /* rts/cts duration */ 4525 ); 4526 bf->bf_flags = flags; 4527 /* 4528 * Setup the multi-rate retry state only when we're 4529 * going to use it. This assumes ath_hal_setuptxdesc 4530 * initializes the descriptors (so we don't have to) 4531 * when the hardware supports multi-rate retry and 4532 * we don't use it. 4533 */ 4534 if (ismrr) 4535 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4536 4537 ath_tx_handoff(sc, txq, bf); 4538 return 0; 4539 } 4540 4541 /* 4542 * Process completed xmit descriptors from the specified queue. 4543 */ 4544 static int 4545 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4546 { 4547 struct ath_hal *ah = sc->sc_ah; 4548 struct ieee80211com *ic = &sc->sc_ic; 4549 struct ath_buf *bf; 4550 struct ath_desc *ds, *ds0; 4551 struct ath_tx_status *ts; 4552 struct ieee80211_node *ni; 4553 struct ath_node *an; 4554 int sr, lr, pri, nacked; 4555 HAL_STATUS status; 4556 4557 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4558 __func__, txq->axq_qnum, 4559 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4560 txq->axq_link); 4561 nacked = 0; 4562 for (;;) { 4563 ATH_TXQ_LOCK(txq); 4564 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4565 bf = STAILQ_FIRST(&txq->axq_q); 4566 if (bf == NULL) { 4567 ATH_TXQ_UNLOCK(txq); 4568 break; 4569 } 4570 ds0 = &bf->bf_desc[0]; 4571 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4572 ts = &bf->bf_status.ds_txstat; 4573 status = ath_hal_txprocdesc(ah, ds, ts); 4574 #ifdef ATH_DEBUG 4575 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4576 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK); 4577 #endif 4578 if (status == HAL_EINPROGRESS) { 4579 ATH_TXQ_UNLOCK(txq); 4580 break; 4581 } 4582 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4583 if (txq->axq_depth == 0) 4584 txq->axq_link = NULL; 4585 ATH_TXQ_UNLOCK(txq); 4586 4587 ni = bf->bf_node; 4588 if (ni != NULL) { 4589 an = ATH_NODE(ni); 4590 if (ts->ts_status == 0) { 4591 u_int8_t txant = ts->ts_antenna; 4592 sc->sc_stats.ast_ant_tx[txant]++; 4593 sc->sc_ant_tx[txant]++; 4594 if (ts->ts_rate & HAL_TXSTAT_ALTRATE) 4595 sc->sc_stats.ast_tx_altrate++; 4596 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4597 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4598 ts->ts_rssi); 4599 pri = M_WME_GETAC(bf->bf_m); 4600 if (pri >= WME_AC_VO) 4601 ic->ic_wme.wme_hipri_traffic++; 4602 ni->ni_inact = ni->ni_inact_reload; 4603 } else { 4604 if (ts->ts_status & HAL_TXERR_XRETRY) 4605 sc->sc_stats.ast_tx_xretries++; 4606 if (ts->ts_status & HAL_TXERR_FIFO) 4607 sc->sc_stats.ast_tx_fifoerr++; 4608 if (ts->ts_status & HAL_TXERR_FILT) 4609 sc->sc_stats.ast_tx_filtered++; 4610 if (bf->bf_m->m_flags & M_FF) 4611 sc->sc_stats.ast_ff_txerr++; 4612 } 4613 sr = ts->ts_shortretry; 4614 lr = ts->ts_longretry; 4615 sc->sc_stats.ast_tx_shortretry += sr; 4616 sc->sc_stats.ast_tx_longretry += lr; 4617 /* 4618 * Hand the descriptor to the rate control algorithm. 4619 */ 4620 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4621 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4622 /* 4623 * If frame was ack'd update the last rx time 4624 * used to workaround phantom bmiss interrupts. 4625 */ 4626 if (ts->ts_status == 0) 4627 nacked++; 4628 ath_rate_tx_complete(sc, an, bf); 4629 } 4630 /* 4631 * Do any tx complete callback. Note this must 4632 * be done before releasing the node reference. 4633 */ 4634 if (bf->bf_m->m_flags & M_TXCB) 4635 ieee80211_process_callback(ni, bf->bf_m, 4636 ts->ts_status); 4637 /* 4638 * Reclaim reference to node. 4639 * 4640 * NB: the node may be reclaimed here if, for example 4641 * this is a DEAUTH message that was sent and the 4642 * node was timed out due to inactivity. 4643 */ 4644 ieee80211_free_node(ni); 4645 } 4646 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4647 BUS_DMASYNC_POSTWRITE); 4648 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4649 4650 m_freem(bf->bf_m); 4651 bf->bf_m = NULL; 4652 bf->bf_node = NULL; 4653 4654 ATH_TXBUF_LOCK(sc); 4655 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4656 ATH_TXBUF_UNLOCK(sc); 4657 } 4658 /* 4659 * Flush fast-frame staging queue when traffic slows. 4660 */ 4661 if (txq->axq_depth <= 1) 4662 ath_ff_stageq_flush(sc, txq, ath_ff_always); 4663 return nacked; 4664 } 4665 4666 static __inline int 4667 txqactive(struct ath_hal *ah, int qnum) 4668 { 4669 u_int32_t txqs = 1<<qnum; 4670 ath_hal_gettxintrtxqs(ah, &txqs); 4671 return (txqs & (1<<qnum)); 4672 } 4673 4674 /* 4675 * Deferred processing of transmit interrupt; special-cased 4676 * for a single hardware transmit queue (e.g. 5210 and 5211). 4677 */ 4678 static void 4679 ath_tx_proc_q0(void *arg, int npending) 4680 { 4681 struct ath_softc *sc = arg; 4682 struct ifnet *ifp = sc->sc_ifp; 4683 4684 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 4685 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4686 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4687 ath_tx_processq(sc, sc->sc_cabq); 4688 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4689 ifp->if_timer = 0; 4690 4691 if (sc->sc_softled) 4692 ath_led_event(sc, ATH_LED_TX); 4693 4694 ath_start(ifp); 4695 } 4696 4697 /* 4698 * Deferred processing of transmit interrupt; special-cased 4699 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4700 */ 4701 static void 4702 ath_tx_proc_q0123(void *arg, int npending) 4703 { 4704 struct ath_softc *sc = arg; 4705 struct ifnet *ifp = sc->sc_ifp; 4706 int nacked; 4707 4708 /* 4709 * Process each active queue. 4710 */ 4711 nacked = 0; 4712 if (txqactive(sc->sc_ah, 0)) 4713 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 4714 if (txqactive(sc->sc_ah, 1)) 4715 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 4716 if (txqactive(sc->sc_ah, 2)) 4717 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 4718 if (txqactive(sc->sc_ah, 3)) 4719 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 4720 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 4721 ath_tx_processq(sc, sc->sc_cabq); 4722 if (nacked) 4723 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4724 4725 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4726 ifp->if_timer = 0; 4727 4728 if (sc->sc_softled) 4729 ath_led_event(sc, ATH_LED_TX); 4730 4731 ath_start(ifp); 4732 } 4733 4734 /* 4735 * Deferred processing of transmit interrupt. 4736 */ 4737 static void 4738 ath_tx_proc(void *arg, int npending) 4739 { 4740 struct ath_softc *sc = arg; 4741 struct ifnet *ifp = sc->sc_ifp; 4742 int i, nacked; 4743 4744 /* 4745 * Process each active queue. 4746 */ 4747 nacked = 0; 4748 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4749 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 4750 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 4751 if (nacked) 4752 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4753 4754 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4755 ifp->if_timer = 0; 4756 4757 if (sc->sc_softled) 4758 ath_led_event(sc, ATH_LED_TX); 4759 4760 ath_start(ifp); 4761 } 4762 4763 static void 4764 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4765 { 4766 #ifdef ATH_DEBUG 4767 struct ath_hal *ah = sc->sc_ah; 4768 #endif 4769 struct ieee80211_node *ni; 4770 struct ath_buf *bf; 4771 u_int ix; 4772 4773 /* 4774 * NB: this assumes output has been stopped and 4775 * we do not need to block ath_tx_tasklet 4776 */ 4777 for (ix = 0;; ix++) { 4778 ATH_TXQ_LOCK(txq); 4779 bf = STAILQ_FIRST(&txq->axq_q); 4780 if (bf == NULL) { 4781 txq->axq_link = NULL; 4782 ATH_TXQ_UNLOCK(txq); 4783 break; 4784 } 4785 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4786 ATH_TXQ_UNLOCK(txq); 4787 #ifdef ATH_DEBUG 4788 if (sc->sc_debug & ATH_DEBUG_RESET) { 4789 ath_printtxbuf(bf, txq->axq_qnum, ix, 4790 ath_hal_txprocdesc(ah, bf->bf_desc, 4791 &bf->bf_status.ds_txstat) == HAL_OK); 4792 ieee80211_dump_pkt(&sc->sc_ic, mtod(bf->bf_m, caddr_t), 4793 bf->bf_m->m_len, 0, -1); 4794 } 4795 #endif /* ATH_DEBUG */ 4796 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4797 ni = bf->bf_node; 4798 bf->bf_node = NULL; 4799 if (ni != NULL) { 4800 /* 4801 * Do any callback and reclaim the node reference. 4802 */ 4803 if (bf->bf_m->m_flags & M_TXCB) 4804 ieee80211_process_callback(ni, bf->bf_m, -1); 4805 ieee80211_free_node(ni); 4806 } 4807 m_freem(bf->bf_m); 4808 bf->bf_m = NULL; 4809 4810 ATH_TXBUF_LOCK(sc); 4811 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4812 ATH_TXBUF_UNLOCK(sc); 4813 } 4814 } 4815 4816 static void 4817 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 4818 { 4819 struct ath_hal *ah = sc->sc_ah; 4820 4821 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4822 __func__, txq->axq_qnum, 4823 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 4824 txq->axq_link); 4825 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 4826 } 4827 4828 /* 4829 * Drain the transmit queues and reclaim resources. 4830 */ 4831 static void 4832 ath_draintxq(struct ath_softc *sc) 4833 { 4834 struct ath_hal *ah = sc->sc_ah; 4835 struct ifnet *ifp = sc->sc_ifp; 4836 int i; 4837 4838 /* XXX return value */ 4839 if (!sc->sc_invalid) { 4840 /* don't touch the hardware if marked invalid */ 4841 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 4842 __func__, sc->sc_bhalq, 4843 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 4844 NULL); 4845 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 4846 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4847 if (ATH_TXQ_SETUP(sc, i)) 4848 ath_tx_stopdma(sc, &sc->sc_txq[i]); 4849 } 4850 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4851 if (ATH_TXQ_SETUP(sc, i)) 4852 ath_tx_draintxq(sc, &sc->sc_txq[i]); 4853 ath_tx_draintxq(sc, &sc->sc_mcastq); 4854 #ifdef ATH_DEBUG 4855 if (sc->sc_debug & ATH_DEBUG_RESET) { 4856 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 4857 if (bf != NULL && bf->bf_m != NULL) { 4858 ath_printtxbuf(bf, sc->sc_bhalq, 0, 4859 ath_hal_txprocdesc(ah, bf->bf_desc, 4860 &bf->bf_status.ds_txstat) == HAL_OK); 4861 ieee80211_dump_pkt(&sc->sc_ic, mtod(bf->bf_m, caddr_t), 4862 bf->bf_m->m_len, 0, -1); 4863 } 4864 } 4865 #endif /* ATH_DEBUG */ 4866 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4867 ifp->if_timer = 0; 4868 } 4869 4870 /* 4871 * Disable the receive h/w in preparation for a reset. 4872 */ 4873 static void 4874 ath_stoprecv(struct ath_softc *sc) 4875 { 4876 #define PA2DESC(_sc, _pa) \ 4877 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 4878 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 4879 struct ath_hal *ah = sc->sc_ah; 4880 4881 ath_hal_stoppcurecv(ah); /* disable PCU */ 4882 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 4883 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 4884 DELAY(3000); /* 3ms is long enough for 1 frame */ 4885 #ifdef ATH_DEBUG 4886 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 4887 struct ath_buf *bf; 4888 u_int ix; 4889 4890 printf("%s: rx queue %p, link %p\n", __func__, 4891 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 4892 ix = 0; 4893 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4894 struct ath_desc *ds = bf->bf_desc; 4895 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 4896 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 4897 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 4898 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 4899 ath_printrxbuf(bf, ix, status == HAL_OK); 4900 ix++; 4901 } 4902 } 4903 #endif 4904 if (sc->sc_rxpending != NULL) { 4905 m_freem(sc->sc_rxpending); 4906 sc->sc_rxpending = NULL; 4907 } 4908 sc->sc_rxlink = NULL; /* just in case */ 4909 #undef PA2DESC 4910 } 4911 4912 /* 4913 * Enable the receive h/w following a reset. 4914 */ 4915 static int 4916 ath_startrecv(struct ath_softc *sc) 4917 { 4918 struct ath_hal *ah = sc->sc_ah; 4919 struct ath_buf *bf; 4920 4921 sc->sc_rxlink = NULL; 4922 sc->sc_rxpending = NULL; 4923 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 4924 int error = ath_rxbuf_init(sc, bf); 4925 if (error != 0) { 4926 DPRINTF(sc, ATH_DEBUG_RECV, 4927 "%s: ath_rxbuf_init failed %d\n", 4928 __func__, error); 4929 return error; 4930 } 4931 } 4932 4933 bf = STAILQ_FIRST(&sc->sc_rxbuf); 4934 ath_hal_putrxbuf(ah, bf->bf_daddr); 4935 ath_hal_rxena(ah); /* enable recv descriptors */ 4936 ath_mode_init(sc); /* set filters, etc. */ 4937 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4938 return 0; 4939 } 4940 4941 /* 4942 * Update internal state after a channel change. 4943 */ 4944 static void 4945 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 4946 { 4947 enum ieee80211_phymode mode; 4948 4949 /* 4950 * Change channels and update the h/w rate map 4951 * if we're switching; e.g. 11a to 11b/g. 4952 */ 4953 if (IEEE80211_IS_CHAN_HALF(chan)) 4954 mode = IEEE80211_MODE_HALF; 4955 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 4956 mode = IEEE80211_MODE_QUARTER; 4957 else 4958 mode = ieee80211_chan2mode(chan); 4959 if (mode != sc->sc_curmode) 4960 ath_setcurmode(sc, mode); 4961 4962 sc->sc_rx_th.wr_chan_flags = htole32(chan->ic_flags); 4963 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags; 4964 sc->sc_rx_th.wr_chan_freq = htole16(chan->ic_freq); 4965 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq; 4966 sc->sc_rx_th.wr_chan_ieee = chan->ic_ieee; 4967 sc->sc_tx_th.wt_chan_ieee = sc->sc_rx_th.wr_chan_ieee; 4968 sc->sc_rx_th.wr_chan_maxpow = chan->ic_maxregpower; 4969 sc->sc_tx_th.wt_chan_maxpow = sc->sc_rx_th.wr_chan_maxpow; 4970 } 4971 4972 /* 4973 * Poll for a channel clear indication; this is required 4974 * for channels requiring DFS and not previously visited 4975 * and/or with a recent radar detection. 4976 */ 4977 static void 4978 ath_dfswait(void *arg) 4979 { 4980 struct ath_softc *sc = arg; 4981 struct ath_hal *ah = sc->sc_ah; 4982 HAL_CHANNEL hchan; 4983 4984 ath_hal_radar_wait(ah, &hchan); 4985 DPRINTF(sc, ATH_DEBUG_DFS, "%s: radar_wait %u/%x/%x\n", 4986 __func__, hchan.channel, hchan.channelFlags, hchan.privFlags); 4987 4988 if (hchan.privFlags & CHANNEL_INTERFERENCE) { 4989 if_printf(sc->sc_ifp, 4990 "channel %u/0x%x/0x%x has interference\n", 4991 hchan.channel, hchan.channelFlags, hchan.privFlags); 4992 return; 4993 } 4994 if ((hchan.privFlags & CHANNEL_DFS) == 0) { 4995 /* XXX should not happen */ 4996 return; 4997 } 4998 if (hchan.privFlags & CHANNEL_DFS_CLEAR) { 4999 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR; 5000 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5001 if_printf(sc->sc_ifp, 5002 "channel %u/0x%x/0x%x marked clear\n", 5003 hchan.channel, hchan.channelFlags, hchan.privFlags); 5004 } else 5005 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc); 5006 } 5007 5008 /* 5009 * Set/change channels. If the channel is really being changed, 5010 * it's done by reseting the chip. To accomplish this we must 5011 * first cleanup any pending DMA, then restart stuff after a la 5012 * ath_init. 5013 */ 5014 static int 5015 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5016 { 5017 struct ath_hal *ah = sc->sc_ah; 5018 struct ieee80211com *ic = &sc->sc_ic; 5019 HAL_CHANNEL hchan; 5020 5021 /* 5022 * Convert to a HAL channel description with 5023 * the flags constrained to reflect the current 5024 * operating mode. 5025 */ 5026 ath_mapchan(&hchan, chan); 5027 5028 DPRINTF(sc, ATH_DEBUG_RESET, 5029 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 5030 __func__, 5031 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 5032 sc->sc_curchan.channelFlags), 5033 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 5034 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 5035 hchan.channel, hchan.channelFlags); 5036 if (hchan.channel != sc->sc_curchan.channel || 5037 hchan.channelFlags != sc->sc_curchan.channelFlags) { 5038 HAL_STATUS status; 5039 5040 /* 5041 * To switch channels clear any pending DMA operations; 5042 * wait long enough for the RX fifo to drain, reset the 5043 * hardware at the new frequency, and then re-enable 5044 * the relevant bits of the h/w. 5045 */ 5046 ath_hal_intrset(ah, 0); /* disable interrupts */ 5047 ath_draintxq(sc); /* clear pending tx frames */ 5048 ath_stoprecv(sc); /* turn off frame recv */ 5049 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) { 5050 if_printf(ic->ic_ifp, "%s: unable to reset " 5051 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x)\n", 5052 __func__, ieee80211_chan2ieee(ic, chan), 5053 chan->ic_freq, chan->ic_flags, hchan.channelFlags); 5054 return EIO; 5055 } 5056 sc->sc_curchan = hchan; 5057 ath_update_txpow(sc); /* update tx power state */ 5058 sc->sc_diversity = ath_hal_getdiversity(ah); 5059 sc->sc_calinterval = 1; 5060 sc->sc_caltries = 0; 5061 5062 /* 5063 * Re-enable rx framework. 5064 */ 5065 if (ath_startrecv(sc) != 0) { 5066 if_printf(ic->ic_ifp, 5067 "%s: unable to restart recv logic\n", __func__); 5068 return EIO; 5069 } 5070 5071 /* 5072 * Change channels and update the h/w rate map 5073 * if we're switching; e.g. 11a to 11b/g. 5074 */ 5075 ath_chan_change(sc, chan); 5076 5077 /* 5078 * Handle DFS required waiting period to determine 5079 * if channel is clear of radar traffic. 5080 */ 5081 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 5082 #define DFS_AND_NOT_CLEAR(_c) \ 5083 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS) 5084 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) { 5085 if_printf(sc->sc_ifp, 5086 "wait for DFS clear channel signal\n"); 5087 /* XXX stop sndq */ 5088 sc->sc_ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5089 callout_reset(&sc->sc_dfs_ch, 5090 2 * hz, ath_dfswait, sc); 5091 } else 5092 callout_stop(&sc->sc_dfs_ch); 5093 #undef DFS_NOT_CLEAR 5094 } 5095 5096 /* 5097 * Re-enable interrupts. 5098 */ 5099 ath_hal_intrset(ah, sc->sc_imask); 5100 } 5101 return 0; 5102 } 5103 5104 /* 5105 * Periodically recalibrate the PHY to account 5106 * for temperature/environment changes. 5107 */ 5108 static void 5109 ath_calibrate(void *arg) 5110 { 5111 struct ath_softc *sc = arg; 5112 struct ath_hal *ah = sc->sc_ah; 5113 HAL_BOOL iqCalDone; 5114 5115 sc->sc_stats.ast_per_cal++; 5116 5117 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5118 /* 5119 * Rfgain is out of bounds, reset the chip 5120 * to load new gain values. 5121 */ 5122 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5123 "%s: rfgain change\n", __func__); 5124 sc->sc_stats.ast_per_rfgain++; 5125 ath_reset(sc->sc_ifp); 5126 } 5127 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 5128 DPRINTF(sc, ATH_DEBUG_ANY, 5129 "%s: calibration of channel %u failed\n", 5130 __func__, sc->sc_curchan.channel); 5131 sc->sc_stats.ast_per_calfail++; 5132 } 5133 /* 5134 * Calibrate noise floor data again in case of change. 5135 */ 5136 ath_hal_process_noisefloor(ah); 5137 /* 5138 * Poll more frequently when the IQ calibration is in 5139 * progress to speedup loading the final settings. 5140 * We temper this aggressive polling with an exponential 5141 * back off after 4 tries up to ath_calinterval. 5142 */ 5143 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 5144 sc->sc_caltries = 0; 5145 sc->sc_calinterval = ath_calinterval; 5146 } else if (sc->sc_caltries > 4) { 5147 sc->sc_caltries = 0; 5148 sc->sc_calinterval <<= 1; 5149 if (sc->sc_calinterval > ath_calinterval) 5150 sc->sc_calinterval = ath_calinterval; 5151 } 5152 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 5153 ("bad calibration interval %u", sc->sc_calinterval)); 5154 5155 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5156 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 5157 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 5158 sc->sc_caltries++; 5159 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 5160 ath_calibrate, sc); 5161 } 5162 5163 static void 5164 ath_scan_start(struct ieee80211com *ic) 5165 { 5166 struct ifnet *ifp = ic->ic_ifp; 5167 struct ath_softc *sc = ifp->if_softc; 5168 struct ath_hal *ah = sc->sc_ah; 5169 u_int32_t rfilt; 5170 5171 /* XXX calibration timer? */ 5172 5173 sc->sc_scanning = 1; 5174 sc->sc_syncbeacon = 0; 5175 rfilt = ath_calcrxfilter(sc); 5176 ath_hal_setrxfilter(ah, rfilt); 5177 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 5178 5179 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5180 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 5181 } 5182 5183 static void 5184 ath_scan_end(struct ieee80211com *ic) 5185 { 5186 struct ifnet *ifp = ic->ic_ifp; 5187 struct ath_softc *sc = ifp->if_softc; 5188 struct ath_hal *ah = sc->sc_ah; 5189 u_int32_t rfilt; 5190 5191 sc->sc_scanning = 0; 5192 rfilt = ath_calcrxfilter(sc); 5193 ath_hal_setrxfilter(ah, rfilt); 5194 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5195 5196 ath_hal_process_noisefloor(ah); 5197 5198 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5199 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5200 sc->sc_curaid); 5201 } 5202 5203 static void 5204 ath_set_channel(struct ieee80211com *ic) 5205 { 5206 struct ifnet *ifp = ic->ic_ifp; 5207 struct ath_softc *sc = ifp->if_softc; 5208 5209 (void) ath_chan_set(sc, ic->ic_curchan); 5210 /* 5211 * If we are returning to our bss channel then mark state 5212 * so the next recv'd beacon's tsf will be used to sync the 5213 * beacon timers. Note that since we only hear beacons in 5214 * sta/ibss mode this has no effect in other operating modes. 5215 */ 5216 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5217 sc->sc_syncbeacon = 1; 5218 } 5219 5220 static int 5221 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 5222 { 5223 struct ifnet *ifp = ic->ic_ifp; 5224 struct ath_softc *sc = ifp->if_softc; 5225 struct ath_hal *ah = sc->sc_ah; 5226 struct ieee80211_node *ni; 5227 int i, error, stamode; 5228 u_int32_t rfilt; 5229 static const HAL_LED_STATE leds[] = { 5230 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5231 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5232 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5233 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5234 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5235 }; 5236 5237 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5238 ieee80211_state_name[ic->ic_state], 5239 ieee80211_state_name[nstate]); 5240 5241 callout_stop(&sc->sc_cal_ch); 5242 callout_stop(&sc->sc_dfs_ch); 5243 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5244 5245 if (nstate == IEEE80211_S_INIT) { 5246 /* 5247 * Shutdown host/driver operation: 5248 * o disable interrupts so we don't rx frames 5249 * o clean any pending items on the task q 5250 * o notify the rate control algorithm 5251 */ 5252 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5253 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5254 #if 0 5255 /* XXX can't use taskqueue_drain 'cuz we're holding sc_mtx */ 5256 taskqueue_drain(sc->sc_tq, &sc->sc_rxtask); 5257 taskqueue_drain(sc->sc_tq, &sc->sc_rxorntask); 5258 taskqueue_drain(sc->sc_tq, &sc->sc_bmisstask); 5259 taskqueue_drain(sc->sc_tq, &sc->sc_bstucktask); 5260 #endif 5261 ath_rate_newstate(sc, nstate); 5262 goto done; 5263 } 5264 ni = ic->ic_bss; 5265 5266 rfilt = ath_calcrxfilter(sc); 5267 stamode = (sc->sc_opmode == HAL_M_STA || sc->sc_opmode == HAL_M_IBSS); 5268 if (stamode && nstate == IEEE80211_S_RUN) { 5269 sc->sc_curaid = ni->ni_associd; 5270 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5271 } else 5272 sc->sc_curaid = 0; 5273 5274 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5275 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5276 sc->sc_curaid); 5277 5278 ath_hal_setrxfilter(ah, rfilt); 5279 if (stamode) 5280 ath_hal_setassocid(ah, sc->sc_curbssid, ni->ni_associd); 5281 5282 if (ic->ic_opmode != IEEE80211_M_STA && 5283 (ic->ic_flags & IEEE80211_F_PRIVACY)) { 5284 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5285 if (ath_hal_keyisvalid(ah, i)) 5286 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5287 } 5288 5289 /* 5290 * Notify the rate control algorithm so rates 5291 * are setup should ath_beacon_alloc be called. 5292 */ 5293 ath_rate_newstate(sc, nstate); 5294 5295 if (nstate == IEEE80211_S_RUN) { 5296 DPRINTF(sc, ATH_DEBUG_STATE, 5297 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 5298 "capinfo=0x%04x chan=%d\n" 5299 , __func__ 5300 , ic->ic_flags 5301 , ni->ni_intval 5302 , ether_sprintf(ni->ni_bssid) 5303 , ni->ni_capinfo 5304 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 5305 5306 switch (ic->ic_opmode) { 5307 case IEEE80211_M_HOSTAP: 5308 case IEEE80211_M_IBSS: 5309 /* 5310 * Allocate and setup the beacon frame. 5311 * 5312 * Stop any previous beacon DMA. This may be 5313 * necessary, for example, when an ibss merge 5314 * causes reconfiguration; there will be a state 5315 * transition from RUN->RUN that means we may 5316 * be called with beacon transmission active. 5317 */ 5318 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5319 ath_beacon_free(sc); 5320 error = ath_beacon_alloc(sc, ni); 5321 if (error != 0) 5322 goto bad; 5323 /* 5324 * If joining an adhoc network defer beacon timer 5325 * configuration to the next beacon frame so we 5326 * have a current TSF to use. Otherwise we're 5327 * starting an ibss/bss so there's no need to delay. 5328 */ 5329 if (ic->ic_opmode == IEEE80211_M_IBSS && 5330 ic->ic_bss->ni_tstamp.tsf != 0) 5331 sc->sc_syncbeacon = 1; 5332 else 5333 ath_beacon_config(sc); 5334 break; 5335 case IEEE80211_M_STA: 5336 /* 5337 * Allocate a key cache slot to the station. 5338 */ 5339 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 5340 sc->sc_hasclrkey && 5341 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5342 ath_setup_stationkey(ni); 5343 /* 5344 * Defer beacon timer configuration to the next 5345 * beacon frame so we have a current TSF to use 5346 * (any TSF collected when scanning is likely old). 5347 */ 5348 sc->sc_syncbeacon = 1; 5349 break; 5350 default: 5351 break; 5352 } 5353 /* 5354 * Let the hal process statistics collected during a 5355 * scan so it can provide calibrated noise floor data. 5356 */ 5357 ath_hal_process_noisefloor(ah); 5358 /* 5359 * Reset rssi stats; maybe not the best place... 5360 */ 5361 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5362 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5363 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5364 } else { 5365 ath_hal_intrset(ah, 5366 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5367 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5368 } 5369 done: 5370 /* 5371 * Invoke the parent method to complete the work. 5372 */ 5373 error = sc->sc_newstate(ic, nstate, arg); 5374 /* 5375 * Finally, start any timers. 5376 */ 5377 if (nstate == IEEE80211_S_RUN) { 5378 /* start periodic recalibration timer */ 5379 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 5380 ath_calibrate, sc); 5381 } 5382 bad: 5383 return error; 5384 } 5385 5386 /* 5387 * Allocate a key cache slot to the station so we can 5388 * setup a mapping from key index to node. The key cache 5389 * slot is needed for managing antenna state and for 5390 * compression when stations do not use crypto. We do 5391 * it uniliaterally here; if crypto is employed this slot 5392 * will be reassigned. 5393 */ 5394 static void 5395 ath_setup_stationkey(struct ieee80211_node *ni) 5396 { 5397 struct ieee80211com *ic = ni->ni_ic; 5398 struct ath_softc *sc = ic->ic_ifp->if_softc; 5399 ieee80211_keyix keyix, rxkeyix; 5400 5401 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5402 /* 5403 * Key cache is full; we'll fall back to doing 5404 * the more expensive lookup in software. Note 5405 * this also means no h/w compression. 5406 */ 5407 /* XXX msg+statistic */ 5408 } else { 5409 /* XXX locking? */ 5410 ni->ni_ucastkey.wk_keyix = keyix; 5411 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5412 /* NB: this will create a pass-thru key entry */ 5413 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 5414 } 5415 } 5416 5417 /* 5418 * Setup driver-specific state for a newly associated node. 5419 * Note that we're called also on a re-associate, the isnew 5420 * param tells us if this is the first time or not. 5421 */ 5422 static void 5423 ath_newassoc(struct ieee80211_node *ni, int isnew) 5424 { 5425 struct ieee80211com *ic = ni->ni_ic; 5426 struct ath_softc *sc = ic->ic_ifp->if_softc; 5427 5428 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 5429 if (isnew && 5430 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 5431 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 5432 ("new assoc with a unicast key already setup (keyix %u)", 5433 ni->ni_ucastkey.wk_keyix)); 5434 ath_setup_stationkey(ni); 5435 } 5436 } 5437 5438 static int 5439 ath_getchannels(struct ath_softc *sc, 5440 HAL_REG_DOMAIN rd, HAL_CTRY_CODE cc, HAL_BOOL outdoor, HAL_BOOL xchanmode) 5441 { 5442 struct ieee80211com *ic = &sc->sc_ic; 5443 struct ifnet *ifp = sc->sc_ifp; 5444 struct ath_hal *ah = sc->sc_ah; 5445 HAL_CHANNEL *chans; 5446 int i, nchan; 5447 u_int32_t regdomain; 5448 5449 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 5450 M_TEMP, M_NOWAIT); 5451 if (chans == NULL) { 5452 if_printf(ifp, "unable to allocate channel table\n"); 5453 return ENOMEM; 5454 } 5455 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 5456 NULL, 0, NULL, cc, HAL_MODE_ALL, outdoor, xchanmode)) { 5457 (void) ath_hal_getregdomain(ah, ®domain); 5458 if_printf(ifp, "unable to collect channel list from hal; " 5459 "regdomain likely %u country code %u\n", regdomain, cc); 5460 free(chans, M_TEMP); 5461 return EINVAL; 5462 } 5463 5464 /* 5465 * Convert HAL channels to ieee80211 ones. 5466 */ 5467 memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); 5468 for (i = 0; i < nchan; i++) { 5469 HAL_CHANNEL *c = &chans[i]; 5470 struct ieee80211_channel *ichan = &ic->ic_channels[i]; 5471 5472 ichan->ic_ieee = ath_hal_mhz2ieee(ah, c->channel, 5473 c->channelFlags); 5474 if (bootverbose) 5475 if_printf(ifp, "hal channel %u/%x -> %u\n", 5476 c->channel, c->channelFlags, ichan->ic_ieee); 5477 ichan->ic_freq = c->channel; 5478 5479 if ((c->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) { 5480 /* 5481 * Except for AR5211, HAL's PUREG means mixed 5482 * DSSS and OFDM. 5483 */ 5484 ichan->ic_flags = c->channelFlags &~ CHANNEL_PUREG; 5485 ichan->ic_flags |= IEEE80211_CHAN_G; 5486 } else { 5487 ichan->ic_flags = c->channelFlags; 5488 } 5489 5490 if (ath_hal_isgsmsku(ah)) { 5491 /* remap to true frequencies */ 5492 ichan->ic_freq = 922 + (2422 - ichan->ic_freq); 5493 ichan->ic_flags |= IEEE80211_CHAN_GSM; 5494 ichan->ic_ieee = ieee80211_mhz2ieee(ichan->ic_freq, 5495 ichan->ic_flags); 5496 } 5497 ichan->ic_maxregpower = c->maxRegTxPower; /* dBm */ 5498 ichan->ic_maxpower = c->maxTxPower; /* 1/2 dBm */ 5499 ichan->ic_minpower = c->minTxPower; /* 1/2 dBm */ 5500 } 5501 ic->ic_nchans = nchan; 5502 free(chans, M_TEMP); 5503 (void) ath_hal_getregdomain(ah, &sc->sc_regdomain); 5504 ath_hal_getcountrycode(ah, &sc->sc_countrycode); 5505 sc->sc_xchanmode = xchanmode; 5506 sc->sc_outdoor = outdoor; 5507 return 0; 5508 } 5509 5510 static void 5511 ath_led_done(void *arg) 5512 { 5513 struct ath_softc *sc = arg; 5514 5515 sc->sc_blinking = 0; 5516 } 5517 5518 /* 5519 * Turn the LED off: flip the pin and then set a timer so no 5520 * update will happen for the specified duration. 5521 */ 5522 static void 5523 ath_led_off(void *arg) 5524 { 5525 struct ath_softc *sc = arg; 5526 5527 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5528 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 5529 } 5530 5531 /* 5532 * Blink the LED according to the specified on/off times. 5533 */ 5534 static void 5535 ath_led_blink(struct ath_softc *sc, int on, int off) 5536 { 5537 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 5538 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 5539 sc->sc_blinking = 1; 5540 sc->sc_ledoff = off; 5541 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 5542 } 5543 5544 static void 5545 ath_led_event(struct ath_softc *sc, int event) 5546 { 5547 5548 sc->sc_ledevent = ticks; /* time of last event */ 5549 if (sc->sc_blinking) /* don't interrupt active blink */ 5550 return; 5551 switch (event) { 5552 case ATH_LED_POLL: 5553 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 5554 sc->sc_hwmap[0].ledoff); 5555 break; 5556 case ATH_LED_TX: 5557 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 5558 sc->sc_hwmap[sc->sc_txrate].ledoff); 5559 break; 5560 case ATH_LED_RX: 5561 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 5562 sc->sc_hwmap[sc->sc_rxrate].ledoff); 5563 break; 5564 } 5565 } 5566 5567 static void 5568 ath_update_txpow(struct ath_softc *sc) 5569 { 5570 struct ieee80211com *ic = &sc->sc_ic; 5571 struct ath_hal *ah = sc->sc_ah; 5572 u_int32_t txpow; 5573 5574 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 5575 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 5576 /* read back in case value is clamped */ 5577 if (ath_hal_gettxpowlimit(ah, &txpow)) 5578 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 5579 } 5580 /* 5581 * Fetch max tx power level for status requests. 5582 */ 5583 if (ath_hal_getmaxtxpow(sc->sc_ah, &txpow)) 5584 ic->ic_bss->ni_txpower = txpow; 5585 } 5586 5587 static int 5588 ath_rate_setup(struct ath_softc *sc, u_int mode) 5589 { 5590 struct ath_hal *ah = sc->sc_ah; 5591 const HAL_RATE_TABLE *rt; 5592 5593 switch (mode) { 5594 case IEEE80211_MODE_11A: 5595 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5596 break; 5597 case IEEE80211_MODE_HALF: 5598 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 5599 break; 5600 case IEEE80211_MODE_QUARTER: 5601 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 5602 break; 5603 case IEEE80211_MODE_11B: 5604 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5605 break; 5606 case IEEE80211_MODE_11G: 5607 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5608 break; 5609 case IEEE80211_MODE_TURBO_A: 5610 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 5611 break; 5612 case IEEE80211_MODE_TURBO_G: 5613 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5614 break; 5615 case IEEE80211_MODE_STURBO_A: 5616 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5617 break; 5618 case IEEE80211_MODE_11NA: 5619 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 5620 break; 5621 case IEEE80211_MODE_11NG: 5622 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 5623 break; 5624 default: 5625 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5626 __func__, mode); 5627 return 0; 5628 } 5629 sc->sc_rates[mode] = rt; 5630 return (rt != NULL); 5631 } 5632 5633 static void 5634 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5635 { 5636 #define N(a) (sizeof(a)/sizeof(a[0])) 5637 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5638 static const struct { 5639 u_int rate; /* tx/rx 802.11 rate */ 5640 u_int16_t timeOn; /* LED on time (ms) */ 5641 u_int16_t timeOff; /* LED off time (ms) */ 5642 } blinkrates[] = { 5643 { 108, 40, 10 }, 5644 { 96, 44, 11 }, 5645 { 72, 50, 13 }, 5646 { 48, 57, 14 }, 5647 { 36, 67, 16 }, 5648 { 24, 80, 20 }, 5649 { 22, 100, 25 }, 5650 { 18, 133, 34 }, 5651 { 12, 160, 40 }, 5652 { 10, 200, 50 }, 5653 { 6, 240, 58 }, 5654 { 4, 267, 66 }, 5655 { 2, 400, 100 }, 5656 { 0, 500, 130 }, 5657 /* XXX half/quarter rates */ 5658 }; 5659 const HAL_RATE_TABLE *rt; 5660 int i, j; 5661 5662 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5663 rt = sc->sc_rates[mode]; 5664 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5665 for (i = 0; i < rt->rateCount; i++) 5666 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 5667 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5668 for (i = 0; i < 32; i++) { 5669 u_int8_t ix = rt->rateCodeToIndex[i]; 5670 if (ix == 0xff) { 5671 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5672 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5673 continue; 5674 } 5675 sc->sc_hwmap[i].ieeerate = 5676 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 5677 if (rt->info[ix].phy == IEEE80211_T_HT) 5678 sc->sc_hwmap[i].ieeerate |= 0x80; /* MCS */ 5679 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 5680 if (rt->info[ix].shortPreamble || 5681 rt->info[ix].phy == IEEE80211_T_OFDM) 5682 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 5683 /* NB: receive frames include FCS */ 5684 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 5685 IEEE80211_RADIOTAP_F_FCS; 5686 /* setup blink rate table to avoid per-packet lookup */ 5687 for (j = 0; j < N(blinkrates)-1; j++) 5688 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 5689 break; 5690 /* NB: this uses the last entry if the rate isn't found */ 5691 /* XXX beware of overlow */ 5692 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 5693 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 5694 } 5695 sc->sc_currates = rt; 5696 sc->sc_curmode = mode; 5697 /* 5698 * All protection frames are transmited at 2Mb/s for 5699 * 11g, otherwise at 1Mb/s. 5700 */ 5701 if (mode == IEEE80211_MODE_11G) 5702 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 5703 else 5704 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 5705 /* rate index used to send management frames */ 5706 sc->sc_minrateix = 0; 5707 /* 5708 * Setup multicast rate state. 5709 */ 5710 /* XXX layering violation */ 5711 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate); 5712 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate; 5713 /* NB: caller is responsible for reseting rate control state */ 5714 #undef N 5715 } 5716 5717 #ifdef ATH_DEBUG 5718 static void 5719 ath_printrxbuf(const struct ath_buf *bf, u_int ix, int done) 5720 { 5721 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5722 const struct ath_desc *ds; 5723 int i; 5724 5725 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5726 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 5727 " %08x %08x %08x %08x\n", 5728 ix, ds, (const struct ath_desc *)bf->bf_daddr + i, 5729 ds->ds_link, ds->ds_data, 5730 !done ? "" : (rs->rs_status == 0) ? " *" : " !", 5731 ds->ds_ctl0, ds->ds_ctl1, 5732 ds->ds_hw[0], ds->ds_hw[1]); 5733 } 5734 } 5735 5736 static void 5737 ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done) 5738 { 5739 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 5740 const struct ath_desc *ds; 5741 int i; 5742 5743 printf("Q%u[%3u]", qnum, ix); 5744 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 5745 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 5746 " %08x %08x %08x %08x %08x %08x\n", 5747 ds, (const struct ath_desc *)bf->bf_daddr + i, 5748 ds->ds_link, ds->ds_data, bf->bf_flags, 5749 !done ? "" : (ts->ts_status == 0) ? " *" : " !", 5750 ds->ds_ctl0, ds->ds_ctl1, 5751 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 5752 } 5753 } 5754 #endif /* ATH_DEBUG */ 5755 5756 static void 5757 ath_watchdog(struct ifnet *ifp) 5758 { 5759 struct ath_softc *sc = ifp->if_softc; 5760 5761 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && !sc->sc_invalid) { 5762 if_printf(ifp, "device timeout\n"); 5763 ath_reset(ifp); 5764 ifp->if_oerrors++; 5765 sc->sc_stats.ast_watchdog++; 5766 } 5767 } 5768 5769 #ifdef ATH_DIAGAPI 5770 /* 5771 * Diagnostic interface to the HAL. This is used by various 5772 * tools to do things like retrieve register contents for 5773 * debugging. The mechanism is intentionally opaque so that 5774 * it can change frequently w/o concern for compatiblity. 5775 */ 5776 static int 5777 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 5778 { 5779 struct ath_hal *ah = sc->sc_ah; 5780 u_int id = ad->ad_id & ATH_DIAG_ID; 5781 void *indata = NULL; 5782 void *outdata = NULL; 5783 u_int32_t insize = ad->ad_in_size; 5784 u_int32_t outsize = ad->ad_out_size; 5785 int error = 0; 5786 5787 if (ad->ad_id & ATH_DIAG_IN) { 5788 /* 5789 * Copy in data. 5790 */ 5791 indata = malloc(insize, M_TEMP, M_NOWAIT); 5792 if (indata == NULL) { 5793 error = ENOMEM; 5794 goto bad; 5795 } 5796 error = copyin(ad->ad_in_data, indata, insize); 5797 if (error) 5798 goto bad; 5799 } 5800 if (ad->ad_id & ATH_DIAG_DYN) { 5801 /* 5802 * Allocate a buffer for the results (otherwise the HAL 5803 * returns a pointer to a buffer where we can read the 5804 * results). Note that we depend on the HAL leaving this 5805 * pointer for us to use below in reclaiming the buffer; 5806 * may want to be more defensive. 5807 */ 5808 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 5809 if (outdata == NULL) { 5810 error = ENOMEM; 5811 goto bad; 5812 } 5813 } 5814 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 5815 if (outsize < ad->ad_out_size) 5816 ad->ad_out_size = outsize; 5817 if (outdata != NULL) 5818 error = copyout(outdata, ad->ad_out_data, 5819 ad->ad_out_size); 5820 } else { 5821 error = EINVAL; 5822 } 5823 bad: 5824 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 5825 free(indata, M_TEMP); 5826 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 5827 free(outdata, M_TEMP); 5828 return error; 5829 } 5830 #endif /* ATH_DIAGAPI */ 5831 5832 static int 5833 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 5834 { 5835 #define IS_RUNNING(ifp) \ 5836 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 5837 struct ath_softc *sc = ifp->if_softc; 5838 struct ieee80211com *ic = &sc->sc_ic; 5839 struct ifreq *ifr = (struct ifreq *)data; 5840 int error = 0; 5841 5842 ATH_LOCK(sc); 5843 switch (cmd) { 5844 case SIOCSIFFLAGS: 5845 if (IS_RUNNING(ifp)) { 5846 /* 5847 * To avoid rescanning another access point, 5848 * do not call ath_init() here. Instead, 5849 * only reflect promisc mode settings. 5850 */ 5851 ath_mode_init(sc); 5852 } else if (ifp->if_flags & IFF_UP) { 5853 /* 5854 * Beware of being called during attach/detach 5855 * to reset promiscuous mode. In that case we 5856 * will still be marked UP but not RUNNING. 5857 * However trying to re-init the interface 5858 * is the wrong thing to do as we've already 5859 * torn down much of our state. There's 5860 * probably a better way to deal with this. 5861 */ 5862 if (!sc->sc_invalid && ic->ic_bss != NULL) 5863 ath_init(sc); /* XXX lose error */ 5864 } else 5865 ath_stop_locked(ifp); 5866 break; 5867 case SIOCADDMULTI: 5868 case SIOCDELMULTI: 5869 /* 5870 * The upper layer has already installed/removed 5871 * the multicast address(es), just recalculate the 5872 * multicast filter for the card. 5873 */ 5874 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5875 ath_mode_init(sc); 5876 break; 5877 case SIOCGATHSTATS: 5878 /* NB: embed these numbers to get a consistent view */ 5879 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 5880 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 5881 ieee80211_getsignal(ic, &sc->sc_stats.ast_rx_rssi, 5882 &sc->sc_stats.ast_rx_noise); 5883 sc->sc_stats.ast_tx_rate = sc->sc_hwmap[sc->sc_txrate].ieeerate; 5884 ATH_UNLOCK(sc); 5885 /* 5886 * NB: Drop the softc lock in case of a page fault; 5887 * we'll accept any potential inconsisentcy in the 5888 * statistics. The alternative is to copy the data 5889 * to a local structure. 5890 */ 5891 return copyout(&sc->sc_stats, 5892 ifr->ifr_data, sizeof (sc->sc_stats)); 5893 #ifdef ATH_DIAGAPI 5894 case SIOCGATHDIAG: 5895 ATH_UNLOCK(sc); 5896 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 5897 ATH_LOCK(sc); 5898 break; 5899 #endif 5900 default: 5901 error = ieee80211_ioctl(ic, cmd, data); 5902 if (error == ENETRESET) { 5903 if (IS_RUNNING(ifp) && 5904 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5905 ath_init(sc); /* XXX lose error */ 5906 error = 0; 5907 } 5908 if (error == ERESTART) 5909 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 5910 break; 5911 } 5912 ATH_UNLOCK(sc); 5913 return error; 5914 #undef IS_RUNNING 5915 } 5916 5917 static int 5918 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 5919 { 5920 struct ath_softc *sc = arg1; 5921 u_int slottime = ath_hal_getslottime(sc->sc_ah); 5922 int error; 5923 5924 error = sysctl_handle_int(oidp, &slottime, 0, req); 5925 if (error || !req->newptr) 5926 return error; 5927 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 5928 } 5929 5930 static int 5931 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 5932 { 5933 struct ath_softc *sc = arg1; 5934 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 5935 int error; 5936 5937 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 5938 if (error || !req->newptr) 5939 return error; 5940 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 5941 } 5942 5943 static int 5944 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 5945 { 5946 struct ath_softc *sc = arg1; 5947 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 5948 int error; 5949 5950 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 5951 if (error || !req->newptr) 5952 return error; 5953 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 5954 } 5955 5956 static int 5957 ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 5958 { 5959 struct ath_softc *sc = arg1; 5960 int softled = sc->sc_softled; 5961 int error; 5962 5963 error = sysctl_handle_int(oidp, &softled, 0, req); 5964 if (error || !req->newptr) 5965 return error; 5966 softled = (softled != 0); 5967 if (softled != sc->sc_softled) { 5968 if (softled) { 5969 /* NB: handle any sc_ledpin change */ 5970 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 5971 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 5972 !sc->sc_ledon); 5973 } 5974 sc->sc_softled = softled; 5975 } 5976 return 0; 5977 } 5978 5979 static int 5980 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) 5981 { 5982 struct ath_softc *sc = arg1; 5983 int ledpin = sc->sc_ledpin; 5984 int error; 5985 5986 error = sysctl_handle_int(oidp, &ledpin, 0, req); 5987 if (error || !req->newptr) 5988 return error; 5989 if (ledpin != sc->sc_ledpin) { 5990 sc->sc_ledpin = ledpin; 5991 if (sc->sc_softled) { 5992 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 5993 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 5994 !sc->sc_ledon); 5995 } 5996 } 5997 return 0; 5998 } 5999 6000 static int 6001 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) 6002 { 6003 struct ath_softc *sc = arg1; 6004 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah); 6005 int error; 6006 6007 error = sysctl_handle_int(oidp, &txantenna, 0, req); 6008 if (!error && req->newptr) { 6009 /* XXX assumes 2 antenna ports */ 6010 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B) 6011 return EINVAL; 6012 ath_hal_setantennaswitch(sc->sc_ah, txantenna); 6013 /* 6014 * NB: with the switch locked this isn't meaningful, 6015 * but set it anyway so things like radiotap get 6016 * consistent info in their data. 6017 */ 6018 sc->sc_txantenna = txantenna; 6019 } 6020 return error; 6021 } 6022 6023 static int 6024 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 6025 { 6026 struct ath_softc *sc = arg1; 6027 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 6028 int error; 6029 6030 error = sysctl_handle_int(oidp, &defantenna, 0, req); 6031 if (!error && req->newptr) 6032 ath_hal_setdefantenna(sc->sc_ah, defantenna); 6033 return error; 6034 } 6035 6036 static int 6037 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 6038 { 6039 struct ath_softc *sc = arg1; 6040 u_int diversity = ath_hal_getdiversity(sc->sc_ah); 6041 int error; 6042 6043 error = sysctl_handle_int(oidp, &diversity, 0, req); 6044 if (error || !req->newptr) 6045 return error; 6046 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 6047 return EINVAL; 6048 sc->sc_diversity = diversity; 6049 return 0; 6050 } 6051 6052 static int 6053 ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 6054 { 6055 struct ath_softc *sc = arg1; 6056 u_int32_t diag; 6057 int error; 6058 6059 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 6060 return EINVAL; 6061 error = sysctl_handle_int(oidp, &diag, 0, req); 6062 if (error || !req->newptr) 6063 return error; 6064 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 6065 } 6066 6067 static int 6068 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 6069 { 6070 struct ath_softc *sc = arg1; 6071 struct ifnet *ifp = sc->sc_ifp; 6072 u_int32_t scale; 6073 int error; 6074 6075 (void) ath_hal_gettpscale(sc->sc_ah, &scale); 6076 error = sysctl_handle_int(oidp, &scale, 0, req); 6077 if (error || !req->newptr) 6078 return error; 6079 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : 6080 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6081 } 6082 6083 static int 6084 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 6085 { 6086 struct ath_softc *sc = arg1; 6087 u_int tpc = ath_hal_gettpc(sc->sc_ah); 6088 int error; 6089 6090 error = sysctl_handle_int(oidp, &tpc, 0, req); 6091 if (error || !req->newptr) 6092 return error; 6093 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 6094 } 6095 6096 static int 6097 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 6098 { 6099 struct ath_softc *sc = arg1; 6100 struct ifnet *ifp = sc->sc_ifp; 6101 struct ath_hal *ah = sc->sc_ah; 6102 u_int rfkill = ath_hal_getrfkill(ah); 6103 int error; 6104 6105 error = sysctl_handle_int(oidp, &rfkill, 0, req); 6106 if (error || !req->newptr) 6107 return error; 6108 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */ 6109 return 0; 6110 if (!ath_hal_setrfkill(ah, rfkill)) 6111 return EINVAL; 6112 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6113 } 6114 6115 static int 6116 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 6117 { 6118 struct ath_softc *sc = arg1; 6119 u_int rfsilent; 6120 int error; 6121 6122 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 6123 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 6124 if (error || !req->newptr) 6125 return error; 6126 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) 6127 return EINVAL; 6128 sc->sc_rfsilentpin = rfsilent & 0x1c; 6129 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 6130 return 0; 6131 } 6132 6133 static int 6134 ath_sysctl_countrycode(SYSCTL_HANDLER_ARGS) 6135 { 6136 struct ath_softc *sc = arg1; 6137 u_int32_t cc = sc->sc_countrycode; 6138 struct ieee80211com *ic = &sc->sc_ic; 6139 int error; 6140 6141 error = sysctl_handle_int(oidp, &cc, 0, req); 6142 if (error || !req->newptr) 6143 return error; 6144 error = ath_getchannels(sc, sc->sc_regdomain, cc, 6145 sc->sc_outdoor != 0, sc->sc_xchanmode != 0); 6146 if (error != 0) 6147 return error; 6148 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 6149 /* setcurmode? */ 6150 return 0; 6151 } 6152 6153 static int 6154 ath_sysctl_regdomain(SYSCTL_HANDLER_ARGS) 6155 { 6156 struct ath_softc *sc = arg1; 6157 u_int32_t rd = sc->sc_regdomain; 6158 struct ieee80211com *ic = &sc->sc_ic; 6159 int error; 6160 6161 error = sysctl_handle_int(oidp, &rd, 0, req); 6162 if (error || !req->newptr) 6163 return error; 6164 if (!ath_hal_setregdomain(sc->sc_ah, rd)) 6165 return EINVAL; 6166 error = ath_getchannels(sc, rd, sc->sc_countrycode, 6167 sc->sc_outdoor != 0, sc->sc_xchanmode != 0); 6168 if (error != 0) 6169 return error; 6170 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 6171 /* setcurmode? */ 6172 return 0; 6173 } 6174 6175 static int 6176 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 6177 { 6178 struct ath_softc *sc = arg1; 6179 u_int32_t tpack; 6180 int error; 6181 6182 (void) ath_hal_gettpack(sc->sc_ah, &tpack); 6183 error = sysctl_handle_int(oidp, &tpack, 0, req); 6184 if (error || !req->newptr) 6185 return error; 6186 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0; 6187 } 6188 6189 static int 6190 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 6191 { 6192 struct ath_softc *sc = arg1; 6193 u_int32_t tpcts; 6194 int error; 6195 6196 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts); 6197 error = sysctl_handle_int(oidp, &tpcts, 0, req); 6198 if (error || !req->newptr) 6199 return error; 6200 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0; 6201 } 6202 6203 static void 6204 ath_sysctlattach(struct ath_softc *sc) 6205 { 6206 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 6207 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 6208 struct ath_hal *ah = sc->sc_ah; 6209 6210 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6211 "countrycode", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6212 ath_sysctl_countrycode, "I", "country code"); 6213 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6214 "regdomain", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6215 ath_sysctl_regdomain, "I", "EEPROM regdomain code"); 6216 #ifdef ATH_DEBUG 6217 sc->sc_debug = ath_debug; 6218 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6219 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 6220 "control debugging printfs"); 6221 #endif 6222 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6223 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6224 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 6225 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6226 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6227 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 6228 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6229 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6230 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 6231 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6232 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6233 ath_sysctl_softled, "I", "enable/disable software LED support"); 6234 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6235 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6236 ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); 6237 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6238 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 6239 "setting to turn LED on"); 6240 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6241 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 6242 "idle time for inactivity LED (ticks)"); 6243 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6244 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6245 ath_sysctl_txantenna, "I", "antenna switch"); 6246 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6247 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6248 ath_sysctl_rxantenna, "I", "default/rx antenna"); 6249 if (ath_hal_hasdiversity(ah)) 6250 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6251 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6252 ath_sysctl_diversity, "I", "antenna diversity"); 6253 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 6254 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6255 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 6256 "tx descriptor batching"); 6257 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6258 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6259 ath_sysctl_diag, "I", "h/w diagnostic control"); 6260 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6261 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6262 ath_sysctl_tpscale, "I", "tx power scaling"); 6263 if (ath_hal_hastpc(ah)) { 6264 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6265 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6266 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 6267 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6268 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6269 ath_sysctl_tpack, "I", "tx power for ack frames"); 6270 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6271 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6272 ath_sysctl_tpcts, "I", "tx power for cts frames"); 6273 } 6274 if (ath_hal_hasfastframes(sc->sc_ah)) { 6275 sc->sc_fftxqmin = ATH_FF_TXQMIN; 6276 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6277 "fftxqmin", CTLFLAG_RW, &sc->sc_fftxqmin, 0, 6278 "min frames before fast-frame staging"); 6279 sc->sc_fftxqmax = ATH_FF_TXQMAX; 6280 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6281 "fftxqmax", CTLFLAG_RW, &sc->sc_fftxqmax, 0, 6282 "max queued frames before tail drop"); 6283 } 6284 if (ath_hal_hasrfsilent(ah)) { 6285 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6286 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6287 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 6288 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6289 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6290 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 6291 } 6292 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 6293 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6294 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 6295 "mask of error frames to pass when monitoring"); 6296 } 6297 6298 static void 6299 ath_bpfattach(struct ath_softc *sc) 6300 { 6301 struct ifnet *ifp = sc->sc_ifp; 6302 6303 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 6304 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 6305 &sc->sc_drvbpf); 6306 /* 6307 * Initialize constant fields. 6308 * XXX make header lengths a multiple of 32-bits so subsequent 6309 * headers are properly aligned; this is a kludge to keep 6310 * certain applications happy. 6311 * 6312 * NB: the channel is setup each time we transition to the 6313 * RUN state to avoid filling it in for each frame. 6314 */ 6315 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 6316 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 6317 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 6318 6319 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 6320 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 6321 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 6322 } 6323 6324 static int 6325 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 6326 struct ath_buf *bf, struct mbuf *m0, 6327 const struct ieee80211_bpf_params *params) 6328 { 6329 struct ieee80211com *ic = &sc->sc_ic; 6330 struct ath_hal *ah = sc->sc_ah; 6331 int error, ismcast, ismrr; 6332 int hdrlen, pktlen, try0, txantenna; 6333 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3; 6334 struct ath_txq *txq; 6335 struct ieee80211_frame *wh; 6336 u_int flags, ctsduration; 6337 HAL_PKT_TYPE atype; 6338 const HAL_RATE_TABLE *rt; 6339 struct ath_desc *ds; 6340 u_int pri; 6341 6342 wh = mtod(m0, struct ieee80211_frame *); 6343 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6344 hdrlen = ieee80211_anyhdrsize(wh); 6345 /* 6346 * Packet length must not include any 6347 * pad bytes; deduct them here. 6348 */ 6349 /* XXX honor IEEE80211_BPF_DATAPAD */ 6350 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 6351 6352 error = ath_tx_dmasetup(sc, bf, m0); 6353 if (error != 0) 6354 return error; 6355 m0 = bf->bf_m; /* NB: may have changed */ 6356 wh = mtod(m0, struct ieee80211_frame *); 6357 bf->bf_node = ni; /* NB: held reference */ 6358 6359 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 6360 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 6361 if (params->ibp_flags & IEEE80211_BPF_RTS) 6362 flags |= HAL_TXDESC_RTSENA; 6363 else if (params->ibp_flags & IEEE80211_BPF_CTS) 6364 flags |= HAL_TXDESC_CTSENA; 6365 /* XXX leave ismcast to injector? */ 6366 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 6367 flags |= HAL_TXDESC_NOACK; 6368 6369 rt = sc->sc_currates; 6370 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 6371 rix = ath_tx_findrix(rt, params->ibp_rate0); 6372 txrate = rt->info[rix].rateCode; 6373 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6374 txrate |= rt->info[rix].shortPreamble; 6375 sc->sc_txrate = txrate; 6376 try0 = params->ibp_try0; 6377 ismrr = (params->ibp_try1 != 0); 6378 txantenna = params->ibp_pri >> 2; 6379 if (txantenna == 0) /* XXX? */ 6380 txantenna = sc->sc_txantenna; 6381 ctsduration = 0; 6382 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { 6383 cix = ath_tx_findrix(rt, params->ibp_ctsrate); 6384 ctsrate = rt->info[cix].rateCode; 6385 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) { 6386 ctsrate |= rt->info[cix].shortPreamble; 6387 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6388 ctsduration += rt->info[cix].spAckDuration; 6389 ctsduration += ath_hal_computetxtime(ah, 6390 rt, pktlen, rix, AH_TRUE); 6391 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6392 ctsduration += rt->info[rix].spAckDuration; 6393 } else { 6394 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6395 ctsduration += rt->info[cix].lpAckDuration; 6396 ctsduration += ath_hal_computetxtime(ah, 6397 rt, pktlen, rix, AH_FALSE); 6398 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6399 ctsduration += rt->info[rix].lpAckDuration; 6400 } 6401 ismrr = 0; /* XXX */ 6402 } else 6403 ctsrate = 0; 6404 pri = params->ibp_pri & 3; 6405 /* 6406 * NB: we mark all packets as type PSPOLL so the h/w won't 6407 * set the sequence number, duration, etc. 6408 */ 6409 atype = HAL_PKT_TYPE_PSPOLL; 6410 6411 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 6412 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 6413 sc->sc_hwmap[txrate].ieeerate, -1); 6414 6415 if (bpf_peers_present(ic->ic_rawbpf)) 6416 bpf_mtap(ic->ic_rawbpf, m0); 6417 if (bpf_peers_present(sc->sc_drvbpf)) { 6418 u_int64_t tsf = ath_hal_gettsf64(ah); 6419 6420 sc->sc_tx_th.wt_tsf = htole64(tsf); 6421 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 6422 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 6423 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6424 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 6425 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 6426 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 6427 6428 bpf_mtap2(sc->sc_drvbpf, 6429 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 6430 } 6431 6432 /* 6433 * Formulate first tx descriptor with tx controls. 6434 */ 6435 ds = bf->bf_desc; 6436 /* XXX check return value? */ 6437 ath_hal_setuptxdesc(ah, ds 6438 , pktlen /* packet length */ 6439 , hdrlen /* header length */ 6440 , atype /* Atheros packet type */ 6441 , params->ibp_power /* txpower */ 6442 , txrate, try0 /* series 0 rate/tries */ 6443 , HAL_TXKEYIX_INVALID /* key cache index */ 6444 , txantenna /* antenna mode */ 6445 , flags /* flags */ 6446 , ctsrate /* rts/cts rate */ 6447 , ctsduration /* rts/cts duration */ 6448 ); 6449 bf->bf_flags = flags; 6450 6451 if (ismrr) { 6452 rix = ath_tx_findrix(rt, params->ibp_rate1); 6453 rate1 = rt->info[rix].rateCode; 6454 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6455 rate1 |= rt->info[rix].shortPreamble; 6456 if (params->ibp_try2) { 6457 rix = ath_tx_findrix(rt, params->ibp_rate2); 6458 rate2 = rt->info[rix].rateCode; 6459 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6460 rate2 |= rt->info[rix].shortPreamble; 6461 } else 6462 rate2 = 0; 6463 if (params->ibp_try3) { 6464 rix = ath_tx_findrix(rt, params->ibp_rate3); 6465 rate3 = rt->info[rix].rateCode; 6466 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6467 rate3 |= rt->info[rix].shortPreamble; 6468 } else 6469 rate3 = 0; 6470 ath_hal_setupxtxdesc(ah, ds 6471 , rate1, params->ibp_try1 /* series 1 */ 6472 , rate2, params->ibp_try2 /* series 2 */ 6473 , rate3, params->ibp_try3 /* series 3 */ 6474 ); 6475 } 6476 6477 /* 6478 * When servicing one or more stations in power-save mode 6479 * (or) if there is some mcast data waiting on the mcast 6480 * queue (to prevent out of order delivery) multicast 6481 * frames must be buffered until after the beacon. 6482 */ 6483 txq = sc->sc_ac2q[pri]; 6484 if (ismcast && (ic->ic_ps_sta || sc->sc_mcastq.axq_depth)) 6485 txq = &sc->sc_mcastq; 6486 ath_tx_handoff(sc, txq, bf); 6487 return 0; 6488 } 6489 6490 static int 6491 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 6492 const struct ieee80211_bpf_params *params) 6493 { 6494 struct ieee80211com *ic = ni->ni_ic; 6495 struct ifnet *ifp = ic->ic_ifp; 6496 struct ath_softc *sc = ifp->if_softc; 6497 struct ath_buf *bf; 6498 6499 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 6500 ieee80211_free_node(ni); 6501 m_freem(m); 6502 return ENETDOWN; 6503 } 6504 /* 6505 * Grab a TX buffer and associated resources. 6506 */ 6507 ATH_TXBUF_LOCK(sc); 6508 bf = STAILQ_FIRST(&sc->sc_txbuf); 6509 if (bf != NULL) 6510 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 6511 ATH_TXBUF_UNLOCK(sc); 6512 if (bf == NULL) { 6513 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 6514 __func__); 6515 sc->sc_stats.ast_tx_qstop++; 6516 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 6517 ieee80211_free_node(ni); 6518 m_freem(m); 6519 return ENOBUFS; 6520 } 6521 6522 ifp->if_opackets++; 6523 sc->sc_stats.ast_tx_raw++; 6524 6525 if (params == NULL) { 6526 /* 6527 * Legacy path; interpret frame contents to decide 6528 * precisely how to send the frame. 6529 */ 6530 if (ath_tx_start(sc, ni, bf, m)) 6531 goto bad; 6532 } else { 6533 /* 6534 * Caller supplied explicit parameters to use in 6535 * sending the frame. 6536 */ 6537 if (ath_tx_raw_start(sc, ni, bf, m, params)) 6538 goto bad; 6539 } 6540 ifp->if_timer = 5; 6541 6542 return 0; 6543 bad: 6544 ifp->if_oerrors++; 6545 ATH_TXBUF_LOCK(sc); 6546 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 6547 ATH_TXBUF_UNLOCK(sc); 6548 ieee80211_free_node(ni); 6549 return EIO; /* XXX */ 6550 } 6551 6552 /* 6553 * Announce various information on device/driver attach. 6554 */ 6555 static void 6556 ath_announce(struct ath_softc *sc) 6557 { 6558 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 6559 struct ifnet *ifp = sc->sc_ifp; 6560 struct ath_hal *ah = sc->sc_ah; 6561 u_int modes, cc; 6562 6563 if_printf(ifp, "mac %d.%d phy %d.%d", 6564 ah->ah_macVersion, ah->ah_macRev, 6565 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 6566 /* 6567 * Print radio revision(s). We check the wireless modes 6568 * to avoid falsely printing revs for inoperable parts. 6569 * Dual-band radio revs are returned in the 5Ghz rev number. 6570 */ 6571 ath_hal_getcountrycode(ah, &cc); 6572 modes = ath_hal_getwirelessmodes(ah, cc); 6573 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 6574 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 6575 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 6576 ah->ah_analog5GhzRev >> 4, 6577 ah->ah_analog5GhzRev & 0xf, 6578 ah->ah_analog2GhzRev >> 4, 6579 ah->ah_analog2GhzRev & 0xf); 6580 else 6581 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 6582 ah->ah_analog5GhzRev & 0xf); 6583 } else 6584 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 6585 ah->ah_analog5GhzRev & 0xf); 6586 printf("\n"); 6587 if (bootverbose) { 6588 int i; 6589 for (i = 0; i <= WME_AC_VO; i++) { 6590 struct ath_txq *txq = sc->sc_ac2q[i]; 6591 if_printf(ifp, "Use hw queue %u for %s traffic\n", 6592 txq->axq_qnum, ieee80211_wme_acnames[i]); 6593 } 6594 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 6595 sc->sc_cabq->axq_qnum); 6596 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 6597 } 6598 if (ath_rxbuf != ATH_RXBUF) 6599 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 6600 if (ath_txbuf != ATH_TXBUF) 6601 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 6602 #undef HAL_MODE_DUALBAND 6603 } 6604