1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 */ 46 #include "opt_ah.h" 47 #include "opt_wlan.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/sysctl.h> 52 #include <sys/mbuf.h> 53 #include <sys/malloc.h> 54 #include <sys/lock.h> 55 #include <sys/mutex.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/sockio.h> 59 #include <sys/errno.h> 60 #include <sys/callout.h> 61 #include <sys/bus.h> 62 #include <sys/endian.h> 63 #include <sys/kthread.h> 64 #include <sys/taskqueue.h> 65 #include <sys/priv.h> 66 #include <sys/module.h> 67 #include <sys/ktr.h> 68 #include <sys/smp.h> /* for mp_ncpus */ 69 70 #include <machine/bus.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_arp.h> 77 #include <net/ethernet.h> 78 #include <net/if_llc.h> 79 80 #include <net80211/ieee80211_var.h> 81 #include <net80211/ieee80211_regdomain.h> 82 #ifdef IEEE80211_SUPPORT_SUPERG 83 #include <net80211/ieee80211_superg.h> 84 #endif 85 #ifdef IEEE80211_SUPPORT_TDMA 86 #include <net80211/ieee80211_tdma.h> 87 #endif 88 89 #include <net/bpf.h> 90 91 #ifdef INET 92 #include <netinet/in.h> 93 #include <netinet/if_ether.h> 94 #endif 95 96 #include <dev/ath/if_athvar.h> 97 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 98 #include <dev/ath/ath_hal/ah_diagcodes.h> 99 100 #include <dev/ath/if_ath_debug.h> 101 #include <dev/ath/if_ath_misc.h> 102 #include <dev/ath/if_ath_tx.h> 103 #include <dev/ath/if_ath_sysctl.h> 104 #include <dev/ath/if_ath_keycache.h> 105 #include <dev/ath/if_athdfs.h> 106 107 #ifdef ATH_TX99_DIAG 108 #include <dev/ath/ath_tx99/ath_tx99.h> 109 #endif 110 111 #define ATH_KTR_INTR KTR_SPARE4 112 #define ATH_KTR_ERR KTR_SPARE3 113 114 /* 115 * ATH_BCBUF determines the number of vap's that can transmit 116 * beacons and also (currently) the number of vap's that can 117 * have unique mac addresses/bssid. When staggering beacons 118 * 4 is probably a good max as otherwise the beacons become 119 * very closely spaced and there is limited time for cab q traffic 120 * to go out. You can burst beacons instead but that is not good 121 * for stations in power save and at some point you really want 122 * another radio (and channel). 123 * 124 * The limit on the number of mac addresses is tied to our use of 125 * the U/L bit and tracking addresses in a byte; it would be 126 * worthwhile to allow more for applications like proxy sta. 127 */ 128 CTASSERT(ATH_BCBUF <= 8); 129 130 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 131 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 132 const uint8_t [IEEE80211_ADDR_LEN], 133 const uint8_t [IEEE80211_ADDR_LEN]); 134 static void ath_vap_delete(struct ieee80211vap *); 135 static void ath_init(void *); 136 static void ath_stop_locked(struct ifnet *); 137 static void ath_stop(struct ifnet *); 138 static void ath_start(struct ifnet *); 139 static int ath_reset_vap(struct ieee80211vap *, u_long); 140 static int ath_media_change(struct ifnet *); 141 static void ath_watchdog(void *); 142 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 143 static void ath_fatal_proc(void *, int); 144 static void ath_bmiss_vap(struct ieee80211vap *); 145 static void ath_bmiss_proc(void *, int); 146 static void ath_key_update_begin(struct ieee80211vap *); 147 static void ath_key_update_end(struct ieee80211vap *); 148 static void ath_update_mcast(struct ifnet *); 149 static void ath_update_promisc(struct ifnet *); 150 static void ath_mode_init(struct ath_softc *); 151 static void ath_setslottime(struct ath_softc *); 152 static void ath_updateslot(struct ifnet *); 153 static int ath_beaconq_setup(struct ath_hal *); 154 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 155 static void ath_beacon_update(struct ieee80211vap *, int item); 156 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 157 static void ath_beacon_proc(void *, int); 158 static struct ath_buf *ath_beacon_generate(struct ath_softc *, 159 struct ieee80211vap *); 160 static void ath_bstuck_proc(void *, int); 161 static void ath_beacon_return(struct ath_softc *, struct ath_buf *); 162 static void ath_beacon_free(struct ath_softc *); 163 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *); 164 static void ath_descdma_cleanup(struct ath_softc *sc, 165 struct ath_descdma *, ath_bufhead *); 166 static int ath_desc_alloc(struct ath_softc *); 167 static void ath_desc_free(struct ath_softc *); 168 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 169 const uint8_t [IEEE80211_ADDR_LEN]); 170 static void ath_node_cleanup(struct ieee80211_node *); 171 static void ath_node_free(struct ieee80211_node *); 172 static void ath_node_getsignal(const struct ieee80211_node *, 173 int8_t *, int8_t *); 174 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 175 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 176 int subtype, int rssi, int nf); 177 static void ath_setdefantenna(struct ath_softc *, u_int); 178 static void ath_rx_proc(struct ath_softc *sc, int); 179 static void ath_rx_tasklet(void *, int); 180 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 181 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 182 static int ath_tx_setup(struct ath_softc *, int, int); 183 static int ath_wme_update(struct ieee80211com *); 184 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 185 static void ath_tx_cleanup(struct ath_softc *); 186 static void ath_tx_proc_q0(void *, int); 187 static void ath_tx_proc_q0123(void *, int); 188 static void ath_tx_proc(void *, int); 189 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 190 static void ath_draintxq(struct ath_softc *, ATH_RESET_TYPE reset_type); 191 static void ath_stoprecv(struct ath_softc *, int); 192 static int ath_startrecv(struct ath_softc *); 193 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 194 static void ath_scan_start(struct ieee80211com *); 195 static void ath_scan_end(struct ieee80211com *); 196 static void ath_set_channel(struct ieee80211com *); 197 static void ath_calibrate(void *); 198 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 199 static void ath_setup_stationkey(struct ieee80211_node *); 200 static void ath_newassoc(struct ieee80211_node *, int); 201 static int ath_setregdomain(struct ieee80211com *, 202 struct ieee80211_regdomain *, int, 203 struct ieee80211_channel []); 204 static void ath_getradiocaps(struct ieee80211com *, int, int *, 205 struct ieee80211_channel []); 206 static int ath_getchannels(struct ath_softc *); 207 static void ath_led_event(struct ath_softc *, int); 208 209 static int ath_rate_setup(struct ath_softc *, u_int mode); 210 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 211 212 static void ath_announce(struct ath_softc *); 213 214 static void ath_dfs_tasklet(void *, int); 215 216 #ifdef IEEE80211_SUPPORT_TDMA 217 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, 218 u_int32_t bintval); 219 static void ath_tdma_bintvalsetup(struct ath_softc *sc, 220 const struct ieee80211_tdma_state *tdma); 221 static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap); 222 static void ath_tdma_update(struct ieee80211_node *ni, 223 const struct ieee80211_tdma_param *tdma, int); 224 static void ath_tdma_beacon_send(struct ath_softc *sc, 225 struct ieee80211vap *vap); 226 227 #define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */ 228 #define TDMA_LPF_LEN 6 229 #define TDMA_DUMMY_MARKER 0x127 230 #define TDMA_EP_MUL(x, mul) ((x) * (mul)) 231 #define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER)) 232 #define TDMA_LPF(x, y, len) \ 233 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y)) 234 #define TDMA_SAMPLE(x, y) do { \ 235 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \ 236 } while (0) 237 #define TDMA_EP_RND(x,mul) \ 238 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 239 #define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER) 240 #endif /* IEEE80211_SUPPORT_TDMA */ 241 242 SYSCTL_DECL(_hw_ath); 243 244 /* XXX validate sysctl values */ 245 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 246 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 247 0, "long chip calibration interval (secs)"); 248 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 249 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 250 0, "short chip calibration interval (msecs)"); 251 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 252 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 253 0, "reset chip calibration results (secs)"); 254 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */ 255 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval, 256 0, "ANI calibration (msecs)"); 257 258 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 259 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 260 0, "rx buffers allocated"); 261 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 262 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 263 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 264 0, "tx buffers allocated"); 265 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 266 267 static int ath_bstuck_threshold = 4; /* max missed beacons */ 268 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 269 0, "max missed beacon xmits before chip reset"); 270 271 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 272 273 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20) 274 #define HAL_MODE_HT40 \ 275 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \ 276 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS) 277 int 278 ath_attach(u_int16_t devid, struct ath_softc *sc) 279 { 280 struct ifnet *ifp; 281 struct ieee80211com *ic; 282 struct ath_hal *ah = NULL; 283 HAL_STATUS status; 284 int error = 0, i; 285 u_int wmodes; 286 uint8_t macaddr[IEEE80211_ADDR_LEN]; 287 288 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 289 290 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 291 if (ifp == NULL) { 292 device_printf(sc->sc_dev, "can not if_alloc()\n"); 293 error = ENOSPC; 294 goto bad; 295 } 296 ic = ifp->if_l2com; 297 298 /* set these up early for if_printf use */ 299 if_initname(ifp, device_get_name(sc->sc_dev), 300 device_get_unit(sc->sc_dev)); 301 302 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, sc->sc_eepromdata, &status); 303 if (ah == NULL) { 304 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 305 status); 306 error = ENXIO; 307 goto bad; 308 } 309 sc->sc_ah = ah; 310 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 311 #ifdef ATH_DEBUG 312 sc->sc_debug = ath_debug; 313 #endif 314 315 /* 316 * Check if the MAC has multi-rate retry support. 317 * We do this by trying to setup a fake extended 318 * descriptor. MAC's that don't have support will 319 * return false w/o doing anything. MAC's that do 320 * support it will return true w/o doing anything. 321 */ 322 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 323 324 /* 325 * Check if the device has hardware counters for PHY 326 * errors. If so we need to enable the MIB interrupt 327 * so we can act on stat triggers. 328 */ 329 if (ath_hal_hwphycounters(ah)) 330 sc->sc_needmib = 1; 331 332 /* 333 * Get the hardware key cache size. 334 */ 335 sc->sc_keymax = ath_hal_keycachesize(ah); 336 if (sc->sc_keymax > ATH_KEYMAX) { 337 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 338 ATH_KEYMAX, sc->sc_keymax); 339 sc->sc_keymax = ATH_KEYMAX; 340 } 341 /* 342 * Reset the key cache since some parts do not 343 * reset the contents on initial power up. 344 */ 345 for (i = 0; i < sc->sc_keymax; i++) 346 ath_hal_keyreset(ah, i); 347 348 /* 349 * Collect the default channel list. 350 */ 351 error = ath_getchannels(sc); 352 if (error != 0) 353 goto bad; 354 355 /* 356 * Setup rate tables for all potential media types. 357 */ 358 ath_rate_setup(sc, IEEE80211_MODE_11A); 359 ath_rate_setup(sc, IEEE80211_MODE_11B); 360 ath_rate_setup(sc, IEEE80211_MODE_11G); 361 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 362 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 363 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 364 ath_rate_setup(sc, IEEE80211_MODE_11NA); 365 ath_rate_setup(sc, IEEE80211_MODE_11NG); 366 ath_rate_setup(sc, IEEE80211_MODE_HALF); 367 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 368 369 /* NB: setup here so ath_rate_update is happy */ 370 ath_setcurmode(sc, IEEE80211_MODE_11A); 371 372 /* 373 * Allocate tx+rx descriptors and populate the lists. 374 */ 375 error = ath_desc_alloc(sc); 376 if (error != 0) { 377 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 378 goto bad; 379 } 380 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0); 381 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0); 382 383 ATH_TXBUF_LOCK_INIT(sc); 384 385 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 386 taskqueue_thread_enqueue, &sc->sc_tq); 387 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 388 "%s taskq", ifp->if_xname); 389 390 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_tasklet, sc); 391 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 392 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 393 394 /* 395 * Allocate hardware transmit queues: one queue for 396 * beacon frames and one data queue for each QoS 397 * priority. Note that the hal handles resetting 398 * these queues at the needed time. 399 * 400 * XXX PS-Poll 401 */ 402 sc->sc_bhalq = ath_beaconq_setup(ah); 403 if (sc->sc_bhalq == (u_int) -1) { 404 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 405 error = EIO; 406 goto bad2; 407 } 408 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 409 if (sc->sc_cabq == NULL) { 410 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 411 error = EIO; 412 goto bad2; 413 } 414 /* NB: insure BK queue is the lowest priority h/w queue */ 415 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 416 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 417 ieee80211_wme_acnames[WME_AC_BK]); 418 error = EIO; 419 goto bad2; 420 } 421 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 422 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 423 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 424 /* 425 * Not enough hardware tx queues to properly do WME; 426 * just punt and assign them all to the same h/w queue. 427 * We could do a better job of this if, for example, 428 * we allocate queues when we switch from station to 429 * AP mode. 430 */ 431 if (sc->sc_ac2q[WME_AC_VI] != NULL) 432 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 433 if (sc->sc_ac2q[WME_AC_BE] != NULL) 434 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 435 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 436 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 437 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 438 } 439 440 /* 441 * Special case certain configurations. Note the 442 * CAB queue is handled by these specially so don't 443 * include them when checking the txq setup mask. 444 */ 445 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 446 case 0x01: 447 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 448 break; 449 case 0x0f: 450 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 451 break; 452 default: 453 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 454 break; 455 } 456 457 /* 458 * Setup rate control. Some rate control modules 459 * call back to change the anntena state so expose 460 * the necessary entry points. 461 * XXX maybe belongs in struct ath_ratectrl? 462 */ 463 sc->sc_setdefantenna = ath_setdefantenna; 464 sc->sc_rc = ath_rate_attach(sc); 465 if (sc->sc_rc == NULL) { 466 error = EIO; 467 goto bad2; 468 } 469 470 /* Attach DFS module */ 471 if (! ath_dfs_attach(sc)) { 472 device_printf(sc->sc_dev, "%s: unable to attach DFS\n", __func__); 473 error = EIO; 474 goto bad2; 475 } 476 477 /* Start DFS processing tasklet */ 478 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc); 479 480 sc->sc_blinking = 0; 481 sc->sc_ledstate = 1; 482 sc->sc_ledon = 0; /* low true */ 483 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 484 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 485 /* 486 * Auto-enable soft led processing for IBM cards and for 487 * 5211 minipci cards. Users can also manually enable/disable 488 * support with a sysctl. 489 */ 490 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 491 if (sc->sc_softled) { 492 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 493 HAL_GPIO_MUX_MAC_NETWORK_LED); 494 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 495 } 496 497 ifp->if_softc = sc; 498 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 499 ifp->if_start = ath_start; 500 ifp->if_ioctl = ath_ioctl; 501 ifp->if_init = ath_init; 502 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 503 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 504 IFQ_SET_READY(&ifp->if_snd); 505 506 ic->ic_ifp = ifp; 507 /* XXX not right but it's not used anywhere important */ 508 ic->ic_phytype = IEEE80211_T_OFDM; 509 ic->ic_opmode = IEEE80211_M_STA; 510 ic->ic_caps = 511 IEEE80211_C_STA /* station mode */ 512 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 513 | IEEE80211_C_HOSTAP /* hostap mode */ 514 | IEEE80211_C_MONITOR /* monitor mode */ 515 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 516 | IEEE80211_C_WDS /* 4-address traffic works */ 517 | IEEE80211_C_MBSS /* mesh point link mode */ 518 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 519 | IEEE80211_C_SHSLOT /* short slot time supported */ 520 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 521 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 522 | IEEE80211_C_TXFRAG /* handle tx frags */ 523 #ifdef ATH_ENABLE_DFS 524 | IEEE80211_C_DFS /* Enable DFS radar detection */ 525 #endif 526 ; 527 /* 528 * Query the hal to figure out h/w crypto support. 529 */ 530 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 531 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 532 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 533 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 535 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 536 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 537 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 538 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 539 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 540 /* 541 * Check if h/w does the MIC and/or whether the 542 * separate key cache entries are required to 543 * handle both tx+rx MIC keys. 544 */ 545 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 546 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 547 /* 548 * If the h/w supports storing tx+rx MIC keys 549 * in one cache slot automatically enable use. 550 */ 551 if (ath_hal_hastkipsplit(ah) || 552 !ath_hal_settkipsplit(ah, AH_FALSE)) 553 sc->sc_splitmic = 1; 554 /* 555 * If the h/w can do TKIP MIC together with WME then 556 * we use it; otherwise we force the MIC to be done 557 * in software by the net80211 layer. 558 */ 559 if (ath_hal_haswmetkipmic(ah)) 560 sc->sc_wmetkipmic = 1; 561 } 562 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 563 /* 564 * Check for multicast key search support. 565 */ 566 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 567 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 568 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 569 } 570 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 571 /* 572 * Mark key cache slots associated with global keys 573 * as in use. If we knew TKIP was not to be used we 574 * could leave the +32, +64, and +32+64 slots free. 575 */ 576 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 577 setbit(sc->sc_keymap, i); 578 setbit(sc->sc_keymap, i+64); 579 if (sc->sc_splitmic) { 580 setbit(sc->sc_keymap, i+32); 581 setbit(sc->sc_keymap, i+32+64); 582 } 583 } 584 /* 585 * TPC support can be done either with a global cap or 586 * per-packet support. The latter is not available on 587 * all parts. We're a bit pedantic here as all parts 588 * support a global cap. 589 */ 590 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 591 ic->ic_caps |= IEEE80211_C_TXPMGT; 592 593 /* 594 * Mark WME capability only if we have sufficient 595 * hardware queues to do proper priority scheduling. 596 */ 597 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 598 ic->ic_caps |= IEEE80211_C_WME; 599 /* 600 * Check for misc other capabilities. 601 */ 602 if (ath_hal_hasbursting(ah)) 603 ic->ic_caps |= IEEE80211_C_BURST; 604 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 605 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 606 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 607 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah); 608 sc->sc_rxtsf32 = ath_hal_has_long_rxdesc_tsf(ah); 609 if (ath_hal_hasfastframes(ah)) 610 ic->ic_caps |= IEEE80211_C_FF; 611 wmodes = ath_hal_getwirelessmodes(ah); 612 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 613 ic->ic_caps |= IEEE80211_C_TURBOP; 614 #ifdef IEEE80211_SUPPORT_TDMA 615 if (ath_hal_macversion(ah) > 0x78) { 616 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 617 ic->ic_tdma_update = ath_tdma_update; 618 } 619 #endif 620 621 /* 622 * The if_ath 11n support is completely not ready for normal use. 623 * Enabling this option will likely break everything and everything. 624 * Don't think of doing that unless you know what you're doing. 625 */ 626 627 #ifdef ATH_ENABLE_11N 628 /* 629 * Query HT capabilities 630 */ 631 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK && 632 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) { 633 int rxs, txs; 634 635 device_printf(sc->sc_dev, "[HT] enabling HT modes\n"); 636 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */ 637 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */ 638 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */ 639 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 640 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */ 641 ; 642 643 /* 644 * Enable short-GI for HT20 only if the hardware 645 * advertises support. 646 * Notably, anything earlier than the AR9287 doesn't. 647 */ 648 if ((ath_hal_getcapability(ah, 649 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) && 650 (wmodes & HAL_MODE_HT20)) { 651 device_printf(sc->sc_dev, 652 "[HT] enabling short-GI in 20MHz mode\n"); 653 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20; 654 } 655 656 if (wmodes & HAL_MODE_HT40) 657 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40 658 | IEEE80211_HTCAP_SHORTGI40; 659 660 /* 661 * rx/tx stream is not currently used anywhere; it needs to be taken 662 * into account when negotiating which MCS rates it'll receive and 663 * what MCS rates are available for TX. 664 */ 665 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &rxs); 666 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &txs); 667 668 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask); 669 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask); 670 671 ic->ic_txstream = txs; 672 ic->ic_rxstream = rxs; 673 674 device_printf(sc->sc_dev, "[HT] %d RX streams; %d TX streams\n", rxs, txs); 675 } 676 #endif 677 678 /* 679 * Check if the hardware requires PCI register serialisation. 680 * Some of the Owl based MACs require this. 681 */ 682 if (mp_ncpus > 1 && 683 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR, 684 0, NULL) == HAL_OK) { 685 sc->sc_ah->ah_config.ah_serialise_reg_war = 1; 686 device_printf(sc->sc_dev, "Enabling register serialisation\n"); 687 } 688 689 /* 690 * Indicate we need the 802.11 header padded to a 691 * 32-bit boundary for 4-address and QoS frames. 692 */ 693 ic->ic_flags |= IEEE80211_F_DATAPAD; 694 695 /* 696 * Query the hal about antenna support. 697 */ 698 sc->sc_defant = ath_hal_getdefantenna(ah); 699 700 /* 701 * Not all chips have the VEOL support we want to 702 * use with IBSS beacons; check here for it. 703 */ 704 sc->sc_hasveol = ath_hal_hasveol(ah); 705 706 /* get mac address from hardware */ 707 ath_hal_getmac(ah, macaddr); 708 if (sc->sc_hasbmask) 709 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 710 711 /* NB: used to size node table key mapping array */ 712 ic->ic_max_keyix = sc->sc_keymax; 713 /* call MI attach routine. */ 714 ieee80211_ifattach(ic, macaddr); 715 ic->ic_setregdomain = ath_setregdomain; 716 ic->ic_getradiocaps = ath_getradiocaps; 717 sc->sc_opmode = HAL_M_STA; 718 719 /* override default methods */ 720 ic->ic_newassoc = ath_newassoc; 721 ic->ic_updateslot = ath_updateslot; 722 ic->ic_wme.wme_update = ath_wme_update; 723 ic->ic_vap_create = ath_vap_create; 724 ic->ic_vap_delete = ath_vap_delete; 725 ic->ic_raw_xmit = ath_raw_xmit; 726 ic->ic_update_mcast = ath_update_mcast; 727 ic->ic_update_promisc = ath_update_promisc; 728 ic->ic_node_alloc = ath_node_alloc; 729 sc->sc_node_free = ic->ic_node_free; 730 ic->ic_node_free = ath_node_free; 731 sc->sc_node_cleanup = ic->ic_node_cleanup; 732 ic->ic_node_cleanup = ath_node_cleanup; 733 ic->ic_node_getsignal = ath_node_getsignal; 734 ic->ic_scan_start = ath_scan_start; 735 ic->ic_scan_end = ath_scan_end; 736 ic->ic_set_channel = ath_set_channel; 737 738 /* 802.11n specific - but just override anyway */ 739 sc->sc_addba_request = ic->ic_addba_request; 740 sc->sc_addba_response = ic->ic_addba_response; 741 sc->sc_addba_stop = ic->ic_addba_stop; 742 sc->sc_bar_response = ic->ic_bar_response; 743 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout; 744 745 ic->ic_addba_request = ath_addba_request; 746 ic->ic_addba_response = ath_addba_response; 747 ic->ic_addba_response_timeout = ath_addba_response_timeout; 748 ic->ic_addba_stop = ath_addba_stop; 749 ic->ic_bar_response = ath_bar_response; 750 751 ieee80211_radiotap_attach(ic, 752 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 753 ATH_TX_RADIOTAP_PRESENT, 754 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 755 ATH_RX_RADIOTAP_PRESENT); 756 757 /* 758 * Setup dynamic sysctl's now that country code and 759 * regdomain are available from the hal. 760 */ 761 ath_sysctlattach(sc); 762 ath_sysctl_stats_attach(sc); 763 ath_sysctl_hal_attach(sc); 764 765 if (bootverbose) 766 ieee80211_announce(ic); 767 ath_announce(sc); 768 return 0; 769 bad2: 770 ath_tx_cleanup(sc); 771 ath_desc_free(sc); 772 bad: 773 if (ah) 774 ath_hal_detach(ah); 775 if (ifp != NULL) 776 if_free(ifp); 777 sc->sc_invalid = 1; 778 return error; 779 } 780 781 int 782 ath_detach(struct ath_softc *sc) 783 { 784 struct ifnet *ifp = sc->sc_ifp; 785 786 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 787 __func__, ifp->if_flags); 788 789 /* 790 * NB: the order of these is important: 791 * o stop the chip so no more interrupts will fire 792 * o call the 802.11 layer before detaching the hal to 793 * insure callbacks into the driver to delete global 794 * key cache entries can be handled 795 * o free the taskqueue which drains any pending tasks 796 * o reclaim the tx queue data structures after calling 797 * the 802.11 layer as we'll get called back to reclaim 798 * node state and potentially want to use them 799 * o to cleanup the tx queues the hal is called, so detach 800 * it last 801 * Other than that, it's straightforward... 802 */ 803 ath_stop(ifp); 804 ieee80211_ifdetach(ifp->if_l2com); 805 taskqueue_free(sc->sc_tq); 806 #ifdef ATH_TX99_DIAG 807 if (sc->sc_tx99 != NULL) 808 sc->sc_tx99->detach(sc->sc_tx99); 809 #endif 810 ath_rate_detach(sc->sc_rc); 811 812 ath_dfs_detach(sc); 813 ath_desc_free(sc); 814 ath_tx_cleanup(sc); 815 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 816 if_free(ifp); 817 818 return 0; 819 } 820 821 /* 822 * MAC address handling for multiple BSS on the same radio. 823 * The first vap uses the MAC address from the EEPROM. For 824 * subsequent vap's we set the U/L bit (bit 1) in the MAC 825 * address and use the next six bits as an index. 826 */ 827 static void 828 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 829 { 830 int i; 831 832 if (clone && sc->sc_hasbmask) { 833 /* NB: we only do this if h/w supports multiple bssid */ 834 for (i = 0; i < 8; i++) 835 if ((sc->sc_bssidmask & (1<<i)) == 0) 836 break; 837 if (i != 0) 838 mac[0] |= (i << 2)|0x2; 839 } else 840 i = 0; 841 sc->sc_bssidmask |= 1<<i; 842 sc->sc_hwbssidmask[0] &= ~mac[0]; 843 if (i == 0) 844 sc->sc_nbssid0++; 845 } 846 847 static void 848 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 849 { 850 int i = mac[0] >> 2; 851 uint8_t mask; 852 853 if (i != 0 || --sc->sc_nbssid0 == 0) { 854 sc->sc_bssidmask &= ~(1<<i); 855 /* recalculate bssid mask from remaining addresses */ 856 mask = 0xff; 857 for (i = 1; i < 8; i++) 858 if (sc->sc_bssidmask & (1<<i)) 859 mask &= ~((i<<2)|0x2); 860 sc->sc_hwbssidmask[0] |= mask; 861 } 862 } 863 864 /* 865 * Assign a beacon xmit slot. We try to space out 866 * assignments so when beacons are staggered the 867 * traffic coming out of the cab q has maximal time 868 * to go out before the next beacon is scheduled. 869 */ 870 static int 871 assign_bslot(struct ath_softc *sc) 872 { 873 u_int slot, free; 874 875 free = 0; 876 for (slot = 0; slot < ATH_BCBUF; slot++) 877 if (sc->sc_bslot[slot] == NULL) { 878 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 879 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 880 return slot; 881 free = slot; 882 /* NB: keep looking for a double slot */ 883 } 884 return free; 885 } 886 887 static struct ieee80211vap * 888 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 889 enum ieee80211_opmode opmode, int flags, 890 const uint8_t bssid[IEEE80211_ADDR_LEN], 891 const uint8_t mac0[IEEE80211_ADDR_LEN]) 892 { 893 struct ath_softc *sc = ic->ic_ifp->if_softc; 894 struct ath_vap *avp; 895 struct ieee80211vap *vap; 896 uint8_t mac[IEEE80211_ADDR_LEN]; 897 int needbeacon, error; 898 enum ieee80211_opmode ic_opmode; 899 900 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap), 901 M_80211_VAP, M_WAITOK | M_ZERO); 902 needbeacon = 0; 903 IEEE80211_ADDR_COPY(mac, mac0); 904 905 ATH_LOCK(sc); 906 ic_opmode = opmode; /* default to opmode of new vap */ 907 switch (opmode) { 908 case IEEE80211_M_STA: 909 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 910 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 911 goto bad; 912 } 913 if (sc->sc_nvaps) { 914 /* 915 * With multiple vaps we must fall back 916 * to s/w beacon miss handling. 917 */ 918 flags |= IEEE80211_CLONE_NOBEACONS; 919 } 920 if (flags & IEEE80211_CLONE_NOBEACONS) { 921 /* 922 * Station mode w/o beacons are implemented w/ AP mode. 923 */ 924 ic_opmode = IEEE80211_M_HOSTAP; 925 } 926 break; 927 case IEEE80211_M_IBSS: 928 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 929 device_printf(sc->sc_dev, 930 "only 1 ibss vap supported\n"); 931 goto bad; 932 } 933 needbeacon = 1; 934 break; 935 case IEEE80211_M_AHDEMO: 936 #ifdef IEEE80211_SUPPORT_TDMA 937 if (flags & IEEE80211_CLONE_TDMA) { 938 if (sc->sc_nvaps != 0) { 939 device_printf(sc->sc_dev, 940 "only 1 tdma vap supported\n"); 941 goto bad; 942 } 943 needbeacon = 1; 944 flags |= IEEE80211_CLONE_NOBEACONS; 945 } 946 /* fall thru... */ 947 #endif 948 case IEEE80211_M_MONITOR: 949 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 950 /* 951 * Adopt existing mode. Adding a monitor or ahdemo 952 * vap to an existing configuration is of dubious 953 * value but should be ok. 954 */ 955 /* XXX not right for monitor mode */ 956 ic_opmode = ic->ic_opmode; 957 } 958 break; 959 case IEEE80211_M_HOSTAP: 960 case IEEE80211_M_MBSS: 961 needbeacon = 1; 962 break; 963 case IEEE80211_M_WDS: 964 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 965 device_printf(sc->sc_dev, 966 "wds not supported in sta mode\n"); 967 goto bad; 968 } 969 /* 970 * Silently remove any request for a unique 971 * bssid; WDS vap's always share the local 972 * mac address. 973 */ 974 flags &= ~IEEE80211_CLONE_BSSID; 975 if (sc->sc_nvaps == 0) 976 ic_opmode = IEEE80211_M_HOSTAP; 977 else 978 ic_opmode = ic->ic_opmode; 979 break; 980 default: 981 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 982 goto bad; 983 } 984 /* 985 * Check that a beacon buffer is available; the code below assumes it. 986 */ 987 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) { 988 device_printf(sc->sc_dev, "no beacon buffer available\n"); 989 goto bad; 990 } 991 992 /* STA, AHDEMO? */ 993 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 994 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 995 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 996 } 997 998 vap = &avp->av_vap; 999 /* XXX can't hold mutex across if_alloc */ 1000 ATH_UNLOCK(sc); 1001 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 1002 bssid, mac); 1003 ATH_LOCK(sc); 1004 if (error != 0) { 1005 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 1006 __func__, error); 1007 goto bad2; 1008 } 1009 1010 /* h/w crypto support */ 1011 vap->iv_key_alloc = ath_key_alloc; 1012 vap->iv_key_delete = ath_key_delete; 1013 vap->iv_key_set = ath_key_set; 1014 vap->iv_key_update_begin = ath_key_update_begin; 1015 vap->iv_key_update_end = ath_key_update_end; 1016 1017 /* override various methods */ 1018 avp->av_recv_mgmt = vap->iv_recv_mgmt; 1019 vap->iv_recv_mgmt = ath_recv_mgmt; 1020 vap->iv_reset = ath_reset_vap; 1021 vap->iv_update_beacon = ath_beacon_update; 1022 avp->av_newstate = vap->iv_newstate; 1023 vap->iv_newstate = ath_newstate; 1024 avp->av_bmiss = vap->iv_bmiss; 1025 vap->iv_bmiss = ath_bmiss_vap; 1026 1027 /* Set default parameters */ 1028 1029 /* 1030 * Anything earlier than some AR9300 series MACs don't 1031 * support a smaller MPDU density. 1032 */ 1033 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8; 1034 /* 1035 * All NICs can handle the maximum size, however 1036 * AR5416 based MACs can only TX aggregates w/ RTS 1037 * protection when the total aggregate size is <= 8k. 1038 * However, for now that's enforced by the TX path. 1039 */ 1040 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 1041 1042 avp->av_bslot = -1; 1043 if (needbeacon) { 1044 /* 1045 * Allocate beacon state and setup the q for buffered 1046 * multicast frames. We know a beacon buffer is 1047 * available because we checked above. 1048 */ 1049 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf); 1050 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list); 1051 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1052 /* 1053 * Assign the vap to a beacon xmit slot. As above 1054 * this cannot fail to find a free one. 1055 */ 1056 avp->av_bslot = assign_bslot(sc); 1057 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1058 ("beacon slot %u not empty", avp->av_bslot)); 1059 sc->sc_bslot[avp->av_bslot] = vap; 1060 sc->sc_nbcnvaps++; 1061 } 1062 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1063 /* 1064 * Multple vaps are to transmit beacons and we 1065 * have h/w support for TSF adjusting; enable 1066 * use of staggered beacons. 1067 */ 1068 sc->sc_stagbeacons = 1; 1069 } 1070 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1071 } 1072 1073 ic->ic_opmode = ic_opmode; 1074 if (opmode != IEEE80211_M_WDS) { 1075 sc->sc_nvaps++; 1076 if (opmode == IEEE80211_M_STA) 1077 sc->sc_nstavaps++; 1078 if (opmode == IEEE80211_M_MBSS) 1079 sc->sc_nmeshvaps++; 1080 } 1081 switch (ic_opmode) { 1082 case IEEE80211_M_IBSS: 1083 sc->sc_opmode = HAL_M_IBSS; 1084 break; 1085 case IEEE80211_M_STA: 1086 sc->sc_opmode = HAL_M_STA; 1087 break; 1088 case IEEE80211_M_AHDEMO: 1089 #ifdef IEEE80211_SUPPORT_TDMA 1090 if (vap->iv_caps & IEEE80211_C_TDMA) { 1091 sc->sc_tdma = 1; 1092 /* NB: disable tsf adjust */ 1093 sc->sc_stagbeacons = 0; 1094 } 1095 /* 1096 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1097 * just ap mode. 1098 */ 1099 /* fall thru... */ 1100 #endif 1101 case IEEE80211_M_HOSTAP: 1102 case IEEE80211_M_MBSS: 1103 sc->sc_opmode = HAL_M_HOSTAP; 1104 break; 1105 case IEEE80211_M_MONITOR: 1106 sc->sc_opmode = HAL_M_MONITOR; 1107 break; 1108 default: 1109 /* XXX should not happen */ 1110 break; 1111 } 1112 if (sc->sc_hastsfadd) { 1113 /* 1114 * Configure whether or not TSF adjust should be done. 1115 */ 1116 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1117 } 1118 if (flags & IEEE80211_CLONE_NOBEACONS) { 1119 /* 1120 * Enable s/w beacon miss handling. 1121 */ 1122 sc->sc_swbmiss = 1; 1123 } 1124 ATH_UNLOCK(sc); 1125 1126 /* complete setup */ 1127 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1128 return vap; 1129 bad2: 1130 reclaim_address(sc, mac); 1131 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1132 bad: 1133 free(avp, M_80211_VAP); 1134 ATH_UNLOCK(sc); 1135 return NULL; 1136 } 1137 1138 static void 1139 ath_vap_delete(struct ieee80211vap *vap) 1140 { 1141 struct ieee80211com *ic = vap->iv_ic; 1142 struct ifnet *ifp = ic->ic_ifp; 1143 struct ath_softc *sc = ifp->if_softc; 1144 struct ath_hal *ah = sc->sc_ah; 1145 struct ath_vap *avp = ATH_VAP(vap); 1146 1147 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 1148 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1149 /* 1150 * Quiesce the hardware while we remove the vap. In 1151 * particular we need to reclaim all references to 1152 * the vap state by any frames pending on the tx queues. 1153 */ 1154 ath_hal_intrset(ah, 0); /* disable interrupts */ 1155 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */ 1156 /* XXX Do all frames from all vaps/nodes need draining here? */ 1157 ath_stoprecv(sc, 1); /* stop recv side */ 1158 } 1159 1160 ieee80211_vap_detach(vap); 1161 1162 /* 1163 * XXX Danger Will Robinson! Danger! 1164 * 1165 * Because ieee80211_vap_detach() can queue a frame (the station 1166 * diassociate message?) after we've drained the TXQ and 1167 * flushed the software TXQ, we will end up with a frame queued 1168 * to a node whose vap is about to be freed. 1169 * 1170 * To work around this, flush the hardware/software again. 1171 * This may be racy - the ath task may be running and the packet 1172 * may be being scheduled between sw->hw txq. Tsk. 1173 * 1174 * TODO: figure out why a new node gets allocated somewhere around 1175 * here (after the ath_tx_swq() call; and after an ath_stop_locked() 1176 * call!) 1177 */ 1178 1179 ath_draintxq(sc, ATH_RESET_DEFAULT); 1180 1181 ATH_LOCK(sc); 1182 /* 1183 * Reclaim beacon state. Note this must be done before 1184 * the vap instance is reclaimed as we may have a reference 1185 * to it in the buffer for the beacon frame. 1186 */ 1187 if (avp->av_bcbuf != NULL) { 1188 if (avp->av_bslot != -1) { 1189 sc->sc_bslot[avp->av_bslot] = NULL; 1190 sc->sc_nbcnvaps--; 1191 } 1192 ath_beacon_return(sc, avp->av_bcbuf); 1193 avp->av_bcbuf = NULL; 1194 if (sc->sc_nbcnvaps == 0) { 1195 sc->sc_stagbeacons = 0; 1196 if (sc->sc_hastsfadd) 1197 ath_hal_settsfadjust(sc->sc_ah, 0); 1198 } 1199 /* 1200 * Reclaim any pending mcast frames for the vap. 1201 */ 1202 ath_tx_draintxq(sc, &avp->av_mcastq); 1203 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq); 1204 } 1205 /* 1206 * Update bookkeeping. 1207 */ 1208 if (vap->iv_opmode == IEEE80211_M_STA) { 1209 sc->sc_nstavaps--; 1210 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1211 sc->sc_swbmiss = 0; 1212 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1213 vap->iv_opmode == IEEE80211_M_MBSS) { 1214 reclaim_address(sc, vap->iv_myaddr); 1215 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1216 if (vap->iv_opmode == IEEE80211_M_MBSS) 1217 sc->sc_nmeshvaps--; 1218 } 1219 if (vap->iv_opmode != IEEE80211_M_WDS) 1220 sc->sc_nvaps--; 1221 #ifdef IEEE80211_SUPPORT_TDMA 1222 /* TDMA operation ceases when the last vap is destroyed */ 1223 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1224 sc->sc_tdma = 0; 1225 sc->sc_swbmiss = 0; 1226 } 1227 #endif 1228 free(avp, M_80211_VAP); 1229 1230 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1231 /* 1232 * Restart rx+tx machines if still running (RUNNING will 1233 * be reset if we just destroyed the last vap). 1234 */ 1235 if (ath_startrecv(sc) != 0) 1236 if_printf(ifp, "%s: unable to restart recv logic\n", 1237 __func__); 1238 if (sc->sc_beacons) { /* restart beacons */ 1239 #ifdef IEEE80211_SUPPORT_TDMA 1240 if (sc->sc_tdma) 1241 ath_tdma_config(sc, NULL); 1242 else 1243 #endif 1244 ath_beacon_config(sc, NULL); 1245 } 1246 ath_hal_intrset(ah, sc->sc_imask); 1247 } 1248 ATH_UNLOCK(sc); 1249 } 1250 1251 void 1252 ath_suspend(struct ath_softc *sc) 1253 { 1254 struct ifnet *ifp = sc->sc_ifp; 1255 struct ieee80211com *ic = ifp->if_l2com; 1256 1257 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1258 __func__, ifp->if_flags); 1259 1260 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1261 if (ic->ic_opmode == IEEE80211_M_STA) 1262 ath_stop(ifp); 1263 else 1264 ieee80211_suspend_all(ic); 1265 /* 1266 * NB: don't worry about putting the chip in low power 1267 * mode; pci will power off our socket on suspend and 1268 * CardBus detaches the device. 1269 */ 1270 } 1271 1272 /* 1273 * Reset the key cache since some parts do not reset the 1274 * contents on resume. First we clear all entries, then 1275 * re-load keys that the 802.11 layer assumes are setup 1276 * in h/w. 1277 */ 1278 static void 1279 ath_reset_keycache(struct ath_softc *sc) 1280 { 1281 struct ifnet *ifp = sc->sc_ifp; 1282 struct ieee80211com *ic = ifp->if_l2com; 1283 struct ath_hal *ah = sc->sc_ah; 1284 int i; 1285 1286 for (i = 0; i < sc->sc_keymax; i++) 1287 ath_hal_keyreset(ah, i); 1288 ieee80211_crypto_reload_keys(ic); 1289 } 1290 1291 void 1292 ath_resume(struct ath_softc *sc) 1293 { 1294 struct ifnet *ifp = sc->sc_ifp; 1295 struct ieee80211com *ic = ifp->if_l2com; 1296 struct ath_hal *ah = sc->sc_ah; 1297 HAL_STATUS status; 1298 1299 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1300 __func__, ifp->if_flags); 1301 1302 /* 1303 * Must reset the chip before we reload the 1304 * keycache as we were powered down on suspend. 1305 */ 1306 ath_hal_reset(ah, sc->sc_opmode, 1307 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1308 AH_FALSE, &status); 1309 ath_reset_keycache(sc); 1310 1311 /* Let DFS at it in case it's a DFS channel */ 1312 ath_dfs_radar_enable(sc, ic->ic_curchan); 1313 1314 if (sc->sc_resume_up) { 1315 if (ic->ic_opmode == IEEE80211_M_STA) { 1316 ath_init(sc); 1317 /* 1318 * Program the beacon registers using the last rx'd 1319 * beacon frame and enable sync on the next beacon 1320 * we see. This should handle the case where we 1321 * wakeup and find the same AP and also the case where 1322 * we wakeup and need to roam. For the latter we 1323 * should get bmiss events that trigger a roam. 1324 */ 1325 ath_beacon_config(sc, NULL); 1326 sc->sc_syncbeacon = 1; 1327 } else 1328 ieee80211_resume_all(ic); 1329 } 1330 if (sc->sc_softled) { 1331 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 1332 HAL_GPIO_MUX_MAC_NETWORK_LED); 1333 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 1334 } 1335 1336 /* XXX beacons ? */ 1337 } 1338 1339 void 1340 ath_shutdown(struct ath_softc *sc) 1341 { 1342 struct ifnet *ifp = sc->sc_ifp; 1343 1344 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1345 __func__, ifp->if_flags); 1346 1347 ath_stop(ifp); 1348 /* NB: no point powering down chip as we're about to reboot */ 1349 } 1350 1351 /* 1352 * Interrupt handler. Most of the actual processing is deferred. 1353 */ 1354 void 1355 ath_intr(void *arg) 1356 { 1357 struct ath_softc *sc = arg; 1358 struct ifnet *ifp = sc->sc_ifp; 1359 struct ath_hal *ah = sc->sc_ah; 1360 HAL_INT status = 0; 1361 uint32_t txqs; 1362 1363 /* 1364 * If we're inside a reset path, just print a warning and 1365 * clear the ISR. The reset routine will finish it for us. 1366 */ 1367 ATH_PCU_LOCK(sc); 1368 if (sc->sc_inreset_cnt) { 1369 HAL_INT status; 1370 ath_hal_getisr(ah, &status); /* clear ISR */ 1371 ath_hal_intrset(ah, 0); /* disable further intr's */ 1372 DPRINTF(sc, ATH_DEBUG_ANY, 1373 "%s: in reset, ignoring: status=0x%x\n", 1374 __func__, status); 1375 ATH_PCU_UNLOCK(sc); 1376 return; 1377 } 1378 1379 if (sc->sc_invalid) { 1380 /* 1381 * The hardware is not ready/present, don't touch anything. 1382 * Note this can happen early on if the IRQ is shared. 1383 */ 1384 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1385 ATH_PCU_UNLOCK(sc); 1386 return; 1387 } 1388 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */ 1389 ATH_PCU_UNLOCK(sc); 1390 return; 1391 } 1392 1393 if ((ifp->if_flags & IFF_UP) == 0 || 1394 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1395 HAL_INT status; 1396 1397 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1398 __func__, ifp->if_flags); 1399 ath_hal_getisr(ah, &status); /* clear ISR */ 1400 ath_hal_intrset(ah, 0); /* disable further intr's */ 1401 ATH_PCU_UNLOCK(sc); 1402 return; 1403 } 1404 1405 /* 1406 * Figure out the reason(s) for the interrupt. Note 1407 * that the hal returns a pseudo-ISR that may include 1408 * bits we haven't explicitly enabled so we mask the 1409 * value to insure we only process bits we requested. 1410 */ 1411 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 1412 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 1413 CTR1(ATH_KTR_INTR, "ath_intr: mask=0x%.8x", status); 1414 #ifdef ATH_KTR_INTR_DEBUG 1415 CTR5(ATH_KTR_INTR, 1416 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x", 1417 ah->ah_intrstate[0], 1418 ah->ah_intrstate[1], 1419 ah->ah_intrstate[2], 1420 ah->ah_intrstate[3], 1421 ah->ah_intrstate[6]); 1422 #endif 1423 status &= sc->sc_imask; /* discard unasked for bits */ 1424 1425 /* Short-circuit un-handled interrupts */ 1426 if (status == 0x0) { 1427 ATH_PCU_UNLOCK(sc); 1428 return; 1429 } 1430 1431 /* 1432 * Take a note that we're inside the interrupt handler, so 1433 * the reset routines know to wait. 1434 */ 1435 sc->sc_intr_cnt++; 1436 ATH_PCU_UNLOCK(sc); 1437 1438 /* 1439 * Handle the interrupt. We won't run concurrent with the reset 1440 * or channel change routines as they'll wait for sc_intr_cnt 1441 * to be 0 before continuing. 1442 */ 1443 if (status & HAL_INT_FATAL) { 1444 sc->sc_stats.ast_hardware++; 1445 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1446 ath_fatal_proc(sc, 0); 1447 } else { 1448 if (status & HAL_INT_SWBA) { 1449 /* 1450 * Software beacon alert--time to send a beacon. 1451 * Handle beacon transmission directly; deferring 1452 * this is too slow to meet timing constraints 1453 * under load. 1454 */ 1455 #ifdef IEEE80211_SUPPORT_TDMA 1456 if (sc->sc_tdma) { 1457 if (sc->sc_tdmaswba == 0) { 1458 struct ieee80211com *ic = ifp->if_l2com; 1459 struct ieee80211vap *vap = 1460 TAILQ_FIRST(&ic->ic_vaps); 1461 ath_tdma_beacon_send(sc, vap); 1462 sc->sc_tdmaswba = 1463 vap->iv_tdma->tdma_bintval; 1464 } else 1465 sc->sc_tdmaswba--; 1466 } else 1467 #endif 1468 { 1469 ath_beacon_proc(sc, 0); 1470 #ifdef IEEE80211_SUPPORT_SUPERG 1471 /* 1472 * Schedule the rx taskq in case there's no 1473 * traffic so any frames held on the staging 1474 * queue are aged and potentially flushed. 1475 */ 1476 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1477 #endif 1478 } 1479 } 1480 if (status & HAL_INT_RXEOL) { 1481 int imask; 1482 CTR0(ATH_KTR_ERR, "ath_intr: RXEOL"); 1483 ATH_PCU_LOCK(sc); 1484 /* 1485 * NB: the hardware should re-read the link when 1486 * RXE bit is written, but it doesn't work at 1487 * least on older hardware revs. 1488 */ 1489 sc->sc_stats.ast_rxeol++; 1490 /* 1491 * Disable RXEOL/RXORN - prevent an interrupt 1492 * storm until the PCU logic can be reset. 1493 * In case the interface is reset some other 1494 * way before "sc_kickpcu" is called, don't 1495 * modify sc_imask - that way if it is reset 1496 * by a call to ath_reset() somehow, the 1497 * interrupt mask will be correctly reprogrammed. 1498 */ 1499 imask = sc->sc_imask; 1500 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN); 1501 ath_hal_intrset(ah, imask); 1502 /* 1503 * Only blank sc_rxlink if we've not yet kicked 1504 * the PCU. 1505 * 1506 * This isn't entirely correct - the correct solution 1507 * would be to have a PCU lock and engage that for 1508 * the duration of the PCU fiddling; which would include 1509 * running the RX process. Otherwise we could end up 1510 * messing up the RX descriptor chain and making the 1511 * RX desc list much shorter. 1512 */ 1513 if (! sc->sc_kickpcu) 1514 sc->sc_rxlink = NULL; 1515 sc->sc_kickpcu = 1; 1516 /* 1517 * Enqueue an RX proc, to handled whatever 1518 * is in the RX queue. 1519 * This will then kick the PCU. 1520 */ 1521 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1522 ATH_PCU_UNLOCK(sc); 1523 } 1524 if (status & HAL_INT_TXURN) { 1525 sc->sc_stats.ast_txurn++; 1526 /* bump tx trigger level */ 1527 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1528 } 1529 if (status & HAL_INT_RX) { 1530 sc->sc_stats.ast_rx_intr++; 1531 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1532 } 1533 if (status & HAL_INT_TX) { 1534 sc->sc_stats.ast_tx_intr++; 1535 /* 1536 * Grab all the currently set bits in the HAL txq bitmap 1537 * and blank them. This is the only place we should be 1538 * doing this. 1539 */ 1540 ATH_PCU_LOCK(sc); 1541 txqs = 0xffffffff; 1542 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs); 1543 sc->sc_txq_active |= txqs; 1544 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1545 ATH_PCU_UNLOCK(sc); 1546 } 1547 if (status & HAL_INT_BMISS) { 1548 sc->sc_stats.ast_bmiss++; 1549 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1550 } 1551 if (status & HAL_INT_GTT) 1552 sc->sc_stats.ast_tx_timeout++; 1553 if (status & HAL_INT_CST) 1554 sc->sc_stats.ast_tx_cst++; 1555 if (status & HAL_INT_MIB) { 1556 sc->sc_stats.ast_mib++; 1557 ATH_PCU_LOCK(sc); 1558 /* 1559 * Disable interrupts until we service the MIB 1560 * interrupt; otherwise it will continue to fire. 1561 */ 1562 ath_hal_intrset(ah, 0); 1563 /* 1564 * Let the hal handle the event. We assume it will 1565 * clear whatever condition caused the interrupt. 1566 */ 1567 ath_hal_mibevent(ah, &sc->sc_halstats); 1568 /* 1569 * Don't reset the interrupt if we've just 1570 * kicked the PCU, or we may get a nested 1571 * RXEOL before the rxproc has had a chance 1572 * to run. 1573 */ 1574 if (sc->sc_kickpcu == 0) 1575 ath_hal_intrset(ah, sc->sc_imask); 1576 ATH_PCU_UNLOCK(sc); 1577 } 1578 if (status & HAL_INT_RXORN) { 1579 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1580 CTR0(ATH_KTR_ERR, "ath_intr: RXORN"); 1581 sc->sc_stats.ast_rxorn++; 1582 } 1583 } 1584 ATH_PCU_LOCK(sc); 1585 sc->sc_intr_cnt--; 1586 ATH_PCU_UNLOCK(sc); 1587 } 1588 1589 static void 1590 ath_fatal_proc(void *arg, int pending) 1591 { 1592 struct ath_softc *sc = arg; 1593 struct ifnet *ifp = sc->sc_ifp; 1594 u_int32_t *state; 1595 u_int32_t len; 1596 void *sp; 1597 1598 if_printf(ifp, "hardware error; resetting\n"); 1599 /* 1600 * Fatal errors are unrecoverable. Typically these 1601 * are caused by DMA errors. Collect h/w state from 1602 * the hal so we can diagnose what's going on. 1603 */ 1604 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1605 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1606 state = sp; 1607 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1608 state[0], state[1] , state[2], state[3], 1609 state[4], state[5]); 1610 } 1611 ath_reset(ifp, ATH_RESET_NOLOSS); 1612 } 1613 1614 static void 1615 ath_bmiss_vap(struct ieee80211vap *vap) 1616 { 1617 /* 1618 * Workaround phantom bmiss interrupts by sanity-checking 1619 * the time of our last rx'd frame. If it is within the 1620 * beacon miss interval then ignore the interrupt. If it's 1621 * truly a bmiss we'll get another interrupt soon and that'll 1622 * be dispatched up for processing. Note this applies only 1623 * for h/w beacon miss events. 1624 */ 1625 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1626 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1627 struct ath_softc *sc = ifp->if_softc; 1628 u_int64_t lastrx = sc->sc_lastrx; 1629 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1630 u_int bmisstimeout = 1631 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1632 1633 DPRINTF(sc, ATH_DEBUG_BEACON, 1634 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1635 __func__, (unsigned long long) tsf, 1636 (unsigned long long)(tsf - lastrx), 1637 (unsigned long long) lastrx, bmisstimeout); 1638 1639 if (tsf - lastrx <= bmisstimeout) { 1640 sc->sc_stats.ast_bmiss_phantom++; 1641 return; 1642 } 1643 } 1644 ATH_VAP(vap)->av_bmiss(vap); 1645 } 1646 1647 static int 1648 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1649 { 1650 uint32_t rsize; 1651 void *sp; 1652 1653 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize)) 1654 return 0; 1655 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1656 *hangs = *(uint32_t *)sp; 1657 return 1; 1658 } 1659 1660 static void 1661 ath_bmiss_proc(void *arg, int pending) 1662 { 1663 struct ath_softc *sc = arg; 1664 struct ifnet *ifp = sc->sc_ifp; 1665 uint32_t hangs; 1666 1667 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1668 1669 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1670 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs); 1671 ath_reset(ifp, ATH_RESET_NOLOSS); 1672 } else 1673 ieee80211_beacon_miss(ifp->if_l2com); 1674 } 1675 1676 /* 1677 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1678 * calcs together with WME. If necessary disable the crypto 1679 * hardware and mark the 802.11 state so keys will be setup 1680 * with the MIC work done in software. 1681 */ 1682 static void 1683 ath_settkipmic(struct ath_softc *sc) 1684 { 1685 struct ifnet *ifp = sc->sc_ifp; 1686 struct ieee80211com *ic = ifp->if_l2com; 1687 1688 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1689 if (ic->ic_flags & IEEE80211_F_WME) { 1690 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1691 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1692 } else { 1693 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1694 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1695 } 1696 } 1697 } 1698 1699 static void 1700 ath_init(void *arg) 1701 { 1702 struct ath_softc *sc = (struct ath_softc *) arg; 1703 struct ifnet *ifp = sc->sc_ifp; 1704 struct ieee80211com *ic = ifp->if_l2com; 1705 struct ath_hal *ah = sc->sc_ah; 1706 HAL_STATUS status; 1707 1708 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1709 __func__, ifp->if_flags); 1710 1711 ATH_LOCK(sc); 1712 /* 1713 * Stop anything previously setup. This is safe 1714 * whether this is the first time through or not. 1715 */ 1716 ath_stop_locked(ifp); 1717 1718 /* 1719 * The basic interface to setting the hardware in a good 1720 * state is ``reset''. On return the hardware is known to 1721 * be powered up and with interrupts disabled. This must 1722 * be followed by initialization of the appropriate bits 1723 * and then setup of the interrupt mask. 1724 */ 1725 ath_settkipmic(sc); 1726 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 1727 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1728 status); 1729 ATH_UNLOCK(sc); 1730 return; 1731 } 1732 ath_chan_change(sc, ic->ic_curchan); 1733 1734 /* Let DFS at it in case it's a DFS channel */ 1735 ath_dfs_radar_enable(sc, ic->ic_curchan); 1736 1737 /* 1738 * Likewise this is set during reset so update 1739 * state cached in the driver. 1740 */ 1741 sc->sc_diversity = ath_hal_getdiversity(ah); 1742 sc->sc_lastlongcal = 0; 1743 sc->sc_resetcal = 1; 1744 sc->sc_lastcalreset = 0; 1745 sc->sc_lastani = 0; 1746 sc->sc_lastshortcal = 0; 1747 sc->sc_doresetcal = AH_FALSE; 1748 /* 1749 * Beacon timers were cleared here; give ath_newstate() 1750 * a hint that the beacon timers should be poked when 1751 * things transition to the RUN state. 1752 */ 1753 sc->sc_beacons = 0; 1754 1755 /* 1756 * Initial aggregation settings. 1757 */ 1758 sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH; 1759 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW; 1760 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH; 1761 1762 /* 1763 * Setup the hardware after reset: the key cache 1764 * is filled as needed and the receive engine is 1765 * set going. Frame transmit is handled entirely 1766 * in the frame output path; there's nothing to do 1767 * here except setup the interrupt mask. 1768 */ 1769 if (ath_startrecv(sc) != 0) { 1770 if_printf(ifp, "unable to start recv logic\n"); 1771 ATH_UNLOCK(sc); 1772 return; 1773 } 1774 1775 /* 1776 * Enable interrupts. 1777 */ 1778 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1779 | HAL_INT_RXEOL | HAL_INT_RXORN 1780 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1781 /* 1782 * Enable MIB interrupts when there are hardware phy counters. 1783 * Note we only do this (at the moment) for station mode. 1784 */ 1785 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1786 sc->sc_imask |= HAL_INT_MIB; 1787 1788 /* Enable global TX timeout and carrier sense timeout if available */ 1789 if (ath_hal_gtxto_supported(ah)) 1790 sc->sc_imask |= HAL_INT_GTT; 1791 1792 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n", 1793 __func__, sc->sc_imask); 1794 1795 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1796 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc); 1797 ath_hal_intrset(ah, sc->sc_imask); 1798 1799 ATH_UNLOCK(sc); 1800 1801 #ifdef ATH_TX99_DIAG 1802 if (sc->sc_tx99 != NULL) 1803 sc->sc_tx99->start(sc->sc_tx99); 1804 else 1805 #endif 1806 ieee80211_start_all(ic); /* start all vap's */ 1807 } 1808 1809 static void 1810 ath_stop_locked(struct ifnet *ifp) 1811 { 1812 struct ath_softc *sc = ifp->if_softc; 1813 struct ath_hal *ah = sc->sc_ah; 1814 1815 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1816 __func__, sc->sc_invalid, ifp->if_flags); 1817 1818 ATH_LOCK_ASSERT(sc); 1819 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1820 /* 1821 * Shutdown the hardware and driver: 1822 * reset 802.11 state machine 1823 * turn off timers 1824 * disable interrupts 1825 * turn off the radio 1826 * clear transmit machinery 1827 * clear receive machinery 1828 * drain and release tx queues 1829 * reclaim beacon resources 1830 * power down hardware 1831 * 1832 * Note that some of this work is not possible if the 1833 * hardware is gone (invalid). 1834 */ 1835 #ifdef ATH_TX99_DIAG 1836 if (sc->sc_tx99 != NULL) 1837 sc->sc_tx99->stop(sc->sc_tx99); 1838 #endif 1839 callout_stop(&sc->sc_wd_ch); 1840 sc->sc_wd_timer = 0; 1841 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1842 if (!sc->sc_invalid) { 1843 if (sc->sc_softled) { 1844 callout_stop(&sc->sc_ledtimer); 1845 ath_hal_gpioset(ah, sc->sc_ledpin, 1846 !sc->sc_ledon); 1847 sc->sc_blinking = 0; 1848 } 1849 ath_hal_intrset(ah, 0); 1850 } 1851 ath_draintxq(sc, ATH_RESET_DEFAULT); 1852 if (!sc->sc_invalid) { 1853 ath_stoprecv(sc, 1); 1854 ath_hal_phydisable(ah); 1855 } else 1856 sc->sc_rxlink = NULL; 1857 ath_beacon_free(sc); /* XXX not needed */ 1858 } 1859 } 1860 1861 #define MAX_TXRX_ITERATIONS 1000 1862 static void 1863 ath_txrx_stop(struct ath_softc *sc) 1864 { 1865 int i = MAX_TXRX_ITERATIONS; 1866 1867 ATH_UNLOCK_ASSERT(sc); 1868 /* Stop any new TX/RX from occuring */ 1869 taskqueue_block(sc->sc_tq); 1870 1871 ATH_PCU_LOCK(sc); 1872 /* 1873 * Sleep until all the pending operations have completed. 1874 * 1875 * The caller must ensure that reset has been incremented 1876 * or the pending operations may continue being queued. 1877 */ 1878 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt || 1879 sc->sc_txstart_cnt || sc->sc_intr_cnt) { 1880 if (i <= 0) 1881 break; 1882 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop", 1); 1883 i--; 1884 } 1885 ATH_PCU_UNLOCK(sc); 1886 1887 if (i <= 0) 1888 device_printf(sc->sc_dev, 1889 "%s: didn't finish after %d iterations\n", 1890 __func__, MAX_TXRX_ITERATIONS); 1891 } 1892 #undef MAX_TXRX_ITERATIONS 1893 1894 static void 1895 ath_txrx_start(struct ath_softc *sc) 1896 { 1897 1898 taskqueue_unblock(sc->sc_tq); 1899 } 1900 1901 static void 1902 ath_stop(struct ifnet *ifp) 1903 { 1904 struct ath_softc *sc = ifp->if_softc; 1905 1906 ATH_LOCK(sc); 1907 ath_stop_locked(ifp); 1908 ATH_UNLOCK(sc); 1909 } 1910 1911 /* 1912 * Reset the hardware w/o losing operational state. This is 1913 * basically a more efficient way of doing ath_stop, ath_init, 1914 * followed by state transitions to the current 802.11 1915 * operational state. Used to recover from various errors and 1916 * to reset or reload hardware state. 1917 */ 1918 int 1919 ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type) 1920 { 1921 struct ath_softc *sc = ifp->if_softc; 1922 struct ieee80211com *ic = ifp->if_l2com; 1923 struct ath_hal *ah = sc->sc_ah; 1924 HAL_STATUS status; 1925 int i; 1926 1927 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 1928 1929 /* XXX ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */ 1930 ATH_PCU_UNLOCK_ASSERT(sc); 1931 ATH_UNLOCK_ASSERT(sc); 1932 1933 ATH_PCU_LOCK(sc); 1934 /* XXX if we're already inside a reset, print out a big warning */ 1935 if (sc->sc_inreset_cnt > 0) { 1936 device_printf(sc->sc_dev, 1937 "%s: concurrent ath_reset()! Danger!\n", 1938 __func__); 1939 } 1940 sc->sc_inreset_cnt++; 1941 ath_hal_intrset(ah, 0); /* disable interrupts */ 1942 ATH_PCU_UNLOCK(sc); 1943 1944 /* 1945 * Should now wait for pending TX/RX to complete 1946 * and block future ones from occuring. This needs to be 1947 * done before the TX queue is drained. 1948 */ 1949 ath_txrx_stop(sc); 1950 ath_draintxq(sc, reset_type); /* stop xmit side */ 1951 1952 /* 1953 * Regardless of whether we're doing a no-loss flush or 1954 * not, stop the PCU and handle what's in the RX queue. 1955 * That way frames aren't dropped which shouldn't be. 1956 */ 1957 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS)); 1958 ath_rx_proc(sc, 0); 1959 1960 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1961 /* NB: indicate channel change so we do a full reset */ 1962 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 1963 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1964 __func__, status); 1965 sc->sc_diversity = ath_hal_getdiversity(ah); 1966 1967 /* Let DFS at it in case it's a DFS channel */ 1968 ath_dfs_radar_enable(sc, ic->ic_curchan); 1969 1970 if (ath_startrecv(sc) != 0) /* restart recv */ 1971 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1972 /* 1973 * We may be doing a reset in response to an ioctl 1974 * that changes the channel so update any state that 1975 * might change as a result. 1976 */ 1977 ath_chan_change(sc, ic->ic_curchan); 1978 if (sc->sc_beacons) { /* restart beacons */ 1979 #ifdef IEEE80211_SUPPORT_TDMA 1980 if (sc->sc_tdma) 1981 ath_tdma_config(sc, NULL); 1982 else 1983 #endif 1984 ath_beacon_config(sc, NULL); 1985 } 1986 1987 /* 1988 * Release the reset lock and re-enable interrupts here. 1989 * If an interrupt was being processed in ath_intr(), 1990 * it would disable interrupts at this point. So we have 1991 * to atomically enable interrupts and decrement the 1992 * reset counter - this way ath_intr() doesn't end up 1993 * disabling interrupts without a corresponding enable 1994 * in the rest or channel change path. 1995 */ 1996 ATH_PCU_LOCK(sc); 1997 sc->sc_inreset_cnt--; 1998 /* XXX only do this if sc_inreset_cnt == 0? */ 1999 ath_hal_intrset(ah, sc->sc_imask); 2000 ATH_PCU_UNLOCK(sc); 2001 2002 /* 2003 * TX and RX can be started here. If it were started with 2004 * sc_inreset_cnt > 0, the TX and RX path would abort. 2005 * Thus if this is a nested call through the reset or 2006 * channel change code, TX completion will occur but 2007 * RX completion and ath_start / ath_tx_start will not 2008 * run. 2009 */ 2010 2011 /* Restart TX/RX as needed */ 2012 ath_txrx_start(sc); 2013 2014 /* XXX Restart TX completion and pending TX */ 2015 if (reset_type == ATH_RESET_NOLOSS) { 2016 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 2017 if (ATH_TXQ_SETUP(sc, i)) { 2018 ATH_TXQ_LOCK(&sc->sc_txq[i]); 2019 ath_txq_restart_dma(sc, &sc->sc_txq[i]); 2020 ath_txq_sched(sc, &sc->sc_txq[i]); 2021 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 2022 } 2023 } 2024 } 2025 2026 /* 2027 * This may have been set during an ath_start() call which 2028 * set this once it detected a concurrent TX was going on. 2029 * So, clear it. 2030 */ 2031 /* XXX do this inside of IF_LOCK? */ 2032 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2033 2034 /* Handle any frames in the TX queue */ 2035 /* 2036 * XXX should this be done by the caller, rather than 2037 * ath_reset() ? 2038 */ 2039 ath_start(ifp); /* restart xmit */ 2040 return 0; 2041 } 2042 2043 static int 2044 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 2045 { 2046 struct ieee80211com *ic = vap->iv_ic; 2047 struct ifnet *ifp = ic->ic_ifp; 2048 struct ath_softc *sc = ifp->if_softc; 2049 struct ath_hal *ah = sc->sc_ah; 2050 2051 switch (cmd) { 2052 case IEEE80211_IOC_TXPOWER: 2053 /* 2054 * If per-packet TPC is enabled, then we have nothing 2055 * to do; otherwise we need to force the global limit. 2056 * All this can happen directly; no need to reset. 2057 */ 2058 if (!ath_hal_gettpc(ah)) 2059 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 2060 return 0; 2061 } 2062 /* XXX? Full or NOLOSS? */ 2063 return ath_reset(ifp, ATH_RESET_FULL); 2064 } 2065 2066 struct ath_buf * 2067 _ath_getbuf_locked(struct ath_softc *sc) 2068 { 2069 struct ath_buf *bf; 2070 2071 ATH_TXBUF_LOCK_ASSERT(sc); 2072 2073 bf = TAILQ_FIRST(&sc->sc_txbuf); 2074 if (bf == NULL) { 2075 sc->sc_stats.ast_tx_getnobuf++; 2076 } else { 2077 if (bf->bf_flags & ATH_BUF_BUSY) { 2078 sc->sc_stats.ast_tx_getbusybuf++; 2079 bf = NULL; 2080 } 2081 } 2082 2083 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) 2084 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list); 2085 else 2086 bf = NULL; 2087 2088 if (bf == NULL) { 2089 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 2090 TAILQ_FIRST(&sc->sc_txbuf) == NULL ? 2091 "out of xmit buffers" : "xmit buffer busy"); 2092 return NULL; 2093 } 2094 2095 /* Valid bf here; clear some basic fields */ 2096 bf->bf_next = NULL; /* XXX just to be sure */ 2097 bf->bf_last = NULL; /* XXX again, just to be sure */ 2098 bf->bf_comp = NULL; /* XXX again, just to be sure */ 2099 bzero(&bf->bf_state, sizeof(bf->bf_state)); 2100 2101 return bf; 2102 } 2103 2104 /* 2105 * When retrying a software frame, buffers marked ATH_BUF_BUSY 2106 * can't be thrown back on the queue as they could still be 2107 * in use by the hardware. 2108 * 2109 * This duplicates the buffer, or returns NULL. 2110 * 2111 * The descriptor is also copied but the link pointers and 2112 * the DMA segments aren't copied; this frame should thus 2113 * be again passed through the descriptor setup/chain routines 2114 * so the link is correct. 2115 * 2116 * The caller must free the buffer using ath_freebuf(). 2117 * 2118 * XXX TODO: this call shouldn't fail as it'll cause packet loss 2119 * XXX in the TX pathway when retries are needed. 2120 * XXX Figure out how to keep some buffers free, or factor the 2121 * XXX number of busy buffers into the xmit path (ath_start()) 2122 * XXX so we don't over-commit. 2123 */ 2124 struct ath_buf * 2125 ath_buf_clone(struct ath_softc *sc, const struct ath_buf *bf) 2126 { 2127 struct ath_buf *tbf; 2128 2129 tbf = ath_getbuf(sc); 2130 if (tbf == NULL) 2131 return NULL; /* XXX failure? Why? */ 2132 2133 /* Copy basics */ 2134 tbf->bf_next = NULL; 2135 tbf->bf_nseg = bf->bf_nseg; 2136 tbf->bf_txflags = bf->bf_txflags; 2137 tbf->bf_flags = bf->bf_flags & ~ATH_BUF_BUSY; 2138 tbf->bf_status = bf->bf_status; 2139 tbf->bf_m = bf->bf_m; 2140 tbf->bf_node = bf->bf_node; 2141 /* will be setup by the chain/setup function */ 2142 tbf->bf_lastds = NULL; 2143 /* for now, last == self */ 2144 tbf->bf_last = tbf; 2145 tbf->bf_comp = bf->bf_comp; 2146 2147 /* NOTE: DMA segments will be setup by the setup/chain functions */ 2148 2149 /* The caller has to re-init the descriptor + links */ 2150 2151 /* Copy state */ 2152 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state)); 2153 2154 return tbf; 2155 } 2156 2157 struct ath_buf * 2158 ath_getbuf(struct ath_softc *sc) 2159 { 2160 struct ath_buf *bf; 2161 2162 ATH_TXBUF_LOCK(sc); 2163 bf = _ath_getbuf_locked(sc); 2164 if (bf == NULL) { 2165 struct ifnet *ifp = sc->sc_ifp; 2166 2167 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 2168 sc->sc_stats.ast_tx_qstop++; 2169 /* XXX do this inside of IF_LOCK? */ 2170 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2171 } 2172 ATH_TXBUF_UNLOCK(sc); 2173 return bf; 2174 } 2175 2176 static void 2177 ath_start(struct ifnet *ifp) 2178 { 2179 struct ath_softc *sc = ifp->if_softc; 2180 struct ieee80211_node *ni; 2181 struct ath_buf *bf; 2182 struct mbuf *m, *next; 2183 ath_bufhead frags; 2184 2185 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 2186 return; 2187 2188 /* XXX is it ok to hold the ATH_LOCK here? */ 2189 ATH_PCU_LOCK(sc); 2190 if (sc->sc_inreset_cnt > 0) { 2191 device_printf(sc->sc_dev, 2192 "%s: sc_inreset_cnt > 0; bailing\n", __func__); 2193 /* XXX do this inside of IF_LOCK? */ 2194 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2195 ATH_PCU_UNLOCK(sc); 2196 return; 2197 } 2198 sc->sc_txstart_cnt++; 2199 ATH_PCU_UNLOCK(sc); 2200 2201 for (;;) { 2202 /* 2203 * Grab a TX buffer and associated resources. 2204 */ 2205 bf = ath_getbuf(sc); 2206 if (bf == NULL) 2207 break; 2208 2209 IFQ_DEQUEUE(&ifp->if_snd, m); 2210 if (m == NULL) { 2211 ATH_TXBUF_LOCK(sc); 2212 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 2213 ATH_TXBUF_UNLOCK(sc); 2214 break; 2215 } 2216 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 2217 /* 2218 * Check for fragmentation. If this frame 2219 * has been broken up verify we have enough 2220 * buffers to send all the fragments so all 2221 * go out or none... 2222 */ 2223 TAILQ_INIT(&frags); 2224 if ((m->m_flags & M_FRAG) && 2225 !ath_txfrag_setup(sc, &frags, m, ni)) { 2226 DPRINTF(sc, ATH_DEBUG_XMIT, 2227 "%s: out of txfrag buffers\n", __func__); 2228 sc->sc_stats.ast_tx_nofrag++; 2229 ifp->if_oerrors++; 2230 ath_freetx(m); 2231 goto bad; 2232 } 2233 ifp->if_opackets++; 2234 nextfrag: 2235 /* 2236 * Pass the frame to the h/w for transmission. 2237 * Fragmented frames have each frag chained together 2238 * with m_nextpkt. We know there are sufficient ath_buf's 2239 * to send all the frags because of work done by 2240 * ath_txfrag_setup. We leave m_nextpkt set while 2241 * calling ath_tx_start so it can use it to extend the 2242 * the tx duration to cover the subsequent frag and 2243 * so it can reclaim all the mbufs in case of an error; 2244 * ath_tx_start clears m_nextpkt once it commits to 2245 * handing the frame to the hardware. 2246 */ 2247 next = m->m_nextpkt; 2248 if (ath_tx_start(sc, ni, bf, m)) { 2249 bad: 2250 ifp->if_oerrors++; 2251 reclaim: 2252 bf->bf_m = NULL; 2253 bf->bf_node = NULL; 2254 ATH_TXBUF_LOCK(sc); 2255 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 2256 ath_txfrag_cleanup(sc, &frags, ni); 2257 ATH_TXBUF_UNLOCK(sc); 2258 if (ni != NULL) 2259 ieee80211_free_node(ni); 2260 continue; 2261 } 2262 if (next != NULL) { 2263 /* 2264 * Beware of state changing between frags. 2265 * XXX check sta power-save state? 2266 */ 2267 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 2268 DPRINTF(sc, ATH_DEBUG_XMIT, 2269 "%s: flush fragmented packet, state %s\n", 2270 __func__, 2271 ieee80211_state_name[ni->ni_vap->iv_state]); 2272 ath_freetx(next); 2273 goto reclaim; 2274 } 2275 m = next; 2276 bf = TAILQ_FIRST(&frags); 2277 KASSERT(bf != NULL, ("no buf for txfrag")); 2278 TAILQ_REMOVE(&frags, bf, bf_list); 2279 goto nextfrag; 2280 } 2281 2282 sc->sc_wd_timer = 5; 2283 } 2284 2285 ATH_PCU_LOCK(sc); 2286 sc->sc_txstart_cnt--; 2287 ATH_PCU_UNLOCK(sc); 2288 } 2289 2290 static int 2291 ath_media_change(struct ifnet *ifp) 2292 { 2293 int error = ieee80211_media_change(ifp); 2294 /* NB: only the fixed rate can change and that doesn't need a reset */ 2295 return (error == ENETRESET ? 0 : error); 2296 } 2297 2298 /* 2299 * Block/unblock tx+rx processing while a key change is done. 2300 * We assume the caller serializes key management operations 2301 * so we only need to worry about synchronization with other 2302 * uses that originate in the driver. 2303 */ 2304 static void 2305 ath_key_update_begin(struct ieee80211vap *vap) 2306 { 2307 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2308 struct ath_softc *sc = ifp->if_softc; 2309 2310 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2311 taskqueue_block(sc->sc_tq); 2312 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2313 } 2314 2315 static void 2316 ath_key_update_end(struct ieee80211vap *vap) 2317 { 2318 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2319 struct ath_softc *sc = ifp->if_softc; 2320 2321 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2322 IF_UNLOCK(&ifp->if_snd); 2323 taskqueue_unblock(sc->sc_tq); 2324 } 2325 2326 /* 2327 * Calculate the receive filter according to the 2328 * operating mode and state: 2329 * 2330 * o always accept unicast, broadcast, and multicast traffic 2331 * o accept PHY error frames when hardware doesn't have MIB support 2332 * to count and we need them for ANI (sta mode only until recently) 2333 * and we are not scanning (ANI is disabled) 2334 * NB: older hal's add rx filter bits out of sight and we need to 2335 * blindly preserve them 2336 * o probe request frames are accepted only when operating in 2337 * hostap, adhoc, mesh, or monitor modes 2338 * o enable promiscuous mode 2339 * - when in monitor mode 2340 * - if interface marked PROMISC (assumes bridge setting is filtered) 2341 * o accept beacons: 2342 * - when operating in station mode for collecting rssi data when 2343 * the station is otherwise quiet, or 2344 * - when operating in adhoc mode so the 802.11 layer creates 2345 * node table entries for peers, 2346 * - when scanning 2347 * - when doing s/w beacon miss (e.g. for ap+sta) 2348 * - when operating in ap mode in 11g to detect overlapping bss that 2349 * require protection 2350 * - when operating in mesh mode to detect neighbors 2351 * o accept control frames: 2352 * - when in monitor mode 2353 * XXX HT protection for 11n 2354 */ 2355 static u_int32_t 2356 ath_calcrxfilter(struct ath_softc *sc) 2357 { 2358 struct ifnet *ifp = sc->sc_ifp; 2359 struct ieee80211com *ic = ifp->if_l2com; 2360 u_int32_t rfilt; 2361 2362 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2363 if (!sc->sc_needmib && !sc->sc_scanning) 2364 rfilt |= HAL_RX_FILTER_PHYERR; 2365 if (ic->ic_opmode != IEEE80211_M_STA) 2366 rfilt |= HAL_RX_FILTER_PROBEREQ; 2367 /* XXX ic->ic_monvaps != 0? */ 2368 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 2369 rfilt |= HAL_RX_FILTER_PROM; 2370 if (ic->ic_opmode == IEEE80211_M_STA || 2371 ic->ic_opmode == IEEE80211_M_IBSS || 2372 sc->sc_swbmiss || sc->sc_scanning) 2373 rfilt |= HAL_RX_FILTER_BEACON; 2374 /* 2375 * NB: We don't recalculate the rx filter when 2376 * ic_protmode changes; otherwise we could do 2377 * this only when ic_protmode != NONE. 2378 */ 2379 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 2380 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 2381 rfilt |= HAL_RX_FILTER_BEACON; 2382 2383 /* 2384 * Enable hardware PS-POLL RX only for hostap mode; 2385 * STA mode sends PS-POLL frames but never 2386 * receives them. 2387 */ 2388 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 2389 0, NULL) == HAL_OK && 2390 ic->ic_opmode == IEEE80211_M_HOSTAP) 2391 rfilt |= HAL_RX_FILTER_PSPOLL; 2392 2393 if (sc->sc_nmeshvaps) { 2394 rfilt |= HAL_RX_FILTER_BEACON; 2395 if (sc->sc_hasbmatch) 2396 rfilt |= HAL_RX_FILTER_BSSID; 2397 else 2398 rfilt |= HAL_RX_FILTER_PROM; 2399 } 2400 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2401 rfilt |= HAL_RX_FILTER_CONTROL; 2402 2403 /* 2404 * Enable RX of compressed BAR frames only when doing 2405 * 802.11n. Required for A-MPDU. 2406 */ 2407 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 2408 rfilt |= HAL_RX_FILTER_COMPBAR; 2409 2410 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 2411 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 2412 return rfilt; 2413 } 2414 2415 static void 2416 ath_update_promisc(struct ifnet *ifp) 2417 { 2418 struct ath_softc *sc = ifp->if_softc; 2419 u_int32_t rfilt; 2420 2421 /* configure rx filter */ 2422 rfilt = ath_calcrxfilter(sc); 2423 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2424 2425 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2426 } 2427 2428 static void 2429 ath_update_mcast(struct ifnet *ifp) 2430 { 2431 struct ath_softc *sc = ifp->if_softc; 2432 u_int32_t mfilt[2]; 2433 2434 /* calculate and install multicast filter */ 2435 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2436 struct ifmultiaddr *ifma; 2437 /* 2438 * Merge multicast addresses to form the hardware filter. 2439 */ 2440 mfilt[0] = mfilt[1] = 0; 2441 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */ 2442 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2443 caddr_t dl; 2444 u_int32_t val; 2445 u_int8_t pos; 2446 2447 /* calculate XOR of eight 6bit values */ 2448 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2449 val = LE_READ_4(dl + 0); 2450 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2451 val = LE_READ_4(dl + 3); 2452 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2453 pos &= 0x3f; 2454 mfilt[pos / 32] |= (1 << (pos % 32)); 2455 } 2456 if_maddr_runlock(ifp); 2457 } else 2458 mfilt[0] = mfilt[1] = ~0; 2459 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2460 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2461 __func__, mfilt[0], mfilt[1]); 2462 } 2463 2464 static void 2465 ath_mode_init(struct ath_softc *sc) 2466 { 2467 struct ifnet *ifp = sc->sc_ifp; 2468 struct ath_hal *ah = sc->sc_ah; 2469 u_int32_t rfilt; 2470 2471 /* configure rx filter */ 2472 rfilt = ath_calcrxfilter(sc); 2473 ath_hal_setrxfilter(ah, rfilt); 2474 2475 /* configure operational mode */ 2476 ath_hal_setopmode(ah); 2477 2478 /* handle any link-level address change */ 2479 ath_hal_setmac(ah, IF_LLADDR(ifp)); 2480 2481 /* calculate and install multicast filter */ 2482 ath_update_mcast(ifp); 2483 } 2484 2485 /* 2486 * Set the slot time based on the current setting. 2487 */ 2488 static void 2489 ath_setslottime(struct ath_softc *sc) 2490 { 2491 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2492 struct ath_hal *ah = sc->sc_ah; 2493 u_int usec; 2494 2495 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2496 usec = 13; 2497 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2498 usec = 21; 2499 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2500 /* honor short/long slot time only in 11g */ 2501 /* XXX shouldn't honor on pure g or turbo g channel */ 2502 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2503 usec = HAL_SLOT_TIME_9; 2504 else 2505 usec = HAL_SLOT_TIME_20; 2506 } else 2507 usec = HAL_SLOT_TIME_9; 2508 2509 DPRINTF(sc, ATH_DEBUG_RESET, 2510 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2511 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2512 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2513 2514 ath_hal_setslottime(ah, usec); 2515 sc->sc_updateslot = OK; 2516 } 2517 2518 /* 2519 * Callback from the 802.11 layer to update the 2520 * slot time based on the current setting. 2521 */ 2522 static void 2523 ath_updateslot(struct ifnet *ifp) 2524 { 2525 struct ath_softc *sc = ifp->if_softc; 2526 struct ieee80211com *ic = ifp->if_l2com; 2527 2528 /* 2529 * When not coordinating the BSS, change the hardware 2530 * immediately. For other operation we defer the change 2531 * until beacon updates have propagated to the stations. 2532 */ 2533 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2534 ic->ic_opmode == IEEE80211_M_MBSS) 2535 sc->sc_updateslot = UPDATE; 2536 else 2537 ath_setslottime(sc); 2538 } 2539 2540 /* 2541 * Setup a h/w transmit queue for beacons. 2542 */ 2543 static int 2544 ath_beaconq_setup(struct ath_hal *ah) 2545 { 2546 HAL_TXQ_INFO qi; 2547 2548 memset(&qi, 0, sizeof(qi)); 2549 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2550 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2551 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2552 /* NB: for dynamic turbo, don't enable any other interrupts */ 2553 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2554 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2555 } 2556 2557 /* 2558 * Setup the transmit queue parameters for the beacon queue. 2559 */ 2560 static int 2561 ath_beaconq_config(struct ath_softc *sc) 2562 { 2563 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2564 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2565 struct ath_hal *ah = sc->sc_ah; 2566 HAL_TXQ_INFO qi; 2567 2568 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2569 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2570 ic->ic_opmode == IEEE80211_M_MBSS) { 2571 /* 2572 * Always burst out beacon and CAB traffic. 2573 */ 2574 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2575 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2576 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2577 } else { 2578 struct wmeParams *wmep = 2579 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2580 /* 2581 * Adhoc mode; important thing is to use 2x cwmin. 2582 */ 2583 qi.tqi_aifs = wmep->wmep_aifsn; 2584 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2585 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2586 } 2587 2588 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2589 device_printf(sc->sc_dev, "unable to update parameters for " 2590 "beacon hardware queue!\n"); 2591 return 0; 2592 } else { 2593 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2594 return 1; 2595 } 2596 #undef ATH_EXPONENT_TO_VALUE 2597 } 2598 2599 /* 2600 * Allocate and setup an initial beacon frame. 2601 */ 2602 static int 2603 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2604 { 2605 struct ieee80211vap *vap = ni->ni_vap; 2606 struct ath_vap *avp = ATH_VAP(vap); 2607 struct ath_buf *bf; 2608 struct mbuf *m; 2609 int error; 2610 2611 bf = avp->av_bcbuf; 2612 if (bf->bf_m != NULL) { 2613 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2614 m_freem(bf->bf_m); 2615 bf->bf_m = NULL; 2616 } 2617 if (bf->bf_node != NULL) { 2618 ieee80211_free_node(bf->bf_node); 2619 bf->bf_node = NULL; 2620 } 2621 2622 /* 2623 * NB: the beacon data buffer must be 32-bit aligned; 2624 * we assume the mbuf routines will return us something 2625 * with this alignment (perhaps should assert). 2626 */ 2627 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 2628 if (m == NULL) { 2629 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 2630 sc->sc_stats.ast_be_nombuf++; 2631 return ENOMEM; 2632 } 2633 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2634 bf->bf_segs, &bf->bf_nseg, 2635 BUS_DMA_NOWAIT); 2636 if (error != 0) { 2637 device_printf(sc->sc_dev, 2638 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 2639 __func__, error); 2640 m_freem(m); 2641 return error; 2642 } 2643 2644 /* 2645 * Calculate a TSF adjustment factor required for staggered 2646 * beacons. Note that we assume the format of the beacon 2647 * frame leaves the tstamp field immediately following the 2648 * header. 2649 */ 2650 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 2651 uint64_t tsfadjust; 2652 struct ieee80211_frame *wh; 2653 2654 /* 2655 * The beacon interval is in TU's; the TSF is in usecs. 2656 * We figure out how many TU's to add to align the timestamp 2657 * then convert to TSF units and handle byte swapping before 2658 * inserting it in the frame. The hardware will then add this 2659 * each time a beacon frame is sent. Note that we align vap's 2660 * 1..N and leave vap 0 untouched. This means vap 0 has a 2661 * timestamp in one beacon interval while the others get a 2662 * timstamp aligned to the next interval. 2663 */ 2664 tsfadjust = ni->ni_intval * 2665 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 2666 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 2667 2668 DPRINTF(sc, ATH_DEBUG_BEACON, 2669 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 2670 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 2671 avp->av_bslot, ni->ni_intval, 2672 (long long unsigned) le64toh(tsfadjust)); 2673 2674 wh = mtod(m, struct ieee80211_frame *); 2675 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 2676 } 2677 bf->bf_m = m; 2678 bf->bf_node = ieee80211_ref_node(ni); 2679 2680 return 0; 2681 } 2682 2683 /* 2684 * Setup the beacon frame for transmit. 2685 */ 2686 static void 2687 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2688 { 2689 #define USE_SHPREAMBLE(_ic) \ 2690 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2691 == IEEE80211_F_SHPREAMBLE) 2692 struct ieee80211_node *ni = bf->bf_node; 2693 struct ieee80211com *ic = ni->ni_ic; 2694 struct mbuf *m = bf->bf_m; 2695 struct ath_hal *ah = sc->sc_ah; 2696 struct ath_desc *ds; 2697 int flags, antenna; 2698 const HAL_RATE_TABLE *rt; 2699 u_int8_t rix, rate; 2700 2701 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2702 __func__, m, m->m_len); 2703 2704 /* setup descriptors */ 2705 ds = bf->bf_desc; 2706 bf->bf_last = bf; 2707 bf->bf_lastds = ds; 2708 2709 flags = HAL_TXDESC_NOACK; 2710 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2711 ds->ds_link = bf->bf_daddr; /* self-linked */ 2712 flags |= HAL_TXDESC_VEOL; 2713 /* 2714 * Let hardware handle antenna switching. 2715 */ 2716 antenna = sc->sc_txantenna; 2717 } else { 2718 ds->ds_link = 0; 2719 /* 2720 * Switch antenna every 4 beacons. 2721 * XXX assumes two antenna 2722 */ 2723 if (sc->sc_txantenna != 0) 2724 antenna = sc->sc_txantenna; 2725 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 2726 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 2727 else 2728 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2729 } 2730 2731 KASSERT(bf->bf_nseg == 1, 2732 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2733 ds->ds_data = bf->bf_segs[0].ds_addr; 2734 /* 2735 * Calculate rate code. 2736 * XXX everything at min xmit rate 2737 */ 2738 rix = 0; 2739 rt = sc->sc_currates; 2740 rate = rt->info[rix].rateCode; 2741 if (USE_SHPREAMBLE(ic)) 2742 rate |= rt->info[rix].shortPreamble; 2743 ath_hal_setuptxdesc(ah, ds 2744 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2745 , sizeof(struct ieee80211_frame)/* header length */ 2746 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2747 , ni->ni_txpower /* txpower XXX */ 2748 , rate, 1 /* series 0 rate/tries */ 2749 , HAL_TXKEYIX_INVALID /* no encryption */ 2750 , antenna /* antenna mode */ 2751 , flags /* no ack, veol for beacons */ 2752 , 0 /* rts/cts rate */ 2753 , 0 /* rts/cts duration */ 2754 ); 2755 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2756 ath_hal_filltxdesc(ah, ds 2757 , roundup(m->m_len, 4) /* buffer length */ 2758 , AH_TRUE /* first segment */ 2759 , AH_TRUE /* last segment */ 2760 , ds /* first descriptor */ 2761 ); 2762 #if 0 2763 ath_desc_swap(ds); 2764 #endif 2765 #undef USE_SHPREAMBLE 2766 } 2767 2768 static void 2769 ath_beacon_update(struct ieee80211vap *vap, int item) 2770 { 2771 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 2772 2773 setbit(bo->bo_flags, item); 2774 } 2775 2776 /* 2777 * Append the contents of src to dst; both queues 2778 * are assumed to be locked. 2779 */ 2780 static void 2781 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2782 { 2783 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list); 2784 dst->axq_link = src->axq_link; 2785 src->axq_link = NULL; 2786 dst->axq_depth += src->axq_depth; 2787 dst->axq_aggr_depth += src->axq_aggr_depth; 2788 src->axq_depth = 0; 2789 src->axq_aggr_depth = 0; 2790 } 2791 2792 /* 2793 * Transmit a beacon frame at SWBA. Dynamic updates to the 2794 * frame contents are done as needed and the slot time is 2795 * also adjusted based on current state. 2796 */ 2797 static void 2798 ath_beacon_proc(void *arg, int pending) 2799 { 2800 struct ath_softc *sc = arg; 2801 struct ath_hal *ah = sc->sc_ah; 2802 struct ieee80211vap *vap; 2803 struct ath_buf *bf; 2804 int slot, otherant; 2805 uint32_t bfaddr; 2806 2807 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2808 __func__, pending); 2809 /* 2810 * Check if the previous beacon has gone out. If 2811 * not don't try to post another, skip this period 2812 * and wait for the next. Missed beacons indicate 2813 * a problem and should not occur. If we miss too 2814 * many consecutive beacons reset the device. 2815 */ 2816 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2817 sc->sc_bmisscount++; 2818 sc->sc_stats.ast_be_missed++; 2819 DPRINTF(sc, ATH_DEBUG_BEACON, 2820 "%s: missed %u consecutive beacons\n", 2821 __func__, sc->sc_bmisscount); 2822 if (sc->sc_bmisscount >= ath_bstuck_threshold) 2823 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2824 return; 2825 } 2826 if (sc->sc_bmisscount != 0) { 2827 DPRINTF(sc, ATH_DEBUG_BEACON, 2828 "%s: resume beacon xmit after %u misses\n", 2829 __func__, sc->sc_bmisscount); 2830 sc->sc_bmisscount = 0; 2831 } 2832 2833 if (sc->sc_stagbeacons) { /* staggered beacons */ 2834 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2835 uint32_t tsftu; 2836 2837 tsftu = ath_hal_gettsf32(ah) >> 10; 2838 /* XXX lintval */ 2839 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 2840 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 2841 bfaddr = 0; 2842 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2843 bf = ath_beacon_generate(sc, vap); 2844 if (bf != NULL) 2845 bfaddr = bf->bf_daddr; 2846 } 2847 } else { /* burst'd beacons */ 2848 uint32_t *bflink = &bfaddr; 2849 2850 for (slot = 0; slot < ATH_BCBUF; slot++) { 2851 vap = sc->sc_bslot[slot]; 2852 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2853 bf = ath_beacon_generate(sc, vap); 2854 if (bf != NULL) { 2855 *bflink = bf->bf_daddr; 2856 bflink = &bf->bf_desc->ds_link; 2857 } 2858 } 2859 } 2860 *bflink = 0; /* terminate list */ 2861 } 2862 2863 /* 2864 * Handle slot time change when a non-ERP station joins/leaves 2865 * an 11g network. The 802.11 layer notifies us via callback, 2866 * we mark updateslot, then wait one beacon before effecting 2867 * the change. This gives associated stations at least one 2868 * beacon interval to note the state change. 2869 */ 2870 /* XXX locking */ 2871 if (sc->sc_updateslot == UPDATE) { 2872 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2873 sc->sc_slotupdate = slot; 2874 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 2875 ath_setslottime(sc); /* commit change to h/w */ 2876 2877 /* 2878 * Check recent per-antenna transmit statistics and flip 2879 * the default antenna if noticeably more frames went out 2880 * on the non-default antenna. 2881 * XXX assumes 2 anntenae 2882 */ 2883 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 2884 otherant = sc->sc_defant & 1 ? 2 : 1; 2885 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2886 ath_setdefantenna(sc, otherant); 2887 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2888 } 2889 2890 if (bfaddr != 0) { 2891 /* 2892 * Stop any current dma and put the new frame on the queue. 2893 * This should never fail since we check above that no frames 2894 * are still pending on the queue. 2895 */ 2896 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2897 DPRINTF(sc, ATH_DEBUG_ANY, 2898 "%s: beacon queue %u did not stop?\n", 2899 __func__, sc->sc_bhalq); 2900 } 2901 /* NB: cabq traffic should already be queued and primed */ 2902 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 2903 ath_hal_txstart(ah, sc->sc_bhalq); 2904 2905 sc->sc_stats.ast_be_xmit++; 2906 } 2907 } 2908 2909 static struct ath_buf * 2910 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 2911 { 2912 struct ath_vap *avp = ATH_VAP(vap); 2913 struct ath_txq *cabq = sc->sc_cabq; 2914 struct ath_buf *bf; 2915 struct mbuf *m; 2916 int nmcastq, error; 2917 2918 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 2919 ("not running, state %d", vap->iv_state)); 2920 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 2921 2922 /* 2923 * Update dynamic beacon contents. If this returns 2924 * non-zero then we need to remap the memory because 2925 * the beacon frame changed size (probably because 2926 * of the TIM bitmap). 2927 */ 2928 bf = avp->av_bcbuf; 2929 m = bf->bf_m; 2930 nmcastq = avp->av_mcastq.axq_depth; 2931 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 2932 /* XXX too conservative? */ 2933 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2934 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2935 bf->bf_segs, &bf->bf_nseg, 2936 BUS_DMA_NOWAIT); 2937 if (error != 0) { 2938 if_printf(vap->iv_ifp, 2939 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 2940 __func__, error); 2941 return NULL; 2942 } 2943 } 2944 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 2945 DPRINTF(sc, ATH_DEBUG_BEACON, 2946 "%s: cabq did not drain, mcastq %u cabq %u\n", 2947 __func__, nmcastq, cabq->axq_depth); 2948 sc->sc_stats.ast_cabq_busy++; 2949 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 2950 /* 2951 * CABQ traffic from a previous vap is still pending. 2952 * We must drain the q before this beacon frame goes 2953 * out as otherwise this vap's stations will get cab 2954 * frames from a different vap. 2955 * XXX could be slow causing us to miss DBA 2956 */ 2957 ath_tx_draintxq(sc, cabq); 2958 } 2959 } 2960 ath_beacon_setup(sc, bf); 2961 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2962 2963 /* 2964 * Enable the CAB queue before the beacon queue to 2965 * insure cab frames are triggered by this beacon. 2966 */ 2967 if (avp->av_boff.bo_tim[4] & 1) { 2968 struct ath_hal *ah = sc->sc_ah; 2969 2970 /* NB: only at DTIM */ 2971 ATH_TXQ_LOCK(cabq); 2972 ATH_TXQ_LOCK(&avp->av_mcastq); 2973 if (nmcastq) { 2974 struct ath_buf *bfm; 2975 2976 /* 2977 * Move frames from the s/w mcast q to the h/w cab q. 2978 * XXX MORE_DATA bit 2979 */ 2980 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q); 2981 if (cabq->axq_link != NULL) { 2982 *cabq->axq_link = bfm->bf_daddr; 2983 } else 2984 ath_hal_puttxbuf(ah, cabq->axq_qnum, 2985 bfm->bf_daddr); 2986 ath_txqmove(cabq, &avp->av_mcastq); 2987 2988 sc->sc_stats.ast_cabq_xmit += nmcastq; 2989 } 2990 /* NB: gated by beacon so safe to start here */ 2991 if (! TAILQ_EMPTY(&(cabq->axq_q))) 2992 ath_hal_txstart(ah, cabq->axq_qnum); 2993 ATH_TXQ_UNLOCK(&avp->av_mcastq); 2994 ATH_TXQ_UNLOCK(cabq); 2995 } 2996 return bf; 2997 } 2998 2999 static void 3000 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 3001 { 3002 struct ath_vap *avp = ATH_VAP(vap); 3003 struct ath_hal *ah = sc->sc_ah; 3004 struct ath_buf *bf; 3005 struct mbuf *m; 3006 int error; 3007 3008 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3009 3010 /* 3011 * Update dynamic beacon contents. If this returns 3012 * non-zero then we need to remap the memory because 3013 * the beacon frame changed size (probably because 3014 * of the TIM bitmap). 3015 */ 3016 bf = avp->av_bcbuf; 3017 m = bf->bf_m; 3018 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 3019 /* XXX too conservative? */ 3020 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3021 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 3022 bf->bf_segs, &bf->bf_nseg, 3023 BUS_DMA_NOWAIT); 3024 if (error != 0) { 3025 if_printf(vap->iv_ifp, 3026 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 3027 __func__, error); 3028 return; 3029 } 3030 } 3031 ath_beacon_setup(sc, bf); 3032 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3033 3034 /* NB: caller is known to have already stopped tx dma */ 3035 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 3036 ath_hal_txstart(ah, sc->sc_bhalq); 3037 } 3038 3039 /* 3040 * Reset the hardware after detecting beacons have stopped. 3041 */ 3042 static void 3043 ath_bstuck_proc(void *arg, int pending) 3044 { 3045 struct ath_softc *sc = arg; 3046 struct ifnet *ifp = sc->sc_ifp; 3047 uint32_t hangs = 0; 3048 3049 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) 3050 if_printf(ifp, "bb hang detected (0x%x)\n", hangs); 3051 3052 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3053 sc->sc_bmisscount); 3054 sc->sc_stats.ast_bstuck++; 3055 /* 3056 * This assumes that there's no simultaneous channel mode change 3057 * occuring. 3058 */ 3059 ath_reset(ifp, ATH_RESET_NOLOSS); 3060 } 3061 3062 /* 3063 * Reclaim beacon resources and return buffer to the pool. 3064 */ 3065 static void 3066 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 3067 { 3068 3069 if (bf->bf_m != NULL) { 3070 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3071 m_freem(bf->bf_m); 3072 bf->bf_m = NULL; 3073 } 3074 if (bf->bf_node != NULL) { 3075 ieee80211_free_node(bf->bf_node); 3076 bf->bf_node = NULL; 3077 } 3078 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 3079 } 3080 3081 /* 3082 * Reclaim beacon resources. 3083 */ 3084 static void 3085 ath_beacon_free(struct ath_softc *sc) 3086 { 3087 struct ath_buf *bf; 3088 3089 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 3090 if (bf->bf_m != NULL) { 3091 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3092 m_freem(bf->bf_m); 3093 bf->bf_m = NULL; 3094 } 3095 if (bf->bf_node != NULL) { 3096 ieee80211_free_node(bf->bf_node); 3097 bf->bf_node = NULL; 3098 } 3099 } 3100 } 3101 3102 /* 3103 * Configure the beacon and sleep timers. 3104 * 3105 * When operating as an AP this resets the TSF and sets 3106 * up the hardware to notify us when we need to issue beacons. 3107 * 3108 * When operating in station mode this sets up the beacon 3109 * timers according to the timestamp of the last received 3110 * beacon and the current TSF, configures PCF and DTIM 3111 * handling, programs the sleep registers so the hardware 3112 * will wakeup in time to receive beacons, and configures 3113 * the beacon miss handling so we'll receive a BMISS 3114 * interrupt when we stop seeing beacons from the AP 3115 * we've associated with. 3116 */ 3117 static void 3118 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 3119 { 3120 #define TSF_TO_TU(_h,_l) \ 3121 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 3122 #define FUDGE 2 3123 struct ath_hal *ah = sc->sc_ah; 3124 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3125 struct ieee80211_node *ni; 3126 u_int32_t nexttbtt, intval, tsftu; 3127 u_int64_t tsf; 3128 3129 if (vap == NULL) 3130 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 3131 ni = vap->iv_bss; 3132 3133 /* extract tstamp from last beacon and convert to TU */ 3134 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 3135 LE_READ_4(ni->ni_tstamp.data)); 3136 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3137 ic->ic_opmode == IEEE80211_M_MBSS) { 3138 /* 3139 * For multi-bss ap/mesh support beacons are either staggered 3140 * evenly over N slots or burst together. For the former 3141 * arrange for the SWBA to be delivered for each slot. 3142 * Slots that are not occupied will generate nothing. 3143 */ 3144 /* NB: the beacon interval is kept internally in TU's */ 3145 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3146 if (sc->sc_stagbeacons) 3147 intval /= ATH_BCBUF; 3148 } else { 3149 /* NB: the beacon interval is kept internally in TU's */ 3150 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3151 } 3152 if (nexttbtt == 0) /* e.g. for ap mode */ 3153 nexttbtt = intval; 3154 else if (intval) /* NB: can be 0 for monitor mode */ 3155 nexttbtt = roundup(nexttbtt, intval); 3156 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 3157 __func__, nexttbtt, intval, ni->ni_intval); 3158 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 3159 HAL_BEACON_STATE bs; 3160 int dtimperiod, dtimcount; 3161 int cfpperiod, cfpcount; 3162 3163 /* 3164 * Setup dtim and cfp parameters according to 3165 * last beacon we received (which may be none). 3166 */ 3167 dtimperiod = ni->ni_dtim_period; 3168 if (dtimperiod <= 0) /* NB: 0 if not known */ 3169 dtimperiod = 1; 3170 dtimcount = ni->ni_dtim_count; 3171 if (dtimcount >= dtimperiod) /* NB: sanity check */ 3172 dtimcount = 0; /* XXX? */ 3173 cfpperiod = 1; /* NB: no PCF support yet */ 3174 cfpcount = 0; 3175 /* 3176 * Pull nexttbtt forward to reflect the current 3177 * TSF and calculate dtim+cfp state for the result. 3178 */ 3179 tsf = ath_hal_gettsf64(ah); 3180 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3181 do { 3182 nexttbtt += intval; 3183 if (--dtimcount < 0) { 3184 dtimcount = dtimperiod - 1; 3185 if (--cfpcount < 0) 3186 cfpcount = cfpperiod - 1; 3187 } 3188 } while (nexttbtt < tsftu); 3189 memset(&bs, 0, sizeof(bs)); 3190 bs.bs_intval = intval; 3191 bs.bs_nexttbtt = nexttbtt; 3192 bs.bs_dtimperiod = dtimperiod*intval; 3193 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 3194 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 3195 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 3196 bs.bs_cfpmaxduration = 0; 3197 #if 0 3198 /* 3199 * The 802.11 layer records the offset to the DTIM 3200 * bitmap while receiving beacons; use it here to 3201 * enable h/w detection of our AID being marked in 3202 * the bitmap vector (to indicate frames for us are 3203 * pending at the AP). 3204 * XXX do DTIM handling in s/w to WAR old h/w bugs 3205 * XXX enable based on h/w rev for newer chips 3206 */ 3207 bs.bs_timoffset = ni->ni_timoff; 3208 #endif 3209 /* 3210 * Calculate the number of consecutive beacons to miss 3211 * before taking a BMISS interrupt. 3212 * Note that we clamp the result to at most 10 beacons. 3213 */ 3214 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 3215 if (bs.bs_bmissthreshold > 10) 3216 bs.bs_bmissthreshold = 10; 3217 else if (bs.bs_bmissthreshold <= 0) 3218 bs.bs_bmissthreshold = 1; 3219 3220 /* 3221 * Calculate sleep duration. The configuration is 3222 * given in ms. We insure a multiple of the beacon 3223 * period is used. Also, if the sleep duration is 3224 * greater than the DTIM period then it makes senses 3225 * to make it a multiple of that. 3226 * 3227 * XXX fixed at 100ms 3228 */ 3229 bs.bs_sleepduration = 3230 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 3231 if (bs.bs_sleepduration > bs.bs_dtimperiod) 3232 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 3233 3234 DPRINTF(sc, ATH_DEBUG_BEACON, 3235 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 3236 , __func__ 3237 , tsf, tsftu 3238 , bs.bs_intval 3239 , bs.bs_nexttbtt 3240 , bs.bs_dtimperiod 3241 , bs.bs_nextdtim 3242 , bs.bs_bmissthreshold 3243 , bs.bs_sleepduration 3244 , bs.bs_cfpperiod 3245 , bs.bs_cfpmaxduration 3246 , bs.bs_cfpnext 3247 , bs.bs_timoffset 3248 ); 3249 ath_hal_intrset(ah, 0); 3250 ath_hal_beacontimers(ah, &bs); 3251 sc->sc_imask |= HAL_INT_BMISS; 3252 ath_hal_intrset(ah, sc->sc_imask); 3253 } else { 3254 ath_hal_intrset(ah, 0); 3255 if (nexttbtt == intval) 3256 intval |= HAL_BEACON_RESET_TSF; 3257 if (ic->ic_opmode == IEEE80211_M_IBSS) { 3258 /* 3259 * In IBSS mode enable the beacon timers but only 3260 * enable SWBA interrupts if we need to manually 3261 * prepare beacon frames. Otherwise we use a 3262 * self-linked tx descriptor and let the hardware 3263 * deal with things. 3264 */ 3265 intval |= HAL_BEACON_ENA; 3266 if (!sc->sc_hasveol) 3267 sc->sc_imask |= HAL_INT_SWBA; 3268 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 3269 /* 3270 * Pull nexttbtt forward to reflect 3271 * the current TSF. 3272 */ 3273 tsf = ath_hal_gettsf64(ah); 3274 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3275 do { 3276 nexttbtt += intval; 3277 } while (nexttbtt < tsftu); 3278 } 3279 ath_beaconq_config(sc); 3280 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3281 ic->ic_opmode == IEEE80211_M_MBSS) { 3282 /* 3283 * In AP/mesh mode we enable the beacon timers 3284 * and SWBA interrupts to prepare beacon frames. 3285 */ 3286 intval |= HAL_BEACON_ENA; 3287 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 3288 ath_beaconq_config(sc); 3289 } 3290 ath_hal_beaconinit(ah, nexttbtt, intval); 3291 sc->sc_bmisscount = 0; 3292 ath_hal_intrset(ah, sc->sc_imask); 3293 /* 3294 * When using a self-linked beacon descriptor in 3295 * ibss mode load it once here. 3296 */ 3297 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 3298 ath_beacon_start_adhoc(sc, vap); 3299 } 3300 sc->sc_syncbeacon = 0; 3301 #undef FUDGE 3302 #undef TSF_TO_TU 3303 } 3304 3305 static void 3306 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3307 { 3308 bus_addr_t *paddr = (bus_addr_t*) arg; 3309 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3310 *paddr = segs->ds_addr; 3311 } 3312 3313 static int 3314 ath_descdma_setup(struct ath_softc *sc, 3315 struct ath_descdma *dd, ath_bufhead *head, 3316 const char *name, int nbuf, int ndesc) 3317 { 3318 #define DS2PHYS(_dd, _ds) \ 3319 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3320 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 3321 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 3322 struct ifnet *ifp = sc->sc_ifp; 3323 uint8_t *ds; 3324 struct ath_buf *bf; 3325 int i, bsize, error; 3326 int desc_len; 3327 3328 desc_len = sizeof(struct ath_desc); 3329 3330 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 3331 __func__, name, nbuf, ndesc); 3332 3333 dd->dd_name = name; 3334 dd->dd_desc_len = desc_len * nbuf * ndesc; 3335 3336 /* 3337 * Merlin work-around: 3338 * Descriptors that cross the 4KB boundary can't be used. 3339 * Assume one skipped descriptor per 4KB page. 3340 */ 3341 if (! ath_hal_split4ktrans(sc->sc_ah)) { 3342 int numdescpage = 4096 / (desc_len * ndesc); 3343 dd->dd_desc_len = (nbuf / numdescpage + 1) * 4096; 3344 } 3345 3346 /* 3347 * Setup DMA descriptor area. 3348 */ 3349 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 3350 PAGE_SIZE, 0, /* alignment, bounds */ 3351 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3352 BUS_SPACE_MAXADDR, /* highaddr */ 3353 NULL, NULL, /* filter, filterarg */ 3354 dd->dd_desc_len, /* maxsize */ 3355 1, /* nsegments */ 3356 dd->dd_desc_len, /* maxsegsize */ 3357 BUS_DMA_ALLOCNOW, /* flags */ 3358 NULL, /* lockfunc */ 3359 NULL, /* lockarg */ 3360 &dd->dd_dmat); 3361 if (error != 0) { 3362 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3363 return error; 3364 } 3365 3366 /* allocate descriptors */ 3367 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3368 if (error != 0) { 3369 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3370 "error %u\n", dd->dd_name, error); 3371 goto fail0; 3372 } 3373 3374 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3375 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3376 &dd->dd_dmamap); 3377 if (error != 0) { 3378 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3379 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3380 goto fail1; 3381 } 3382 3383 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3384 dd->dd_desc, dd->dd_desc_len, 3385 ath_load_cb, &dd->dd_desc_paddr, 3386 BUS_DMA_NOWAIT); 3387 if (error != 0) { 3388 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3389 dd->dd_name, error); 3390 goto fail2; 3391 } 3392 3393 ds = (uint8_t *) dd->dd_desc; 3394 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3395 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3396 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3397 3398 /* allocate rx buffers */ 3399 bsize = sizeof(struct ath_buf) * nbuf; 3400 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3401 if (bf == NULL) { 3402 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3403 dd->dd_name, bsize); 3404 goto fail3; 3405 } 3406 dd->dd_bufptr = bf; 3407 3408 TAILQ_INIT(head); 3409 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * desc_len)) { 3410 bf->bf_desc = (struct ath_desc *) ds; 3411 bf->bf_daddr = DS2PHYS(dd, ds); 3412 if (! ath_hal_split4ktrans(sc->sc_ah)) { 3413 /* 3414 * Merlin WAR: Skip descriptor addresses which 3415 * cause 4KB boundary crossing along any point 3416 * in the descriptor. 3417 */ 3418 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr, 3419 desc_len * ndesc)) { 3420 /* Start at the next page */ 3421 ds += 0x1000 - (bf->bf_daddr & 0xFFF); 3422 bf->bf_desc = (struct ath_desc *) ds; 3423 bf->bf_daddr = DS2PHYS(dd, ds); 3424 } 3425 } 3426 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3427 &bf->bf_dmamap); 3428 if (error != 0) { 3429 if_printf(ifp, "unable to create dmamap for %s " 3430 "buffer %u, error %u\n", dd->dd_name, i, error); 3431 ath_descdma_cleanup(sc, dd, head); 3432 return error; 3433 } 3434 bf->bf_lastds = bf->bf_desc; /* Just an initial value */ 3435 TAILQ_INSERT_TAIL(head, bf, bf_list); 3436 } 3437 return 0; 3438 fail3: 3439 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3440 fail2: 3441 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3442 fail1: 3443 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3444 fail0: 3445 bus_dma_tag_destroy(dd->dd_dmat); 3446 memset(dd, 0, sizeof(*dd)); 3447 return error; 3448 #undef DS2PHYS 3449 #undef ATH_DESC_4KB_BOUND_CHECK 3450 } 3451 3452 static void 3453 ath_descdma_cleanup(struct ath_softc *sc, 3454 struct ath_descdma *dd, ath_bufhead *head) 3455 { 3456 struct ath_buf *bf; 3457 struct ieee80211_node *ni; 3458 3459 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3460 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3461 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3462 bus_dma_tag_destroy(dd->dd_dmat); 3463 3464 TAILQ_FOREACH(bf, head, bf_list) { 3465 if (bf->bf_m) { 3466 m_freem(bf->bf_m); 3467 bf->bf_m = NULL; 3468 } 3469 if (bf->bf_dmamap != NULL) { 3470 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3471 bf->bf_dmamap = NULL; 3472 } 3473 ni = bf->bf_node; 3474 bf->bf_node = NULL; 3475 if (ni != NULL) { 3476 /* 3477 * Reclaim node reference. 3478 */ 3479 ieee80211_free_node(ni); 3480 } 3481 } 3482 3483 TAILQ_INIT(head); 3484 free(dd->dd_bufptr, M_ATHDEV); 3485 memset(dd, 0, sizeof(*dd)); 3486 } 3487 3488 static int 3489 ath_desc_alloc(struct ath_softc *sc) 3490 { 3491 int error; 3492 3493 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3494 "rx", ath_rxbuf, 1); 3495 if (error != 0) 3496 return error; 3497 3498 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3499 "tx", ath_txbuf, ATH_TXDESC); 3500 if (error != 0) { 3501 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3502 return error; 3503 } 3504 3505 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3506 "beacon", ATH_BCBUF, 1); 3507 if (error != 0) { 3508 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3509 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3510 return error; 3511 } 3512 return 0; 3513 } 3514 3515 static void 3516 ath_desc_free(struct ath_softc *sc) 3517 { 3518 3519 if (sc->sc_bdma.dd_desc_len != 0) 3520 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3521 if (sc->sc_txdma.dd_desc_len != 0) 3522 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3523 if (sc->sc_rxdma.dd_desc_len != 0) 3524 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3525 } 3526 3527 static struct ieee80211_node * 3528 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3529 { 3530 struct ieee80211com *ic = vap->iv_ic; 3531 struct ath_softc *sc = ic->ic_ifp->if_softc; 3532 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3533 struct ath_node *an; 3534 3535 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3536 if (an == NULL) { 3537 /* XXX stat+msg */ 3538 return NULL; 3539 } 3540 ath_rate_node_init(sc, an); 3541 3542 /* Setup the mutex - there's no associd yet so set the name to NULL */ 3543 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p", 3544 device_get_nameunit(sc->sc_dev), an); 3545 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF); 3546 3547 /* XXX setup ath_tid */ 3548 ath_tx_tid_init(sc, an); 3549 3550 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3551 return &an->an_node; 3552 } 3553 3554 static void 3555 ath_node_cleanup(struct ieee80211_node *ni) 3556 { 3557 struct ieee80211com *ic = ni->ni_ic; 3558 struct ath_softc *sc = ic->ic_ifp->if_softc; 3559 3560 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */ 3561 ath_tx_node_flush(sc, ATH_NODE(ni)); 3562 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3563 sc->sc_node_cleanup(ni); 3564 } 3565 3566 static void 3567 ath_node_free(struct ieee80211_node *ni) 3568 { 3569 struct ieee80211com *ic = ni->ni_ic; 3570 struct ath_softc *sc = ic->ic_ifp->if_softc; 3571 3572 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3573 mtx_destroy(&ATH_NODE(ni)->an_mtx); 3574 sc->sc_node_free(ni); 3575 } 3576 3577 static void 3578 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3579 { 3580 struct ieee80211com *ic = ni->ni_ic; 3581 struct ath_softc *sc = ic->ic_ifp->if_softc; 3582 struct ath_hal *ah = sc->sc_ah; 3583 3584 *rssi = ic->ic_node_getrssi(ni); 3585 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3586 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3587 else 3588 *noise = -95; /* nominally correct */ 3589 } 3590 3591 static int 3592 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3593 { 3594 struct ath_hal *ah = sc->sc_ah; 3595 int error; 3596 struct mbuf *m; 3597 struct ath_desc *ds; 3598 3599 m = bf->bf_m; 3600 if (m == NULL) { 3601 /* 3602 * NB: by assigning a page to the rx dma buffer we 3603 * implicitly satisfy the Atheros requirement that 3604 * this buffer be cache-line-aligned and sized to be 3605 * multiple of the cache line size. Not doing this 3606 * causes weird stuff to happen (for the 5210 at least). 3607 */ 3608 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3609 if (m == NULL) { 3610 DPRINTF(sc, ATH_DEBUG_ANY, 3611 "%s: no mbuf/cluster\n", __func__); 3612 sc->sc_stats.ast_rx_nombuf++; 3613 return ENOMEM; 3614 } 3615 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3616 3617 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 3618 bf->bf_dmamap, m, 3619 bf->bf_segs, &bf->bf_nseg, 3620 BUS_DMA_NOWAIT); 3621 if (error != 0) { 3622 DPRINTF(sc, ATH_DEBUG_ANY, 3623 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 3624 __func__, error); 3625 sc->sc_stats.ast_rx_busdma++; 3626 m_freem(m); 3627 return error; 3628 } 3629 KASSERT(bf->bf_nseg == 1, 3630 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3631 bf->bf_m = m; 3632 } 3633 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3634 3635 /* 3636 * Setup descriptors. For receive we always terminate 3637 * the descriptor list with a self-linked entry so we'll 3638 * not get overrun under high load (as can happen with a 3639 * 5212 when ANI processing enables PHY error frames). 3640 * 3641 * To insure the last descriptor is self-linked we create 3642 * each descriptor as self-linked and add it to the end. As 3643 * each additional descriptor is added the previous self-linked 3644 * entry is ``fixed'' naturally. This should be safe even 3645 * if DMA is happening. When processing RX interrupts we 3646 * never remove/process the last, self-linked, entry on the 3647 * descriptor list. This insures the hardware always has 3648 * someplace to write a new frame. 3649 */ 3650 /* 3651 * 11N: we can no longer afford to self link the last descriptor. 3652 * MAC acknowledges BA status as long as it copies frames to host 3653 * buffer (or rx fifo). This can incorrectly acknowledge packets 3654 * to a sender if last desc is self-linked. 3655 */ 3656 ds = bf->bf_desc; 3657 if (sc->sc_rxslink) 3658 ds->ds_link = bf->bf_daddr; /* link to self */ 3659 else 3660 ds->ds_link = 0; /* terminate the list */ 3661 ds->ds_data = bf->bf_segs[0].ds_addr; 3662 ath_hal_setuprxdesc(ah, ds 3663 , m->m_len /* buffer size */ 3664 , 0 3665 ); 3666 3667 if (sc->sc_rxlink != NULL) 3668 *sc->sc_rxlink = bf->bf_daddr; 3669 sc->sc_rxlink = &ds->ds_link; 3670 return 0; 3671 } 3672 3673 /* 3674 * Extend 15-bit time stamp from rx descriptor to 3675 * a full 64-bit TSF using the specified TSF. 3676 */ 3677 static __inline u_int64_t 3678 ath_extend_tsf15(u_int32_t rstamp, u_int64_t tsf) 3679 { 3680 if ((tsf & 0x7fff) < rstamp) 3681 tsf -= 0x8000; 3682 3683 return ((tsf &~ 0x7fff) | rstamp); 3684 } 3685 3686 /* 3687 * Extend 32-bit time stamp from rx descriptor to 3688 * a full 64-bit TSF using the specified TSF. 3689 */ 3690 static __inline u_int64_t 3691 ath_extend_tsf32(u_int32_t rstamp, u_int64_t tsf) 3692 { 3693 u_int32_t tsf_low = tsf & 0xffffffff; 3694 u_int64_t tsf64 = (tsf & ~0xffffffffULL) | rstamp; 3695 3696 if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000)) 3697 tsf64 -= 0x100000000ULL; 3698 3699 if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000)) 3700 tsf64 += 0x100000000ULL; 3701 3702 return tsf64; 3703 } 3704 3705 /* 3706 * Extend the TSF from the RX descriptor to a full 64 bit TSF. 3707 * Earlier hardware versions only wrote the low 15 bits of the 3708 * TSF into the RX descriptor; later versions (AR5416 and up) 3709 * include the 32 bit TSF value. 3710 */ 3711 static __inline u_int64_t 3712 ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp, u_int64_t tsf) 3713 { 3714 if (sc->sc_rxtsf32) 3715 return ath_extend_tsf32(rstamp, tsf); 3716 else 3717 return ath_extend_tsf15(rstamp, tsf); 3718 } 3719 3720 /* 3721 * Intercept management frames to collect beacon rssi data 3722 * and to do ibss merges. 3723 */ 3724 static void 3725 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 3726 int subtype, int rssi, int nf) 3727 { 3728 struct ieee80211vap *vap = ni->ni_vap; 3729 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 3730 3731 /* 3732 * Call up first so subsequent work can use information 3733 * potentially stored in the node (e.g. for ibss merge). 3734 */ 3735 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 3736 switch (subtype) { 3737 case IEEE80211_FC0_SUBTYPE_BEACON: 3738 /* update rssi statistics for use by the hal */ 3739 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3740 if (sc->sc_syncbeacon && 3741 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 3742 /* 3743 * Resync beacon timers using the tsf of the beacon 3744 * frame we just received. 3745 */ 3746 ath_beacon_config(sc, vap); 3747 } 3748 /* fall thru... */ 3749 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3750 if (vap->iv_opmode == IEEE80211_M_IBSS && 3751 vap->iv_state == IEEE80211_S_RUN) { 3752 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 3753 uint64_t tsf = ath_extend_tsf(sc, rstamp, 3754 ath_hal_gettsf64(sc->sc_ah)); 3755 /* 3756 * Handle ibss merge as needed; check the tsf on the 3757 * frame before attempting the merge. The 802.11 spec 3758 * says the station should change it's bssid to match 3759 * the oldest station with the same ssid, where oldest 3760 * is determined by the tsf. Note that hardware 3761 * reconfiguration happens through callback to 3762 * ath_newstate as the state machine will go from 3763 * RUN -> RUN when this happens. 3764 */ 3765 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3766 DPRINTF(sc, ATH_DEBUG_STATE, 3767 "ibss merge, rstamp %u tsf %ju " 3768 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3769 (uintmax_t)ni->ni_tstamp.tsf); 3770 (void) ieee80211_ibss_merge(ni); 3771 } 3772 } 3773 break; 3774 } 3775 } 3776 3777 /* 3778 * Set the default antenna. 3779 */ 3780 static void 3781 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3782 { 3783 struct ath_hal *ah = sc->sc_ah; 3784 3785 /* XXX block beacon interrupts */ 3786 ath_hal_setdefantenna(ah, antenna); 3787 if (sc->sc_defant != antenna) 3788 sc->sc_stats.ast_ant_defswitch++; 3789 sc->sc_defant = antenna; 3790 sc->sc_rxotherant = 0; 3791 } 3792 3793 static void 3794 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 3795 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 3796 { 3797 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 3798 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 3799 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 3800 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 3801 struct ath_softc *sc = ifp->if_softc; 3802 const HAL_RATE_TABLE *rt; 3803 uint8_t rix; 3804 3805 rt = sc->sc_currates; 3806 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3807 rix = rt->rateCodeToIndex[rs->rs_rate]; 3808 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3809 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3810 #ifdef AH_SUPPORT_AR5416 3811 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 3812 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 3813 struct ieee80211com *ic = ifp->if_l2com; 3814 3815 if ((rs->rs_flags & HAL_RX_2040) == 0) 3816 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 3817 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 3818 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 3819 else 3820 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 3821 if ((rs->rs_flags & HAL_RX_GI) == 0) 3822 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 3823 } 3824 #endif 3825 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 3826 if (rs->rs_status & HAL_RXERR_CRC) 3827 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3828 /* XXX propagate other error flags from descriptor */ 3829 sc->sc_rx_th.wr_antnoise = nf; 3830 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 3831 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 3832 #undef CHAN_HT 3833 #undef CHAN_HT20 3834 #undef CHAN_HT40U 3835 #undef CHAN_HT40D 3836 } 3837 3838 static void 3839 ath_handle_micerror(struct ieee80211com *ic, 3840 struct ieee80211_frame *wh, int keyix) 3841 { 3842 struct ieee80211_node *ni; 3843 3844 /* XXX recheck MIC to deal w/ chips that lie */ 3845 /* XXX discard MIC errors on !data frames */ 3846 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 3847 if (ni != NULL) { 3848 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 3849 ieee80211_free_node(ni); 3850 } 3851 } 3852 3853 /* 3854 * Only run the RX proc if it's not already running. 3855 * Since this may get run as part of the reset/flush path, 3856 * the task can't clash with an existing, running tasklet. 3857 */ 3858 static void 3859 ath_rx_tasklet(void *arg, int npending) 3860 { 3861 struct ath_softc *sc = arg; 3862 3863 CTR1(ATH_KTR_INTR, "ath_rx_proc: pending=%d", npending); 3864 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3865 ATH_PCU_LOCK(sc); 3866 if (sc->sc_inreset_cnt > 0) { 3867 device_printf(sc->sc_dev, 3868 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 3869 ATH_PCU_UNLOCK(sc); 3870 return; 3871 } 3872 ATH_PCU_UNLOCK(sc); 3873 ath_rx_proc(sc, 1); 3874 } 3875 3876 static void 3877 ath_rx_proc(struct ath_softc *sc, int resched) 3878 { 3879 #define PA2DESC(_sc, _pa) \ 3880 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3881 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3882 struct ath_buf *bf; 3883 struct ifnet *ifp = sc->sc_ifp; 3884 struct ieee80211com *ic = ifp->if_l2com; 3885 struct ath_hal *ah = sc->sc_ah; 3886 struct ath_desc *ds; 3887 struct ath_rx_status *rs; 3888 struct mbuf *m; 3889 struct ieee80211_node *ni; 3890 int len, type, ngood; 3891 HAL_STATUS status; 3892 int16_t nf; 3893 u_int64_t tsf; 3894 int npkts = 0; 3895 3896 /* XXX we must not hold the ATH_LOCK here */ 3897 ATH_UNLOCK_ASSERT(sc); 3898 ATH_PCU_UNLOCK_ASSERT(sc); 3899 3900 ATH_PCU_LOCK(sc); 3901 sc->sc_rxproc_cnt++; 3902 ATH_PCU_UNLOCK(sc); 3903 3904 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 3905 ngood = 0; 3906 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 3907 sc->sc_stats.ast_rx_noise = nf; 3908 tsf = ath_hal_gettsf64(ah); 3909 do { 3910 bf = TAILQ_FIRST(&sc->sc_rxbuf); 3911 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 3912 if_printf(ifp, "%s: no buffer!\n", __func__); 3913 break; 3914 } else if (bf == NULL) { 3915 /* 3916 * End of List: 3917 * this can happen for non-self-linked RX chains 3918 */ 3919 sc->sc_stats.ast_rx_hitqueueend++; 3920 break; 3921 } 3922 m = bf->bf_m; 3923 if (m == NULL) { /* NB: shouldn't happen */ 3924 /* 3925 * If mbuf allocation failed previously there 3926 * will be no mbuf; try again to re-populate it. 3927 */ 3928 /* XXX make debug msg */ 3929 if_printf(ifp, "%s: no mbuf!\n", __func__); 3930 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 3931 goto rx_next; 3932 } 3933 ds = bf->bf_desc; 3934 if (ds->ds_link == bf->bf_daddr) { 3935 /* NB: never process the self-linked entry at the end */ 3936 sc->sc_stats.ast_rx_hitqueueend++; 3937 break; 3938 } 3939 /* XXX sync descriptor memory */ 3940 /* 3941 * Must provide the virtual address of the current 3942 * descriptor, the physical address, and the virtual 3943 * address of the next descriptor in the h/w chain. 3944 * This allows the HAL to look ahead to see if the 3945 * hardware is done with a descriptor by checking the 3946 * done bit in the following descriptor and the address 3947 * of the current descriptor the DMA engine is working 3948 * on. All this is necessary because of our use of 3949 * a self-linked list to avoid rx overruns. 3950 */ 3951 rs = &bf->bf_status.ds_rxstat; 3952 status = ath_hal_rxprocdesc(ah, ds, 3953 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 3954 #ifdef ATH_DEBUG 3955 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3956 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 3957 #endif 3958 if (status == HAL_EINPROGRESS) 3959 break; 3960 3961 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 3962 npkts++; 3963 3964 /* These aren't specifically errors */ 3965 if (rs->rs_flags & HAL_RX_GI) 3966 sc->sc_stats.ast_rx_halfgi++; 3967 if (rs->rs_flags & HAL_RX_2040) 3968 sc->sc_stats.ast_rx_2040++; 3969 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 3970 sc->sc_stats.ast_rx_pre_crc_err++; 3971 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 3972 sc->sc_stats.ast_rx_post_crc_err++; 3973 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 3974 sc->sc_stats.ast_rx_decrypt_busy_err++; 3975 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 3976 sc->sc_stats.ast_rx_hi_rx_chain++; 3977 3978 if (rs->rs_status != 0) { 3979 if (rs->rs_status & HAL_RXERR_CRC) 3980 sc->sc_stats.ast_rx_crcerr++; 3981 if (rs->rs_status & HAL_RXERR_FIFO) 3982 sc->sc_stats.ast_rx_fifoerr++; 3983 if (rs->rs_status & HAL_RXERR_PHY) { 3984 sc->sc_stats.ast_rx_phyerr++; 3985 /* Process DFS radar events */ 3986 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 3987 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 3988 /* Since we're touching the frame data, sync it */ 3989 bus_dmamap_sync(sc->sc_dmat, 3990 bf->bf_dmamap, 3991 BUS_DMASYNC_POSTREAD); 3992 /* Now pass it to the radar processing code */ 3993 ath_dfs_process_phy_err(sc, mtod(m, char *), tsf, rs); 3994 } 3995 3996 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 3997 if (rs->rs_phyerr < 64) 3998 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 3999 goto rx_error; /* NB: don't count in ierrors */ 4000 } 4001 if (rs->rs_status & HAL_RXERR_DECRYPT) { 4002 /* 4003 * Decrypt error. If the error occurred 4004 * because there was no hardware key, then 4005 * let the frame through so the upper layers 4006 * can process it. This is necessary for 5210 4007 * parts which have no way to setup a ``clear'' 4008 * key cache entry. 4009 * 4010 * XXX do key cache faulting 4011 */ 4012 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 4013 goto rx_accept; 4014 sc->sc_stats.ast_rx_badcrypt++; 4015 } 4016 if (rs->rs_status & HAL_RXERR_MIC) { 4017 sc->sc_stats.ast_rx_badmic++; 4018 /* 4019 * Do minimal work required to hand off 4020 * the 802.11 header for notification. 4021 */ 4022 /* XXX frag's and qos frames */ 4023 len = rs->rs_datalen; 4024 if (len >= sizeof (struct ieee80211_frame)) { 4025 bus_dmamap_sync(sc->sc_dmat, 4026 bf->bf_dmamap, 4027 BUS_DMASYNC_POSTREAD); 4028 ath_handle_micerror(ic, 4029 mtod(m, struct ieee80211_frame *), 4030 sc->sc_splitmic ? 4031 rs->rs_keyix-32 : rs->rs_keyix); 4032 } 4033 } 4034 ifp->if_ierrors++; 4035 rx_error: 4036 /* 4037 * Cleanup any pending partial frame. 4038 */ 4039 if (sc->sc_rxpending != NULL) { 4040 m_freem(sc->sc_rxpending); 4041 sc->sc_rxpending = NULL; 4042 } 4043 /* 4044 * When a tap is present pass error frames 4045 * that have been requested. By default we 4046 * pass decrypt+mic errors but others may be 4047 * interesting (e.g. crc). 4048 */ 4049 if (ieee80211_radiotap_active(ic) && 4050 (rs->rs_status & sc->sc_monpass)) { 4051 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4052 BUS_DMASYNC_POSTREAD); 4053 /* NB: bpf needs the mbuf length setup */ 4054 len = rs->rs_datalen; 4055 m->m_pkthdr.len = m->m_len = len; 4056 bf->bf_m = NULL; 4057 ath_rx_tap(ifp, m, rs, tsf, nf); 4058 ieee80211_radiotap_rx_all(ic, m); 4059 m_freem(m); 4060 } 4061 /* XXX pass MIC errors up for s/w reclaculation */ 4062 goto rx_next; 4063 } 4064 rx_accept: 4065 /* 4066 * Sync and unmap the frame. At this point we're 4067 * committed to passing the mbuf somewhere so clear 4068 * bf_m; this means a new mbuf must be allocated 4069 * when the rx descriptor is setup again to receive 4070 * another frame. 4071 */ 4072 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4073 BUS_DMASYNC_POSTREAD); 4074 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4075 bf->bf_m = NULL; 4076 4077 len = rs->rs_datalen; 4078 m->m_len = len; 4079 4080 if (rs->rs_more) { 4081 /* 4082 * Frame spans multiple descriptors; save 4083 * it for the next completed descriptor, it 4084 * will be used to construct a jumbogram. 4085 */ 4086 if (sc->sc_rxpending != NULL) { 4087 /* NB: max frame size is currently 2 clusters */ 4088 sc->sc_stats.ast_rx_toobig++; 4089 m_freem(sc->sc_rxpending); 4090 } 4091 m->m_pkthdr.rcvif = ifp; 4092 m->m_pkthdr.len = len; 4093 sc->sc_rxpending = m; 4094 goto rx_next; 4095 } else if (sc->sc_rxpending != NULL) { 4096 /* 4097 * This is the second part of a jumbogram, 4098 * chain it to the first mbuf, adjust the 4099 * frame length, and clear the rxpending state. 4100 */ 4101 sc->sc_rxpending->m_next = m; 4102 sc->sc_rxpending->m_pkthdr.len += len; 4103 m = sc->sc_rxpending; 4104 sc->sc_rxpending = NULL; 4105 } else { 4106 /* 4107 * Normal single-descriptor receive; setup 4108 * the rcvif and packet length. 4109 */ 4110 m->m_pkthdr.rcvif = ifp; 4111 m->m_pkthdr.len = len; 4112 } 4113 4114 ifp->if_ipackets++; 4115 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 4116 4117 /* 4118 * Populate the rx status block. When there are bpf 4119 * listeners we do the additional work to provide 4120 * complete status. Otherwise we fill in only the 4121 * material required by ieee80211_input. Note that 4122 * noise setting is filled in above. 4123 */ 4124 if (ieee80211_radiotap_active(ic)) 4125 ath_rx_tap(ifp, m, rs, tsf, nf); 4126 4127 /* 4128 * From this point on we assume the frame is at least 4129 * as large as ieee80211_frame_min; verify that. 4130 */ 4131 if (len < IEEE80211_MIN_LEN) { 4132 if (!ieee80211_radiotap_active(ic)) { 4133 DPRINTF(sc, ATH_DEBUG_RECV, 4134 "%s: short packet %d\n", __func__, len); 4135 sc->sc_stats.ast_rx_tooshort++; 4136 } else { 4137 /* NB: in particular this captures ack's */ 4138 ieee80211_radiotap_rx_all(ic, m); 4139 } 4140 m_freem(m); 4141 goto rx_next; 4142 } 4143 4144 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 4145 const HAL_RATE_TABLE *rt = sc->sc_currates; 4146 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 4147 4148 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 4149 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 4150 } 4151 4152 m_adj(m, -IEEE80211_CRC_LEN); 4153 4154 /* 4155 * Locate the node for sender, track state, and then 4156 * pass the (referenced) node up to the 802.11 layer 4157 * for its use. 4158 */ 4159 ni = ieee80211_find_rxnode_withkey(ic, 4160 mtod(m, const struct ieee80211_frame_min *), 4161 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 4162 IEEE80211_KEYIX_NONE : rs->rs_keyix); 4163 sc->sc_lastrs = rs; 4164 4165 if (rs->rs_isaggr) 4166 sc->sc_stats.ast_rx_agg++; 4167 4168 if (ni != NULL) { 4169 /* 4170 * Only punt packets for ampdu reorder processing for 4171 * 11n nodes; net80211 enforces that M_AMPDU is only 4172 * set for 11n nodes. 4173 */ 4174 if (ni->ni_flags & IEEE80211_NODE_HT) 4175 m->m_flags |= M_AMPDU; 4176 4177 /* 4178 * Sending station is known, dispatch directly. 4179 */ 4180 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 4181 ieee80211_free_node(ni); 4182 /* 4183 * Arrange to update the last rx timestamp only for 4184 * frames from our ap when operating in station mode. 4185 * This assumes the rx key is always setup when 4186 * associated. 4187 */ 4188 if (ic->ic_opmode == IEEE80211_M_STA && 4189 rs->rs_keyix != HAL_RXKEYIX_INVALID) 4190 ngood++; 4191 } else { 4192 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 4193 } 4194 /* 4195 * Track rx rssi and do any rx antenna management. 4196 */ 4197 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 4198 if (sc->sc_diversity) { 4199 /* 4200 * When using fast diversity, change the default rx 4201 * antenna if diversity chooses the other antenna 3 4202 * times in a row. 4203 */ 4204 if (sc->sc_defant != rs->rs_antenna) { 4205 if (++sc->sc_rxotherant >= 3) 4206 ath_setdefantenna(sc, rs->rs_antenna); 4207 } else 4208 sc->sc_rxotherant = 0; 4209 } 4210 4211 /* Newer school diversity - kite specific for now */ 4212 /* XXX perhaps migrate the normal diversity code to this? */ 4213 if ((ah)->ah_rxAntCombDiversity) 4214 (*(ah)->ah_rxAntCombDiversity)(ah, rs, ticks, hz); 4215 4216 if (sc->sc_softled) { 4217 /* 4218 * Blink for any data frame. Otherwise do a 4219 * heartbeat-style blink when idle. The latter 4220 * is mainly for station mode where we depend on 4221 * periodic beacon frames to trigger the poll event. 4222 */ 4223 if (type == IEEE80211_FC0_TYPE_DATA) { 4224 const HAL_RATE_TABLE *rt = sc->sc_currates; 4225 ath_led_event(sc, 4226 rt->rateCodeToIndex[rs->rs_rate]); 4227 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 4228 ath_led_event(sc, 0); 4229 } 4230 rx_next: 4231 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 4232 } while (ath_rxbuf_init(sc, bf) == 0); 4233 4234 /* rx signal state monitoring */ 4235 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 4236 if (ngood) 4237 sc->sc_lastrx = tsf; 4238 4239 CTR2(ATH_KTR_INTR, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 4240 /* Queue DFS tasklet if needed */ 4241 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 4242 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 4243 4244 /* 4245 * Now that all the RX frames were handled that 4246 * need to be handled, kick the PCU if there's 4247 * been an RXEOL condition. 4248 */ 4249 ATH_PCU_LOCK(sc); 4250 if (resched && sc->sc_kickpcu) { 4251 CTR0(ATH_KTR_ERR, "ath_rx_proc: kickpcu"); 4252 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 4253 __func__, npkts); 4254 4255 /* XXX rxslink? */ 4256 /* 4257 * XXX can we hold the PCU lock here? 4258 * Are there any net80211 buffer calls involved? 4259 */ 4260 bf = TAILQ_FIRST(&sc->sc_rxbuf); 4261 ath_hal_putrxbuf(ah, bf->bf_daddr); 4262 ath_hal_rxena(ah); /* enable recv descriptors */ 4263 ath_mode_init(sc); /* set filters, etc. */ 4264 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 4265 4266 ath_hal_intrset(ah, sc->sc_imask); 4267 sc->sc_kickpcu = 0; 4268 } 4269 ATH_PCU_UNLOCK(sc); 4270 4271 /* XXX check this inside of IF_LOCK? */ 4272 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 4273 #ifdef IEEE80211_SUPPORT_SUPERG 4274 ieee80211_ff_age_all(ic, 100); 4275 #endif 4276 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 4277 ath_start(ifp); 4278 } 4279 #undef PA2DESC 4280 4281 ATH_PCU_LOCK(sc); 4282 sc->sc_rxproc_cnt--; 4283 ATH_PCU_UNLOCK(sc); 4284 } 4285 4286 static void 4287 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 4288 { 4289 txq->axq_qnum = qnum; 4290 txq->axq_ac = 0; 4291 txq->axq_depth = 0; 4292 txq->axq_aggr_depth = 0; 4293 txq->axq_intrcnt = 0; 4294 txq->axq_link = NULL; 4295 txq->axq_softc = sc; 4296 TAILQ_INIT(&txq->axq_q); 4297 TAILQ_INIT(&txq->axq_tidq); 4298 ATH_TXQ_LOCK_INIT(sc, txq); 4299 } 4300 4301 /* 4302 * Setup a h/w transmit queue. 4303 */ 4304 static struct ath_txq * 4305 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 4306 { 4307 #define N(a) (sizeof(a)/sizeof(a[0])) 4308 struct ath_hal *ah = sc->sc_ah; 4309 HAL_TXQ_INFO qi; 4310 int qnum; 4311 4312 memset(&qi, 0, sizeof(qi)); 4313 qi.tqi_subtype = subtype; 4314 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 4315 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 4316 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 4317 /* 4318 * Enable interrupts only for EOL and DESC conditions. 4319 * We mark tx descriptors to receive a DESC interrupt 4320 * when a tx queue gets deep; otherwise waiting for the 4321 * EOL to reap descriptors. Note that this is done to 4322 * reduce interrupt load and this only defers reaping 4323 * descriptors, never transmitting frames. Aside from 4324 * reducing interrupts this also permits more concurrency. 4325 * The only potential downside is if the tx queue backs 4326 * up in which case the top half of the kernel may backup 4327 * due to a lack of tx descriptors. 4328 */ 4329 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 4330 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 4331 if (qnum == -1) { 4332 /* 4333 * NB: don't print a message, this happens 4334 * normally on parts with too few tx queues 4335 */ 4336 return NULL; 4337 } 4338 if (qnum >= N(sc->sc_txq)) { 4339 device_printf(sc->sc_dev, 4340 "hal qnum %u out of range, max %zu!\n", 4341 qnum, N(sc->sc_txq)); 4342 ath_hal_releasetxqueue(ah, qnum); 4343 return NULL; 4344 } 4345 if (!ATH_TXQ_SETUP(sc, qnum)) { 4346 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4347 sc->sc_txqsetup |= 1<<qnum; 4348 } 4349 return &sc->sc_txq[qnum]; 4350 #undef N 4351 } 4352 4353 /* 4354 * Setup a hardware data transmit queue for the specified 4355 * access control. The hal may not support all requested 4356 * queues in which case it will return a reference to a 4357 * previously setup queue. We record the mapping from ac's 4358 * to h/w queues for use by ath_tx_start and also track 4359 * the set of h/w queues being used to optimize work in the 4360 * transmit interrupt handler and related routines. 4361 */ 4362 static int 4363 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4364 { 4365 #define N(a) (sizeof(a)/sizeof(a[0])) 4366 struct ath_txq *txq; 4367 4368 if (ac >= N(sc->sc_ac2q)) { 4369 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4370 ac, N(sc->sc_ac2q)); 4371 return 0; 4372 } 4373 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4374 if (txq != NULL) { 4375 txq->axq_ac = ac; 4376 sc->sc_ac2q[ac] = txq; 4377 return 1; 4378 } else 4379 return 0; 4380 #undef N 4381 } 4382 4383 /* 4384 * Update WME parameters for a transmit queue. 4385 */ 4386 static int 4387 ath_txq_update(struct ath_softc *sc, int ac) 4388 { 4389 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4390 #define ATH_TXOP_TO_US(v) (v<<5) 4391 struct ifnet *ifp = sc->sc_ifp; 4392 struct ieee80211com *ic = ifp->if_l2com; 4393 struct ath_txq *txq = sc->sc_ac2q[ac]; 4394 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4395 struct ath_hal *ah = sc->sc_ah; 4396 HAL_TXQ_INFO qi; 4397 4398 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4399 #ifdef IEEE80211_SUPPORT_TDMA 4400 if (sc->sc_tdma) { 4401 /* 4402 * AIFS is zero so there's no pre-transmit wait. The 4403 * burst time defines the slot duration and is configured 4404 * through net80211. The QCU is setup to not do post-xmit 4405 * back off, lockout all lower-priority QCU's, and fire 4406 * off the DMA beacon alert timer which is setup based 4407 * on the slot configuration. 4408 */ 4409 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4410 | HAL_TXQ_TXERRINT_ENABLE 4411 | HAL_TXQ_TXURNINT_ENABLE 4412 | HAL_TXQ_TXEOLINT_ENABLE 4413 | HAL_TXQ_DBA_GATED 4414 | HAL_TXQ_BACKOFF_DISABLE 4415 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4416 ; 4417 qi.tqi_aifs = 0; 4418 /* XXX +dbaprep? */ 4419 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4420 qi.tqi_burstTime = qi.tqi_readyTime; 4421 } else { 4422 #endif 4423 /* 4424 * XXX shouldn't this just use the default flags 4425 * used in the previous queue setup? 4426 */ 4427 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4428 | HAL_TXQ_TXERRINT_ENABLE 4429 | HAL_TXQ_TXDESCINT_ENABLE 4430 | HAL_TXQ_TXURNINT_ENABLE 4431 | HAL_TXQ_TXEOLINT_ENABLE 4432 ; 4433 qi.tqi_aifs = wmep->wmep_aifsn; 4434 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4435 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4436 qi.tqi_readyTime = 0; 4437 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 4438 #ifdef IEEE80211_SUPPORT_TDMA 4439 } 4440 #endif 4441 4442 DPRINTF(sc, ATH_DEBUG_RESET, 4443 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4444 __func__, txq->axq_qnum, qi.tqi_qflags, 4445 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4446 4447 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4448 if_printf(ifp, "unable to update hardware queue " 4449 "parameters for %s traffic!\n", 4450 ieee80211_wme_acnames[ac]); 4451 return 0; 4452 } else { 4453 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4454 return 1; 4455 } 4456 #undef ATH_TXOP_TO_US 4457 #undef ATH_EXPONENT_TO_VALUE 4458 } 4459 4460 /* 4461 * Callback from the 802.11 layer to update WME parameters. 4462 */ 4463 static int 4464 ath_wme_update(struct ieee80211com *ic) 4465 { 4466 struct ath_softc *sc = ic->ic_ifp->if_softc; 4467 4468 return !ath_txq_update(sc, WME_AC_BE) || 4469 !ath_txq_update(sc, WME_AC_BK) || 4470 !ath_txq_update(sc, WME_AC_VI) || 4471 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4472 } 4473 4474 /* 4475 * Reclaim resources for a setup queue. 4476 */ 4477 static void 4478 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4479 { 4480 4481 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4482 ATH_TXQ_LOCK_DESTROY(txq); 4483 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4484 } 4485 4486 /* 4487 * Reclaim all tx queue resources. 4488 */ 4489 static void 4490 ath_tx_cleanup(struct ath_softc *sc) 4491 { 4492 int i; 4493 4494 ATH_TXBUF_LOCK_DESTROY(sc); 4495 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4496 if (ATH_TXQ_SETUP(sc, i)) 4497 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4498 } 4499 4500 /* 4501 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 4502 * using the current rates in sc_rixmap. 4503 */ 4504 int 4505 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 4506 { 4507 int rix = sc->sc_rixmap[rate]; 4508 /* NB: return lowest rix for invalid rate */ 4509 return (rix == 0xff ? 0 : rix); 4510 } 4511 4512 static void 4513 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts, 4514 struct ath_buf *bf) 4515 { 4516 struct ieee80211_node *ni = bf->bf_node; 4517 struct ifnet *ifp = sc->sc_ifp; 4518 struct ieee80211com *ic = ifp->if_l2com; 4519 int sr, lr, pri; 4520 4521 if (ts->ts_status == 0) { 4522 u_int8_t txant = ts->ts_antenna; 4523 sc->sc_stats.ast_ant_tx[txant]++; 4524 sc->sc_ant_tx[txant]++; 4525 if (ts->ts_finaltsi != 0) 4526 sc->sc_stats.ast_tx_altrate++; 4527 pri = M_WME_GETAC(bf->bf_m); 4528 if (pri >= WME_AC_VO) 4529 ic->ic_wme.wme_hipri_traffic++; 4530 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0) 4531 ni->ni_inact = ni->ni_inact_reload; 4532 } else { 4533 if (ts->ts_status & HAL_TXERR_XRETRY) 4534 sc->sc_stats.ast_tx_xretries++; 4535 if (ts->ts_status & HAL_TXERR_FIFO) 4536 sc->sc_stats.ast_tx_fifoerr++; 4537 if (ts->ts_status & HAL_TXERR_FILT) 4538 sc->sc_stats.ast_tx_filtered++; 4539 if (ts->ts_status & HAL_TXERR_XTXOP) 4540 sc->sc_stats.ast_tx_xtxop++; 4541 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED) 4542 sc->sc_stats.ast_tx_timerexpired++; 4543 4544 if (ts->ts_status & HAL_TX_DATA_UNDERRUN) 4545 sc->sc_stats.ast_tx_data_underrun++; 4546 if (ts->ts_status & HAL_TX_DELIM_UNDERRUN) 4547 sc->sc_stats.ast_tx_delim_underrun++; 4548 4549 if (bf->bf_m->m_flags & M_FF) 4550 sc->sc_stats.ast_ff_txerr++; 4551 } 4552 /* XXX when is this valid? */ 4553 if (ts->ts_status & HAL_TX_DESC_CFG_ERR) 4554 sc->sc_stats.ast_tx_desccfgerr++; 4555 4556 sr = ts->ts_shortretry; 4557 lr = ts->ts_longretry; 4558 sc->sc_stats.ast_tx_shortretry += sr; 4559 sc->sc_stats.ast_tx_longretry += lr; 4560 4561 } 4562 4563 /* 4564 * The default completion. If fail is 1, this means 4565 * "please don't retry the frame, and just return -1 status 4566 * to the net80211 stack. 4567 */ 4568 void 4569 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 4570 { 4571 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 4572 int st; 4573 4574 if (fail == 1) 4575 st = -1; 4576 else 4577 st = ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0) ? 4578 ts->ts_status : HAL_TXERR_XRETRY; 4579 4580 if (bf->bf_state.bfs_dobaw) 4581 device_printf(sc->sc_dev, 4582 "%s: dobaw should've been cleared!\n", __func__); 4583 if (bf->bf_next != NULL) 4584 device_printf(sc->sc_dev, 4585 "%s: bf_next not NULL!\n", __func__); 4586 4587 /* 4588 * Do any tx complete callback. Note this must 4589 * be done before releasing the node reference. 4590 * This will free the mbuf, release the net80211 4591 * node and recycle the ath_buf. 4592 */ 4593 ath_tx_freebuf(sc, bf, st); 4594 } 4595 4596 /* 4597 * Update rate control with the given completion status. 4598 */ 4599 void 4600 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 4601 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen, 4602 int nframes, int nbad) 4603 { 4604 struct ath_node *an; 4605 4606 /* Only for unicast frames */ 4607 if (ni == NULL) 4608 return; 4609 4610 an = ATH_NODE(ni); 4611 4612 if ((ts->ts_status & HAL_TXERR_FILT) == 0) { 4613 ATH_NODE_LOCK(an); 4614 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad); 4615 ATH_NODE_UNLOCK(an); 4616 } 4617 } 4618 4619 /* 4620 * Update the busy status of the last frame on the free list. 4621 * When doing TDMA, the busy flag tracks whether the hardware 4622 * currently points to this buffer or not, and thus gated DMA 4623 * may restart by re-reading the last descriptor in this 4624 * buffer. 4625 * 4626 * This should be called in the completion function once one 4627 * of the buffers has been used. 4628 */ 4629 static void 4630 ath_tx_update_busy(struct ath_softc *sc) 4631 { 4632 struct ath_buf *last; 4633 4634 /* 4635 * Since the last frame may still be marked 4636 * as ATH_BUF_BUSY, unmark it here before 4637 * finishing the frame processing. 4638 * Since we've completed a frame (aggregate 4639 * or otherwise), the hardware has moved on 4640 * and is no longer referencing the previous 4641 * descriptor. 4642 */ 4643 ATH_TXBUF_LOCK_ASSERT(sc); 4644 last = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s); 4645 if (last != NULL) 4646 last->bf_flags &= ~ATH_BUF_BUSY; 4647 } 4648 4649 4650 /* 4651 * Process completed xmit descriptors from the specified queue. 4652 * Kick the packet scheduler if needed. This can occur from this 4653 * particular task. 4654 */ 4655 static int 4656 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched) 4657 { 4658 struct ath_hal *ah = sc->sc_ah; 4659 struct ath_buf *bf; 4660 struct ath_desc *ds; 4661 struct ath_tx_status *ts; 4662 struct ieee80211_node *ni; 4663 struct ath_node *an; 4664 int nacked; 4665 HAL_STATUS status; 4666 4667 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4668 __func__, txq->axq_qnum, 4669 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4670 txq->axq_link); 4671 nacked = 0; 4672 for (;;) { 4673 ATH_TXQ_LOCK(txq); 4674 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4675 bf = TAILQ_FIRST(&txq->axq_q); 4676 if (bf == NULL) { 4677 ATH_TXQ_UNLOCK(txq); 4678 break; 4679 } 4680 ds = bf->bf_lastds; /* XXX must be setup correctly! */ 4681 ts = &bf->bf_status.ds_txstat; 4682 status = ath_hal_txprocdesc(ah, ds, ts); 4683 #ifdef ATH_DEBUG 4684 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4685 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4686 status == HAL_OK); 4687 #endif 4688 if (status == HAL_EINPROGRESS) { 4689 ATH_TXQ_UNLOCK(txq); 4690 break; 4691 } 4692 ATH_TXQ_REMOVE(txq, bf, bf_list); 4693 #ifdef IEEE80211_SUPPORT_TDMA 4694 if (txq->axq_depth > 0) { 4695 /* 4696 * More frames follow. Mark the buffer busy 4697 * so it's not re-used while the hardware may 4698 * still re-read the link field in the descriptor. 4699 * 4700 * Use the last buffer in an aggregate as that 4701 * is where the hardware may be - intermediate 4702 * descriptors won't be "busy". 4703 */ 4704 bf->bf_last->bf_flags |= ATH_BUF_BUSY; 4705 } else 4706 #else 4707 if (txq->axq_depth == 0) 4708 #endif 4709 txq->axq_link = NULL; 4710 if (bf->bf_state.bfs_aggr) 4711 txq->axq_aggr_depth--; 4712 4713 ni = bf->bf_node; 4714 /* 4715 * If unicast frame was ack'd update RSSI, 4716 * including the last rx time used to 4717 * workaround phantom bmiss interrupts. 4718 */ 4719 if (ni != NULL && ts->ts_status == 0 && 4720 ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0)) { 4721 nacked++; 4722 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4723 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4724 ts->ts_rssi); 4725 } 4726 ATH_TXQ_UNLOCK(txq); 4727 4728 /* If unicast frame, update general statistics */ 4729 if (ni != NULL) { 4730 an = ATH_NODE(ni); 4731 /* update statistics */ 4732 ath_tx_update_stats(sc, ts, bf); 4733 } 4734 4735 /* 4736 * Call the completion handler. 4737 * The completion handler is responsible for 4738 * calling the rate control code. 4739 * 4740 * Frames with no completion handler get the 4741 * rate control code called here. 4742 */ 4743 if (bf->bf_comp == NULL) { 4744 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4745 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) { 4746 /* 4747 * XXX assume this isn't an aggregate 4748 * frame. 4749 */ 4750 ath_tx_update_ratectrl(sc, ni, 4751 bf->bf_state.bfs_rc, ts, 4752 bf->bf_state.bfs_pktlen, 1, 4753 (ts->ts_status == 0 ? 0 : 1)); 4754 } 4755 ath_tx_default_comp(sc, bf, 0); 4756 } else 4757 bf->bf_comp(sc, bf, 0); 4758 } 4759 #ifdef IEEE80211_SUPPORT_SUPERG 4760 /* 4761 * Flush fast-frame staging queue when traffic slows. 4762 */ 4763 if (txq->axq_depth <= 1) 4764 ieee80211_ff_flush(ic, txq->axq_ac); 4765 #endif 4766 4767 /* Kick the TXQ scheduler */ 4768 if (dosched) { 4769 ATH_TXQ_LOCK(txq); 4770 ath_txq_sched(sc, txq); 4771 ATH_TXQ_UNLOCK(txq); 4772 } 4773 4774 return nacked; 4775 } 4776 4777 #define TXQACTIVE(t, q) ( (t) & (1 << (q))) 4778 4779 /* 4780 * Deferred processing of transmit interrupt; special-cased 4781 * for a single hardware transmit queue (e.g. 5210 and 5211). 4782 */ 4783 static void 4784 ath_tx_proc_q0(void *arg, int npending) 4785 { 4786 struct ath_softc *sc = arg; 4787 struct ifnet *ifp = sc->sc_ifp; 4788 uint32_t txqs; 4789 4790 ATH_PCU_LOCK(sc); 4791 sc->sc_txproc_cnt++; 4792 txqs = sc->sc_txq_active; 4793 sc->sc_txq_active &= ~txqs; 4794 ATH_PCU_UNLOCK(sc); 4795 4796 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1)) 4797 /* XXX why is lastrx updated in tx code? */ 4798 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4799 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4800 ath_tx_processq(sc, sc->sc_cabq, 1); 4801 /* XXX check this inside of IF_LOCK? */ 4802 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4803 sc->sc_wd_timer = 0; 4804 4805 if (sc->sc_softled) 4806 ath_led_event(sc, sc->sc_txrix); 4807 4808 ATH_PCU_LOCK(sc); 4809 sc->sc_txproc_cnt--; 4810 ATH_PCU_UNLOCK(sc); 4811 4812 ath_start(ifp); 4813 } 4814 4815 /* 4816 * Deferred processing of transmit interrupt; special-cased 4817 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 4818 */ 4819 static void 4820 ath_tx_proc_q0123(void *arg, int npending) 4821 { 4822 struct ath_softc *sc = arg; 4823 struct ifnet *ifp = sc->sc_ifp; 4824 int nacked; 4825 uint32_t txqs; 4826 4827 ATH_PCU_LOCK(sc); 4828 sc->sc_txproc_cnt++; 4829 txqs = sc->sc_txq_active; 4830 sc->sc_txq_active &= ~txqs; 4831 ATH_PCU_UNLOCK(sc); 4832 4833 /* 4834 * Process each active queue. 4835 */ 4836 nacked = 0; 4837 if (TXQACTIVE(txqs, 0)) 4838 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1); 4839 if (TXQACTIVE(txqs, 1)) 4840 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1); 4841 if (TXQACTIVE(txqs, 2)) 4842 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1); 4843 if (TXQACTIVE(txqs, 3)) 4844 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1); 4845 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum)) 4846 ath_tx_processq(sc, sc->sc_cabq, 1); 4847 if (nacked) 4848 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4849 4850 /* XXX check this inside of IF_LOCK? */ 4851 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4852 sc->sc_wd_timer = 0; 4853 4854 if (sc->sc_softled) 4855 ath_led_event(sc, sc->sc_txrix); 4856 4857 ATH_PCU_LOCK(sc); 4858 sc->sc_txproc_cnt--; 4859 ATH_PCU_UNLOCK(sc); 4860 4861 ath_start(ifp); 4862 } 4863 4864 /* 4865 * Deferred processing of transmit interrupt. 4866 */ 4867 static void 4868 ath_tx_proc(void *arg, int npending) 4869 { 4870 struct ath_softc *sc = arg; 4871 struct ifnet *ifp = sc->sc_ifp; 4872 int i, nacked; 4873 uint32_t txqs; 4874 4875 ATH_PCU_LOCK(sc); 4876 sc->sc_txproc_cnt++; 4877 txqs = sc->sc_txq_active; 4878 sc->sc_txq_active &= ~txqs; 4879 ATH_PCU_UNLOCK(sc); 4880 4881 /* 4882 * Process each active queue. 4883 */ 4884 nacked = 0; 4885 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4886 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i)) 4887 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1); 4888 if (nacked) 4889 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 4890 4891 /* XXX check this inside of IF_LOCK? */ 4892 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4893 sc->sc_wd_timer = 0; 4894 4895 if (sc->sc_softled) 4896 ath_led_event(sc, sc->sc_txrix); 4897 4898 ATH_PCU_LOCK(sc); 4899 sc->sc_txproc_cnt--; 4900 ATH_PCU_UNLOCK(sc); 4901 4902 ath_start(ifp); 4903 } 4904 #undef TXQACTIVE 4905 4906 /* 4907 * Return a buffer to the pool and update the 'busy' flag on the 4908 * previous 'tail' entry. 4909 * 4910 * This _must_ only be called when the buffer is involved in a completed 4911 * TX. The logic is that if it was part of an active TX, the previous 4912 * buffer on the list is now not involved in a halted TX DMA queue, waiting 4913 * for restart (eg for TDMA.) 4914 * 4915 * The caller must free the mbuf and recycle the node reference. 4916 */ 4917 void 4918 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf) 4919 { 4920 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4921 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTWRITE); 4922 4923 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__)); 4924 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__)); 4925 4926 ATH_TXBUF_LOCK(sc); 4927 ath_tx_update_busy(sc); 4928 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 4929 ATH_TXBUF_UNLOCK(sc); 4930 } 4931 4932 /* 4933 * This is currently used by ath_tx_draintxq() and 4934 * ath_tx_tid_free_pkts(). 4935 * 4936 * It recycles a single ath_buf. 4937 */ 4938 void 4939 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status) 4940 { 4941 struct ieee80211_node *ni = bf->bf_node; 4942 struct mbuf *m0 = bf->bf_m; 4943 4944 bf->bf_node = NULL; 4945 bf->bf_m = NULL; 4946 4947 /* Free the buffer, it's not needed any longer */ 4948 ath_freebuf(sc, bf); 4949 4950 if (ni != NULL) { 4951 /* 4952 * Do any callback and reclaim the node reference. 4953 */ 4954 if (m0->m_flags & M_TXCB) 4955 ieee80211_process_callback(ni, m0, status); 4956 ieee80211_free_node(ni); 4957 } 4958 m_freem(m0); 4959 4960 /* 4961 * XXX the buffer used to be freed -after-, but the DMA map was 4962 * freed where ath_freebuf() now is. I've no idea what this 4963 * will do. 4964 */ 4965 } 4966 4967 void 4968 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 4969 { 4970 #ifdef ATH_DEBUG 4971 struct ath_hal *ah = sc->sc_ah; 4972 #endif 4973 struct ath_buf *bf; 4974 u_int ix; 4975 4976 /* 4977 * NB: this assumes output has been stopped and 4978 * we do not need to block ath_tx_proc 4979 */ 4980 ATH_TXBUF_LOCK(sc); 4981 bf = TAILQ_LAST(&sc->sc_txbuf, ath_bufhead_s); 4982 if (bf != NULL) 4983 bf->bf_flags &= ~ATH_BUF_BUSY; 4984 ATH_TXBUF_UNLOCK(sc); 4985 4986 for (ix = 0;; ix++) { 4987 ATH_TXQ_LOCK(txq); 4988 bf = TAILQ_FIRST(&txq->axq_q); 4989 if (bf == NULL) { 4990 txq->axq_link = NULL; 4991 ATH_TXQ_UNLOCK(txq); 4992 break; 4993 } 4994 ATH_TXQ_REMOVE(txq, bf, bf_list); 4995 if (bf->bf_state.bfs_aggr) 4996 txq->axq_aggr_depth--; 4997 #ifdef ATH_DEBUG 4998 if (sc->sc_debug & ATH_DEBUG_RESET) { 4999 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5000 5001 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, 5002 ath_hal_txprocdesc(ah, bf->bf_lastds, 5003 &bf->bf_status.ds_txstat) == HAL_OK); 5004 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 5005 bf->bf_m->m_len, 0, -1); 5006 } 5007 #endif /* ATH_DEBUG */ 5008 /* 5009 * Since we're now doing magic in the completion 5010 * functions, we -must- call it for aggregation 5011 * destinations or BAW tracking will get upset. 5012 */ 5013 /* 5014 * Clear ATH_BUF_BUSY; the completion handler 5015 * will free the buffer. 5016 */ 5017 ATH_TXQ_UNLOCK(txq); 5018 bf->bf_flags &= ~ATH_BUF_BUSY; 5019 if (bf->bf_comp) 5020 bf->bf_comp(sc, bf, 1); 5021 else 5022 ath_tx_default_comp(sc, bf, 1); 5023 } 5024 5025 /* 5026 * Drain software queued frames which are on 5027 * active TIDs. 5028 */ 5029 ath_tx_txq_drain(sc, txq); 5030 } 5031 5032 static void 5033 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5034 { 5035 struct ath_hal *ah = sc->sc_ah; 5036 5037 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5038 __func__, txq->axq_qnum, 5039 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5040 txq->axq_link); 5041 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5042 } 5043 5044 static int 5045 ath_stoptxdma(struct ath_softc *sc) 5046 { 5047 struct ath_hal *ah = sc->sc_ah; 5048 int i; 5049 5050 /* XXX return value */ 5051 if (sc->sc_invalid) 5052 return 0; 5053 5054 if (!sc->sc_invalid) { 5055 /* don't touch the hardware if marked invalid */ 5056 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5057 __func__, sc->sc_bhalq, 5058 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5059 NULL); 5060 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5061 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5062 if (ATH_TXQ_SETUP(sc, i)) 5063 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5064 } 5065 5066 return 1; 5067 } 5068 5069 /* 5070 * Drain the transmit queues and reclaim resources. 5071 */ 5072 static void 5073 ath_draintxq(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 5074 { 5075 #ifdef ATH_DEBUG 5076 struct ath_hal *ah = sc->sc_ah; 5077 #endif 5078 struct ifnet *ifp = sc->sc_ifp; 5079 int i; 5080 5081 (void) ath_stoptxdma(sc); 5082 5083 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5084 /* 5085 * XXX TODO: should we just handle the completed TX frames 5086 * here, whether or not the reset is a full one or not? 5087 */ 5088 if (ATH_TXQ_SETUP(sc, i)) { 5089 if (reset_type == ATH_RESET_NOLOSS) 5090 ath_tx_processq(sc, &sc->sc_txq[i], 0); 5091 else 5092 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5093 } 5094 } 5095 #ifdef ATH_DEBUG 5096 if (sc->sc_debug & ATH_DEBUG_RESET) { 5097 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf); 5098 if (bf != NULL && bf->bf_m != NULL) { 5099 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5100 ath_hal_txprocdesc(ah, bf->bf_lastds, 5101 &bf->bf_status.ds_txstat) == HAL_OK); 5102 ieee80211_dump_pkt(ifp->if_l2com, 5103 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 5104 0, -1); 5105 } 5106 } 5107 #endif /* ATH_DEBUG */ 5108 /* XXX check this inside of IF_LOCK? */ 5109 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5110 sc->sc_wd_timer = 0; 5111 } 5112 5113 /* 5114 * Disable the receive h/w in preparation for a reset. 5115 */ 5116 static void 5117 ath_stoprecv(struct ath_softc *sc, int dodelay) 5118 { 5119 #define PA2DESC(_sc, _pa) \ 5120 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 5121 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 5122 struct ath_hal *ah = sc->sc_ah; 5123 5124 ath_hal_stoppcurecv(ah); /* disable PCU */ 5125 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 5126 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 5127 if (dodelay) 5128 DELAY(3000); /* 3ms is long enough for 1 frame */ 5129 #ifdef ATH_DEBUG 5130 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 5131 struct ath_buf *bf; 5132 u_int ix; 5133 5134 printf("%s: rx queue %p, link %p\n", __func__, 5135 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 5136 ix = 0; 5137 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5138 struct ath_desc *ds = bf->bf_desc; 5139 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5140 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 5141 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 5142 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 5143 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 5144 ix++; 5145 } 5146 } 5147 #endif 5148 if (sc->sc_rxpending != NULL) { 5149 m_freem(sc->sc_rxpending); 5150 sc->sc_rxpending = NULL; 5151 } 5152 sc->sc_rxlink = NULL; /* just in case */ 5153 #undef PA2DESC 5154 } 5155 5156 /* 5157 * Enable the receive h/w following a reset. 5158 */ 5159 static int 5160 ath_startrecv(struct ath_softc *sc) 5161 { 5162 struct ath_hal *ah = sc->sc_ah; 5163 struct ath_buf *bf; 5164 5165 sc->sc_rxlink = NULL; 5166 sc->sc_rxpending = NULL; 5167 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5168 int error = ath_rxbuf_init(sc, bf); 5169 if (error != 0) { 5170 DPRINTF(sc, ATH_DEBUG_RECV, 5171 "%s: ath_rxbuf_init failed %d\n", 5172 __func__, error); 5173 return error; 5174 } 5175 } 5176 5177 bf = TAILQ_FIRST(&sc->sc_rxbuf); 5178 ath_hal_putrxbuf(ah, bf->bf_daddr); 5179 ath_hal_rxena(ah); /* enable recv descriptors */ 5180 ath_mode_init(sc); /* set filters, etc. */ 5181 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 5182 return 0; 5183 } 5184 5185 /* 5186 * Update internal state after a channel change. 5187 */ 5188 static void 5189 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5190 { 5191 enum ieee80211_phymode mode; 5192 5193 /* 5194 * Change channels and update the h/w rate map 5195 * if we're switching; e.g. 11a to 11b/g. 5196 */ 5197 mode = ieee80211_chan2mode(chan); 5198 if (mode != sc->sc_curmode) 5199 ath_setcurmode(sc, mode); 5200 sc->sc_curchan = chan; 5201 } 5202 5203 /* 5204 * Set/change channels. If the channel is really being changed, 5205 * it's done by resetting the chip. To accomplish this we must 5206 * first cleanup any pending DMA, then restart stuff after a la 5207 * ath_init. 5208 */ 5209 static int 5210 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5211 { 5212 struct ifnet *ifp = sc->sc_ifp; 5213 struct ieee80211com *ic = ifp->if_l2com; 5214 struct ath_hal *ah = sc->sc_ah; 5215 int ret = 0; 5216 int dointr = 0; 5217 5218 /* Treat this as an interface reset */ 5219 ATH_PCU_LOCK(sc); 5220 if (sc->sc_inreset_cnt > 0) 5221 device_printf(sc->sc_dev, "%s: danger! concurrent reset!\n", 5222 __func__); 5223 sc->sc_inreset_cnt++; 5224 if (chan != sc->sc_curchan) { 5225 dointr = 1; 5226 /* XXX only do this if inreset_cnt is 1? */ 5227 ath_hal_intrset(ah, 0); 5228 } 5229 ATH_PCU_UNLOCK(sc); 5230 ath_txrx_stop(sc); 5231 5232 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 5233 __func__, ieee80211_chan2ieee(ic, chan), 5234 chan->ic_freq, chan->ic_flags); 5235 if (chan != sc->sc_curchan) { 5236 HAL_STATUS status; 5237 /* 5238 * To switch channels clear any pending DMA operations; 5239 * wait long enough for the RX fifo to drain, reset the 5240 * hardware at the new frequency, and then re-enable 5241 * the relevant bits of the h/w. 5242 */ 5243 #if 0 5244 ath_hal_intrset(ah, 0); /* disable interrupts */ 5245 #endif 5246 ath_stoprecv(sc, 1); /* turn off frame recv */ 5247 /* 5248 * First, handle completed TX/RX frames. 5249 */ 5250 ath_rx_proc(sc, 0); 5251 ath_draintxq(sc, ATH_RESET_NOLOSS); 5252 /* 5253 * Next, flush the non-scheduled frames. 5254 */ 5255 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */ 5256 5257 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 5258 if_printf(ifp, "%s: unable to reset " 5259 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 5260 __func__, ieee80211_chan2ieee(ic, chan), 5261 chan->ic_freq, chan->ic_flags, status); 5262 ret = EIO; 5263 goto finish; 5264 } 5265 sc->sc_diversity = ath_hal_getdiversity(ah); 5266 5267 /* Let DFS at it in case it's a DFS channel */ 5268 ath_dfs_radar_enable(sc, ic->ic_curchan); 5269 5270 /* 5271 * Re-enable rx framework. 5272 */ 5273 if (ath_startrecv(sc) != 0) { 5274 if_printf(ifp, "%s: unable to restart recv logic\n", 5275 __func__); 5276 ret = EIO; 5277 goto finish; 5278 } 5279 5280 /* 5281 * Change channels and update the h/w rate map 5282 * if we're switching; e.g. 11a to 11b/g. 5283 */ 5284 ath_chan_change(sc, chan); 5285 5286 /* 5287 * Reset clears the beacon timers; reset them 5288 * here if needed. 5289 */ 5290 if (sc->sc_beacons) { /* restart beacons */ 5291 #ifdef IEEE80211_SUPPORT_TDMA 5292 if (sc->sc_tdma) 5293 ath_tdma_config(sc, NULL); 5294 else 5295 #endif 5296 ath_beacon_config(sc, NULL); 5297 } 5298 5299 #if 0 5300 /* 5301 * Re-enable interrupts. 5302 */ 5303 ath_hal_intrset(ah, sc->sc_imask); 5304 #endif 5305 } 5306 5307 finish: 5308 ATH_PCU_LOCK(sc); 5309 sc->sc_inreset_cnt--; 5310 /* XXX only do this if sc_inreset_cnt == 0? */ 5311 if (dointr) 5312 ath_hal_intrset(ah, sc->sc_imask); 5313 ATH_PCU_UNLOCK(sc); 5314 5315 /* XXX do this inside of IF_LOCK? */ 5316 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5317 ath_txrx_start(sc); 5318 /* XXX ath_start? */ 5319 5320 return ret; 5321 } 5322 5323 /* 5324 * Periodically recalibrate the PHY to account 5325 * for temperature/environment changes. 5326 */ 5327 static void 5328 ath_calibrate(void *arg) 5329 { 5330 struct ath_softc *sc = arg; 5331 struct ath_hal *ah = sc->sc_ah; 5332 struct ifnet *ifp = sc->sc_ifp; 5333 struct ieee80211com *ic = ifp->if_l2com; 5334 HAL_BOOL longCal, isCalDone; 5335 HAL_BOOL aniCal, shortCal = AH_FALSE; 5336 int nextcal; 5337 5338 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 5339 goto restart; 5340 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5341 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000); 5342 if (sc->sc_doresetcal) 5343 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000); 5344 5345 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal); 5346 if (aniCal) { 5347 sc->sc_stats.ast_ani_cal++; 5348 sc->sc_lastani = ticks; 5349 ath_hal_ani_poll(ah, sc->sc_curchan); 5350 } 5351 5352 if (longCal) { 5353 sc->sc_stats.ast_per_cal++; 5354 sc->sc_lastlongcal = ticks; 5355 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5356 /* 5357 * Rfgain is out of bounds, reset the chip 5358 * to load new gain values. 5359 */ 5360 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5361 "%s: rfgain change\n", __func__); 5362 sc->sc_stats.ast_per_rfgain++; 5363 /* 5364 * Drop lock - we can't hold it across the 5365 * ath_reset() call. Instead, we'll drop 5366 * out here, do a reset, then reschedule 5367 * the callout. 5368 */ 5369 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 5370 sc->sc_resetcal = 0; 5371 sc->sc_doresetcal = AH_TRUE; 5372 ATH_UNLOCK(sc); 5373 ath_reset(ifp, ATH_RESET_NOLOSS); 5374 ATH_LOCK(sc); 5375 return; 5376 } 5377 /* 5378 * If this long cal is after an idle period, then 5379 * reset the data collection state so we start fresh. 5380 */ 5381 if (sc->sc_resetcal) { 5382 (void) ath_hal_calreset(ah, sc->sc_curchan); 5383 sc->sc_lastcalreset = ticks; 5384 sc->sc_lastshortcal = ticks; 5385 sc->sc_resetcal = 0; 5386 sc->sc_doresetcal = AH_TRUE; 5387 } 5388 } 5389 5390 /* Only call if we're doing a short/long cal, not for ANI calibration */ 5391 if (shortCal || longCal) { 5392 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 5393 if (longCal) { 5394 /* 5395 * Calibrate noise floor data again in case of change. 5396 */ 5397 ath_hal_process_noisefloor(ah); 5398 } 5399 } else { 5400 DPRINTF(sc, ATH_DEBUG_ANY, 5401 "%s: calibration of channel %u failed\n", 5402 __func__, sc->sc_curchan->ic_freq); 5403 sc->sc_stats.ast_per_calfail++; 5404 } 5405 if (shortCal) 5406 sc->sc_lastshortcal = ticks; 5407 } 5408 if (!isCalDone) { 5409 restart: 5410 /* 5411 * Use a shorter interval to potentially collect multiple 5412 * data samples required to complete calibration. Once 5413 * we're told the work is done we drop back to a longer 5414 * interval between requests. We're more aggressive doing 5415 * work when operating as an AP to improve operation right 5416 * after startup. 5417 */ 5418 sc->sc_lastshortcal = ticks; 5419 nextcal = ath_shortcalinterval*hz/1000; 5420 if (sc->sc_opmode != HAL_M_HOSTAP) 5421 nextcal *= 10; 5422 sc->sc_doresetcal = AH_TRUE; 5423 } else { 5424 /* nextcal should be the shortest time for next event */ 5425 nextcal = ath_longcalinterval*hz; 5426 if (sc->sc_lastcalreset == 0) 5427 sc->sc_lastcalreset = sc->sc_lastlongcal; 5428 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 5429 sc->sc_resetcal = 1; /* setup reset next trip */ 5430 sc->sc_doresetcal = AH_FALSE; 5431 } 5432 /* ANI calibration may occur more often than short/long/resetcal */ 5433 if (ath_anicalinterval > 0) 5434 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000); 5435 5436 if (nextcal != 0) { 5437 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 5438 __func__, nextcal, isCalDone ? "" : "!"); 5439 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc); 5440 } else { 5441 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 5442 __func__); 5443 /* NB: don't rearm timer */ 5444 } 5445 } 5446 5447 static void 5448 ath_scan_start(struct ieee80211com *ic) 5449 { 5450 struct ifnet *ifp = ic->ic_ifp; 5451 struct ath_softc *sc = ifp->if_softc; 5452 struct ath_hal *ah = sc->sc_ah; 5453 u_int32_t rfilt; 5454 5455 /* XXX calibration timer? */ 5456 5457 sc->sc_scanning = 1; 5458 sc->sc_syncbeacon = 0; 5459 rfilt = ath_calcrxfilter(sc); 5460 ath_hal_setrxfilter(ah, rfilt); 5461 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 5462 5463 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5464 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 5465 } 5466 5467 static void 5468 ath_scan_end(struct ieee80211com *ic) 5469 { 5470 struct ifnet *ifp = ic->ic_ifp; 5471 struct ath_softc *sc = ifp->if_softc; 5472 struct ath_hal *ah = sc->sc_ah; 5473 u_int32_t rfilt; 5474 5475 sc->sc_scanning = 0; 5476 rfilt = ath_calcrxfilter(sc); 5477 ath_hal_setrxfilter(ah, rfilt); 5478 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5479 5480 ath_hal_process_noisefloor(ah); 5481 5482 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5483 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5484 sc->sc_curaid); 5485 } 5486 5487 static void 5488 ath_set_channel(struct ieee80211com *ic) 5489 { 5490 struct ifnet *ifp = ic->ic_ifp; 5491 struct ath_softc *sc = ifp->if_softc; 5492 5493 (void) ath_chan_set(sc, ic->ic_curchan); 5494 /* 5495 * If we are returning to our bss channel then mark state 5496 * so the next recv'd beacon's tsf will be used to sync the 5497 * beacon timers. Note that since we only hear beacons in 5498 * sta/ibss mode this has no effect in other operating modes. 5499 */ 5500 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5501 sc->sc_syncbeacon = 1; 5502 } 5503 5504 /* 5505 * Walk the vap list and check if there any vap's in RUN state. 5506 */ 5507 static int 5508 ath_isanyrunningvaps(struct ieee80211vap *this) 5509 { 5510 struct ieee80211com *ic = this->iv_ic; 5511 struct ieee80211vap *vap; 5512 5513 IEEE80211_LOCK_ASSERT(ic); 5514 5515 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5516 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 5517 return 1; 5518 } 5519 return 0; 5520 } 5521 5522 static int 5523 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5524 { 5525 struct ieee80211com *ic = vap->iv_ic; 5526 struct ath_softc *sc = ic->ic_ifp->if_softc; 5527 struct ath_vap *avp = ATH_VAP(vap); 5528 struct ath_hal *ah = sc->sc_ah; 5529 struct ieee80211_node *ni = NULL; 5530 int i, error, stamode; 5531 u_int32_t rfilt; 5532 int csa_run_transition = 0; 5533 static const HAL_LED_STATE leds[] = { 5534 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5535 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5536 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5537 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5538 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5539 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5540 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5541 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5542 }; 5543 5544 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5545 ieee80211_state_name[vap->iv_state], 5546 ieee80211_state_name[nstate]); 5547 5548 if (vap->iv_state == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN) 5549 csa_run_transition = 1; 5550 5551 callout_drain(&sc->sc_cal_ch); 5552 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5553 5554 if (nstate == IEEE80211_S_SCAN) { 5555 /* 5556 * Scanning: turn off beacon miss and don't beacon. 5557 * Mark beacon state so when we reach RUN state we'll 5558 * [re]setup beacons. Unblock the task q thread so 5559 * deferred interrupt processing is done. 5560 */ 5561 ath_hal_intrset(ah, 5562 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5563 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5564 sc->sc_beacons = 0; 5565 taskqueue_unblock(sc->sc_tq); 5566 } 5567 5568 ni = vap->iv_bss; 5569 rfilt = ath_calcrxfilter(sc); 5570 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5571 vap->iv_opmode == IEEE80211_M_AHDEMO || 5572 vap->iv_opmode == IEEE80211_M_IBSS); 5573 if (stamode && nstate == IEEE80211_S_RUN) { 5574 sc->sc_curaid = ni->ni_associd; 5575 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5576 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5577 } 5578 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5579 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5580 ath_hal_setrxfilter(ah, rfilt); 5581 5582 /* XXX is this to restore keycache on resume? */ 5583 if (vap->iv_opmode != IEEE80211_M_STA && 5584 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5585 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5586 if (ath_hal_keyisvalid(ah, i)) 5587 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5588 } 5589 5590 /* 5591 * Invoke the parent method to do net80211 work. 5592 */ 5593 error = avp->av_newstate(vap, nstate, arg); 5594 if (error != 0) 5595 goto bad; 5596 5597 if (nstate == IEEE80211_S_RUN) { 5598 /* NB: collect bss node again, it may have changed */ 5599 ni = vap->iv_bss; 5600 5601 DPRINTF(sc, ATH_DEBUG_STATE, 5602 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5603 "capinfo 0x%04x chan %d\n", __func__, 5604 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5605 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5606 5607 switch (vap->iv_opmode) { 5608 #ifdef IEEE80211_SUPPORT_TDMA 5609 case IEEE80211_M_AHDEMO: 5610 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5611 break; 5612 /* fall thru... */ 5613 #endif 5614 case IEEE80211_M_HOSTAP: 5615 case IEEE80211_M_IBSS: 5616 case IEEE80211_M_MBSS: 5617 /* 5618 * Allocate and setup the beacon frame. 5619 * 5620 * Stop any previous beacon DMA. This may be 5621 * necessary, for example, when an ibss merge 5622 * causes reconfiguration; there will be a state 5623 * transition from RUN->RUN that means we may 5624 * be called with beacon transmission active. 5625 */ 5626 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5627 5628 error = ath_beacon_alloc(sc, ni); 5629 if (error != 0) 5630 goto bad; 5631 /* 5632 * If joining an adhoc network defer beacon timer 5633 * configuration to the next beacon frame so we 5634 * have a current TSF to use. Otherwise we're 5635 * starting an ibss/bss so there's no need to delay; 5636 * if this is the first vap moving to RUN state, then 5637 * beacon state needs to be [re]configured. 5638 */ 5639 if (vap->iv_opmode == IEEE80211_M_IBSS && 5640 ni->ni_tstamp.tsf != 0) { 5641 sc->sc_syncbeacon = 1; 5642 } else if (!sc->sc_beacons) { 5643 #ifdef IEEE80211_SUPPORT_TDMA 5644 if (vap->iv_caps & IEEE80211_C_TDMA) 5645 ath_tdma_config(sc, vap); 5646 else 5647 #endif 5648 ath_beacon_config(sc, vap); 5649 sc->sc_beacons = 1; 5650 } 5651 break; 5652 case IEEE80211_M_STA: 5653 /* 5654 * Defer beacon timer configuration to the next 5655 * beacon frame so we have a current TSF to use 5656 * (any TSF collected when scanning is likely old). 5657 * However if it's due to a CSA -> RUN transition, 5658 * force a beacon update so we pick up a lack of 5659 * beacons from an AP in CAC and thus force a 5660 * scan. 5661 */ 5662 sc->sc_syncbeacon = 1; 5663 if (csa_run_transition) 5664 ath_beacon_config(sc, vap); 5665 break; 5666 case IEEE80211_M_MONITOR: 5667 /* 5668 * Monitor mode vaps have only INIT->RUN and RUN->RUN 5669 * transitions so we must re-enable interrupts here to 5670 * handle the case of a single monitor mode vap. 5671 */ 5672 ath_hal_intrset(ah, sc->sc_imask); 5673 break; 5674 case IEEE80211_M_WDS: 5675 break; 5676 default: 5677 break; 5678 } 5679 /* 5680 * Let the hal process statistics collected during a 5681 * scan so it can provide calibrated noise floor data. 5682 */ 5683 ath_hal_process_noisefloor(ah); 5684 /* 5685 * Reset rssi stats; maybe not the best place... 5686 */ 5687 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5688 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5689 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5690 /* 5691 * Finally, start any timers and the task q thread 5692 * (in case we didn't go through SCAN state). 5693 */ 5694 if (ath_longcalinterval != 0) { 5695 /* start periodic recalibration timer */ 5696 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc); 5697 } else { 5698 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5699 "%s: calibration disabled\n", __func__); 5700 } 5701 taskqueue_unblock(sc->sc_tq); 5702 } else if (nstate == IEEE80211_S_INIT) { 5703 /* 5704 * If there are no vaps left in RUN state then 5705 * shutdown host/driver operation: 5706 * o disable interrupts 5707 * o disable the task queue thread 5708 * o mark beacon processing as stopped 5709 */ 5710 if (!ath_isanyrunningvaps(vap)) { 5711 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5712 /* disable interrupts */ 5713 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5714 taskqueue_block(sc->sc_tq); 5715 sc->sc_beacons = 0; 5716 } 5717 #ifdef IEEE80211_SUPPORT_TDMA 5718 ath_hal_setcca(ah, AH_TRUE); 5719 #endif 5720 } 5721 bad: 5722 return error; 5723 } 5724 5725 /* 5726 * Allocate a key cache slot to the station so we can 5727 * setup a mapping from key index to node. The key cache 5728 * slot is needed for managing antenna state and for 5729 * compression when stations do not use crypto. We do 5730 * it uniliaterally here; if crypto is employed this slot 5731 * will be reassigned. 5732 */ 5733 static void 5734 ath_setup_stationkey(struct ieee80211_node *ni) 5735 { 5736 struct ieee80211vap *vap = ni->ni_vap; 5737 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5738 ieee80211_keyix keyix, rxkeyix; 5739 5740 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5741 /* 5742 * Key cache is full; we'll fall back to doing 5743 * the more expensive lookup in software. Note 5744 * this also means no h/w compression. 5745 */ 5746 /* XXX msg+statistic */ 5747 } else { 5748 /* XXX locking? */ 5749 ni->ni_ucastkey.wk_keyix = keyix; 5750 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5751 /* NB: must mark device key to get called back on delete */ 5752 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 5753 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 5754 /* NB: this will create a pass-thru key entry */ 5755 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss); 5756 } 5757 } 5758 5759 /* 5760 * Setup driver-specific state for a newly associated node. 5761 * Note that we're called also on a re-associate, the isnew 5762 * param tells us if this is the first time or not. 5763 */ 5764 static void 5765 ath_newassoc(struct ieee80211_node *ni, int isnew) 5766 { 5767 struct ath_node *an = ATH_NODE(ni); 5768 struct ieee80211vap *vap = ni->ni_vap; 5769 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5770 const struct ieee80211_txparam *tp = ni->ni_txparms; 5771 5772 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 5773 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 5774 5775 ath_rate_newassoc(sc, an, isnew); 5776 if (isnew && 5777 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 5778 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5779 ath_setup_stationkey(ni); 5780 } 5781 5782 static int 5783 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 5784 int nchans, struct ieee80211_channel chans[]) 5785 { 5786 struct ath_softc *sc = ic->ic_ifp->if_softc; 5787 struct ath_hal *ah = sc->sc_ah; 5788 HAL_STATUS status; 5789 5790 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5791 "%s: rd %u cc %u location %c%s\n", 5792 __func__, reg->regdomain, reg->country, reg->location, 5793 reg->ecm ? " ecm" : ""); 5794 5795 status = ath_hal_set_channels(ah, chans, nchans, 5796 reg->country, reg->regdomain); 5797 if (status != HAL_OK) { 5798 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 5799 __func__, status); 5800 return EINVAL; /* XXX */ 5801 } 5802 5803 return 0; 5804 } 5805 5806 static void 5807 ath_getradiocaps(struct ieee80211com *ic, 5808 int maxchans, int *nchans, struct ieee80211_channel chans[]) 5809 { 5810 struct ath_softc *sc = ic->ic_ifp->if_softc; 5811 struct ath_hal *ah = sc->sc_ah; 5812 5813 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 5814 __func__, SKU_DEBUG, CTRY_DEFAULT); 5815 5816 /* XXX check return */ 5817 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 5818 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 5819 5820 } 5821 5822 static int 5823 ath_getchannels(struct ath_softc *sc) 5824 { 5825 struct ifnet *ifp = sc->sc_ifp; 5826 struct ieee80211com *ic = ifp->if_l2com; 5827 struct ath_hal *ah = sc->sc_ah; 5828 HAL_STATUS status; 5829 5830 /* 5831 * Collect channel set based on EEPROM contents. 5832 */ 5833 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 5834 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 5835 if (status != HAL_OK) { 5836 if_printf(ifp, "%s: unable to collect channel list from hal, " 5837 "status %d\n", __func__, status); 5838 return EINVAL; 5839 } 5840 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 5841 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 5842 /* XXX map Atheros sku's to net80211 SKU's */ 5843 /* XXX net80211 types too small */ 5844 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 5845 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 5846 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 5847 ic->ic_regdomain.isocc[1] = ' '; 5848 5849 ic->ic_regdomain.ecm = 1; 5850 ic->ic_regdomain.location = 'I'; 5851 5852 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5853 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 5854 __func__, sc->sc_eerd, sc->sc_eecc, 5855 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 5856 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 5857 return 0; 5858 } 5859 5860 static void 5861 ath_led_done(void *arg) 5862 { 5863 struct ath_softc *sc = arg; 5864 5865 sc->sc_blinking = 0; 5866 } 5867 5868 /* 5869 * Turn the LED off: flip the pin and then set a timer so no 5870 * update will happen for the specified duration. 5871 */ 5872 static void 5873 ath_led_off(void *arg) 5874 { 5875 struct ath_softc *sc = arg; 5876 5877 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5878 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 5879 } 5880 5881 /* 5882 * Blink the LED according to the specified on/off times. 5883 */ 5884 static void 5885 ath_led_blink(struct ath_softc *sc, int on, int off) 5886 { 5887 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 5888 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 5889 sc->sc_blinking = 1; 5890 sc->sc_ledoff = off; 5891 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 5892 } 5893 5894 static void 5895 ath_led_event(struct ath_softc *sc, int rix) 5896 { 5897 sc->sc_ledevent = ticks; /* time of last event */ 5898 if (sc->sc_blinking) /* don't interrupt active blink */ 5899 return; 5900 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff); 5901 } 5902 5903 static int 5904 ath_rate_setup(struct ath_softc *sc, u_int mode) 5905 { 5906 struct ath_hal *ah = sc->sc_ah; 5907 const HAL_RATE_TABLE *rt; 5908 5909 switch (mode) { 5910 case IEEE80211_MODE_11A: 5911 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5912 break; 5913 case IEEE80211_MODE_HALF: 5914 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 5915 break; 5916 case IEEE80211_MODE_QUARTER: 5917 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 5918 break; 5919 case IEEE80211_MODE_11B: 5920 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5921 break; 5922 case IEEE80211_MODE_11G: 5923 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5924 break; 5925 case IEEE80211_MODE_TURBO_A: 5926 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 5927 break; 5928 case IEEE80211_MODE_TURBO_G: 5929 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5930 break; 5931 case IEEE80211_MODE_STURBO_A: 5932 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5933 break; 5934 case IEEE80211_MODE_11NA: 5935 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 5936 break; 5937 case IEEE80211_MODE_11NG: 5938 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 5939 break; 5940 default: 5941 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5942 __func__, mode); 5943 return 0; 5944 } 5945 sc->sc_rates[mode] = rt; 5946 return (rt != NULL); 5947 } 5948 5949 static void 5950 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5951 { 5952 #define N(a) (sizeof(a)/sizeof(a[0])) 5953 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5954 static const struct { 5955 u_int rate; /* tx/rx 802.11 rate */ 5956 u_int16_t timeOn; /* LED on time (ms) */ 5957 u_int16_t timeOff; /* LED off time (ms) */ 5958 } blinkrates[] = { 5959 { 108, 40, 10 }, 5960 { 96, 44, 11 }, 5961 { 72, 50, 13 }, 5962 { 48, 57, 14 }, 5963 { 36, 67, 16 }, 5964 { 24, 80, 20 }, 5965 { 22, 100, 25 }, 5966 { 18, 133, 34 }, 5967 { 12, 160, 40 }, 5968 { 10, 200, 50 }, 5969 { 6, 240, 58 }, 5970 { 4, 267, 66 }, 5971 { 2, 400, 100 }, 5972 { 0, 500, 130 }, 5973 /* XXX half/quarter rates */ 5974 }; 5975 const HAL_RATE_TABLE *rt; 5976 int i, j; 5977 5978 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 5979 rt = sc->sc_rates[mode]; 5980 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 5981 for (i = 0; i < rt->rateCount; i++) { 5982 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 5983 if (rt->info[i].phy != IEEE80211_T_HT) 5984 sc->sc_rixmap[ieeerate] = i; 5985 else 5986 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 5987 } 5988 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 5989 for (i = 0; i < N(sc->sc_hwmap); i++) { 5990 if (i >= rt->rateCount) { 5991 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 5992 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 5993 continue; 5994 } 5995 sc->sc_hwmap[i].ieeerate = 5996 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 5997 if (rt->info[i].phy == IEEE80211_T_HT) 5998 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 5999 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6000 if (rt->info[i].shortPreamble || 6001 rt->info[i].phy == IEEE80211_T_OFDM) 6002 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6003 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 6004 for (j = 0; j < N(blinkrates)-1; j++) 6005 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6006 break; 6007 /* NB: this uses the last entry if the rate isn't found */ 6008 /* XXX beware of overlow */ 6009 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6010 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6011 } 6012 sc->sc_currates = rt; 6013 sc->sc_curmode = mode; 6014 /* 6015 * All protection frames are transmited at 2Mb/s for 6016 * 11g, otherwise at 1Mb/s. 6017 */ 6018 if (mode == IEEE80211_MODE_11G) 6019 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 6020 else 6021 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 6022 /* NB: caller is responsible for resetting rate control state */ 6023 #undef N 6024 } 6025 6026 static void 6027 ath_watchdog(void *arg) 6028 { 6029 struct ath_softc *sc = arg; 6030 int do_reset = 0; 6031 6032 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 6033 struct ifnet *ifp = sc->sc_ifp; 6034 uint32_t hangs; 6035 6036 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 6037 hangs != 0) { 6038 if_printf(ifp, "%s hang detected (0x%x)\n", 6039 hangs & 0xff ? "bb" : "mac", hangs); 6040 } else 6041 if_printf(ifp, "device timeout\n"); 6042 do_reset = 1; 6043 ifp->if_oerrors++; 6044 sc->sc_stats.ast_watchdog++; 6045 } 6046 6047 /* 6048 * We can't hold the lock across the ath_reset() call. 6049 */ 6050 if (do_reset) { 6051 ATH_UNLOCK(sc); 6052 ath_reset(sc->sc_ifp, ATH_RESET_NOLOSS); 6053 ATH_LOCK(sc); 6054 } 6055 6056 callout_schedule(&sc->sc_wd_ch, hz); 6057 } 6058 6059 #ifdef ATH_DIAGAPI 6060 /* 6061 * Diagnostic interface to the HAL. This is used by various 6062 * tools to do things like retrieve register contents for 6063 * debugging. The mechanism is intentionally opaque so that 6064 * it can change frequently w/o concern for compatiblity. 6065 */ 6066 static int 6067 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 6068 { 6069 struct ath_hal *ah = sc->sc_ah; 6070 u_int id = ad->ad_id & ATH_DIAG_ID; 6071 void *indata = NULL; 6072 void *outdata = NULL; 6073 u_int32_t insize = ad->ad_in_size; 6074 u_int32_t outsize = ad->ad_out_size; 6075 int error = 0; 6076 6077 if (ad->ad_id & ATH_DIAG_IN) { 6078 /* 6079 * Copy in data. 6080 */ 6081 indata = malloc(insize, M_TEMP, M_NOWAIT); 6082 if (indata == NULL) { 6083 error = ENOMEM; 6084 goto bad; 6085 } 6086 error = copyin(ad->ad_in_data, indata, insize); 6087 if (error) 6088 goto bad; 6089 } 6090 if (ad->ad_id & ATH_DIAG_DYN) { 6091 /* 6092 * Allocate a buffer for the results (otherwise the HAL 6093 * returns a pointer to a buffer where we can read the 6094 * results). Note that we depend on the HAL leaving this 6095 * pointer for us to use below in reclaiming the buffer; 6096 * may want to be more defensive. 6097 */ 6098 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 6099 if (outdata == NULL) { 6100 error = ENOMEM; 6101 goto bad; 6102 } 6103 } 6104 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 6105 if (outsize < ad->ad_out_size) 6106 ad->ad_out_size = outsize; 6107 if (outdata != NULL) 6108 error = copyout(outdata, ad->ad_out_data, 6109 ad->ad_out_size); 6110 } else { 6111 error = EINVAL; 6112 } 6113 bad: 6114 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 6115 free(indata, M_TEMP); 6116 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 6117 free(outdata, M_TEMP); 6118 return error; 6119 } 6120 #endif /* ATH_DIAGAPI */ 6121 6122 static int 6123 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 6124 { 6125 #define IS_RUNNING(ifp) \ 6126 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 6127 struct ath_softc *sc = ifp->if_softc; 6128 struct ieee80211com *ic = ifp->if_l2com; 6129 struct ifreq *ifr = (struct ifreq *)data; 6130 const HAL_RATE_TABLE *rt; 6131 int error = 0; 6132 6133 switch (cmd) { 6134 case SIOCSIFFLAGS: 6135 ATH_LOCK(sc); 6136 if (IS_RUNNING(ifp)) { 6137 /* 6138 * To avoid rescanning another access point, 6139 * do not call ath_init() here. Instead, 6140 * only reflect promisc mode settings. 6141 */ 6142 ath_mode_init(sc); 6143 } else if (ifp->if_flags & IFF_UP) { 6144 /* 6145 * Beware of being called during attach/detach 6146 * to reset promiscuous mode. In that case we 6147 * will still be marked UP but not RUNNING. 6148 * However trying to re-init the interface 6149 * is the wrong thing to do as we've already 6150 * torn down much of our state. There's 6151 * probably a better way to deal with this. 6152 */ 6153 if (!sc->sc_invalid) 6154 ath_init(sc); /* XXX lose error */ 6155 } else { 6156 ath_stop_locked(ifp); 6157 #ifdef notyet 6158 /* XXX must wakeup in places like ath_vap_delete */ 6159 if (!sc->sc_invalid) 6160 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 6161 #endif 6162 } 6163 ATH_UNLOCK(sc); 6164 break; 6165 case SIOCGIFMEDIA: 6166 case SIOCSIFMEDIA: 6167 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 6168 break; 6169 case SIOCGATHSTATS: 6170 /* NB: embed these numbers to get a consistent view */ 6171 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 6172 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 6173 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 6174 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 6175 #ifdef IEEE80211_SUPPORT_TDMA 6176 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 6177 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 6178 #endif 6179 rt = sc->sc_currates; 6180 sc->sc_stats.ast_tx_rate = 6181 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 6182 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT) 6183 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS; 6184 return copyout(&sc->sc_stats, 6185 ifr->ifr_data, sizeof (sc->sc_stats)); 6186 case SIOCZATHSTATS: 6187 error = priv_check(curthread, PRIV_DRIVER); 6188 if (error == 0) 6189 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 6190 break; 6191 #ifdef ATH_DIAGAPI 6192 case SIOCGATHDIAG: 6193 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 6194 break; 6195 case SIOCGATHPHYERR: 6196 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr); 6197 break; 6198 #endif 6199 case SIOCGIFADDR: 6200 error = ether_ioctl(ifp, cmd, data); 6201 break; 6202 default: 6203 error = EINVAL; 6204 break; 6205 } 6206 return error; 6207 #undef IS_RUNNING 6208 } 6209 6210 /* 6211 * Announce various information on device/driver attach. 6212 */ 6213 static void 6214 ath_announce(struct ath_softc *sc) 6215 { 6216 struct ifnet *ifp = sc->sc_ifp; 6217 struct ath_hal *ah = sc->sc_ah; 6218 6219 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 6220 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 6221 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 6222 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n", 6223 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev); 6224 if (bootverbose) { 6225 int i; 6226 for (i = 0; i <= WME_AC_VO; i++) { 6227 struct ath_txq *txq = sc->sc_ac2q[i]; 6228 if_printf(ifp, "Use hw queue %u for %s traffic\n", 6229 txq->axq_qnum, ieee80211_wme_acnames[i]); 6230 } 6231 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 6232 sc->sc_cabq->axq_qnum); 6233 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 6234 } 6235 if (ath_rxbuf != ATH_RXBUF) 6236 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 6237 if (ath_txbuf != ATH_TXBUF) 6238 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 6239 if (sc->sc_mcastkey && bootverbose) 6240 if_printf(ifp, "using multicast key search\n"); 6241 } 6242 6243 #ifdef IEEE80211_SUPPORT_TDMA 6244 static void 6245 ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval) 6246 { 6247 struct ath_hal *ah = sc->sc_ah; 6248 HAL_BEACON_TIMERS bt; 6249 6250 bt.bt_intval = bintval | HAL_BEACON_ENA; 6251 bt.bt_nexttbtt = nexttbtt; 6252 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep; 6253 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep; 6254 bt.bt_nextatim = nexttbtt+1; 6255 /* Enables TBTT, DBA, SWBA timers by default */ 6256 bt.bt_flags = 0; 6257 ath_hal_beaconsettimers(ah, &bt); 6258 } 6259 6260 /* 6261 * Calculate the beacon interval. This is periodic in the 6262 * superframe for the bss. We assume each station is configured 6263 * identically wrt transmit rate so the guard time we calculate 6264 * above will be the same on all stations. Note we need to 6265 * factor in the xmit time because the hardware will schedule 6266 * a frame for transmit if the start of the frame is within 6267 * the burst time. When we get hardware that properly kills 6268 * frames in the PCU we can reduce/eliminate the guard time. 6269 * 6270 * Roundup to 1024 is so we have 1 TU buffer in the guard time 6271 * to deal with the granularity of the nexttbtt timer. 11n MAC's 6272 * with 1us timer granularity should allow us to reduce/eliminate 6273 * this. 6274 */ 6275 static void 6276 ath_tdma_bintvalsetup(struct ath_softc *sc, 6277 const struct ieee80211_tdma_state *tdma) 6278 { 6279 /* copy from vap state (XXX check all vaps have same value?) */ 6280 sc->sc_tdmaslotlen = tdma->tdma_slotlen; 6281 6282 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) * 6283 tdma->tdma_slotcnt, 1024); 6284 sc->sc_tdmabintval >>= 10; /* TSF -> TU */ 6285 if (sc->sc_tdmabintval & 1) 6286 sc->sc_tdmabintval++; 6287 6288 if (tdma->tdma_slot == 0) { 6289 /* 6290 * Only slot 0 beacons; other slots respond. 6291 */ 6292 sc->sc_imask |= HAL_INT_SWBA; 6293 sc->sc_tdmaswba = 0; /* beacon immediately */ 6294 } else { 6295 /* XXX all vaps must be slot 0 or slot !0 */ 6296 sc->sc_imask &= ~HAL_INT_SWBA; 6297 } 6298 } 6299 6300 /* 6301 * Max 802.11 overhead. This assumes no 4-address frames and 6302 * the encapsulation done by ieee80211_encap (llc). We also 6303 * include potential crypto overhead. 6304 */ 6305 #define IEEE80211_MAXOVERHEAD \ 6306 (sizeof(struct ieee80211_qosframe) \ 6307 + sizeof(struct llc) \ 6308 + IEEE80211_ADDR_LEN \ 6309 + IEEE80211_WEP_IVLEN \ 6310 + IEEE80211_WEP_KIDLEN \ 6311 + IEEE80211_WEP_CRCLEN \ 6312 + IEEE80211_WEP_MICLEN \ 6313 + IEEE80211_CRC_LEN) 6314 6315 /* 6316 * Setup initially for tdma operation. Start the beacon 6317 * timers and enable SWBA if we are slot 0. Otherwise 6318 * we wait for slot 0 to arrive so we can sync up before 6319 * starting to transmit. 6320 */ 6321 static void 6322 ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap) 6323 { 6324 struct ath_hal *ah = sc->sc_ah; 6325 struct ifnet *ifp = sc->sc_ifp; 6326 struct ieee80211com *ic = ifp->if_l2com; 6327 const struct ieee80211_txparam *tp; 6328 const struct ieee80211_tdma_state *tdma = NULL; 6329 int rix; 6330 6331 if (vap == NULL) { 6332 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 6333 if (vap == NULL) { 6334 if_printf(ifp, "%s: no vaps?\n", __func__); 6335 return; 6336 } 6337 } 6338 tp = vap->iv_bss->ni_txparms; 6339 /* 6340 * Calculate the guard time for each slot. This is the 6341 * time to send a maximal-size frame according to the 6342 * fixed/lowest transmit rate. Note that the interface 6343 * mtu does not include the 802.11 overhead so we must 6344 * tack that on (ath_hal_computetxtime includes the 6345 * preamble and plcp in it's calculation). 6346 */ 6347 tdma = vap->iv_tdma; 6348 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 6349 rix = ath_tx_findrix(sc, tp->ucastrate); 6350 else 6351 rix = ath_tx_findrix(sc, tp->mcastrate); 6352 /* XXX short preamble assumed */ 6353 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates, 6354 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE); 6355 6356 ath_hal_intrset(ah, 0); 6357 6358 ath_beaconq_config(sc); /* setup h/w beacon q */ 6359 if (sc->sc_setcca) 6360 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */ 6361 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */ 6362 ath_tdma_settimers(sc, sc->sc_tdmabintval, 6363 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF); 6364 sc->sc_syncbeacon = 0; 6365 6366 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER; 6367 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER; 6368 6369 ath_hal_intrset(ah, sc->sc_imask); 6370 6371 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u " 6372 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__, 6373 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt, 6374 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval, 6375 sc->sc_tdmadbaprep); 6376 } 6377 6378 /* 6379 * Update tdma operation. Called from the 802.11 layer 6380 * when a beacon is received from the TDMA station operating 6381 * in the slot immediately preceding us in the bss. Use 6382 * the rx timestamp for the beacon frame to update our 6383 * beacon timers so we follow their schedule. Note that 6384 * by using the rx timestamp we implicitly include the 6385 * propagation delay in our schedule. 6386 */ 6387 static void 6388 ath_tdma_update(struct ieee80211_node *ni, 6389 const struct ieee80211_tdma_param *tdma, int changed) 6390 { 6391 #define TSF_TO_TU(_h,_l) \ 6392 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 6393 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 6394 struct ieee80211vap *vap = ni->ni_vap; 6395 struct ieee80211com *ic = ni->ni_ic; 6396 struct ath_softc *sc = ic->ic_ifp->if_softc; 6397 struct ath_hal *ah = sc->sc_ah; 6398 const HAL_RATE_TABLE *rt = sc->sc_currates; 6399 u_int64_t tsf, rstamp, nextslot, nexttbtt; 6400 u_int32_t txtime, nextslottu; 6401 int32_t tudelta, tsfdelta; 6402 const struct ath_rx_status *rs; 6403 int rix; 6404 6405 sc->sc_stats.ast_tdma_update++; 6406 6407 /* 6408 * Check for and adopt configuration changes. 6409 */ 6410 if (changed != 0) { 6411 const struct ieee80211_tdma_state *ts = vap->iv_tdma; 6412 6413 ath_tdma_bintvalsetup(sc, ts); 6414 if (changed & TDMA_UPDATE_SLOTLEN) 6415 ath_wme_update(ic); 6416 6417 DPRINTF(sc, ATH_DEBUG_TDMA, 6418 "%s: adopt slot %u slotcnt %u slotlen %u us " 6419 "bintval %u TU\n", __func__, 6420 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen, 6421 sc->sc_tdmabintval); 6422 6423 /* XXX right? */ 6424 ath_hal_intrset(ah, sc->sc_imask); 6425 /* NB: beacon timers programmed below */ 6426 } 6427 6428 /* extend rx timestamp to 64 bits */ 6429 rs = sc->sc_lastrs; 6430 tsf = ath_hal_gettsf64(ah); 6431 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 6432 /* 6433 * The rx timestamp is set by the hardware on completing 6434 * reception (at the point where the rx descriptor is DMA'd 6435 * to the host). To find the start of our next slot we 6436 * must adjust this time by the time required to send 6437 * the packet just received. 6438 */ 6439 rix = rt->rateCodeToIndex[rs->rs_rate]; 6440 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix, 6441 rt->info[rix].shortPreamble); 6442 /* NB: << 9 is to cvt to TU and /2 */ 6443 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9); 6444 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD; 6445 6446 /* 6447 * Retrieve the hardware NextTBTT in usecs 6448 * and calculate the difference between what the 6449 * other station thinks and what we have programmed. This 6450 * lets us figure how to adjust our timers to match. The 6451 * adjustments are done by pulling the TSF forward and possibly 6452 * rewriting the beacon timers. 6453 */ 6454 nexttbtt = ath_hal_getnexttbtt(ah); 6455 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD + 1)) - nexttbtt); 6456 6457 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 6458 "tsfdelta %d avg +%d/-%d\n", tsfdelta, 6459 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam)); 6460 6461 if (tsfdelta < 0) { 6462 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 6463 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta); 6464 tsfdelta = -tsfdelta % 1024; 6465 nextslottu++; 6466 } else if (tsfdelta > 0) { 6467 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta); 6468 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 6469 tsfdelta = 1024 - (tsfdelta % 1024); 6470 nextslottu++; 6471 } else { 6472 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 6473 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 6474 } 6475 tudelta = nextslottu - TSF_TO_TU(nexttbtt >> 32, nexttbtt); 6476 6477 /* 6478 * Copy sender's timetstamp into tdma ie so they can 6479 * calculate roundtrip time. We submit a beacon frame 6480 * below after any timer adjustment. The frame goes out 6481 * at the next TBTT so the sender can calculate the 6482 * roundtrip by inspecting the tdma ie in our beacon frame. 6483 * 6484 * NB: This tstamp is subtlely preserved when 6485 * IEEE80211_BEACON_TDMA is marked (e.g. when the 6486 * slot position changes) because ieee80211_add_tdma 6487 * skips over the data. 6488 */ 6489 memcpy(ATH_VAP(vap)->av_boff.bo_tdma + 6490 __offsetof(struct ieee80211_tdma_param, tdma_tstamp), 6491 &ni->ni_tstamp.data, 8); 6492 #if 0 6493 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 6494 "tsf %llu nextslot %llu (%d, %d) nextslottu %u nexttbtt %llu (%d)\n", 6495 (unsigned long long) tsf, (unsigned long long) nextslot, 6496 (int)(nextslot - tsf), tsfdelta, nextslottu, nexttbtt, tudelta); 6497 #endif 6498 /* 6499 * Adjust the beacon timers only when pulling them forward 6500 * or when going back by less than the beacon interval. 6501 * Negative jumps larger than the beacon interval seem to 6502 * cause the timers to stop and generally cause instability. 6503 * This basically filters out jumps due to missed beacons. 6504 */ 6505 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) { 6506 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval); 6507 sc->sc_stats.ast_tdma_timers++; 6508 } 6509 if (tsfdelta > 0) { 6510 ath_hal_adjusttsf(ah, tsfdelta); 6511 sc->sc_stats.ast_tdma_tsf++; 6512 } 6513 ath_tdma_beacon_send(sc, vap); /* prepare response */ 6514 #undef TU_TO_TSF 6515 #undef TSF_TO_TU 6516 } 6517 6518 /* 6519 * Transmit a beacon frame at SWBA. Dynamic updates 6520 * to the frame contents are done as needed. 6521 */ 6522 static void 6523 ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap) 6524 { 6525 struct ath_hal *ah = sc->sc_ah; 6526 struct ath_buf *bf; 6527 int otherant; 6528 6529 /* 6530 * Check if the previous beacon has gone out. If 6531 * not don't try to post another, skip this period 6532 * and wait for the next. Missed beacons indicate 6533 * a problem and should not occur. If we miss too 6534 * many consecutive beacons reset the device. 6535 */ 6536 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 6537 sc->sc_bmisscount++; 6538 DPRINTF(sc, ATH_DEBUG_BEACON, 6539 "%s: missed %u consecutive beacons\n", 6540 __func__, sc->sc_bmisscount); 6541 if (sc->sc_bmisscount >= ath_bstuck_threshold) 6542 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 6543 return; 6544 } 6545 if (sc->sc_bmisscount != 0) { 6546 DPRINTF(sc, ATH_DEBUG_BEACON, 6547 "%s: resume beacon xmit after %u misses\n", 6548 __func__, sc->sc_bmisscount); 6549 sc->sc_bmisscount = 0; 6550 } 6551 6552 /* 6553 * Check recent per-antenna transmit statistics and flip 6554 * the default antenna if noticeably more frames went out 6555 * on the non-default antenna. 6556 * XXX assumes 2 anntenae 6557 */ 6558 if (!sc->sc_diversity) { 6559 otherant = sc->sc_defant & 1 ? 2 : 1; 6560 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 6561 ath_setdefantenna(sc, otherant); 6562 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 6563 } 6564 6565 bf = ath_beacon_generate(sc, vap); 6566 if (bf != NULL) { 6567 /* 6568 * Stop any current dma and put the new frame on the queue. 6569 * This should never fail since we check above that no frames 6570 * are still pending on the queue. 6571 */ 6572 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 6573 DPRINTF(sc, ATH_DEBUG_ANY, 6574 "%s: beacon queue %u did not stop?\n", 6575 __func__, sc->sc_bhalq); 6576 /* NB: the HAL still stops DMA, so proceed */ 6577 } 6578 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 6579 ath_hal_txstart(ah, sc->sc_bhalq); 6580 6581 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */ 6582 6583 /* 6584 * Record local TSF for our last send for use 6585 * in arbitrating slot collisions. 6586 */ 6587 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah); 6588 } 6589 } 6590 #endif /* IEEE80211_SUPPORT_TDMA */ 6591 6592 static void 6593 ath_dfs_tasklet(void *p, int npending) 6594 { 6595 struct ath_softc *sc = (struct ath_softc *) p; 6596 struct ifnet *ifp = sc->sc_ifp; 6597 struct ieee80211com *ic = ifp->if_l2com; 6598 6599 /* 6600 * If previous processing has found a radar event, 6601 * signal this to the net80211 layer to begin DFS 6602 * processing. 6603 */ 6604 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) { 6605 /* DFS event found, initiate channel change */ 6606 ieee80211_dfs_notify_radar(ic, sc->sc_curchan); 6607 } 6608 } 6609 6610 MODULE_VERSION(if_ath, 1); 6611 MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */ 6612