1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sysctl.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/errno.h> 54 #include <sys/callout.h> 55 #include <sys/bus.h> 56 #include <sys/endian.h> 57 #include <sys/kthread.h> 58 #include <sys/taskqueue.h> 59 60 #include <machine/bus.h> 61 62 #include <net/if.h> 63 #include <net/if_dl.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 #include <net/if_arp.h> 67 #include <net/ethernet.h> 68 #include <net/if_llc.h> 69 70 #include <net80211/ieee80211_var.h> 71 72 #include <net/bpf.h> 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/if_ether.h> 77 #endif 78 79 #include <dev/ath/if_athvar.h> 80 #include <contrib/dev/ath/ah_desc.h> 81 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 82 83 #ifdef ATH_TX99_DIAG 84 #include <dev/ath/ath_tx99/ath_tx99.h> 85 #endif 86 87 /* 88 * We require a HAL w/ the changes for split tx/rx MIC. 89 */ 90 CTASSERT(HAL_ABI_VERSION > 0x06052200); 91 92 /* 93 * ATH_BCBUF determines the number of vap's that can transmit 94 * beacons and also (currently) the number of vap's that can 95 * have unique mac addresses/bssid. When staggering beacons 96 * 4 is probably a good max as otherwise the beacons become 97 * very closely spaced and there is limited time for cab q traffic 98 * to go out. You can burst beacons instead but that is not good 99 * for stations in power save and at some point you really want 100 * another radio (and channel). 101 * 102 * The limit on the number of mac addresses is tied to our use of 103 * the U/L bit and tracking addresses in a byte; it would be 104 * worthwhile to allow more for applications like proxy sta. 105 */ 106 CTASSERT(ATH_BCBUF <= 8); 107 108 /* unaligned little endian access */ 109 #define LE_READ_2(p) \ 110 ((u_int16_t) \ 111 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 112 #define LE_READ_4(p) \ 113 ((u_int32_t) \ 114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 115 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 116 117 enum { 118 ATH_LED_TX, 119 ATH_LED_RX, 120 ATH_LED_POLL, 121 }; 122 123 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 124 const char name[IFNAMSIZ], int unit, int opmode, 125 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 126 const uint8_t mac[IEEE80211_ADDR_LEN]); 127 static void ath_vap_delete(struct ieee80211vap *); 128 static void ath_init(void *); 129 static void ath_stop_locked(struct ifnet *); 130 static void ath_stop(struct ifnet *); 131 static void ath_start(struct ifnet *); 132 static int ath_reset(struct ifnet *); 133 static int ath_reset_vap(struct ieee80211vap *, u_long); 134 static int ath_media_change(struct ifnet *); 135 static void ath_watchdog(struct ifnet *); 136 static int ath_ioctl(struct ifnet *, u_long, caddr_t); 137 static void ath_fatal_proc(void *, int); 138 static void ath_rxorn_proc(void *, int); 139 static void ath_bmiss_vap(struct ieee80211vap *); 140 static void ath_bmiss_proc(void *, int); 141 static int ath_key_alloc(struct ieee80211vap *, 142 const struct ieee80211_key *, 143 ieee80211_keyix *, ieee80211_keyix *); 144 static int ath_key_delete(struct ieee80211vap *, 145 const struct ieee80211_key *); 146 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *, 147 const u_int8_t mac[IEEE80211_ADDR_LEN]); 148 static void ath_key_update_begin(struct ieee80211vap *); 149 static void ath_key_update_end(struct ieee80211vap *); 150 static void ath_update_mcast(struct ifnet *); 151 static void ath_update_promisc(struct ifnet *); 152 static void ath_mode_init(struct ath_softc *); 153 static void ath_setslottime(struct ath_softc *); 154 static void ath_updateslot(struct ifnet *); 155 static int ath_beaconq_setup(struct ath_hal *); 156 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 157 static void ath_beacon_update(struct ieee80211vap *, int item); 158 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 159 static void ath_beacon_proc(void *, int); 160 static struct ath_buf *ath_beacon_generate(struct ath_softc *, 161 struct ieee80211vap *); 162 static void ath_bstuck_proc(void *, int); 163 static void ath_beacon_return(struct ath_softc *, struct ath_buf *); 164 static void ath_beacon_free(struct ath_softc *); 165 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *); 166 static void ath_descdma_cleanup(struct ath_softc *sc, 167 struct ath_descdma *, ath_bufhead *); 168 static int ath_desc_alloc(struct ath_softc *); 169 static void ath_desc_free(struct ath_softc *); 170 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 171 static void ath_node_free(struct ieee80211_node *); 172 static void ath_node_getsignal(const struct ieee80211_node *, 173 int8_t *, int8_t *); 174 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 175 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 176 int subtype, int rssi, int noise, u_int32_t rstamp); 177 static void ath_setdefantenna(struct ath_softc *, u_int); 178 static void ath_rx_proc(void *, int); 179 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 180 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 181 static int ath_tx_setup(struct ath_softc *, int, int); 182 static int ath_wme_update(struct ieee80211com *); 183 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 184 static void ath_tx_cleanup(struct ath_softc *); 185 static void ath_freetx(struct mbuf *); 186 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 187 struct ath_buf *, struct mbuf *); 188 static void ath_tx_proc_q0(void *, int); 189 static void ath_tx_proc_q0123(void *, int); 190 static void ath_tx_proc(void *, int); 191 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *); 192 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 193 static void ath_draintxq(struct ath_softc *); 194 static void ath_stoprecv(struct ath_softc *); 195 static int ath_startrecv(struct ath_softc *); 196 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 197 static void ath_scan_start(struct ieee80211com *); 198 static void ath_scan_end(struct ieee80211com *); 199 static void ath_set_channel(struct ieee80211com *); 200 static void ath_calibrate(void *); 201 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 202 static void ath_setup_stationkey(struct ieee80211_node *); 203 static void ath_newassoc(struct ieee80211_node *, int); 204 static int ath_setregdomain(struct ieee80211com *, 205 struct ieee80211_regdomain *, int, 206 struct ieee80211_channel []); 207 static void ath_getradiocaps(struct ieee80211com *, int *, 208 struct ieee80211_channel []); 209 static int ath_getchannels(struct ath_softc *); 210 static void ath_led_event(struct ath_softc *, int); 211 212 static int ath_rate_setup(struct ath_softc *, u_int mode); 213 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 214 215 static void ath_sysctlattach(struct ath_softc *); 216 static int ath_raw_xmit(struct ieee80211_node *, 217 struct mbuf *, const struct ieee80211_bpf_params *); 218 static void ath_bpfattach(struct ath_softc *); 219 static void ath_announce(struct ath_softc *); 220 221 SYSCTL_DECL(_hw_ath); 222 223 /* XXX validate sysctl values */ 224 static int ath_calinterval = 30; /* calibrate every 30 secs */ 225 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 226 0, "chip calibration interval (secs)"); 227 228 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 229 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 230 0, "rx buffers allocated"); 231 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 232 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 233 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 234 0, "tx buffers allocated"); 235 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 236 237 #ifdef ATH_DEBUG 238 static int ath_debug = 0; 239 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 240 0, "control debugging printfs"); 241 TUNABLE_INT("hw.ath.debug", &ath_debug); 242 enum { 243 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 244 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 245 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 246 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 247 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 248 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 249 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 250 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 251 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 252 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 253 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 254 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 255 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 256 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 257 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 258 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 259 ATH_DEBUG_NODE = 0x00080000, /* node management */ 260 ATH_DEBUG_LED = 0x00100000, /* led management */ 261 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 262 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 263 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 264 ATH_DEBUG_ANY = 0xffffffff 265 }; 266 #define IFF_DUMPPKTS(sc, m) \ 267 ((sc->sc_debug & (m)) || \ 268 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 269 #define DPRINTF(sc, m, fmt, ...) do { \ 270 if (sc->sc_debug & (m)) \ 271 printf(fmt, __VA_ARGS__); \ 272 } while (0) 273 #define KEYPRINTF(sc, ix, hk, mac) do { \ 274 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 275 ath_keyprint(sc, __func__, ix, hk, mac); \ 276 } while (0) 277 static void ath_printrxbuf(const struct ath_buf *bf, u_int ix, int); 278 static void ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done); 279 #else 280 #define IFF_DUMPPKTS(sc, m) \ 281 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 282 #define DPRINTF(sc, m, fmt, ...) do { \ 283 (void) sc; \ 284 } while (0) 285 #define KEYPRINTF(sc, k, ix, mac) do { \ 286 (void) sc; \ 287 } while (0) 288 #endif 289 290 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 291 292 int 293 ath_attach(u_int16_t devid, struct ath_softc *sc) 294 { 295 struct ifnet *ifp; 296 struct ieee80211com *ic; 297 struct ath_hal *ah = NULL; 298 HAL_STATUS status; 299 int error = 0, i; 300 301 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 302 303 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 304 if (ifp == NULL) { 305 device_printf(sc->sc_dev, "can not if_alloc()\n"); 306 error = ENOSPC; 307 goto bad; 308 } 309 ic = ifp->if_l2com; 310 311 /* set these up early for if_printf use */ 312 if_initname(ifp, device_get_name(sc->sc_dev), 313 device_get_unit(sc->sc_dev)); 314 315 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 316 if (ah == NULL) { 317 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 318 status); 319 error = ENXIO; 320 goto bad; 321 } 322 if (ah->ah_abi != HAL_ABI_VERSION) { 323 if_printf(ifp, "HAL ABI mismatch detected " 324 "(HAL:0x%x != driver:0x%x)\n", 325 ah->ah_abi, HAL_ABI_VERSION); 326 error = ENXIO; 327 goto bad; 328 } 329 sc->sc_ah = ah; 330 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 331 332 /* 333 * Check if the MAC has multi-rate retry support. 334 * We do this by trying to setup a fake extended 335 * descriptor. MAC's that don't have support will 336 * return false w/o doing anything. MAC's that do 337 * support it will return true w/o doing anything. 338 */ 339 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 340 341 /* 342 * Check if the device has hardware counters for PHY 343 * errors. If so we need to enable the MIB interrupt 344 * so we can act on stat triggers. 345 */ 346 if (ath_hal_hwphycounters(ah)) 347 sc->sc_needmib = 1; 348 349 /* 350 * Get the hardware key cache size. 351 */ 352 sc->sc_keymax = ath_hal_keycachesize(ah); 353 if (sc->sc_keymax > ATH_KEYMAX) { 354 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 355 ATH_KEYMAX, sc->sc_keymax); 356 sc->sc_keymax = ATH_KEYMAX; 357 } 358 /* 359 * Reset the key cache since some parts do not 360 * reset the contents on initial power up. 361 */ 362 for (i = 0; i < sc->sc_keymax; i++) 363 ath_hal_keyreset(ah, i); 364 365 /* 366 * Collect the default channel list. 367 */ 368 error = ath_getchannels(sc); 369 if (error != 0) 370 goto bad; 371 372 /* 373 * Setup rate tables for all potential media types. 374 */ 375 ath_rate_setup(sc, IEEE80211_MODE_11A); 376 ath_rate_setup(sc, IEEE80211_MODE_11B); 377 ath_rate_setup(sc, IEEE80211_MODE_11G); 378 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 379 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 380 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 381 ath_rate_setup(sc, IEEE80211_MODE_11NA); 382 ath_rate_setup(sc, IEEE80211_MODE_11NG); 383 ath_rate_setup(sc, IEEE80211_MODE_HALF); 384 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 385 386 /* NB: setup here so ath_rate_update is happy */ 387 ath_setcurmode(sc, IEEE80211_MODE_11A); 388 389 /* 390 * Allocate tx+rx descriptors and populate the lists. 391 */ 392 error = ath_desc_alloc(sc); 393 if (error != 0) { 394 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 395 goto bad; 396 } 397 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 398 399 ATH_TXBUF_LOCK_INIT(sc); 400 401 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT, 402 taskqueue_thread_enqueue, &sc->sc_tq); 403 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 404 "%s taskq", ifp->if_xname); 405 406 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 407 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 408 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 409 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc); 410 411 /* 412 * Allocate hardware transmit queues: one queue for 413 * beacon frames and one data queue for each QoS 414 * priority. Note that the hal handles reseting 415 * these queues at the needed time. 416 * 417 * XXX PS-Poll 418 */ 419 sc->sc_bhalq = ath_beaconq_setup(ah); 420 if (sc->sc_bhalq == (u_int) -1) { 421 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 422 error = EIO; 423 goto bad2; 424 } 425 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 426 if (sc->sc_cabq == NULL) { 427 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 428 error = EIO; 429 goto bad2; 430 } 431 /* NB: insure BK queue is the lowest priority h/w queue */ 432 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 433 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 434 ieee80211_wme_acnames[WME_AC_BK]); 435 error = EIO; 436 goto bad2; 437 } 438 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 439 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 440 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 441 /* 442 * Not enough hardware tx queues to properly do WME; 443 * just punt and assign them all to the same h/w queue. 444 * We could do a better job of this if, for example, 445 * we allocate queues when we switch from station to 446 * AP mode. 447 */ 448 if (sc->sc_ac2q[WME_AC_VI] != NULL) 449 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 450 if (sc->sc_ac2q[WME_AC_BE] != NULL) 451 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 452 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 453 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 454 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 455 } 456 457 /* 458 * Special case certain configurations. Note the 459 * CAB queue is handled by these specially so don't 460 * include them when checking the txq setup mask. 461 */ 462 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 463 case 0x01: 464 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 465 break; 466 case 0x0f: 467 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 468 break; 469 default: 470 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 471 break; 472 } 473 474 /* 475 * Setup rate control. Some rate control modules 476 * call back to change the anntena state so expose 477 * the necessary entry points. 478 * XXX maybe belongs in struct ath_ratectrl? 479 */ 480 sc->sc_setdefantenna = ath_setdefantenna; 481 sc->sc_rc = ath_rate_attach(sc); 482 if (sc->sc_rc == NULL) { 483 error = EIO; 484 goto bad2; 485 } 486 487 sc->sc_blinking = 0; 488 sc->sc_ledstate = 1; 489 sc->sc_ledon = 0; /* low true */ 490 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 491 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 492 /* 493 * Auto-enable soft led processing for IBM cards and for 494 * 5211 minipci cards. Users can also manually enable/disable 495 * support with a sysctl. 496 */ 497 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 498 if (sc->sc_softled) { 499 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 500 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 501 } 502 503 ifp->if_softc = sc; 504 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 505 ifp->if_start = ath_start; 506 ifp->if_watchdog = ath_watchdog; 507 ifp->if_ioctl = ath_ioctl; 508 ifp->if_init = ath_init; 509 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 510 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 511 IFQ_SET_READY(&ifp->if_snd); 512 513 ic->ic_ifp = ifp; 514 /* XXX not right but it's not used anywhere important */ 515 ic->ic_phytype = IEEE80211_T_OFDM; 516 ic->ic_opmode = IEEE80211_M_STA; 517 ic->ic_caps = 518 IEEE80211_C_STA /* station mode */ 519 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 520 | IEEE80211_C_HOSTAP /* hostap mode */ 521 | IEEE80211_C_MONITOR /* monitor mode */ 522 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 523 | IEEE80211_C_WDS /* 4-address traffic works */ 524 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 525 | IEEE80211_C_SHSLOT /* short slot time supported */ 526 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 527 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 528 | IEEE80211_C_TXFRAG /* handle tx frags */ 529 ; 530 /* 531 * Query the hal to figure out h/w crypto support. 532 */ 533 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 534 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 535 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 536 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 537 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 538 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 539 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 540 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 541 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 542 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 543 /* 544 * Check if h/w does the MIC and/or whether the 545 * separate key cache entries are required to 546 * handle both tx+rx MIC keys. 547 */ 548 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 549 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 550 /* 551 * If the h/w supports storing tx+rx MIC keys 552 * in one cache slot automatically enable use. 553 */ 554 if (ath_hal_hastkipsplit(ah) || 555 !ath_hal_settkipsplit(ah, AH_FALSE)) 556 sc->sc_splitmic = 1; 557 /* 558 * If the h/w can do TKIP MIC together with WME then 559 * we use it; otherwise we force the MIC to be done 560 * in software by the net80211 layer. 561 */ 562 if (ath_hal_haswmetkipmic(ah)) 563 sc->sc_wmetkipmic = 1; 564 } 565 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 566 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 567 /* 568 * Mark key cache slots associated with global keys 569 * as in use. If we knew TKIP was not to be used we 570 * could leave the +32, +64, and +32+64 slots free. 571 */ 572 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 573 setbit(sc->sc_keymap, i); 574 setbit(sc->sc_keymap, i+64); 575 if (sc->sc_splitmic) { 576 setbit(sc->sc_keymap, i+32); 577 setbit(sc->sc_keymap, i+32+64); 578 } 579 } 580 /* 581 * TPC support can be done either with a global cap or 582 * per-packet support. The latter is not available on 583 * all parts. We're a bit pedantic here as all parts 584 * support a global cap. 585 */ 586 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 587 ic->ic_caps |= IEEE80211_C_TXPMGT; 588 589 /* 590 * Mark WME capability only if we have sufficient 591 * hardware queues to do proper priority scheduling. 592 */ 593 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 594 ic->ic_caps |= IEEE80211_C_WME; 595 /* 596 * Check for misc other capabilities. 597 */ 598 if (ath_hal_hasbursting(ah)) 599 ic->ic_caps |= IEEE80211_C_BURST; 600 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 601 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 602 if (ath_hal_hasfastframes(ah)) 603 ic->ic_caps |= IEEE80211_C_FF; 604 if (ath_hal_getwirelessmodes(ah, ic->ic_regdomain.country) & (HAL_MODE_108G|HAL_MODE_TURBO)) 605 ic->ic_caps |= IEEE80211_C_TURBOP; 606 607 /* 608 * Indicate we need the 802.11 header padded to a 609 * 32-bit boundary for 4-address and QoS frames. 610 */ 611 ic->ic_flags |= IEEE80211_F_DATAPAD; 612 613 /* 614 * Query the hal about antenna support. 615 */ 616 sc->sc_defant = ath_hal_getdefantenna(ah); 617 618 /* 619 * Not all chips have the VEOL support we want to 620 * use with IBSS beacons; check here for it. 621 */ 622 sc->sc_hasveol = ath_hal_hasveol(ah); 623 624 /* get mac address from hardware */ 625 ath_hal_getmac(ah, ic->ic_myaddr); 626 if (sc->sc_hasbmask) 627 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 628 629 /* NB: used to size node table key mapping array */ 630 ic->ic_max_keyix = sc->sc_keymax; 631 /* call MI attach routine. */ 632 ieee80211_ifattach(ic); 633 ic->ic_setregdomain = ath_setregdomain; 634 ic->ic_getradiocaps = ath_getradiocaps; 635 sc->sc_opmode = HAL_M_STA; 636 637 /* override default methods */ 638 ic->ic_newassoc = ath_newassoc; 639 ic->ic_updateslot = ath_updateslot; 640 ic->ic_wme.wme_update = ath_wme_update; 641 ic->ic_vap_create = ath_vap_create; 642 ic->ic_vap_delete = ath_vap_delete; 643 ic->ic_raw_xmit = ath_raw_xmit; 644 ic->ic_update_mcast = ath_update_mcast; 645 ic->ic_update_promisc = ath_update_promisc; 646 ic->ic_node_alloc = ath_node_alloc; 647 sc->sc_node_free = ic->ic_node_free; 648 ic->ic_node_free = ath_node_free; 649 ic->ic_node_getsignal = ath_node_getsignal; 650 ic->ic_scan_start = ath_scan_start; 651 ic->ic_scan_end = ath_scan_end; 652 ic->ic_set_channel = ath_set_channel; 653 654 ath_bpfattach(sc); 655 /* 656 * Setup dynamic sysctl's now that country code and 657 * regdomain are available from the hal. 658 */ 659 ath_sysctlattach(sc); 660 661 if (bootverbose) 662 ieee80211_announce(ic); 663 ath_announce(sc); 664 return 0; 665 bad2: 666 ath_tx_cleanup(sc); 667 ath_desc_free(sc); 668 bad: 669 if (ah) 670 ath_hal_detach(ah); 671 if (ifp != NULL) 672 if_free(ifp); 673 sc->sc_invalid = 1; 674 return error; 675 } 676 677 int 678 ath_detach(struct ath_softc *sc) 679 { 680 struct ifnet *ifp = sc->sc_ifp; 681 682 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 683 __func__, ifp->if_flags); 684 685 ath_stop(ifp); 686 bpfdetach(ifp); 687 /* 688 * NB: the order of these is important: 689 * o call the 802.11 layer before detaching the hal to 690 * insure callbacks into the driver to delete global 691 * key cache entries can be handled 692 * o reclaim the tx queue data structures after calling 693 * the 802.11 layer as we'll get called back to reclaim 694 * node state and potentially want to use them 695 * o to cleanup the tx queues the hal is called, so detach 696 * it last 697 * Other than that, it's straightforward... 698 */ 699 ieee80211_ifdetach(ifp->if_l2com); 700 #ifdef ATH_TX99_DIAG 701 if (sc->sc_tx99 != NULL) 702 sc->sc_tx99->detach(sc->sc_tx99); 703 #endif 704 taskqueue_free(sc->sc_tq); 705 ath_rate_detach(sc->sc_rc); 706 ath_desc_free(sc); 707 ath_tx_cleanup(sc); 708 ath_hal_detach(sc->sc_ah); 709 if_free(ifp); 710 711 return 0; 712 } 713 714 /* 715 * MAC address handling for multiple BSS on the same radio. 716 * The first vap uses the MAC address from the EEPROM. For 717 * subsequent vap's we set the U/L bit (bit 1) in the MAC 718 * address and use the next six bits as an index. 719 */ 720 static void 721 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 722 { 723 int i; 724 725 if (clone && sc->sc_hasbmask) { 726 /* NB: we only do this if h/w supports multiple bssid */ 727 for (i = 0; i < 8; i++) 728 if ((sc->sc_bssidmask & (1<<i)) == 0) 729 break; 730 if (i != 0) 731 mac[0] |= (i << 2)|0x2; 732 } else 733 i = 0; 734 sc->sc_bssidmask |= 1<<i; 735 sc->sc_hwbssidmask[0] &= ~mac[0]; 736 if (i == 0) 737 sc->sc_nbssid0++; 738 } 739 740 static void 741 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 742 { 743 int i = mac[0] >> 2; 744 uint8_t mask; 745 746 if (i != 0 || --sc->sc_nbssid0 == 0) { 747 sc->sc_bssidmask &= ~(1<<i); 748 /* recalculate bssid mask from remaining addresses */ 749 mask = 0xff; 750 for (i = 1; i < 8; i++) 751 if (sc->sc_bssidmask & (1<<i)) 752 mask &= ~((i<<2)|0x2); 753 sc->sc_hwbssidmask[0] |= mask; 754 } 755 } 756 757 /* 758 * Assign a beacon xmit slot. We try to space out 759 * assignments so when beacons are staggered the 760 * traffic coming out of the cab q has maximal time 761 * to go out before the next beacon is scheduled. 762 */ 763 static int 764 assign_bslot(struct ath_softc *sc) 765 { 766 u_int slot, free; 767 768 free = 0; 769 for (slot = 0; slot < ATH_BCBUF; slot++) 770 if (sc->sc_bslot[slot] == NULL) { 771 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 772 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 773 return slot; 774 free = slot; 775 /* NB: keep looking for a double slot */ 776 } 777 return free; 778 } 779 780 static struct ieee80211vap * 781 ath_vap_create(struct ieee80211com *ic, 782 const char name[IFNAMSIZ], int unit, int opmode, int flags, 783 const uint8_t bssid[IEEE80211_ADDR_LEN], 784 const uint8_t mac0[IEEE80211_ADDR_LEN]) 785 { 786 struct ath_softc *sc = ic->ic_ifp->if_softc; 787 struct ath_vap *avp; 788 struct ieee80211vap *vap; 789 uint8_t mac[IEEE80211_ADDR_LEN]; 790 int ic_opmode, needbeacon, error; 791 792 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap), 793 M_80211_VAP, M_WAITOK | M_ZERO); 794 needbeacon = 0; 795 IEEE80211_ADDR_COPY(mac, mac0); 796 797 ATH_LOCK(sc); 798 switch (opmode) { 799 case IEEE80211_M_STA: 800 if (sc->sc_nstavaps != 0) { /* XXX only 1 sta for now */ 801 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 802 goto bad; 803 } 804 if (sc->sc_nvaps) { 805 /* 806 * When there are multiple vaps we must fall 807 * back to s/w beacon miss handling. 808 */ 809 flags |= IEEE80211_CLONE_NOBEACONS; 810 } 811 if (flags & IEEE80211_CLONE_NOBEACONS) { 812 sc->sc_swbmiss = 1; 813 ic_opmode = IEEE80211_M_HOSTAP; 814 } else 815 ic_opmode = opmode; 816 break; 817 case IEEE80211_M_IBSS: 818 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 819 device_printf(sc->sc_dev, 820 "only 1 ibss vap supported\n"); 821 goto bad; 822 } 823 ic_opmode = opmode; 824 needbeacon = 1; 825 break; 826 case IEEE80211_M_AHDEMO: 827 /* fall thru... */ 828 case IEEE80211_M_MONITOR: 829 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 830 /* XXX not right for monitor mode */ 831 ic_opmode = ic->ic_opmode; 832 } else 833 ic_opmode = opmode; 834 break; 835 case IEEE80211_M_HOSTAP: 836 needbeacon = 1; 837 /* fall thru... */ 838 case IEEE80211_M_WDS: 839 if (sc->sc_nvaps && ic->ic_opmode == IEEE80211_M_STA) { 840 device_printf(sc->sc_dev, 841 "wds not supported in sta mode\n"); 842 goto bad; 843 } 844 if (opmode == IEEE80211_M_WDS) { 845 /* 846 * Silently remove any request for a unique 847 * bssid; WDS vap's always share the local 848 * mac address. 849 */ 850 flags &= ~IEEE80211_CLONE_BSSID; 851 } 852 ic_opmode = IEEE80211_M_HOSTAP; 853 break; 854 default: 855 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 856 goto bad; 857 } 858 /* 859 * Check that a beacon buffer is available; the code below assumes it. 860 */ 861 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) { 862 device_printf(sc->sc_dev, "no beacon buffer available\n"); 863 goto bad; 864 } 865 866 /* STA, AHDEMO? */ 867 if (opmode == IEEE80211_M_HOSTAP) { 868 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 869 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 870 } 871 872 vap = &avp->av_vap; 873 /* XXX can't hold mutex across if_alloc */ 874 ATH_UNLOCK(sc); 875 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 876 bssid, mac); 877 ATH_LOCK(sc); 878 if (error != 0) { 879 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 880 __func__, error); 881 goto bad2; 882 } 883 884 /* h/w crypto support */ 885 vap->iv_key_alloc = ath_key_alloc; 886 vap->iv_key_delete = ath_key_delete; 887 vap->iv_key_set = ath_key_set; 888 vap->iv_key_update_begin = ath_key_update_begin; 889 vap->iv_key_update_end = ath_key_update_end; 890 891 /* override various methods */ 892 avp->av_recv_mgmt = vap->iv_recv_mgmt; 893 vap->iv_recv_mgmt = ath_recv_mgmt; 894 vap->iv_reset = ath_reset_vap; 895 vap->iv_update_beacon = ath_beacon_update; 896 avp->av_newstate = vap->iv_newstate; 897 vap->iv_newstate = ath_newstate; 898 avp->av_bmiss = vap->iv_bmiss; 899 vap->iv_bmiss = ath_bmiss_vap; 900 901 avp->av_bslot = -1; 902 if (needbeacon) { 903 /* 904 * Allocate beacon state and setup the q for buffered 905 * multicast frames. We know a beacon buffer is 906 * available because we checked above. 907 */ 908 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf); 909 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list); 910 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 911 /* 912 * Assign the vap to a beacon xmit slot. As above 913 * this cannot fail to find a free one. 914 */ 915 avp->av_bslot = assign_bslot(sc); 916 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 917 ("beacon slot %u not empty", avp->av_bslot)); 918 sc->sc_bslot[avp->av_bslot] = vap; 919 sc->sc_nbcnvaps++; 920 } 921 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 922 /* 923 * Multple vaps are to transmit beacons and we 924 * have h/w support for TSF adjusting; enable 925 * use of staggered beacons. 926 */ 927 sc->sc_stagbeacons = 1; 928 } 929 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 930 } 931 932 ic->ic_opmode = ic_opmode; 933 if (opmode != IEEE80211_M_WDS) { 934 sc->sc_nvaps++; 935 if (opmode == IEEE80211_M_STA) 936 sc->sc_nstavaps++; 937 } 938 switch (ic_opmode) { 939 case IEEE80211_M_IBSS: 940 sc->sc_opmode = HAL_M_IBSS; 941 break; 942 case IEEE80211_M_STA: 943 sc->sc_opmode = HAL_M_STA; 944 break; 945 case IEEE80211_M_AHDEMO: 946 case IEEE80211_M_HOSTAP: 947 sc->sc_opmode = HAL_M_HOSTAP; 948 break; 949 case IEEE80211_M_MONITOR: 950 sc->sc_opmode = HAL_M_MONITOR; 951 break; 952 default: 953 /* XXX should not happen */ 954 break; 955 } 956 if (sc->sc_hastsfadd) { 957 /* 958 * Configure whether or not TSF adjust should be done. 959 */ 960 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 961 } 962 ATH_UNLOCK(sc); 963 964 /* complete setup */ 965 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 966 return vap; 967 bad2: 968 reclaim_address(sc, mac); 969 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 970 bad: 971 free(avp, M_80211_VAP); 972 ATH_UNLOCK(sc); 973 return NULL; 974 } 975 976 static void 977 ath_vap_delete(struct ieee80211vap *vap) 978 { 979 struct ieee80211com *ic = vap->iv_ic; 980 struct ifnet *ifp = ic->ic_ifp; 981 struct ath_softc *sc = ifp->if_softc; 982 struct ath_hal *ah = sc->sc_ah; 983 struct ath_vap *avp = ATH_VAP(vap); 984 985 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 986 /* 987 * Quiesce the hardware while we remove the vap. In 988 * particular we need to reclaim all references to 989 * the vap state by any frames pending on the tx queues. 990 */ 991 ath_hal_intrset(ah, 0); /* disable interrupts */ 992 ath_draintxq(sc); /* stop xmit side */ 993 ath_stoprecv(sc); /* stop recv side */ 994 } 995 996 ieee80211_vap_detach(vap); 997 ATH_LOCK(sc); 998 /* 999 * Reclaim beacon state. Note this must be done before 1000 * the vap instance is reclaimed as we may have a reference 1001 * to it in the buffer for the beacon frame. 1002 */ 1003 if (avp->av_bcbuf != NULL) { 1004 if (avp->av_bslot != -1) { 1005 sc->sc_bslot[avp->av_bslot] = NULL; 1006 sc->sc_nbcnvaps--; 1007 } 1008 ath_beacon_return(sc, avp->av_bcbuf); 1009 avp->av_bcbuf = NULL; 1010 if (sc->sc_nbcnvaps == 0) { 1011 sc->sc_stagbeacons = 0; 1012 if (sc->sc_hastsfadd) 1013 ath_hal_settsfadjust(sc->sc_ah, 0); 1014 } 1015 /* 1016 * Reclaim any pending mcast frames for the vap. 1017 */ 1018 ath_tx_draintxq(sc, &avp->av_mcastq); 1019 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq); 1020 } 1021 /* 1022 * Update bookkeeping. 1023 */ 1024 if (vap->iv_opmode == IEEE80211_M_STA) { 1025 sc->sc_nstavaps--; 1026 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1027 sc->sc_swbmiss = 0; 1028 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 1029 reclaim_address(sc, vap->iv_myaddr); 1030 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1031 } 1032 if (vap->iv_opmode != IEEE80211_M_WDS) 1033 sc->sc_nvaps--; 1034 ATH_UNLOCK(sc); 1035 free(avp, M_80211_VAP); 1036 1037 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1038 /* 1039 * Restart rx+tx machines if still running (RUNNING will 1040 * be reset if we just destroyed the last vap). 1041 */ 1042 if (ath_startrecv(sc) != 0) 1043 if_printf(ifp, "%s: unable to restart recv logic\n", 1044 __func__); 1045 if (sc->sc_beacons) 1046 ath_beacon_config(sc, NULL); 1047 ath_hal_intrset(ah, sc->sc_imask); 1048 } 1049 } 1050 1051 void 1052 ath_suspend(struct ath_softc *sc) 1053 { 1054 struct ifnet *ifp = sc->sc_ifp; 1055 1056 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1057 __func__, ifp->if_flags); 1058 1059 ath_stop(ifp); 1060 } 1061 1062 void 1063 ath_resume(struct ath_softc *sc) 1064 { 1065 struct ifnet *ifp = sc->sc_ifp; 1066 1067 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1068 __func__, ifp->if_flags); 1069 1070 if (ifp->if_flags & IFF_UP) { 1071 ath_init(sc); 1072 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1073 ath_start(ifp); 1074 } 1075 if (sc->sc_softled) { 1076 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 1077 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 1078 } 1079 } 1080 1081 void 1082 ath_shutdown(struct ath_softc *sc) 1083 { 1084 struct ifnet *ifp = sc->sc_ifp; 1085 1086 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1087 __func__, ifp->if_flags); 1088 1089 ath_stop(ifp); 1090 } 1091 1092 /* 1093 * Interrupt handler. Most of the actual processing is deferred. 1094 */ 1095 void 1096 ath_intr(void *arg) 1097 { 1098 struct ath_softc *sc = arg; 1099 struct ifnet *ifp = sc->sc_ifp; 1100 struct ath_hal *ah = sc->sc_ah; 1101 HAL_INT status; 1102 1103 if (sc->sc_invalid) { 1104 /* 1105 * The hardware is not ready/present, don't touch anything. 1106 * Note this can happen early on if the IRQ is shared. 1107 */ 1108 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1109 return; 1110 } 1111 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 1112 return; 1113 if ((ifp->if_flags & IFF_UP) == 0 || 1114 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1115 HAL_INT status; 1116 1117 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1118 __func__, ifp->if_flags); 1119 ath_hal_getisr(ah, &status); /* clear ISR */ 1120 ath_hal_intrset(ah, 0); /* disable further intr's */ 1121 return; 1122 } 1123 /* 1124 * Figure out the reason(s) for the interrupt. Note 1125 * that the hal returns a pseudo-ISR that may include 1126 * bits we haven't explicitly enabled so we mask the 1127 * value to insure we only process bits we requested. 1128 */ 1129 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 1130 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 1131 status &= sc->sc_imask; /* discard unasked for bits */ 1132 if (status & HAL_INT_FATAL) { 1133 sc->sc_stats.ast_hardware++; 1134 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1135 ath_fatal_proc(sc, 0); 1136 } else if (status & HAL_INT_RXORN) { 1137 sc->sc_stats.ast_rxorn++; 1138 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1139 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxorntask); 1140 } else { 1141 if (status & HAL_INT_SWBA) { 1142 /* 1143 * Software beacon alert--time to send a beacon. 1144 * Handle beacon transmission directly; deferring 1145 * this is too slow to meet timing constraints 1146 * under load. 1147 */ 1148 ath_beacon_proc(sc, 0); 1149 } 1150 if (status & HAL_INT_RXEOL) { 1151 /* 1152 * NB: the hardware should re-read the link when 1153 * RXE bit is written, but it doesn't work at 1154 * least on older hardware revs. 1155 */ 1156 sc->sc_stats.ast_rxeol++; 1157 sc->sc_rxlink = NULL; 1158 } 1159 if (status & HAL_INT_TXURN) { 1160 sc->sc_stats.ast_txurn++; 1161 /* bump tx trigger level */ 1162 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1163 } 1164 if (status & HAL_INT_RX) 1165 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1166 if (status & HAL_INT_TX) 1167 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1168 if (status & HAL_INT_BMISS) { 1169 sc->sc_stats.ast_bmiss++; 1170 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1171 } 1172 if (status & HAL_INT_MIB) { 1173 sc->sc_stats.ast_mib++; 1174 /* 1175 * Disable interrupts until we service the MIB 1176 * interrupt; otherwise it will continue to fire. 1177 */ 1178 ath_hal_intrset(ah, 0); 1179 /* 1180 * Let the hal handle the event. We assume it will 1181 * clear whatever condition caused the interrupt. 1182 */ 1183 ath_hal_mibevent(ah, &sc->sc_halstats); 1184 ath_hal_intrset(ah, sc->sc_imask); 1185 } 1186 } 1187 } 1188 1189 static void 1190 ath_fatal_proc(void *arg, int pending) 1191 { 1192 struct ath_softc *sc = arg; 1193 struct ifnet *ifp = sc->sc_ifp; 1194 u_int32_t *state; 1195 u_int32_t len; 1196 void *sp; 1197 1198 if_printf(ifp, "hardware error; resetting\n"); 1199 /* 1200 * Fatal errors are unrecoverable. Typically these 1201 * are caused by DMA errors. Collect h/w state from 1202 * the hal so we can diagnose what's going on. 1203 */ 1204 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1205 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1206 state = sp; 1207 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1208 state[0], state[1] , state[2], state[3], 1209 state[4], state[5]); 1210 } 1211 ath_reset(ifp); 1212 } 1213 1214 static void 1215 ath_rxorn_proc(void *arg, int pending) 1216 { 1217 struct ath_softc *sc = arg; 1218 struct ifnet *ifp = sc->sc_ifp; 1219 1220 if_printf(ifp, "rx FIFO overrun; resetting\n"); 1221 ath_reset(ifp); 1222 } 1223 1224 static void 1225 ath_bmiss_vap(struct ieee80211vap *vap) 1226 { 1227 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 1228 u_int64_t lastrx = sc->sc_lastrx; 1229 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1230 u_int bmisstimeout = 1231 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1232 1233 DPRINTF(sc, ATH_DEBUG_BEACON, 1234 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1235 __func__, (unsigned long long) tsf, 1236 (unsigned long long)(tsf - lastrx), 1237 (unsigned long long) lastrx, bmisstimeout); 1238 /* 1239 * Workaround phantom bmiss interrupts by sanity-checking 1240 * the time of our last rx'd frame. If it is within the 1241 * beacon miss interval then ignore the interrupt. If it's 1242 * truly a bmiss we'll get another interrupt soon and that'll 1243 * be dispatched up for processing. 1244 */ 1245 if (tsf - lastrx > bmisstimeout) 1246 ATH_VAP(vap)->av_bmiss(vap); 1247 else 1248 sc->sc_stats.ast_bmiss_phantom++; 1249 } 1250 1251 static void 1252 ath_bmiss_proc(void *arg, int pending) 1253 { 1254 struct ath_softc *sc = arg; 1255 struct ifnet *ifp = sc->sc_ifp; 1256 1257 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1258 ieee80211_beacon_miss(ifp->if_l2com); 1259 } 1260 1261 /* 1262 * Convert net80211 channel to a HAL channel with the flags 1263 * constrained to reflect the current operating mode and 1264 * the frequency possibly mapped for GSM channels. 1265 */ 1266 static void 1267 ath_mapchan(HAL_CHANNEL *hc, const struct ieee80211_channel *chan) 1268 { 1269 #define N(a) (sizeof(a) / sizeof(a[0])) 1270 static const u_int modeflags[IEEE80211_MODE_MAX] = { 1271 0, /* IEEE80211_MODE_AUTO */ 1272 CHANNEL_A, /* IEEE80211_MODE_11A */ 1273 CHANNEL_B, /* IEEE80211_MODE_11B */ 1274 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 1275 0, /* IEEE80211_MODE_FH */ 1276 CHANNEL_108A, /* IEEE80211_MODE_TURBO_A */ 1277 CHANNEL_108G, /* IEEE80211_MODE_TURBO_G */ 1278 CHANNEL_ST, /* IEEE80211_MODE_STURBO_A */ 1279 CHANNEL_A, /* IEEE80211_MODE_11NA */ 1280 CHANNEL_PUREG, /* IEEE80211_MODE_11NG */ 1281 }; 1282 enum ieee80211_phymode mode = ieee80211_chan2mode(chan); 1283 1284 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 1285 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 1286 hc->channelFlags = modeflags[mode]; 1287 if (IEEE80211_IS_CHAN_HALF(chan)) 1288 hc->channelFlags |= CHANNEL_HALF; 1289 if (IEEE80211_IS_CHAN_QUARTER(chan)) 1290 hc->channelFlags |= CHANNEL_QUARTER; 1291 if (IEEE80211_IS_CHAN_HT20(chan)) 1292 hc->channelFlags |= CHANNEL_HT20; 1293 if (IEEE80211_IS_CHAN_HT40D(chan)) 1294 hc->channelFlags |= CHANNEL_HT40MINUS; 1295 if (IEEE80211_IS_CHAN_HT40U(chan)) 1296 hc->channelFlags |= CHANNEL_HT40PLUS; 1297 1298 hc->channel = IEEE80211_IS_CHAN_GSM(chan) ? 1299 2422 + (922 - chan->ic_freq) : chan->ic_freq; 1300 #undef N 1301 } 1302 1303 /* 1304 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1305 * calcs together with WME. If necessary disable the crypto 1306 * hardware and mark the 802.11 state so keys will be setup 1307 * with the MIC work done in software. 1308 */ 1309 static void 1310 ath_settkipmic(struct ath_softc *sc) 1311 { 1312 struct ifnet *ifp = sc->sc_ifp; 1313 struct ieee80211com *ic = ifp->if_l2com; 1314 1315 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1316 if (ic->ic_flags & IEEE80211_F_WME) { 1317 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1318 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1319 } else { 1320 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1321 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1322 } 1323 } 1324 } 1325 1326 static void 1327 ath_init(void *arg) 1328 { 1329 struct ath_softc *sc = (struct ath_softc *) arg; 1330 struct ifnet *ifp = sc->sc_ifp; 1331 struct ieee80211com *ic = ifp->if_l2com; 1332 struct ath_hal *ah = sc->sc_ah; 1333 HAL_STATUS status; 1334 1335 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1336 __func__, ifp->if_flags); 1337 1338 ATH_LOCK(sc); 1339 /* 1340 * Stop anything previously setup. This is safe 1341 * whether this is the first time through or not. 1342 */ 1343 ath_stop_locked(ifp); 1344 1345 /* 1346 * The basic interface to setting the hardware in a good 1347 * state is ``reset''. On return the hardware is known to 1348 * be powered up and with interrupts disabled. This must 1349 * be followed by initialization of the appropriate bits 1350 * and then setup of the interrupt mask. 1351 */ 1352 ath_mapchan(&sc->sc_curchan, ic->ic_curchan); 1353 ath_settkipmic(sc); 1354 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 1355 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1356 status); 1357 ATH_UNLOCK(sc); 1358 return; 1359 } 1360 ath_chan_change(sc, ic->ic_curchan); 1361 1362 /* 1363 * Likewise this is set during reset so update 1364 * state cached in the driver. 1365 */ 1366 sc->sc_diversity = ath_hal_getdiversity(ah); 1367 sc->sc_calinterval = 1; 1368 sc->sc_caltries = 0; 1369 1370 /* 1371 * Setup the hardware after reset: the key cache 1372 * is filled as needed and the receive engine is 1373 * set going. Frame transmit is handled entirely 1374 * in the frame output path; there's nothing to do 1375 * here except setup the interrupt mask. 1376 */ 1377 if (ath_startrecv(sc) != 0) { 1378 if_printf(ifp, "unable to start recv logic\n"); 1379 ATH_UNLOCK(sc); 1380 return; 1381 } 1382 1383 /* 1384 * Enable interrupts. 1385 */ 1386 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1387 | HAL_INT_RXEOL | HAL_INT_RXORN 1388 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1389 /* 1390 * Enable MIB interrupts when there are hardware phy counters. 1391 * Note we only do this (at the moment) for station mode. 1392 */ 1393 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1394 sc->sc_imask |= HAL_INT_MIB; 1395 1396 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1397 ath_hal_intrset(ah, sc->sc_imask); 1398 1399 ATH_UNLOCK(sc); 1400 1401 #ifdef ATH_TX99_DIAG 1402 if (sc->sc_tx99 != NULL) 1403 sc->sc_tx99->start(sc->sc_tx99); 1404 else 1405 #endif 1406 ieee80211_start_all(ic); /* start all vap's */ 1407 } 1408 1409 static void 1410 ath_stop_locked(struct ifnet *ifp) 1411 { 1412 struct ath_softc *sc = ifp->if_softc; 1413 struct ath_hal *ah = sc->sc_ah; 1414 1415 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1416 __func__, sc->sc_invalid, ifp->if_flags); 1417 1418 ATH_LOCK_ASSERT(sc); 1419 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1420 /* 1421 * Shutdown the hardware and driver: 1422 * reset 802.11 state machine 1423 * turn off timers 1424 * disable interrupts 1425 * turn off the radio 1426 * clear transmit machinery 1427 * clear receive machinery 1428 * drain and release tx queues 1429 * reclaim beacon resources 1430 * power down hardware 1431 * 1432 * Note that some of this work is not possible if the 1433 * hardware is gone (invalid). 1434 */ 1435 #ifdef ATH_TX99_DIAG 1436 if (sc->sc_tx99 != NULL) 1437 sc->sc_tx99->stop(sc->sc_tx99); 1438 #endif 1439 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1440 ifp->if_timer = 0; 1441 if (!sc->sc_invalid) { 1442 if (sc->sc_softled) { 1443 callout_stop(&sc->sc_ledtimer); 1444 ath_hal_gpioset(ah, sc->sc_ledpin, 1445 !sc->sc_ledon); 1446 sc->sc_blinking = 0; 1447 } 1448 ath_hal_intrset(ah, 0); 1449 } 1450 ath_draintxq(sc); 1451 if (!sc->sc_invalid) { 1452 ath_stoprecv(sc); 1453 ath_hal_phydisable(ah); 1454 } else 1455 sc->sc_rxlink = NULL; 1456 ath_beacon_free(sc); /* XXX not needed */ 1457 } 1458 } 1459 1460 static void 1461 ath_stop(struct ifnet *ifp) 1462 { 1463 struct ath_softc *sc = ifp->if_softc; 1464 1465 ATH_LOCK(sc); 1466 ath_stop_locked(ifp); 1467 if (!sc->sc_invalid) { 1468 /* 1469 * Set the chip in full sleep mode. Note that we are 1470 * careful to do this only when bringing the interface 1471 * completely to a stop. When the chip is in this state 1472 * it must be carefully woken up or references to 1473 * registers in the PCI clock domain may freeze the bus 1474 * (and system). This varies by chip and is mostly an 1475 * issue with newer parts that go to sleep more quickly. 1476 */ 1477 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 1478 } 1479 ATH_UNLOCK(sc); 1480 } 1481 1482 /* 1483 * Reset the hardware w/o losing operational state. This is 1484 * basically a more efficient way of doing ath_stop, ath_init, 1485 * followed by state transitions to the current 802.11 1486 * operational state. Used to recover from various errors and 1487 * to reset or reload hardware state. 1488 */ 1489 static int 1490 ath_reset(struct ifnet *ifp) 1491 { 1492 struct ath_softc *sc = ifp->if_softc; 1493 struct ieee80211com *ic = ifp->if_l2com; 1494 struct ath_hal *ah = sc->sc_ah; 1495 HAL_STATUS status; 1496 1497 /* 1498 * Convert to a HAL channel description with the flags 1499 * constrained to reflect the current operating mode. 1500 */ 1501 ath_mapchan(&sc->sc_curchan, ic->ic_curchan); 1502 1503 ath_hal_intrset(ah, 0); /* disable interrupts */ 1504 ath_draintxq(sc); /* stop xmit side */ 1505 ath_stoprecv(sc); /* stop recv side */ 1506 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1507 /* NB: indicate channel change so we do a full reset */ 1508 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1509 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1510 __func__, status); 1511 sc->sc_diversity = ath_hal_getdiversity(ah); 1512 sc->sc_calinterval = 1; 1513 sc->sc_caltries = 0; 1514 if (ath_startrecv(sc) != 0) /* restart recv */ 1515 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1516 /* 1517 * We may be doing a reset in response to an ioctl 1518 * that changes the channel so update any state that 1519 * might change as a result. 1520 */ 1521 ath_chan_change(sc, ic->ic_curchan); 1522 if (sc->sc_beacons) 1523 ath_beacon_config(sc, NULL); /* restart beacons */ 1524 ath_hal_intrset(ah, sc->sc_imask); 1525 1526 ath_start(ifp); /* restart xmit */ 1527 return 0; 1528 } 1529 1530 static int 1531 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 1532 { 1533 return ath_reset(vap->iv_ic->ic_ifp); 1534 } 1535 1536 static int 1537 ath_ff_always(struct ath_txq *txq, struct ath_buf *bf) 1538 { 1539 return 0; 1540 } 1541 1542 #if 0 1543 static int 1544 ath_ff_ageflushtestdone(struct ath_txq *txq, struct ath_buf *bf) 1545 { 1546 return (txq->axq_curage - bf->bf_age) < ATH_FF_STAGEMAX; 1547 } 1548 #endif 1549 1550 /* 1551 * Flush FF staging queue. 1552 */ 1553 static void 1554 ath_ff_stageq_flush(struct ath_softc *sc, struct ath_txq *txq, 1555 int (*ath_ff_flushdonetest)(struct ath_txq *txq, struct ath_buf *bf)) 1556 { 1557 struct ath_buf *bf; 1558 struct ieee80211_node *ni; 1559 int pktlen, pri; 1560 1561 for (;;) { 1562 ATH_TXQ_LOCK(txq); 1563 /* 1564 * Go from the back (oldest) to front so we can 1565 * stop early based on the age of the entry. 1566 */ 1567 bf = TAILQ_LAST(&txq->axq_stageq, axq_headtype); 1568 if (bf == NULL || ath_ff_flushdonetest(txq, bf)) { 1569 ATH_TXQ_UNLOCK(txq); 1570 break; 1571 } 1572 1573 ni = bf->bf_node; 1574 pri = M_WME_GETAC(bf->bf_m); 1575 KASSERT(ATH_NODE(ni)->an_ff_buf[pri], 1576 ("no bf on staging queue %p", bf)); 1577 ATH_NODE(ni)->an_ff_buf[pri] = NULL; 1578 TAILQ_REMOVE(&txq->axq_stageq, bf, bf_stagelist); 1579 1580 ATH_TXQ_UNLOCK(txq); 1581 1582 DPRINTF(sc, ATH_DEBUG_FF, "%s: flush frame, age %u\n", 1583 __func__, bf->bf_age); 1584 1585 sc->sc_stats.ast_ff_flush++; 1586 1587 /* encap and xmit */ 1588 bf->bf_m = ieee80211_encap(ni, bf->bf_m); 1589 if (bf->bf_m == NULL) { 1590 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1591 "%s: discard, encapsulation failure\n", 1592 __func__); 1593 sc->sc_stats.ast_tx_encap++; 1594 goto bad; 1595 } 1596 pktlen = bf->bf_m->m_pkthdr.len; /* NB: don't reference below */ 1597 if (ath_tx_start(sc, ni, bf, bf->bf_m) == 0) { 1598 #if 0 /*XXX*/ 1599 ifp->if_opackets++; 1600 #endif 1601 continue; 1602 } 1603 bad: 1604 if (ni != NULL) 1605 ieee80211_free_node(ni); 1606 bf->bf_node = NULL; 1607 if (bf->bf_m != NULL) { 1608 m_freem(bf->bf_m); 1609 bf->bf_m = NULL; 1610 } 1611 1612 ATH_TXBUF_LOCK(sc); 1613 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1614 ATH_TXBUF_UNLOCK(sc); 1615 } 1616 } 1617 1618 static __inline u_int32_t 1619 ath_ff_approx_txtime(struct ath_softc *sc, struct ath_node *an, struct mbuf *m) 1620 { 1621 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1622 u_int32_t framelen; 1623 struct ath_buf *bf; 1624 1625 /* 1626 * Approximate the frame length to be transmitted. A swag to add 1627 * the following maximal values to the skb payload: 1628 * - 32: 802.11 encap + CRC 1629 * - 24: encryption overhead (if wep bit) 1630 * - 4 + 6: fast-frame header and padding 1631 * - 16: 2 LLC FF tunnel headers 1632 * - 14: 1 802.3 FF tunnel header (skb already accounts for 2nd) 1633 */ 1634 framelen = m->m_pkthdr.len + 32 + 4 + 6 + 16 + 14; 1635 if (ic->ic_flags & IEEE80211_F_PRIVACY) 1636 framelen += 24; 1637 bf = an->an_ff_buf[M_WME_GETAC(m)]; 1638 if (bf != NULL) 1639 framelen += bf->bf_m->m_pkthdr.len; 1640 return ath_hal_computetxtime(sc->sc_ah, sc->sc_currates, framelen, 1641 sc->sc_lastdatarix, AH_FALSE); 1642 } 1643 1644 /* 1645 * Determine if a data frame may be aggregated via ff tunnelling. 1646 * Note the caller is responsible for checking if the destination 1647 * supports fast frames. 1648 * 1649 * NB: allowing EAPOL frames to be aggregated with other unicast traffic. 1650 * Do 802.1x EAPOL frames proceed in the clear? Then they couldn't 1651 * be aggregated with other types of frames when encryption is on? 1652 * 1653 * NB: assumes lock on an_ff_buf effectively held by txq lock mechanism. 1654 */ 1655 static __inline int 1656 ath_ff_can_aggregate(struct ath_softc *sc, 1657 struct ath_node *an, struct mbuf *m, int *flushq) 1658 { 1659 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1660 struct ath_txq *txq; 1661 u_int32_t txoplimit; 1662 u_int pri; 1663 1664 *flushq = 0; 1665 1666 /* 1667 * If there is no frame to combine with and the txq has 1668 * fewer frames than the minimum required; then do not 1669 * attempt to aggregate this frame. 1670 */ 1671 pri = M_WME_GETAC(m); 1672 txq = sc->sc_ac2q[pri]; 1673 if (an->an_ff_buf[pri] == NULL && txq->axq_depth < sc->sc_fftxqmin) 1674 return 0; 1675 /* 1676 * When not in station mode never aggregate a multicast 1677 * frame; this insures, for example, that a combined frame 1678 * does not require multiple encryption keys when using 1679 * 802.1x/WPA. 1680 */ 1681 if (ic->ic_opmode != IEEE80211_M_STA && 1682 ETHER_IS_MULTICAST(mtod(m, struct ether_header *)->ether_dhost)) 1683 return 0; 1684 /* 1685 * Consult the max bursting interval to insure a combined 1686 * frame fits within the TxOp window. 1687 */ 1688 txoplimit = IEEE80211_TXOP_TO_US( 1689 ic->ic_wme.wme_chanParams.cap_wmeParams[pri].wmep_txopLimit); 1690 if (txoplimit != 0 && ath_ff_approx_txtime(sc, an, m) > txoplimit) { 1691 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1692 "%s: FF TxOp violation\n", __func__); 1693 if (an->an_ff_buf[pri] != NULL) 1694 *flushq = 1; 1695 return 0; 1696 } 1697 return 1; /* try to aggregate */ 1698 } 1699 1700 /* 1701 * Check if the supplied frame can be partnered with an existing 1702 * or pending frame. Return a reference to any frame that should be 1703 * sent on return; otherwise return NULL. 1704 */ 1705 static struct mbuf * 1706 ath_ff_check(struct ath_softc *sc, struct ath_txq *txq, 1707 struct ath_buf *bf, struct mbuf *m, struct ieee80211_node *ni) 1708 { 1709 struct ath_node *an = ATH_NODE(ni); 1710 struct ath_buf *bfstaged; 1711 int ff_flush, pri; 1712 1713 /* 1714 * Check if the supplied frame can be aggregated. 1715 * 1716 * NB: we use the txq lock to protect references to 1717 * an->an_ff_txbuf in ath_ff_can_aggregate(). 1718 */ 1719 ATH_TXQ_LOCK(txq); 1720 pri = M_WME_GETAC(m); 1721 if (ath_ff_can_aggregate(sc, an, m, &ff_flush)) { 1722 struct ath_buf *bfstaged = an->an_ff_buf[pri]; 1723 if (bfstaged != NULL) { 1724 /* 1725 * A frame is available for partnering; remove 1726 * it, chain it to this one, and encapsulate. 1727 */ 1728 an->an_ff_buf[pri] = NULL; 1729 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist); 1730 ATH_TXQ_UNLOCK(txq); 1731 1732 /* 1733 * Chain mbufs and add FF magic. 1734 */ 1735 DPRINTF(sc, ATH_DEBUG_FF, 1736 "[%s] aggregate fast-frame, age %u\n", 1737 ether_sprintf(ni->ni_macaddr), txq->axq_curage); 1738 m->m_nextpkt = NULL; 1739 bfstaged->bf_m->m_nextpkt = m; 1740 m = bfstaged->bf_m; 1741 bfstaged->bf_m = NULL; 1742 m->m_flags |= M_FF; 1743 /* 1744 * Release the node reference held while 1745 * the packet sat on an_ff_buf[] 1746 */ 1747 bfstaged->bf_node = NULL; 1748 ieee80211_free_node(ni); 1749 1750 /* 1751 * Return bfstaged to the free list. 1752 */ 1753 ATH_TXBUF_LOCK(sc); 1754 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bfstaged, bf_list); 1755 ATH_TXBUF_UNLOCK(sc); 1756 1757 return m; /* ready to go */ 1758 } else { 1759 /* 1760 * No frame available, queue this frame to wait 1761 * for a partner. Note that we hold the buffer 1762 * and a reference to the node; we need the 1763 * buffer in particular so we're certain we 1764 * can flush the frame at a later time. 1765 */ 1766 DPRINTF(sc, ATH_DEBUG_FF, 1767 "[%s] stage fast-frame, age %u\n", 1768 ether_sprintf(ni->ni_macaddr), txq->axq_curage); 1769 1770 bf->bf_m = m; 1771 bf->bf_node = ni; /* NB: held reference */ 1772 bf->bf_age = txq->axq_curage; 1773 an->an_ff_buf[pri] = bf; 1774 TAILQ_INSERT_HEAD(&txq->axq_stageq, bf, bf_stagelist); 1775 ATH_TXQ_UNLOCK(txq); 1776 1777 return NULL; /* consumed */ 1778 } 1779 } 1780 /* 1781 * Frame could not be aggregated, it needs to be returned 1782 * to the caller for immediate transmission. In addition 1783 * we check if we should first flush a frame from the 1784 * staging queue before sending this one. 1785 * 1786 * NB: ath_ff_can_aggregate only marks ff_flush if a frame 1787 * is present to flush. 1788 */ 1789 if (ff_flush) { 1790 int pktlen; 1791 1792 bfstaged = an->an_ff_buf[pri]; 1793 an->an_ff_buf[pri] = NULL; 1794 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist); 1795 ATH_TXQ_UNLOCK(txq); 1796 1797 DPRINTF(sc, ATH_DEBUG_FF, "[%s] flush staged frame\n", 1798 ether_sprintf(an->an_node.ni_macaddr)); 1799 1800 /* encap and xmit */ 1801 bfstaged->bf_m = ieee80211_encap(ni, bfstaged->bf_m); 1802 if (bfstaged->bf_m == NULL) { 1803 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF, 1804 "%s: discard, encap failure\n", __func__); 1805 sc->sc_stats.ast_tx_encap++; 1806 goto ff_flushbad; 1807 } 1808 pktlen = bfstaged->bf_m->m_pkthdr.len; 1809 if (ath_tx_start(sc, ni, bfstaged, bfstaged->bf_m)) { 1810 DPRINTF(sc, ATH_DEBUG_XMIT, 1811 "%s: discard, xmit failure\n", __func__); 1812 ff_flushbad: 1813 /* 1814 * Unable to transmit frame that was on the staging 1815 * queue. Reclaim the node reference and other 1816 * resources. 1817 */ 1818 if (ni != NULL) 1819 ieee80211_free_node(ni); 1820 bfstaged->bf_node = NULL; 1821 if (bfstaged->bf_m != NULL) { 1822 m_freem(bfstaged->bf_m); 1823 bfstaged->bf_m = NULL; 1824 } 1825 1826 ATH_TXBUF_LOCK(sc); 1827 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bfstaged, bf_list); 1828 ATH_TXBUF_UNLOCK(sc); 1829 } else { 1830 #if 0 1831 ifp->if_opackets++; 1832 #endif 1833 } 1834 } else { 1835 if (an->an_ff_buf[pri] != NULL) { 1836 /* 1837 * XXX: out-of-order condition only occurs for AP 1838 * mode and multicast. There may be no valid way 1839 * to get this condition. 1840 */ 1841 DPRINTF(sc, ATH_DEBUG_FF, "[%s] out-of-order frame\n", 1842 ether_sprintf(an->an_node.ni_macaddr)); 1843 /* XXX stat */ 1844 } 1845 ATH_TXQ_UNLOCK(txq); 1846 } 1847 return m; 1848 } 1849 1850 /* 1851 * Cleanup driver resources when we run out of buffers 1852 * while processing fragments; return the tx buffers 1853 * allocated and drop node references. 1854 */ 1855 static void 1856 ath_txfrag_cleanup(struct ath_softc *sc, 1857 ath_bufhead *frags, struct ieee80211_node *ni) 1858 { 1859 struct ath_buf *bf, *next; 1860 1861 ATH_TXBUF_LOCK_ASSERT(sc); 1862 1863 STAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 1864 /* NB: bf assumed clean */ 1865 STAILQ_REMOVE_HEAD(frags, bf_list); 1866 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1867 ieee80211_node_decref(ni); 1868 } 1869 } 1870 1871 /* 1872 * Setup xmit of a fragmented frame. Allocate a buffer 1873 * for each frag and bump the node reference count to 1874 * reflect the held reference to be setup by ath_tx_start. 1875 */ 1876 static int 1877 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1878 struct mbuf *m0, struct ieee80211_node *ni) 1879 { 1880 struct mbuf *m; 1881 struct ath_buf *bf; 1882 1883 ATH_TXBUF_LOCK(sc); 1884 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1885 bf = STAILQ_FIRST(&sc->sc_txbuf); 1886 if (bf == NULL) { /* out of buffers, cleanup */ 1887 ath_txfrag_cleanup(sc, frags, ni); 1888 break; 1889 } 1890 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1891 ieee80211_node_incref(ni); 1892 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1893 } 1894 ATH_TXBUF_UNLOCK(sc); 1895 1896 return !STAILQ_EMPTY(frags); 1897 } 1898 1899 static void 1900 ath_start(struct ifnet *ifp) 1901 { 1902 struct ath_softc *sc = ifp->if_softc; 1903 struct ieee80211com *ic = ifp->if_l2com; 1904 struct ieee80211_node *ni; 1905 struct ath_buf *bf; 1906 struct mbuf *m, *next; 1907 struct ath_txq *txq; 1908 ath_bufhead frags; 1909 int pri; 1910 1911 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 1912 return; 1913 for (;;) { 1914 /* 1915 * Grab a TX buffer and associated resources. 1916 */ 1917 ATH_TXBUF_LOCK(sc); 1918 bf = STAILQ_FIRST(&sc->sc_txbuf); 1919 if (bf != NULL) 1920 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1921 ATH_TXBUF_UNLOCK(sc); 1922 if (bf == NULL) { 1923 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 1924 __func__); 1925 sc->sc_stats.ast_tx_qstop++; 1926 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1927 break; 1928 } 1929 1930 IFQ_DEQUEUE(&ifp->if_snd, m); 1931 if (m == NULL) { 1932 ATH_TXBUF_LOCK(sc); 1933 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1934 ATH_TXBUF_UNLOCK(sc); 1935 break; 1936 } 1937 STAILQ_INIT(&frags); 1938 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1939 pri = M_WME_GETAC(m); 1940 txq = sc->sc_ac2q[pri]; 1941 if (ni->ni_ath_flags & IEEE80211_NODE_FF) { 1942 /* 1943 * Check queue length; if too deep drop this 1944 * frame (tail drop considered good). 1945 */ 1946 if (txq->axq_depth >= sc->sc_fftxqmax) { 1947 DPRINTF(sc, ATH_DEBUG_FF, 1948 "[%s] tail drop on q %u depth %u\n", 1949 ether_sprintf(ni->ni_macaddr), 1950 txq->axq_qnum, txq->axq_depth); 1951 sc->sc_stats.ast_tx_qfull++; 1952 m_freem(m); 1953 goto reclaim; 1954 } 1955 m = ath_ff_check(sc, txq, bf, m, ni); 1956 if (m == NULL) { 1957 /* NB: ni ref & bf held on stageq */ 1958 continue; 1959 } 1960 } 1961 ifp->if_opackets++; 1962 /* 1963 * Encapsulate the packet in prep for transmission. 1964 */ 1965 m = ieee80211_encap(ni, m); 1966 if (m == NULL) { 1967 DPRINTF(sc, ATH_DEBUG_XMIT, 1968 "%s: encapsulation failure\n", __func__); 1969 sc->sc_stats.ast_tx_encap++; 1970 goto bad; 1971 } 1972 /* 1973 * Check for fragmentation. If this frame 1974 * has been broken up verify we have enough 1975 * buffers to send all the fragments so all 1976 * go out or none... 1977 */ 1978 if ((m->m_flags & M_FRAG) && 1979 !ath_txfrag_setup(sc, &frags, m, ni)) { 1980 DPRINTF(sc, ATH_DEBUG_XMIT, 1981 "%s: out of txfrag buffers\n", __func__); 1982 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1983 ath_freetx(m); 1984 goto bad; 1985 } 1986 nextfrag: 1987 /* 1988 * Pass the frame to the h/w for transmission. 1989 * Fragmented frames have each frag chained together 1990 * with m_nextpkt. We know there are sufficient ath_buf's 1991 * to send all the frags because of work done by 1992 * ath_txfrag_setup. We leave m_nextpkt set while 1993 * calling ath_tx_start so it can use it to extend the 1994 * the tx duration to cover the subsequent frag and 1995 * so it can reclaim all the mbufs in case of an error; 1996 * ath_tx_start clears m_nextpkt once it commits to 1997 * handing the frame to the hardware. 1998 */ 1999 next = m->m_nextpkt; 2000 if (ath_tx_start(sc, ni, bf, m)) { 2001 bad: 2002 ifp->if_oerrors++; 2003 reclaim: 2004 bf->bf_m = NULL; 2005 bf->bf_node = NULL; 2006 ATH_TXBUF_LOCK(sc); 2007 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 2008 ath_txfrag_cleanup(sc, &frags, ni); 2009 ATH_TXBUF_UNLOCK(sc); 2010 if (ni != NULL) 2011 ieee80211_free_node(ni); 2012 continue; 2013 } 2014 if (next != NULL) { 2015 /* 2016 * Beware of state changing between frags. 2017 * XXX check sta power-save state? 2018 */ 2019 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 2020 DPRINTF(sc, ATH_DEBUG_XMIT, 2021 "%s: flush fragmented packet, state %s\n", 2022 __func__, 2023 ieee80211_state_name[ni->ni_vap->iv_state]); 2024 ath_freetx(next); 2025 goto reclaim; 2026 } 2027 m = next; 2028 bf = STAILQ_FIRST(&frags); 2029 KASSERT(bf != NULL, ("no buf for txfrag")); 2030 STAILQ_REMOVE_HEAD(&frags, bf_list); 2031 goto nextfrag; 2032 } 2033 2034 ifp->if_timer = 5; 2035 #if 0 2036 /* 2037 * Flush stale frames from the fast-frame staging queue. 2038 */ 2039 if (ic->ic_opmode != IEEE80211_M_STA) 2040 ath_ff_stageq_flush(sc, txq, ath_ff_ageflushtestdone); 2041 #endif 2042 } 2043 } 2044 2045 static int 2046 ath_media_change(struct ifnet *ifp) 2047 { 2048 int error = ieee80211_media_change(ifp); 2049 /* NB: only the fixed rate can change and that doesn't need a reset */ 2050 return (error == ENETRESET ? 0 : error); 2051 } 2052 2053 #ifdef ATH_DEBUG 2054 static void 2055 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 2056 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 2057 { 2058 static const char *ciphers[] = { 2059 "WEP", 2060 "AES-OCB", 2061 "AES-CCM", 2062 "CKIP", 2063 "TKIP", 2064 "CLR", 2065 }; 2066 int i, n; 2067 2068 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 2069 for (i = 0, n = hk->kv_len; i < n; i++) 2070 printf("%02x", hk->kv_val[i]); 2071 printf(" mac %s", ether_sprintf(mac)); 2072 if (hk->kv_type == HAL_CIPHER_TKIP) { 2073 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 2074 for (i = 0; i < sizeof(hk->kv_mic); i++) 2075 printf("%02x", hk->kv_mic[i]); 2076 if (!sc->sc_splitmic) { 2077 printf(" txmic "); 2078 for (i = 0; i < sizeof(hk->kv_txmic); i++) 2079 printf("%02x", hk->kv_txmic[i]); 2080 } 2081 } 2082 printf("\n"); 2083 } 2084 #endif 2085 2086 /* 2087 * Set a TKIP key into the hardware. This handles the 2088 * potential distribution of key state to multiple key 2089 * cache slots for TKIP. 2090 */ 2091 static int 2092 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 2093 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 2094 { 2095 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 2096 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 2097 struct ath_hal *ah = sc->sc_ah; 2098 2099 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 2100 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 2101 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 2102 if (sc->sc_splitmic) { 2103 /* 2104 * TX key goes at first index, RX key at the rx index. 2105 * The hal handles the MIC keys at index+64. 2106 */ 2107 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 2108 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 2109 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 2110 return 0; 2111 2112 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2113 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 2114 /* XXX delete tx key on failure? */ 2115 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 2116 } else { 2117 /* 2118 * Room for both TX+RX MIC keys in one key cache 2119 * slot, just set key at the first index; the hal 2120 * will handle the rest. 2121 */ 2122 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2123 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 2124 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2125 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2126 } 2127 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 2128 if (sc->sc_splitmic) { 2129 /* 2130 * NB: must pass MIC key in expected location when 2131 * the keycache only holds one MIC key per entry. 2132 */ 2133 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 2134 } else 2135 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 2136 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2137 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2138 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 2139 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2140 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2141 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2142 } 2143 return 0; 2144 #undef IEEE80211_KEY_XR 2145 } 2146 2147 /* 2148 * Set a net80211 key into the hardware. This handles the 2149 * potential distribution of key state to multiple key 2150 * cache slots for TKIP with hardware MIC support. 2151 */ 2152 static int 2153 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 2154 const u_int8_t mac0[IEEE80211_ADDR_LEN], 2155 struct ieee80211_node *bss) 2156 { 2157 #define N(a) (sizeof(a)/sizeof(a[0])) 2158 static const u_int8_t ciphermap[] = { 2159 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 2160 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 2161 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 2162 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 2163 (u_int8_t) -1, /* 4 is not allocated */ 2164 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 2165 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 2166 }; 2167 struct ath_hal *ah = sc->sc_ah; 2168 const struct ieee80211_cipher *cip = k->wk_cipher; 2169 u_int8_t gmac[IEEE80211_ADDR_LEN]; 2170 const u_int8_t *mac; 2171 HAL_KEYVAL hk; 2172 2173 memset(&hk, 0, sizeof(hk)); 2174 /* 2175 * Software crypto uses a "clear key" so non-crypto 2176 * state kept in the key cache are maintained and 2177 * so that rx frames have an entry to match. 2178 */ 2179 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 2180 KASSERT(cip->ic_cipher < N(ciphermap), 2181 ("invalid cipher type %u", cip->ic_cipher)); 2182 hk.kv_type = ciphermap[cip->ic_cipher]; 2183 hk.kv_len = k->wk_keylen; 2184 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 2185 } else 2186 hk.kv_type = HAL_CIPHER_CLR; 2187 2188 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 2189 /* 2190 * Group keys on hardware that supports multicast frame 2191 * key search use a mac that is the sender's address with 2192 * the high bit set instead of the app-specified address. 2193 */ 2194 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 2195 gmac[0] |= 0x80; 2196 mac = gmac; 2197 } else 2198 mac = mac0; 2199 2200 if (hk.kv_type == HAL_CIPHER_TKIP && 2201 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2202 return ath_keyset_tkip(sc, k, &hk, mac); 2203 } else { 2204 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 2205 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 2206 } 2207 #undef N 2208 } 2209 2210 /* 2211 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2212 * each key, one for decrypt/encrypt and the other for the MIC. 2213 */ 2214 static u_int16_t 2215 key_alloc_2pair(struct ath_softc *sc, 2216 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2217 { 2218 #define N(a) (sizeof(a)/sizeof(a[0])) 2219 u_int i, keyix; 2220 2221 KASSERT(sc->sc_splitmic, ("key cache !split")); 2222 /* XXX could optimize */ 2223 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2224 u_int8_t b = sc->sc_keymap[i]; 2225 if (b != 0xff) { 2226 /* 2227 * One or more slots in this byte are free. 2228 */ 2229 keyix = i*NBBY; 2230 while (b & 1) { 2231 again: 2232 keyix++; 2233 b >>= 1; 2234 } 2235 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 2236 if (isset(sc->sc_keymap, keyix+32) || 2237 isset(sc->sc_keymap, keyix+64) || 2238 isset(sc->sc_keymap, keyix+32+64)) { 2239 /* full pair unavailable */ 2240 /* XXX statistic */ 2241 if (keyix == (i+1)*NBBY) { 2242 /* no slots were appropriate, advance */ 2243 continue; 2244 } 2245 goto again; 2246 } 2247 setbit(sc->sc_keymap, keyix); 2248 setbit(sc->sc_keymap, keyix+64); 2249 setbit(sc->sc_keymap, keyix+32); 2250 setbit(sc->sc_keymap, keyix+32+64); 2251 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2252 "%s: key pair %u,%u %u,%u\n", 2253 __func__, keyix, keyix+64, 2254 keyix+32, keyix+32+64); 2255 *txkeyix = keyix; 2256 *rxkeyix = keyix+32; 2257 return 1; 2258 } 2259 } 2260 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2261 return 0; 2262 #undef N 2263 } 2264 2265 /* 2266 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2267 * each key, one for decrypt/encrypt and the other for the MIC. 2268 */ 2269 static u_int16_t 2270 key_alloc_pair(struct ath_softc *sc, 2271 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2272 { 2273 #define N(a) (sizeof(a)/sizeof(a[0])) 2274 u_int i, keyix; 2275 2276 KASSERT(!sc->sc_splitmic, ("key cache split")); 2277 /* XXX could optimize */ 2278 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2279 u_int8_t b = sc->sc_keymap[i]; 2280 if (b != 0xff) { 2281 /* 2282 * One or more slots in this byte are free. 2283 */ 2284 keyix = i*NBBY; 2285 while (b & 1) { 2286 again: 2287 keyix++; 2288 b >>= 1; 2289 } 2290 if (isset(sc->sc_keymap, keyix+64)) { 2291 /* full pair unavailable */ 2292 /* XXX statistic */ 2293 if (keyix == (i+1)*NBBY) { 2294 /* no slots were appropriate, advance */ 2295 continue; 2296 } 2297 goto again; 2298 } 2299 setbit(sc->sc_keymap, keyix); 2300 setbit(sc->sc_keymap, keyix+64); 2301 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2302 "%s: key pair %u,%u\n", 2303 __func__, keyix, keyix+64); 2304 *txkeyix = *rxkeyix = keyix; 2305 return 1; 2306 } 2307 } 2308 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2309 return 0; 2310 #undef N 2311 } 2312 2313 /* 2314 * Allocate a single key cache slot. 2315 */ 2316 static int 2317 key_alloc_single(struct ath_softc *sc, 2318 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2319 { 2320 #define N(a) (sizeof(a)/sizeof(a[0])) 2321 u_int i, keyix; 2322 2323 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 2324 for (i = 0; i < N(sc->sc_keymap); i++) { 2325 u_int8_t b = sc->sc_keymap[i]; 2326 if (b != 0xff) { 2327 /* 2328 * One or more slots are free. 2329 */ 2330 keyix = i*NBBY; 2331 while (b & 1) 2332 keyix++, b >>= 1; 2333 setbit(sc->sc_keymap, keyix); 2334 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 2335 __func__, keyix); 2336 *txkeyix = *rxkeyix = keyix; 2337 return 1; 2338 } 2339 } 2340 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 2341 return 0; 2342 #undef N 2343 } 2344 2345 /* 2346 * Allocate one or more key cache slots for a uniacst key. The 2347 * key itself is needed only to identify the cipher. For hardware 2348 * TKIP with split cipher+MIC keys we allocate two key cache slot 2349 * pairs so that we can setup separate TX and RX MIC keys. Note 2350 * that the MIC key for a TKIP key at slot i is assumed by the 2351 * hardware to be at slot i+64. This limits TKIP keys to the first 2352 * 64 entries. 2353 */ 2354 static int 2355 ath_key_alloc(struct ieee80211vap *vap, const struct ieee80211_key *k, 2356 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2357 { 2358 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2359 2360 /* 2361 * Group key allocation must be handled specially for 2362 * parts that do not support multicast key cache search 2363 * functionality. For those parts the key id must match 2364 * the h/w key index so lookups find the right key. On 2365 * parts w/ the key search facility we install the sender's 2366 * mac address (with the high bit set) and let the hardware 2367 * find the key w/o using the key id. This is preferred as 2368 * it permits us to support multiple users for adhoc and/or 2369 * multi-station operation. 2370 */ 2371 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 2372 if (!(&vap->iv_nw_keys[0] <= k && 2373 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2374 /* should not happen */ 2375 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2376 "%s: bogus group key\n", __func__); 2377 return 0; 2378 } 2379 /* 2380 * XXX we pre-allocate the global keys so 2381 * have no way to check if they've already been allocated. 2382 */ 2383 *keyix = *rxkeyix = k - vap->iv_nw_keys; 2384 return 1; 2385 } 2386 2387 /* 2388 * We allocate two pair for TKIP when using the h/w to do 2389 * the MIC. For everything else, including software crypto, 2390 * we allocate a single entry. Note that s/w crypto requires 2391 * a pass-through slot on the 5211 and 5212. The 5210 does 2392 * not support pass-through cache entries and we map all 2393 * those requests to slot 0. 2394 */ 2395 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2396 return key_alloc_single(sc, keyix, rxkeyix); 2397 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 2398 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2399 if (sc->sc_splitmic) 2400 return key_alloc_2pair(sc, keyix, rxkeyix); 2401 else 2402 return key_alloc_pair(sc, keyix, rxkeyix); 2403 } else { 2404 return key_alloc_single(sc, keyix, rxkeyix); 2405 } 2406 } 2407 2408 /* 2409 * Delete an entry in the key cache allocated by ath_key_alloc. 2410 */ 2411 static int 2412 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2413 { 2414 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2415 struct ath_hal *ah = sc->sc_ah; 2416 const struct ieee80211_cipher *cip = k->wk_cipher; 2417 u_int keyix = k->wk_keyix; 2418 2419 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 2420 2421 ath_hal_keyreset(ah, keyix); 2422 /* 2423 * Handle split tx/rx keying required for TKIP with h/w MIC. 2424 */ 2425 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2426 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 2427 ath_hal_keyreset(ah, keyix+32); /* RX key */ 2428 if (keyix >= IEEE80211_WEP_NKID) { 2429 /* 2430 * Don't touch keymap entries for global keys so 2431 * they are never considered for dynamic allocation. 2432 */ 2433 clrbit(sc->sc_keymap, keyix); 2434 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2435 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2436 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 2437 if (sc->sc_splitmic) { 2438 /* +32 for RX key, +32+64 for RX key MIC */ 2439 clrbit(sc->sc_keymap, keyix+32); 2440 clrbit(sc->sc_keymap, keyix+32+64); 2441 } 2442 } 2443 } 2444 return 1; 2445 } 2446 2447 /* 2448 * Set the key cache contents for the specified key. Key cache 2449 * slot(s) must already have been allocated by ath_key_alloc. 2450 */ 2451 static int 2452 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 2453 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2454 { 2455 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2456 2457 return ath_keyset(sc, k, mac, vap->iv_bss); 2458 } 2459 2460 /* 2461 * Block/unblock tx+rx processing while a key change is done. 2462 * We assume the caller serializes key management operations 2463 * so we only need to worry about synchronization with other 2464 * uses that originate in the driver. 2465 */ 2466 static void 2467 ath_key_update_begin(struct ieee80211vap *vap) 2468 { 2469 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2470 struct ath_softc *sc = ifp->if_softc; 2471 2472 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2473 taskqueue_block(sc->sc_tq); 2474 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 2475 } 2476 2477 static void 2478 ath_key_update_end(struct ieee80211vap *vap) 2479 { 2480 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2481 struct ath_softc *sc = ifp->if_softc; 2482 2483 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2484 IF_UNLOCK(&ifp->if_snd); 2485 taskqueue_unblock(sc->sc_tq); 2486 } 2487 2488 /* 2489 * Calculate the receive filter according to the 2490 * operating mode and state: 2491 * 2492 * o always accept unicast, broadcast, and multicast traffic 2493 * o accept PHY error frames when hardware doesn't have MIB support 2494 * to count and we need them for ANI (sta mode only at the moment) 2495 * and we are not scanning (ANI is disabled) 2496 * NB: only with recent hal's; older hal's add rx filter bits out 2497 * of sight and we need to blindly preserve them 2498 * o probe request frames are accepted only when operating in 2499 * hostap, adhoc, or monitor modes 2500 * o enable promiscuous mode 2501 * - when in monitor mode 2502 * - if interface marked PROMISC (assumes bridge setting is filtered) 2503 * o accept beacons: 2504 * - when operating in station mode for collecting rssi data when 2505 * the station is otherwise quiet, or 2506 * - when operating in adhoc mode so the 802.11 layer creates 2507 * node table entries for peers, 2508 * - when scanning 2509 * - when doing s/w beacon miss (e.g. for ap+sta) 2510 * - when operating in ap mode in 11g to detect overlapping bss that 2511 * require protection 2512 * o accept control frames: 2513 * - when in monitor mode 2514 * XXX BAR frames for 11n 2515 * XXX HT protection for 11n 2516 */ 2517 static u_int32_t 2518 ath_calcrxfilter(struct ath_softc *sc) 2519 { 2520 struct ifnet *ifp = sc->sc_ifp; 2521 struct ieee80211com *ic = ifp->if_l2com; 2522 u_int32_t rfilt; 2523 2524 #if HAL_ABI_VERSION < 0x08011600 2525 rfilt = (ath_hal_getrxfilter(sc->sc_ah) & 2526 (HAL_RX_FILTER_PHYRADAR | HAL_RX_FILTER_PHYERR)) 2527 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2528 #else 2529 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2530 if (ic->ic_opmode == IEEE80211_M_STA && 2531 !sc->sc_needmib && !sc->sc_scanning) 2532 rfilt |= HAL_RX_FILTER_PHYERR; 2533 #endif 2534 if (ic->ic_opmode != IEEE80211_M_STA) 2535 rfilt |= HAL_RX_FILTER_PROBEREQ; 2536 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 2537 rfilt |= HAL_RX_FILTER_PROM; 2538 if (ic->ic_opmode == IEEE80211_M_STA || 2539 sc->sc_opmode == HAL_M_IBSS || 2540 sc->sc_swbmiss || sc->sc_scanning) 2541 rfilt |= HAL_RX_FILTER_BEACON; 2542 /* 2543 * NB: We don't recalculate the rx filter when 2544 * ic_protmode changes; otherwise we could do 2545 * this only when ic_protmode != NONE. 2546 */ 2547 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 2548 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 2549 rfilt |= HAL_RX_FILTER_BEACON; 2550 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2551 rfilt |= HAL_RX_FILTER_CONTROL; 2552 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 2553 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 2554 return rfilt; 2555 } 2556 2557 static void 2558 ath_update_promisc(struct ifnet *ifp) 2559 { 2560 struct ath_softc *sc = ifp->if_softc; 2561 u_int32_t rfilt; 2562 2563 /* configure rx filter */ 2564 rfilt = ath_calcrxfilter(sc); 2565 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2566 2567 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2568 } 2569 2570 static void 2571 ath_update_mcast(struct ifnet *ifp) 2572 { 2573 struct ath_softc *sc = ifp->if_softc; 2574 u_int32_t mfilt[2]; 2575 2576 /* calculate and install multicast filter */ 2577 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2578 struct ifmultiaddr *ifma; 2579 /* 2580 * Merge multicast addresses to form the hardware filter. 2581 */ 2582 mfilt[0] = mfilt[1] = 0; 2583 IF_ADDR_LOCK(ifp); /* XXX need some fiddling to remove? */ 2584 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2585 caddr_t dl; 2586 u_int32_t val; 2587 u_int8_t pos; 2588 2589 /* calculate XOR of eight 6bit values */ 2590 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2591 val = LE_READ_4(dl + 0); 2592 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2593 val = LE_READ_4(dl + 3); 2594 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2595 pos &= 0x3f; 2596 mfilt[pos / 32] |= (1 << (pos % 32)); 2597 } 2598 IF_ADDR_UNLOCK(ifp); 2599 } else 2600 mfilt[0] = mfilt[1] = ~0; 2601 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2602 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2603 __func__, mfilt[0], mfilt[1]); 2604 } 2605 2606 static void 2607 ath_mode_init(struct ath_softc *sc) 2608 { 2609 struct ifnet *ifp = sc->sc_ifp; 2610 struct ieee80211com *ic = ifp->if_l2com; 2611 struct ath_hal *ah = sc->sc_ah; 2612 u_int32_t rfilt; 2613 2614 /* configure rx filter */ 2615 rfilt = ath_calcrxfilter(sc); 2616 ath_hal_setrxfilter(ah, rfilt); 2617 2618 /* configure operational mode */ 2619 ath_hal_setopmode(ah); 2620 2621 /* 2622 * Handle any link-level address change. Note that we only 2623 * need to force ic_myaddr; any other addresses are handled 2624 * as a byproduct of the ifnet code marking the interface 2625 * down then up. 2626 * 2627 * XXX should get from lladdr instead of arpcom but that's more work 2628 */ 2629 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2630 ath_hal_setmac(ah, ic->ic_myaddr); 2631 2632 /* calculate and install multicast filter */ 2633 ath_update_mcast(ifp); 2634 } 2635 2636 /* 2637 * Set the slot time based on the current setting. 2638 */ 2639 static void 2640 ath_setslottime(struct ath_softc *sc) 2641 { 2642 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2643 struct ath_hal *ah = sc->sc_ah; 2644 u_int usec; 2645 2646 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2647 usec = 13; 2648 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2649 usec = 21; 2650 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2651 /* honor short/long slot time only in 11g */ 2652 /* XXX shouldn't honor on pure g or turbo g channel */ 2653 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2654 usec = HAL_SLOT_TIME_9; 2655 else 2656 usec = HAL_SLOT_TIME_20; 2657 } else 2658 usec = HAL_SLOT_TIME_9; 2659 2660 DPRINTF(sc, ATH_DEBUG_RESET, 2661 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2662 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2663 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2664 2665 ath_hal_setslottime(ah, usec); 2666 sc->sc_updateslot = OK; 2667 } 2668 2669 /* 2670 * Callback from the 802.11 layer to update the 2671 * slot time based on the current setting. 2672 */ 2673 static void 2674 ath_updateslot(struct ifnet *ifp) 2675 { 2676 struct ath_softc *sc = ifp->if_softc; 2677 struct ieee80211com *ic = ifp->if_l2com; 2678 2679 /* 2680 * When not coordinating the BSS, change the hardware 2681 * immediately. For other operation we defer the change 2682 * until beacon updates have propagated to the stations. 2683 */ 2684 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 2685 sc->sc_updateslot = UPDATE; 2686 else 2687 ath_setslottime(sc); 2688 } 2689 2690 /* 2691 * Setup a h/w transmit queue for beacons. 2692 */ 2693 static int 2694 ath_beaconq_setup(struct ath_hal *ah) 2695 { 2696 HAL_TXQ_INFO qi; 2697 2698 memset(&qi, 0, sizeof(qi)); 2699 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2700 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2701 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2702 /* NB: for dynamic turbo, don't enable any other interrupts */ 2703 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2704 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2705 } 2706 2707 /* 2708 * Setup the transmit queue parameters for the beacon queue. 2709 */ 2710 static int 2711 ath_beaconq_config(struct ath_softc *sc) 2712 { 2713 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2714 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2715 struct ath_hal *ah = sc->sc_ah; 2716 HAL_TXQ_INFO qi; 2717 2718 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2719 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2720 /* 2721 * Always burst out beacon and CAB traffic. 2722 */ 2723 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2724 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2725 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2726 } else { 2727 struct wmeParams *wmep = 2728 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2729 /* 2730 * Adhoc mode; important thing is to use 2x cwmin. 2731 */ 2732 qi.tqi_aifs = wmep->wmep_aifsn; 2733 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2734 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2735 } 2736 2737 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2738 device_printf(sc->sc_dev, "unable to update parameters for " 2739 "beacon hardware queue!\n"); 2740 return 0; 2741 } else { 2742 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2743 return 1; 2744 } 2745 #undef ATH_EXPONENT_TO_VALUE 2746 } 2747 2748 /* 2749 * Allocate and setup an initial beacon frame. 2750 */ 2751 static int 2752 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2753 { 2754 struct ieee80211vap *vap = ni->ni_vap; 2755 struct ath_vap *avp = ATH_VAP(vap); 2756 struct ath_buf *bf; 2757 struct mbuf *m; 2758 int error; 2759 2760 bf = avp->av_bcbuf; 2761 if (bf->bf_m != NULL) { 2762 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2763 m_freem(bf->bf_m); 2764 bf->bf_m = NULL; 2765 } 2766 if (bf->bf_node != NULL) { 2767 ieee80211_free_node(bf->bf_node); 2768 bf->bf_node = NULL; 2769 } 2770 2771 /* 2772 * NB: the beacon data buffer must be 32-bit aligned; 2773 * we assume the mbuf routines will return us something 2774 * with this alignment (perhaps should assert). 2775 */ 2776 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 2777 if (m == NULL) { 2778 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 2779 sc->sc_stats.ast_be_nombuf++; 2780 return ENOMEM; 2781 } 2782 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 2783 bf->bf_segs, &bf->bf_nseg, 2784 BUS_DMA_NOWAIT); 2785 if (error != 0) { 2786 device_printf(sc->sc_dev, 2787 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 2788 __func__, error); 2789 m_freem(m); 2790 return error; 2791 } 2792 2793 /* 2794 * Calculate a TSF adjustment factor required for staggered 2795 * beacons. Note that we assume the format of the beacon 2796 * frame leaves the tstamp field immediately following the 2797 * header. 2798 */ 2799 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 2800 uint64_t tsfadjust; 2801 struct ieee80211_frame *wh; 2802 2803 /* 2804 * The beacon interval is in TU's; the TSF is in usecs. 2805 * We figure out how many TU's to add to align the timestamp 2806 * then convert to TSF units and handle byte swapping before 2807 * inserting it in the frame. The hardware will then add this 2808 * each time a beacon frame is sent. Note that we align vap's 2809 * 1..N and leave vap 0 untouched. This means vap 0 has a 2810 * timestamp in one beacon interval while the others get a 2811 * timstamp aligned to the next interval. 2812 */ 2813 tsfadjust = ni->ni_intval * 2814 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 2815 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 2816 2817 DPRINTF(sc, ATH_DEBUG_BEACON, 2818 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 2819 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 2820 avp->av_bslot, ni->ni_intval, le64toh(tsfadjust)); 2821 2822 wh = mtod(m, struct ieee80211_frame *); 2823 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 2824 } 2825 bf->bf_m = m; 2826 bf->bf_node = ieee80211_ref_node(ni); 2827 2828 return 0; 2829 } 2830 2831 /* 2832 * Setup the beacon frame for transmit. 2833 */ 2834 static void 2835 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2836 { 2837 #define USE_SHPREAMBLE(_ic) \ 2838 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2839 == IEEE80211_F_SHPREAMBLE) 2840 struct ieee80211_node *ni = bf->bf_node; 2841 struct ieee80211com *ic = ni->ni_ic; 2842 struct mbuf *m = bf->bf_m; 2843 struct ath_hal *ah = sc->sc_ah; 2844 struct ath_desc *ds; 2845 int flags, antenna; 2846 const HAL_RATE_TABLE *rt; 2847 u_int8_t rix, rate; 2848 2849 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2850 __func__, m, m->m_len); 2851 2852 /* setup descriptors */ 2853 ds = bf->bf_desc; 2854 2855 flags = HAL_TXDESC_NOACK; 2856 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2857 ds->ds_link = bf->bf_daddr; /* self-linked */ 2858 flags |= HAL_TXDESC_VEOL; 2859 /* 2860 * Let hardware handle antenna switching. 2861 */ 2862 antenna = sc->sc_txantenna; 2863 } else { 2864 ds->ds_link = 0; 2865 /* 2866 * Switch antenna every 4 beacons. 2867 * XXX assumes two antenna 2868 */ 2869 if (sc->sc_txantenna != 0) 2870 antenna = sc->sc_txantenna; 2871 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 2872 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 2873 else 2874 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2875 } 2876 2877 KASSERT(bf->bf_nseg == 1, 2878 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2879 ds->ds_data = bf->bf_segs[0].ds_addr; 2880 /* 2881 * Calculate rate code. 2882 * XXX everything at min xmit rate 2883 */ 2884 rix = 0; 2885 rt = sc->sc_currates; 2886 rate = rt->info[rix].rateCode; 2887 if (USE_SHPREAMBLE(ic)) 2888 rate |= rt->info[rix].shortPreamble; 2889 ath_hal_setuptxdesc(ah, ds 2890 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2891 , sizeof(struct ieee80211_frame)/* header length */ 2892 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2893 , ni->ni_txpower /* txpower XXX */ 2894 , rate, 1 /* series 0 rate/tries */ 2895 , HAL_TXKEYIX_INVALID /* no encryption */ 2896 , antenna /* antenna mode */ 2897 , flags /* no ack, veol for beacons */ 2898 , 0 /* rts/cts rate */ 2899 , 0 /* rts/cts duration */ 2900 ); 2901 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2902 ath_hal_filltxdesc(ah, ds 2903 , roundup(m->m_len, 4) /* buffer length */ 2904 , AH_TRUE /* first segment */ 2905 , AH_TRUE /* last segment */ 2906 , ds /* first descriptor */ 2907 ); 2908 #if 0 2909 ath_desc_swap(ds); 2910 #endif 2911 #undef USE_SHPREAMBLE 2912 } 2913 2914 static void 2915 ath_beacon_update(struct ieee80211vap *vap, int item) 2916 { 2917 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 2918 2919 setbit(bo->bo_flags, item); 2920 } 2921 2922 /* 2923 * Append the contents of src to dst; both queues 2924 * are assumed to be locked. 2925 */ 2926 static void 2927 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2928 { 2929 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 2930 dst->axq_link = src->axq_link; 2931 src->axq_link = NULL; 2932 dst->axq_depth += src->axq_depth; 2933 src->axq_depth = 0; 2934 } 2935 2936 /* 2937 * Transmit a beacon frame at SWBA. Dynamic updates to the 2938 * frame contents are done as needed and the slot time is 2939 * also adjusted based on current state. 2940 */ 2941 static void 2942 ath_beacon_proc(void *arg, int pending) 2943 { 2944 struct ath_softc *sc = arg; 2945 struct ath_hal *ah = sc->sc_ah; 2946 struct ieee80211vap *vap; 2947 struct ath_buf *bf; 2948 int slot, otherant; 2949 uint32_t bfaddr; 2950 2951 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2952 __func__, pending); 2953 /* 2954 * Check if the previous beacon has gone out. If 2955 * not don't try to post another, skip this period 2956 * and wait for the next. Missed beacons indicate 2957 * a problem and should not occur. If we miss too 2958 * many consecutive beacons reset the device. 2959 */ 2960 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2961 sc->sc_bmisscount++; 2962 DPRINTF(sc, ATH_DEBUG_BEACON, 2963 "%s: missed %u consecutive beacons\n", 2964 __func__, sc->sc_bmisscount); 2965 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 2966 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2967 return; 2968 } 2969 if (sc->sc_bmisscount != 0) { 2970 DPRINTF(sc, ATH_DEBUG_BEACON, 2971 "%s: resume beacon xmit after %u misses\n", 2972 __func__, sc->sc_bmisscount); 2973 sc->sc_bmisscount = 0; 2974 } 2975 2976 if (sc->sc_stagbeacons) { /* staggered beacons */ 2977 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2978 uint32_t tsftu; 2979 2980 tsftu = ath_hal_gettsf32(ah) >> 10; 2981 /* XXX lintval */ 2982 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 2983 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 2984 bfaddr = 0; 2985 if (vap != NULL && vap->iv_state == IEEE80211_S_RUN) { 2986 bf = ath_beacon_generate(sc, vap); 2987 if (bf != NULL) 2988 bfaddr = bf->bf_daddr; 2989 } 2990 } else { /* burst'd beacons */ 2991 uint32_t *bflink = &bfaddr; 2992 2993 for (slot = 0; slot < ATH_BCBUF; slot++) { 2994 vap = sc->sc_bslot[slot]; 2995 if (vap != NULL && vap->iv_state == IEEE80211_S_RUN) { 2996 bf = ath_beacon_generate(sc, vap); 2997 if (bf != NULL) { 2998 *bflink = bf->bf_daddr; 2999 bflink = &bf->bf_desc->ds_link; 3000 } 3001 } 3002 } 3003 *bflink = 0; /* terminate list */ 3004 } 3005 3006 /* 3007 * Handle slot time change when a non-ERP station joins/leaves 3008 * an 11g network. The 802.11 layer notifies us via callback, 3009 * we mark updateslot, then wait one beacon before effecting 3010 * the change. This gives associated stations at least one 3011 * beacon interval to note the state change. 3012 */ 3013 /* XXX locking */ 3014 if (sc->sc_updateslot == UPDATE) { 3015 sc->sc_updateslot = COMMIT; /* commit next beacon */ 3016 sc->sc_slotupdate = slot; 3017 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 3018 ath_setslottime(sc); /* commit change to h/w */ 3019 3020 /* 3021 * Check recent per-antenna transmit statistics and flip 3022 * the default antenna if noticeably more frames went out 3023 * on the non-default antenna. 3024 * XXX assumes 2 anntenae 3025 */ 3026 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 3027 otherant = sc->sc_defant & 1 ? 2 : 1; 3028 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 3029 ath_setdefantenna(sc, otherant); 3030 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 3031 } 3032 3033 if (bfaddr != 0) { 3034 /* 3035 * Stop any current dma and put the new frame on the queue. 3036 * This should never fail since we check above that no frames 3037 * are still pending on the queue. 3038 */ 3039 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 3040 DPRINTF(sc, ATH_DEBUG_ANY, 3041 "%s: beacon queue %u did not stop?\n", 3042 __func__, sc->sc_bhalq); 3043 } 3044 /* NB: cabq traffic should already be queued and primed */ 3045 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 3046 ath_hal_txstart(ah, sc->sc_bhalq); 3047 3048 sc->sc_stats.ast_be_xmit++; 3049 } 3050 } 3051 3052 static struct ath_buf * 3053 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 3054 { 3055 struct ath_vap *avp = ATH_VAP(vap); 3056 struct ath_txq *cabq = sc->sc_cabq; 3057 struct ath_buf *bf; 3058 struct mbuf *m; 3059 int nmcastq, error; 3060 3061 KASSERT(vap->iv_state == IEEE80211_S_RUN, 3062 ("not running, state %d", vap->iv_state)); 3063 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3064 3065 /* 3066 * Update dynamic beacon contents. If this returns 3067 * non-zero then we need to remap the memory because 3068 * the beacon frame changed size (probably because 3069 * of the TIM bitmap). 3070 */ 3071 bf = avp->av_bcbuf; 3072 m = bf->bf_m; 3073 nmcastq = avp->av_mcastq.axq_depth; 3074 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 3075 /* XXX too conservative? */ 3076 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3077 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 3078 bf->bf_segs, &bf->bf_nseg, 3079 BUS_DMA_NOWAIT); 3080 if (error != 0) { 3081 if_printf(vap->iv_ifp, 3082 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 3083 __func__, error); 3084 return NULL; 3085 } 3086 } 3087 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 3088 DPRINTF(sc, ATH_DEBUG_BEACON, 3089 "%s: cabq did not drain, mcastq %u cabq %u\n", 3090 __func__, nmcastq, cabq->axq_depth); 3091 sc->sc_stats.ast_cabq_busy++; 3092 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 3093 /* 3094 * CABQ traffic from a previous vap is still pending. 3095 * We must drain the q before this beacon frame goes 3096 * out as otherwise this vap's stations will get cab 3097 * frames from a different vap. 3098 * XXX could be slow causing us to miss DBA 3099 */ 3100 ath_tx_draintxq(sc, cabq); 3101 } 3102 } 3103 ath_beacon_setup(sc, bf); 3104 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3105 3106 /* 3107 * Enable the CAB queue before the beacon queue to 3108 * insure cab frames are triggered by this beacon. 3109 */ 3110 if (avp->av_boff.bo_tim[4] & 1) { 3111 struct ath_hal *ah = sc->sc_ah; 3112 3113 /* NB: only at DTIM */ 3114 ATH_TXQ_LOCK(cabq); 3115 ATH_TXQ_LOCK(&avp->av_mcastq); 3116 if (nmcastq) { 3117 struct ath_buf *bfm; 3118 3119 /* 3120 * Move frames from the s/w mcast q to the h/w cab q. 3121 * XXX MORE_DATA bit 3122 */ 3123 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q); 3124 if (cabq->axq_link != NULL) { 3125 *cabq->axq_link = bfm->bf_daddr; 3126 } else 3127 ath_hal_puttxbuf(ah, cabq->axq_qnum, 3128 bfm->bf_daddr); 3129 ath_txqmove(cabq, &avp->av_mcastq); 3130 3131 sc->sc_stats.ast_cabq_xmit += nmcastq; 3132 } 3133 /* NB: gated by beacon so safe to start here */ 3134 ath_hal_txstart(ah, cabq->axq_qnum); 3135 ATH_TXQ_UNLOCK(cabq); 3136 ATH_TXQ_UNLOCK(&avp->av_mcastq); 3137 } 3138 return bf; 3139 } 3140 3141 static void 3142 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 3143 { 3144 struct ath_vap *avp = ATH_VAP(vap); 3145 struct ath_hal *ah = sc->sc_ah; 3146 struct ath_buf *bf; 3147 struct mbuf *m; 3148 int error; 3149 3150 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3151 3152 /* 3153 * Update dynamic beacon contents. If this returns 3154 * non-zero then we need to remap the memory because 3155 * the beacon frame changed size (probably because 3156 * of the TIM bitmap). 3157 */ 3158 bf = avp->av_bcbuf; 3159 m = bf->bf_m; 3160 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 3161 /* XXX too conservative? */ 3162 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3163 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 3164 bf->bf_segs, &bf->bf_nseg, 3165 BUS_DMA_NOWAIT); 3166 if (error != 0) { 3167 if_printf(vap->iv_ifp, 3168 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 3169 __func__, error); 3170 return; 3171 } 3172 } 3173 ath_beacon_setup(sc, bf); 3174 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3175 3176 /* NB: caller is known to have already stopped tx dma */ 3177 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 3178 ath_hal_txstart(ah, sc->sc_bhalq); 3179 } 3180 3181 /* 3182 * Reset the hardware after detecting beacons have stopped. 3183 */ 3184 static void 3185 ath_bstuck_proc(void *arg, int pending) 3186 { 3187 struct ath_softc *sc = arg; 3188 struct ifnet *ifp = sc->sc_ifp; 3189 3190 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3191 sc->sc_bmisscount); 3192 ath_reset(ifp); 3193 } 3194 3195 /* 3196 * Reclaim beacon resources and return buffer to the pool. 3197 */ 3198 static void 3199 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 3200 { 3201 3202 if (bf->bf_m != NULL) { 3203 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3204 m_freem(bf->bf_m); 3205 bf->bf_m = NULL; 3206 } 3207 if (bf->bf_node != NULL) { 3208 ieee80211_free_node(bf->bf_node); 3209 bf->bf_node = NULL; 3210 } 3211 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 3212 } 3213 3214 /* 3215 * Reclaim beacon resources. 3216 */ 3217 static void 3218 ath_beacon_free(struct ath_softc *sc) 3219 { 3220 struct ath_buf *bf; 3221 3222 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 3223 if (bf->bf_m != NULL) { 3224 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3225 m_freem(bf->bf_m); 3226 bf->bf_m = NULL; 3227 } 3228 if (bf->bf_node != NULL) { 3229 ieee80211_free_node(bf->bf_node); 3230 bf->bf_node = NULL; 3231 } 3232 } 3233 } 3234 3235 /* 3236 * Configure the beacon and sleep timers. 3237 * 3238 * When operating as an AP this resets the TSF and sets 3239 * up the hardware to notify us when we need to issue beacons. 3240 * 3241 * When operating in station mode this sets up the beacon 3242 * timers according to the timestamp of the last received 3243 * beacon and the current TSF, configures PCF and DTIM 3244 * handling, programs the sleep registers so the hardware 3245 * will wakeup in time to receive beacons, and configures 3246 * the beacon miss handling so we'll receive a BMISS 3247 * interrupt when we stop seeing beacons from the AP 3248 * we've associated with. 3249 */ 3250 static void 3251 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 3252 { 3253 #define TSF_TO_TU(_h,_l) \ 3254 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 3255 #define FUDGE 2 3256 struct ath_hal *ah = sc->sc_ah; 3257 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3258 struct ieee80211_node *ni; 3259 u_int32_t nexttbtt, intval, tsftu; 3260 u_int64_t tsf; 3261 3262 if (vap == NULL) 3263 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 3264 ni = vap->iv_bss; 3265 3266 /* extract tstamp from last beacon and convert to TU */ 3267 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 3268 LE_READ_4(ni->ni_tstamp.data)); 3269 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3270 /* 3271 * For multi-bss ap support beacons are either staggered 3272 * evenly over N slots or burst together. For the former 3273 * arrange for the SWBA to be delivered for each slot. 3274 * Slots that are not occupied will generate nothing. 3275 */ 3276 /* NB: the beacon interval is kept internally in TU's */ 3277 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3278 if (sc->sc_stagbeacons) 3279 intval /= ATH_BCBUF; 3280 } else { 3281 /* NB: the beacon interval is kept internally in TU's */ 3282 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3283 } 3284 if (nexttbtt == 0) /* e.g. for ap mode */ 3285 nexttbtt = intval; 3286 else if (intval) /* NB: can be 0 for monitor mode */ 3287 nexttbtt = roundup(nexttbtt, intval); 3288 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 3289 __func__, nexttbtt, intval, ni->ni_intval); 3290 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 3291 HAL_BEACON_STATE bs; 3292 int dtimperiod, dtimcount; 3293 int cfpperiod, cfpcount; 3294 3295 /* 3296 * Setup dtim and cfp parameters according to 3297 * last beacon we received (which may be none). 3298 */ 3299 dtimperiod = ni->ni_dtim_period; 3300 if (dtimperiod <= 0) /* NB: 0 if not known */ 3301 dtimperiod = 1; 3302 dtimcount = ni->ni_dtim_count; 3303 if (dtimcount >= dtimperiod) /* NB: sanity check */ 3304 dtimcount = 0; /* XXX? */ 3305 cfpperiod = 1; /* NB: no PCF support yet */ 3306 cfpcount = 0; 3307 /* 3308 * Pull nexttbtt forward to reflect the current 3309 * TSF and calculate dtim+cfp state for the result. 3310 */ 3311 tsf = ath_hal_gettsf64(ah); 3312 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3313 do { 3314 nexttbtt += intval; 3315 if (--dtimcount < 0) { 3316 dtimcount = dtimperiod - 1; 3317 if (--cfpcount < 0) 3318 cfpcount = cfpperiod - 1; 3319 } 3320 } while (nexttbtt < tsftu); 3321 memset(&bs, 0, sizeof(bs)); 3322 bs.bs_intval = intval; 3323 bs.bs_nexttbtt = nexttbtt; 3324 bs.bs_dtimperiod = dtimperiod*intval; 3325 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 3326 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 3327 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 3328 bs.bs_cfpmaxduration = 0; 3329 #if 0 3330 /* 3331 * The 802.11 layer records the offset to the DTIM 3332 * bitmap while receiving beacons; use it here to 3333 * enable h/w detection of our AID being marked in 3334 * the bitmap vector (to indicate frames for us are 3335 * pending at the AP). 3336 * XXX do DTIM handling in s/w to WAR old h/w bugs 3337 * XXX enable based on h/w rev for newer chips 3338 */ 3339 bs.bs_timoffset = ni->ni_timoff; 3340 #endif 3341 /* 3342 * Calculate the number of consecutive beacons to miss 3343 * before taking a BMISS interrupt. 3344 * Note that we clamp the result to at most 10 beacons. 3345 */ 3346 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 3347 if (bs.bs_bmissthreshold > 10) 3348 bs.bs_bmissthreshold = 10; 3349 else if (bs.bs_bmissthreshold <= 0) 3350 bs.bs_bmissthreshold = 1; 3351 3352 /* 3353 * Calculate sleep duration. The configuration is 3354 * given in ms. We insure a multiple of the beacon 3355 * period is used. Also, if the sleep duration is 3356 * greater than the DTIM period then it makes senses 3357 * to make it a multiple of that. 3358 * 3359 * XXX fixed at 100ms 3360 */ 3361 bs.bs_sleepduration = 3362 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 3363 if (bs.bs_sleepduration > bs.bs_dtimperiod) 3364 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 3365 3366 DPRINTF(sc, ATH_DEBUG_BEACON, 3367 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 3368 , __func__ 3369 , tsf, tsftu 3370 , bs.bs_intval 3371 , bs.bs_nexttbtt 3372 , bs.bs_dtimperiod 3373 , bs.bs_nextdtim 3374 , bs.bs_bmissthreshold 3375 , bs.bs_sleepduration 3376 , bs.bs_cfpperiod 3377 , bs.bs_cfpmaxduration 3378 , bs.bs_cfpnext 3379 , bs.bs_timoffset 3380 ); 3381 ath_hal_intrset(ah, 0); 3382 ath_hal_beacontimers(ah, &bs); 3383 sc->sc_imask |= HAL_INT_BMISS; 3384 ath_hal_intrset(ah, sc->sc_imask); 3385 } else { 3386 ath_hal_intrset(ah, 0); 3387 if (nexttbtt == intval) 3388 intval |= HAL_BEACON_RESET_TSF; 3389 if (ic->ic_opmode == IEEE80211_M_IBSS) { 3390 /* 3391 * In IBSS mode enable the beacon timers but only 3392 * enable SWBA interrupts if we need to manually 3393 * prepare beacon frames. Otherwise we use a 3394 * self-linked tx descriptor and let the hardware 3395 * deal with things. 3396 */ 3397 intval |= HAL_BEACON_ENA; 3398 if (!sc->sc_hasveol) 3399 sc->sc_imask |= HAL_INT_SWBA; 3400 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 3401 /* 3402 * Pull nexttbtt forward to reflect 3403 * the current TSF. 3404 */ 3405 tsf = ath_hal_gettsf64(ah); 3406 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3407 do { 3408 nexttbtt += intval; 3409 } while (nexttbtt < tsftu); 3410 } 3411 ath_beaconq_config(sc); 3412 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3413 /* 3414 * In AP mode we enable the beacon timers and 3415 * SWBA interrupts to prepare beacon frames. 3416 */ 3417 intval |= HAL_BEACON_ENA; 3418 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 3419 ath_beaconq_config(sc); 3420 } 3421 ath_hal_beaconinit(ah, nexttbtt, intval); 3422 sc->sc_bmisscount = 0; 3423 ath_hal_intrset(ah, sc->sc_imask); 3424 /* 3425 * When using a self-linked beacon descriptor in 3426 * ibss mode load it once here. 3427 */ 3428 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 3429 ath_beacon_start_adhoc(sc, vap); 3430 } 3431 sc->sc_syncbeacon = 0; 3432 #undef FUDGE 3433 #undef TSF_TO_TU 3434 } 3435 3436 static void 3437 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3438 { 3439 bus_addr_t *paddr = (bus_addr_t*) arg; 3440 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3441 *paddr = segs->ds_addr; 3442 } 3443 3444 static int 3445 ath_descdma_setup(struct ath_softc *sc, 3446 struct ath_descdma *dd, ath_bufhead *head, 3447 const char *name, int nbuf, int ndesc) 3448 { 3449 #define DS2PHYS(_dd, _ds) \ 3450 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3451 struct ifnet *ifp = sc->sc_ifp; 3452 struct ath_desc *ds; 3453 struct ath_buf *bf; 3454 int i, bsize, error; 3455 3456 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 3457 __func__, name, nbuf, ndesc); 3458 3459 dd->dd_name = name; 3460 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 3461 3462 /* 3463 * Setup DMA descriptor area. 3464 */ 3465 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 3466 PAGE_SIZE, 0, /* alignment, bounds */ 3467 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3468 BUS_SPACE_MAXADDR, /* highaddr */ 3469 NULL, NULL, /* filter, filterarg */ 3470 dd->dd_desc_len, /* maxsize */ 3471 1, /* nsegments */ 3472 dd->dd_desc_len, /* maxsegsize */ 3473 BUS_DMA_ALLOCNOW, /* flags */ 3474 NULL, /* lockfunc */ 3475 NULL, /* lockarg */ 3476 &dd->dd_dmat); 3477 if (error != 0) { 3478 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3479 return error; 3480 } 3481 3482 /* allocate descriptors */ 3483 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3484 if (error != 0) { 3485 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3486 "error %u\n", dd->dd_name, error); 3487 goto fail0; 3488 } 3489 3490 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3491 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3492 &dd->dd_dmamap); 3493 if (error != 0) { 3494 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3495 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3496 goto fail1; 3497 } 3498 3499 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3500 dd->dd_desc, dd->dd_desc_len, 3501 ath_load_cb, &dd->dd_desc_paddr, 3502 BUS_DMA_NOWAIT); 3503 if (error != 0) { 3504 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3505 dd->dd_name, error); 3506 goto fail2; 3507 } 3508 3509 ds = dd->dd_desc; 3510 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3511 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3512 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3513 3514 /* allocate rx buffers */ 3515 bsize = sizeof(struct ath_buf) * nbuf; 3516 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 3517 if (bf == NULL) { 3518 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3519 dd->dd_name, bsize); 3520 goto fail3; 3521 } 3522 dd->dd_bufptr = bf; 3523 3524 STAILQ_INIT(head); 3525 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 3526 bf->bf_desc = ds; 3527 bf->bf_daddr = DS2PHYS(dd, ds); 3528 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3529 &bf->bf_dmamap); 3530 if (error != 0) { 3531 if_printf(ifp, "unable to create dmamap for %s " 3532 "buffer %u, error %u\n", dd->dd_name, i, error); 3533 ath_descdma_cleanup(sc, dd, head); 3534 return error; 3535 } 3536 STAILQ_INSERT_TAIL(head, bf, bf_list); 3537 } 3538 return 0; 3539 fail3: 3540 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3541 fail2: 3542 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3543 fail1: 3544 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3545 fail0: 3546 bus_dma_tag_destroy(dd->dd_dmat); 3547 memset(dd, 0, sizeof(*dd)); 3548 return error; 3549 #undef DS2PHYS 3550 } 3551 3552 static void 3553 ath_descdma_cleanup(struct ath_softc *sc, 3554 struct ath_descdma *dd, ath_bufhead *head) 3555 { 3556 struct ath_buf *bf; 3557 struct ieee80211_node *ni; 3558 3559 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3560 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3561 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3562 bus_dma_tag_destroy(dd->dd_dmat); 3563 3564 STAILQ_FOREACH(bf, head, bf_list) { 3565 if (bf->bf_m) { 3566 m_freem(bf->bf_m); 3567 bf->bf_m = NULL; 3568 } 3569 if (bf->bf_dmamap != NULL) { 3570 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3571 bf->bf_dmamap = NULL; 3572 } 3573 ni = bf->bf_node; 3574 bf->bf_node = NULL; 3575 if (ni != NULL) { 3576 /* 3577 * Reclaim node reference. 3578 */ 3579 ieee80211_free_node(ni); 3580 } 3581 } 3582 3583 STAILQ_INIT(head); 3584 free(dd->dd_bufptr, M_ATHDEV); 3585 memset(dd, 0, sizeof(*dd)); 3586 } 3587 3588 static int 3589 ath_desc_alloc(struct ath_softc *sc) 3590 { 3591 int error; 3592 3593 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3594 "rx", ath_rxbuf, 1); 3595 if (error != 0) 3596 return error; 3597 3598 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3599 "tx", ath_txbuf, ATH_TXDESC); 3600 if (error != 0) { 3601 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3602 return error; 3603 } 3604 3605 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3606 "beacon", ATH_BCBUF, 1); 3607 if (error != 0) { 3608 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3609 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3610 return error; 3611 } 3612 return 0; 3613 } 3614 3615 static void 3616 ath_desc_free(struct ath_softc *sc) 3617 { 3618 3619 if (sc->sc_bdma.dd_desc_len != 0) 3620 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3621 if (sc->sc_txdma.dd_desc_len != 0) 3622 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3623 if (sc->sc_rxdma.dd_desc_len != 0) 3624 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3625 } 3626 3627 static struct ieee80211_node * 3628 ath_node_alloc(struct ieee80211_node_table *nt) 3629 { 3630 struct ieee80211com *ic = nt->nt_ic; 3631 struct ath_softc *sc = ic->ic_ifp->if_softc; 3632 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3633 struct ath_node *an; 3634 3635 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 3636 if (an == NULL) { 3637 /* XXX stat+msg */ 3638 return NULL; 3639 } 3640 ath_rate_node_init(sc, an); 3641 3642 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3643 return &an->an_node; 3644 } 3645 3646 static void 3647 ath_node_free(struct ieee80211_node *ni) 3648 { 3649 struct ieee80211com *ic = ni->ni_ic; 3650 struct ath_softc *sc = ic->ic_ifp->if_softc; 3651 3652 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3653 3654 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3655 sc->sc_node_free(ni); 3656 } 3657 3658 static void 3659 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3660 { 3661 struct ieee80211com *ic = ni->ni_ic; 3662 struct ath_softc *sc = ic->ic_ifp->if_softc; 3663 struct ath_hal *ah = sc->sc_ah; 3664 HAL_CHANNEL hchan; 3665 3666 *rssi = ic->ic_node_getrssi(ni); 3667 if (ni->ni_chan != IEEE80211_CHAN_ANYC) { 3668 ath_mapchan(&hchan, ni->ni_chan); 3669 *noise = ath_hal_getchannoise(ah, &hchan); 3670 } else 3671 *noise = -95; /* nominally correct */ 3672 } 3673 3674 static int 3675 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3676 { 3677 struct ath_hal *ah = sc->sc_ah; 3678 int error; 3679 struct mbuf *m; 3680 struct ath_desc *ds; 3681 3682 m = bf->bf_m; 3683 if (m == NULL) { 3684 /* 3685 * NB: by assigning a page to the rx dma buffer we 3686 * implicitly satisfy the Atheros requirement that 3687 * this buffer be cache-line-aligned and sized to be 3688 * multiple of the cache line size. Not doing this 3689 * causes weird stuff to happen (for the 5210 at least). 3690 */ 3691 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3692 if (m == NULL) { 3693 DPRINTF(sc, ATH_DEBUG_ANY, 3694 "%s: no mbuf/cluster\n", __func__); 3695 sc->sc_stats.ast_rx_nombuf++; 3696 return ENOMEM; 3697 } 3698 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3699 3700 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 3701 bf->bf_dmamap, m, 3702 bf->bf_segs, &bf->bf_nseg, 3703 BUS_DMA_NOWAIT); 3704 if (error != 0) { 3705 DPRINTF(sc, ATH_DEBUG_ANY, 3706 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 3707 __func__, error); 3708 sc->sc_stats.ast_rx_busdma++; 3709 m_freem(m); 3710 return error; 3711 } 3712 KASSERT(bf->bf_nseg == 1, 3713 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3714 bf->bf_m = m; 3715 } 3716 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3717 3718 /* 3719 * Setup descriptors. For receive we always terminate 3720 * the descriptor list with a self-linked entry so we'll 3721 * not get overrun under high load (as can happen with a 3722 * 5212 when ANI processing enables PHY error frames). 3723 * 3724 * To insure the last descriptor is self-linked we create 3725 * each descriptor as self-linked and add it to the end. As 3726 * each additional descriptor is added the previous self-linked 3727 * entry is ``fixed'' naturally. This should be safe even 3728 * if DMA is happening. When processing RX interrupts we 3729 * never remove/process the last, self-linked, entry on the 3730 * descriptor list. This insures the hardware always has 3731 * someplace to write a new frame. 3732 */ 3733 ds = bf->bf_desc; 3734 ds->ds_link = bf->bf_daddr; /* link to self */ 3735 ds->ds_data = bf->bf_segs[0].ds_addr; 3736 ath_hal_setuprxdesc(ah, ds 3737 , m->m_len /* buffer size */ 3738 , 0 3739 ); 3740 3741 if (sc->sc_rxlink != NULL) 3742 *sc->sc_rxlink = bf->bf_daddr; 3743 sc->sc_rxlink = &ds->ds_link; 3744 return 0; 3745 } 3746 3747 /* 3748 * Extend 15-bit time stamp from rx descriptor to 3749 * a full 64-bit TSF using the specified TSF. 3750 */ 3751 static __inline u_int64_t 3752 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 3753 { 3754 if ((tsf & 0x7fff) < rstamp) 3755 tsf -= 0x8000; 3756 return ((tsf &~ 0x7fff) | rstamp); 3757 } 3758 3759 /* 3760 * Intercept management frames to collect beacon rssi data 3761 * and to do ibss merges. 3762 */ 3763 static void 3764 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 3765 int subtype, int rssi, int noise, u_int32_t rstamp) 3766 { 3767 struct ieee80211vap *vap = ni->ni_vap; 3768 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 3769 3770 /* 3771 * Call up first so subsequent work can use information 3772 * potentially stored in the node (e.g. for ibss merge). 3773 */ 3774 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, noise, rstamp); 3775 switch (subtype) { 3776 case IEEE80211_FC0_SUBTYPE_BEACON: 3777 /* update rssi statistics for use by the hal */ 3778 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3779 if (sc->sc_syncbeacon && 3780 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 3781 /* 3782 * Resync beacon timers using the tsf of the beacon 3783 * frame we just received. 3784 */ 3785 ath_beacon_config(sc, vap); 3786 } 3787 /* fall thru... */ 3788 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3789 if (vap->iv_opmode == IEEE80211_M_IBSS && 3790 vap->iv_state == IEEE80211_S_RUN) { 3791 u_int64_t tsf = ath_extend_tsf(rstamp, 3792 ath_hal_gettsf64(sc->sc_ah)); 3793 /* 3794 * Handle ibss merge as needed; check the tsf on the 3795 * frame before attempting the merge. The 802.11 spec 3796 * says the station should change it's bssid to match 3797 * the oldest station with the same ssid, where oldest 3798 * is determined by the tsf. Note that hardware 3799 * reconfiguration happens through callback to 3800 * ath_newstate as the state machine will go from 3801 * RUN -> RUN when this happens. 3802 */ 3803 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3804 DPRINTF(sc, ATH_DEBUG_STATE, 3805 "ibss merge, rstamp %u tsf %ju " 3806 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3807 (uintmax_t)ni->ni_tstamp.tsf); 3808 (void) ieee80211_ibss_merge(ni); 3809 } 3810 } 3811 break; 3812 } 3813 } 3814 3815 /* 3816 * Set the default antenna. 3817 */ 3818 static void 3819 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3820 { 3821 struct ath_hal *ah = sc->sc_ah; 3822 3823 /* XXX block beacon interrupts */ 3824 ath_hal_setdefantenna(ah, antenna); 3825 if (sc->sc_defant != antenna) 3826 sc->sc_stats.ast_ant_defswitch++; 3827 sc->sc_defant = antenna; 3828 sc->sc_rxotherant = 0; 3829 } 3830 3831 static int 3832 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 3833 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 3834 { 3835 #define CHANNEL_HT (CHANNEL_HT20|CHANNEL_HT40PLUS|CHANNEL_HT40MINUS) 3836 struct ath_softc *sc = ifp->if_softc; 3837 u_int8_t rix; 3838 3839 /* 3840 * Discard anything shorter than an ack or cts. 3841 */ 3842 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) { 3843 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n", 3844 __func__, m->m_pkthdr.len); 3845 sc->sc_stats.ast_rx_tooshort++; 3846 return 0; 3847 } 3848 rix = rs->rs_rate; 3849 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3850 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3851 #if HAL_ABI_VERSION >= 0x07050400 3852 if (sc->sc_curchan.channelFlags & CHANNEL_HT) { 3853 /* 3854 * For HT operation we must specify the channel 3855 * attributes for each packet since they vary. 3856 * We deduce this by from HT40 bit in the rx 3857 * status and the MCS/legacy rate bit. 3858 */ 3859 sc->sc_rx_th.wr_chan_flags &= ~IEEE80211_CHAN_HT; 3860 if (sc->sc_rx_th.wr_rate & 0x80) { /* HT rate */ 3861 /* XXX 40U/40D */ 3862 sc->sc_rx_th.wr_chan_flags |= 3863 (rs->rs_flags & HAL_RX_2040) ? 3864 IEEE80211_CHAN_HT40U : IEEE80211_CHAN_HT20; 3865 if ((rs->rs_flags & HAL_RX_GI) == 0) 3866 sc->sc_rx_th.wr_flags |= 3867 IEEE80211_RADIOTAP_F_SHORTGI; 3868 } 3869 } 3870 #endif 3871 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 3872 if (rs->rs_status & HAL_RXERR_CRC) 3873 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3874 /* XXX propagate other error flags from descriptor */ 3875 sc->sc_rx_th.wr_antsignal = rs->rs_rssi + nf; 3876 sc->sc_rx_th.wr_antnoise = nf; 3877 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 3878 3879 bpf_mtap2(ifp->if_bpf, &sc->sc_rx_th, sc->sc_rx_th_len, m); 3880 3881 return 1; 3882 #undef CHANNEL_HT 3883 } 3884 3885 static void 3886 ath_handle_micerror(struct ieee80211com *ic, 3887 struct ieee80211_frame *wh, int keyix) 3888 { 3889 struct ieee80211_node *ni; 3890 3891 /* XXX recheck MIC to deal w/ chips that lie */ 3892 /* XXX discard MIC errors on !data frames */ 3893 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 3894 if (ni != NULL) { 3895 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 3896 ieee80211_free_node(ni); 3897 } 3898 } 3899 3900 static void 3901 ath_rx_proc(void *arg, int npending) 3902 { 3903 #define PA2DESC(_sc, _pa) \ 3904 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3905 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3906 struct ath_softc *sc = arg; 3907 struct ath_buf *bf; 3908 struct ifnet *ifp = sc->sc_ifp; 3909 struct ieee80211com *ic = ifp->if_l2com; 3910 struct ath_hal *ah = sc->sc_ah; 3911 struct ath_desc *ds; 3912 struct ath_rx_status *rs; 3913 struct mbuf *m; 3914 struct ieee80211_node *ni; 3915 int len, type, ngood; 3916 u_int phyerr; 3917 HAL_STATUS status; 3918 int16_t nf; 3919 u_int64_t tsf; 3920 3921 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3922 ngood = 0; 3923 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 3924 tsf = ath_hal_gettsf64(ah); 3925 do { 3926 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3927 if (bf == NULL) { /* NB: shouldn't happen */ 3928 if_printf(ifp, "%s: no buffer!\n", __func__); 3929 break; 3930 } 3931 m = bf->bf_m; 3932 if (m == NULL) { /* NB: shouldn't happen */ 3933 /* 3934 * If mbuf allocation failed previously there 3935 * will be no mbuf; try again to re-populate it. 3936 */ 3937 /* XXX make debug msg */ 3938 if_printf(ifp, "%s: no mbuf!\n", __func__); 3939 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3940 goto rx_next; 3941 } 3942 ds = bf->bf_desc; 3943 if (ds->ds_link == bf->bf_daddr) { 3944 /* NB: never process the self-linked entry at the end */ 3945 break; 3946 } 3947 /* XXX sync descriptor memory */ 3948 /* 3949 * Must provide the virtual address of the current 3950 * descriptor, the physical address, and the virtual 3951 * address of the next descriptor in the h/w chain. 3952 * This allows the HAL to look ahead to see if the 3953 * hardware is done with a descriptor by checking the 3954 * done bit in the following descriptor and the address 3955 * of the current descriptor the DMA engine is working 3956 * on. All this is necessary because of our use of 3957 * a self-linked list to avoid rx overruns. 3958 */ 3959 rs = &bf->bf_status.ds_rxstat; 3960 status = ath_hal_rxprocdesc(ah, ds, 3961 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 3962 #ifdef ATH_DEBUG 3963 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3964 ath_printrxbuf(bf, 0, status == HAL_OK); 3965 #endif 3966 if (status == HAL_EINPROGRESS) 3967 break; 3968 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3969 if (rs->rs_status != 0) { 3970 if (rs->rs_status & HAL_RXERR_CRC) 3971 sc->sc_stats.ast_rx_crcerr++; 3972 if (rs->rs_status & HAL_RXERR_FIFO) 3973 sc->sc_stats.ast_rx_fifoerr++; 3974 if (rs->rs_status & HAL_RXERR_PHY) { 3975 sc->sc_stats.ast_rx_phyerr++; 3976 phyerr = rs->rs_phyerr & 0x1f; 3977 sc->sc_stats.ast_rx_phy[phyerr]++; 3978 goto rx_error; /* NB: don't count in ierrors */ 3979 } 3980 if (rs->rs_status & HAL_RXERR_DECRYPT) { 3981 /* 3982 * Decrypt error. If the error occurred 3983 * because there was no hardware key, then 3984 * let the frame through so the upper layers 3985 * can process it. This is necessary for 5210 3986 * parts which have no way to setup a ``clear'' 3987 * key cache entry. 3988 * 3989 * XXX do key cache faulting 3990 */ 3991 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 3992 goto rx_accept; 3993 sc->sc_stats.ast_rx_badcrypt++; 3994 } 3995 if (rs->rs_status & HAL_RXERR_MIC) { 3996 sc->sc_stats.ast_rx_badmic++; 3997 /* 3998 * Do minimal work required to hand off 3999 * the 802.11 header for notifcation. 4000 */ 4001 /* XXX frag's and qos frames */ 4002 len = rs->rs_datalen; 4003 if (len >= sizeof (struct ieee80211_frame)) { 4004 bus_dmamap_sync(sc->sc_dmat, 4005 bf->bf_dmamap, 4006 BUS_DMASYNC_POSTREAD); 4007 ath_handle_micerror(ic, 4008 mtod(m, struct ieee80211_frame *), 4009 sc->sc_splitmic ? 4010 rs->rs_keyix-32 : rs->rs_keyix); 4011 } 4012 } 4013 ifp->if_ierrors++; 4014 rx_error: 4015 /* 4016 * Cleanup any pending partial frame. 4017 */ 4018 if (sc->sc_rxpending != NULL) { 4019 m_freem(sc->sc_rxpending); 4020 sc->sc_rxpending = NULL; 4021 } 4022 /* 4023 * When a tap is present pass error frames 4024 * that have been requested. By default we 4025 * pass decrypt+mic errors but others may be 4026 * interesting (e.g. crc). 4027 */ 4028 if (bpf_peers_present(ifp->if_bpf) && 4029 (rs->rs_status & sc->sc_monpass)) { 4030 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4031 BUS_DMASYNC_POSTREAD); 4032 /* NB: bpf needs the mbuf length setup */ 4033 len = rs->rs_datalen; 4034 m->m_pkthdr.len = m->m_len = len; 4035 (void) ath_rx_tap(ifp, m, rs, tsf, nf); 4036 } 4037 /* XXX pass MIC errors up for s/w reclaculation */ 4038 goto rx_next; 4039 } 4040 rx_accept: 4041 /* 4042 * Sync and unmap the frame. At this point we're 4043 * committed to passing the mbuf somewhere so clear 4044 * bf_m; this means a new mbuf must be allocated 4045 * when the rx descriptor is setup again to receive 4046 * another frame. 4047 */ 4048 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4049 BUS_DMASYNC_POSTREAD); 4050 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 4051 bf->bf_m = NULL; 4052 4053 len = rs->rs_datalen; 4054 m->m_len = len; 4055 4056 if (rs->rs_more) { 4057 /* 4058 * Frame spans multiple descriptors; save 4059 * it for the next completed descriptor, it 4060 * will be used to construct a jumbogram. 4061 */ 4062 if (sc->sc_rxpending != NULL) { 4063 /* NB: max frame size is currently 2 clusters */ 4064 sc->sc_stats.ast_rx_toobig++; 4065 m_freem(sc->sc_rxpending); 4066 } 4067 m->m_pkthdr.rcvif = ifp; 4068 m->m_pkthdr.len = len; 4069 sc->sc_rxpending = m; 4070 goto rx_next; 4071 } else if (sc->sc_rxpending != NULL) { 4072 /* 4073 * This is the second part of a jumbogram, 4074 * chain it to the first mbuf, adjust the 4075 * frame length, and clear the rxpending state. 4076 */ 4077 sc->sc_rxpending->m_next = m; 4078 sc->sc_rxpending->m_pkthdr.len += len; 4079 m = sc->sc_rxpending; 4080 sc->sc_rxpending = NULL; 4081 } else { 4082 /* 4083 * Normal single-descriptor receive; setup 4084 * the rcvif and packet length. 4085 */ 4086 m->m_pkthdr.rcvif = ifp; 4087 m->m_pkthdr.len = len; 4088 } 4089 4090 ifp->if_ipackets++; 4091 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 4092 4093 if (bpf_peers_present(ifp->if_bpf) && 4094 !ath_rx_tap(ifp, m, rs, tsf, nf)) { 4095 m_freem(m); /* XXX reclaim */ 4096 goto rx_next; 4097 } 4098 4099 /* 4100 * From this point on we assume the frame is at least 4101 * as large as ieee80211_frame_min; verify that. 4102 */ 4103 if (len < IEEE80211_MIN_LEN) { 4104 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 4105 __func__, len); 4106 sc->sc_stats.ast_rx_tooshort++; 4107 m_freem(m); 4108 goto rx_next; 4109 } 4110 4111 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 4112 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 4113 sc->sc_hwmap[rs->rs_rate].ieeerate, 4114 rs->rs_rssi); 4115 } 4116 4117 m_adj(m, -IEEE80211_CRC_LEN); 4118 4119 /* 4120 * Locate the node for sender, track state, and then 4121 * pass the (referenced) node up to the 802.11 layer 4122 * for its use. 4123 */ 4124 ni = ieee80211_find_rxnode_withkey(ic, 4125 mtod(m, const struct ieee80211_frame_min *), 4126 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 4127 IEEE80211_KEYIX_NONE : rs->rs_keyix); 4128 if (ni != NULL) { 4129 /* 4130 * Sending station is known, dispatch directly. 4131 */ 4132 type = ieee80211_input(ni, m, 4133 rs->rs_rssi, nf, rs->rs_tstamp); 4134 ieee80211_free_node(ni); 4135 /* 4136 * Arrange to update the last rx timestamp only for 4137 * frames from our ap when operating in station mode. 4138 * This assumes the rx key is always setup when 4139 * associated. 4140 */ 4141 if (ic->ic_opmode == IEEE80211_M_STA && 4142 rs->rs_keyix != HAL_RXKEYIX_INVALID) 4143 ngood++; 4144 } else { 4145 type = ieee80211_input_all(ic, m, 4146 rs->rs_rssi, nf, rs->rs_tstamp); 4147 } 4148 /* 4149 * Track rx rssi and do any rx antenna management. 4150 */ 4151 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 4152 if (sc->sc_diversity) { 4153 /* 4154 * When using fast diversity, change the default rx 4155 * antenna if diversity chooses the other antenna 3 4156 * times in a row. 4157 */ 4158 if (sc->sc_defant != rs->rs_antenna) { 4159 if (++sc->sc_rxotherant >= 3) 4160 ath_setdefantenna(sc, rs->rs_antenna); 4161 } else 4162 sc->sc_rxotherant = 0; 4163 } 4164 if (sc->sc_softled) { 4165 /* 4166 * Blink for any data frame. Otherwise do a 4167 * heartbeat-style blink when idle. The latter 4168 * is mainly for station mode where we depend on 4169 * periodic beacon frames to trigger the poll event. 4170 */ 4171 if (type == IEEE80211_FC0_TYPE_DATA) { 4172 sc->sc_rxrate = rs->rs_rate; 4173 ath_led_event(sc, ATH_LED_RX); 4174 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 4175 ath_led_event(sc, ATH_LED_POLL); 4176 } 4177 rx_next: 4178 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 4179 } while (ath_rxbuf_init(sc, bf) == 0); 4180 4181 /* rx signal state monitoring */ 4182 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan); 4183 if (ngood) 4184 sc->sc_lastrx = tsf; 4185 4186 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 && 4187 !IFQ_IS_EMPTY(&ifp->if_snd)) 4188 ath_start(ifp); 4189 4190 #undef PA2DESC 4191 } 4192 4193 static void 4194 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 4195 { 4196 txq->axq_qnum = qnum; 4197 txq->axq_depth = 0; 4198 txq->axq_intrcnt = 0; 4199 txq->axq_link = NULL; 4200 STAILQ_INIT(&txq->axq_q); 4201 ATH_TXQ_LOCK_INIT(sc, txq); 4202 TAILQ_INIT(&txq->axq_stageq); 4203 txq->axq_curage = 0; 4204 } 4205 4206 /* 4207 * Setup a h/w transmit queue. 4208 */ 4209 static struct ath_txq * 4210 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 4211 { 4212 #define N(a) (sizeof(a)/sizeof(a[0])) 4213 struct ath_hal *ah = sc->sc_ah; 4214 HAL_TXQ_INFO qi; 4215 int qnum; 4216 4217 memset(&qi, 0, sizeof(qi)); 4218 qi.tqi_subtype = subtype; 4219 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 4220 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 4221 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 4222 /* 4223 * Enable interrupts only for EOL and DESC conditions. 4224 * We mark tx descriptors to receive a DESC interrupt 4225 * when a tx queue gets deep; otherwise waiting for the 4226 * EOL to reap descriptors. Note that this is done to 4227 * reduce interrupt load and this only defers reaping 4228 * descriptors, never transmitting frames. Aside from 4229 * reducing interrupts this also permits more concurrency. 4230 * The only potential downside is if the tx queue backs 4231 * up in which case the top half of the kernel may backup 4232 * due to a lack of tx descriptors. 4233 */ 4234 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 4235 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 4236 if (qnum == -1) { 4237 /* 4238 * NB: don't print a message, this happens 4239 * normally on parts with too few tx queues 4240 */ 4241 return NULL; 4242 } 4243 if (qnum >= N(sc->sc_txq)) { 4244 device_printf(sc->sc_dev, 4245 "hal qnum %u out of range, max %zu!\n", 4246 qnum, N(sc->sc_txq)); 4247 ath_hal_releasetxqueue(ah, qnum); 4248 return NULL; 4249 } 4250 if (!ATH_TXQ_SETUP(sc, qnum)) { 4251 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4252 sc->sc_txqsetup |= 1<<qnum; 4253 } 4254 return &sc->sc_txq[qnum]; 4255 #undef N 4256 } 4257 4258 /* 4259 * Setup a hardware data transmit queue for the specified 4260 * access control. The hal may not support all requested 4261 * queues in which case it will return a reference to a 4262 * previously setup queue. We record the mapping from ac's 4263 * to h/w queues for use by ath_tx_start and also track 4264 * the set of h/w queues being used to optimize work in the 4265 * transmit interrupt handler and related routines. 4266 */ 4267 static int 4268 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4269 { 4270 #define N(a) (sizeof(a)/sizeof(a[0])) 4271 struct ath_txq *txq; 4272 4273 if (ac >= N(sc->sc_ac2q)) { 4274 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4275 ac, N(sc->sc_ac2q)); 4276 return 0; 4277 } 4278 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4279 if (txq != NULL) { 4280 sc->sc_ac2q[ac] = txq; 4281 return 1; 4282 } else 4283 return 0; 4284 #undef N 4285 } 4286 4287 /* 4288 * Update WME parameters for a transmit queue. 4289 */ 4290 static int 4291 ath_txq_update(struct ath_softc *sc, int ac) 4292 { 4293 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4294 #define ATH_TXOP_TO_US(v) (v<<5) 4295 struct ifnet *ifp = sc->sc_ifp; 4296 struct ieee80211com *ic = ifp->if_l2com; 4297 struct ath_txq *txq = sc->sc_ac2q[ac]; 4298 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4299 struct ath_hal *ah = sc->sc_ah; 4300 HAL_TXQ_INFO qi; 4301 4302 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4303 qi.tqi_aifs = wmep->wmep_aifsn; 4304 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4305 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4306 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 4307 4308 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4309 if_printf(ifp, "unable to update hardware queue " 4310 "parameters for %s traffic!\n", 4311 ieee80211_wme_acnames[ac]); 4312 return 0; 4313 } else { 4314 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4315 return 1; 4316 } 4317 #undef ATH_TXOP_TO_US 4318 #undef ATH_EXPONENT_TO_VALUE 4319 } 4320 4321 /* 4322 * Callback from the 802.11 layer to update WME parameters. 4323 */ 4324 static int 4325 ath_wme_update(struct ieee80211com *ic) 4326 { 4327 struct ath_softc *sc = ic->ic_ifp->if_softc; 4328 4329 return !ath_txq_update(sc, WME_AC_BE) || 4330 !ath_txq_update(sc, WME_AC_BK) || 4331 !ath_txq_update(sc, WME_AC_VI) || 4332 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4333 } 4334 4335 /* 4336 * Reclaim resources for a setup queue. 4337 */ 4338 static void 4339 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4340 { 4341 4342 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4343 ATH_TXQ_LOCK_DESTROY(txq); 4344 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4345 } 4346 4347 /* 4348 * Reclaim all tx queue resources. 4349 */ 4350 static void 4351 ath_tx_cleanup(struct ath_softc *sc) 4352 { 4353 int i; 4354 4355 ATH_TXBUF_LOCK_DESTROY(sc); 4356 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4357 if (ATH_TXQ_SETUP(sc, i)) 4358 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4359 } 4360 4361 /* 4362 * Return h/w rate index for an IEEE rate (w/o basic rate bit). 4363 */ 4364 static int 4365 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate) 4366 { 4367 int i; 4368 4369 for (i = 0; i < rt->rateCount; i++) 4370 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate) 4371 return i; 4372 return 0; /* NB: lowest rate */ 4373 } 4374 4375 /* 4376 * Reclaim mbuf resources. For fragmented frames we 4377 * need to claim each frag chained with m_nextpkt. 4378 */ 4379 static void 4380 ath_freetx(struct mbuf *m) 4381 { 4382 struct mbuf *next; 4383 4384 do { 4385 next = m->m_nextpkt; 4386 m->m_nextpkt = NULL; 4387 m_freem(m); 4388 } while ((m = next) != NULL); 4389 } 4390 4391 static int 4392 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 4393 { 4394 struct mbuf *m; 4395 int error; 4396 4397 /* 4398 * Load the DMA map so any coalescing is done. This 4399 * also calculates the number of descriptors we need. 4400 */ 4401 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4402 bf->bf_segs, &bf->bf_nseg, 4403 BUS_DMA_NOWAIT); 4404 if (error == EFBIG) { 4405 /* XXX packet requires too many descriptors */ 4406 bf->bf_nseg = ATH_TXDESC+1; 4407 } else if (error != 0) { 4408 sc->sc_stats.ast_tx_busdma++; 4409 ath_freetx(m0); 4410 return error; 4411 } 4412 /* 4413 * Discard null packets and check for packets that 4414 * require too many TX descriptors. We try to convert 4415 * the latter to a cluster. 4416 */ 4417 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 4418 sc->sc_stats.ast_tx_linear++; 4419 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); 4420 if (m == NULL) { 4421 ath_freetx(m0); 4422 sc->sc_stats.ast_tx_nombuf++; 4423 return ENOMEM; 4424 } 4425 m0 = m; 4426 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 4427 bf->bf_segs, &bf->bf_nseg, 4428 BUS_DMA_NOWAIT); 4429 if (error != 0) { 4430 sc->sc_stats.ast_tx_busdma++; 4431 ath_freetx(m0); 4432 return error; 4433 } 4434 KASSERT(bf->bf_nseg <= ATH_TXDESC, 4435 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 4436 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 4437 sc->sc_stats.ast_tx_nodata++; 4438 ath_freetx(m0); 4439 return EIO; 4440 } 4441 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 4442 __func__, m0, m0->m_pkthdr.len); 4443 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 4444 bf->bf_m = m0; 4445 4446 return 0; 4447 } 4448 4449 static void 4450 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 4451 { 4452 struct ath_hal *ah = sc->sc_ah; 4453 struct ath_desc *ds, *ds0; 4454 int i; 4455 4456 /* 4457 * Fillin the remainder of the descriptor info. 4458 */ 4459 ds0 = ds = bf->bf_desc; 4460 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4461 ds->ds_data = bf->bf_segs[i].ds_addr; 4462 if (i == bf->bf_nseg - 1) 4463 ds->ds_link = 0; 4464 else 4465 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4466 ath_hal_filltxdesc(ah, ds 4467 , bf->bf_segs[i].ds_len /* segment length */ 4468 , i == 0 /* first segment */ 4469 , i == bf->bf_nseg - 1 /* last segment */ 4470 , ds0 /* first descriptor */ 4471 ); 4472 DPRINTF(sc, ATH_DEBUG_XMIT, 4473 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4474 __func__, i, ds->ds_link, ds->ds_data, 4475 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4476 } 4477 /* 4478 * Insert the frame on the outbound list and pass it on 4479 * to the hardware. Multicast frames buffered for power 4480 * save stations and transmit from the CAB queue are stored 4481 * on a s/w only queue and loaded on to the CAB queue in 4482 * the SWBA handler since frames only go out on DTIM and 4483 * to avoid possible races. 4484 */ 4485 ATH_TXQ_LOCK(txq); 4486 if (txq->axq_qnum != ATH_TXQ_SWQ) { 4487 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4488 if (txq->axq_link == NULL) { 4489 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4490 DPRINTF(sc, ATH_DEBUG_XMIT, 4491 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 4492 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 4493 txq->axq_depth); 4494 } else { 4495 *txq->axq_link = bf->bf_daddr; 4496 DPRINTF(sc, ATH_DEBUG_XMIT, 4497 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4498 txq->axq_qnum, txq->axq_link, 4499 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4500 } 4501 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4502 ath_hal_txstart(ah, txq->axq_qnum); 4503 } else { 4504 if (txq->axq_link != NULL) { 4505 struct ath_buf *last = ATH_TXQ_LAST(txq); 4506 struct ieee80211_frame *wh; 4507 4508 /* mark previous frame */ 4509 wh = mtod(last->bf_m, struct ieee80211_frame *); 4510 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 4511 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 4512 BUS_DMASYNC_PREWRITE); 4513 4514 /* link descriptor */ 4515 *txq->axq_link = bf->bf_daddr; 4516 } 4517 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4518 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4519 } 4520 ATH_TXQ_UNLOCK(txq); 4521 } 4522 4523 static int 4524 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 4525 struct mbuf *m0) 4526 { 4527 struct ieee80211vap *vap = ni->ni_vap; 4528 struct ath_vap *avp = ATH_VAP(vap); 4529 struct ath_hal *ah = sc->sc_ah; 4530 struct ifnet *ifp = sc->sc_ifp; 4531 struct ieee80211com *ic = ifp->if_l2com; 4532 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 4533 int error, iswep, ismcast, isfrag, ismrr; 4534 int keyix, hdrlen, pktlen, try0; 4535 u_int8_t rix, txrate, ctsrate; 4536 u_int8_t cix = 0xff; /* NB: silence compiler */ 4537 struct ath_desc *ds; 4538 struct ath_txq *txq; 4539 struct ieee80211_frame *wh; 4540 u_int subtype, flags, ctsduration; 4541 HAL_PKT_TYPE atype; 4542 const HAL_RATE_TABLE *rt; 4543 HAL_BOOL shortPreamble; 4544 struct ath_node *an; 4545 u_int pri; 4546 4547 wh = mtod(m0, struct ieee80211_frame *); 4548 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 4549 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 4550 isfrag = m0->m_flags & M_FRAG; 4551 hdrlen = ieee80211_anyhdrsize(wh); 4552 /* 4553 * Packet length must not include any 4554 * pad bytes; deduct them here. 4555 */ 4556 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 4557 4558 if (iswep) { 4559 const struct ieee80211_cipher *cip; 4560 struct ieee80211_key *k; 4561 4562 /* 4563 * Construct the 802.11 header+trailer for an encrypted 4564 * frame. The only reason this can fail is because of an 4565 * unknown or unsupported cipher/key type. 4566 */ 4567 k = ieee80211_crypto_encap(ni, m0); 4568 if (k == NULL) { 4569 /* 4570 * This can happen when the key is yanked after the 4571 * frame was queued. Just discard the frame; the 4572 * 802.11 layer counts failures and provides 4573 * debugging/diagnostics. 4574 */ 4575 ath_freetx(m0); 4576 return EIO; 4577 } 4578 /* 4579 * Adjust the packet + header lengths for the crypto 4580 * additions and calculate the h/w key index. When 4581 * a s/w mic is done the frame will have had any mic 4582 * added to it prior to entry so m0->m_pkthdr.len will 4583 * account for it. Otherwise we need to add it to the 4584 * packet length. 4585 */ 4586 cip = k->wk_cipher; 4587 hdrlen += cip->ic_header; 4588 pktlen += cip->ic_header + cip->ic_trailer; 4589 /* NB: frags always have any TKIP MIC done in s/w */ 4590 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 4591 pktlen += cip->ic_miclen; 4592 keyix = k->wk_keyix; 4593 4594 /* packet header may have moved, reset our local pointer */ 4595 wh = mtod(m0, struct ieee80211_frame *); 4596 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 4597 /* 4598 * Use station key cache slot, if assigned. 4599 */ 4600 keyix = ni->ni_ucastkey.wk_keyix; 4601 if (keyix == IEEE80211_KEYIX_NONE) 4602 keyix = HAL_TXKEYIX_INVALID; 4603 } else 4604 keyix = HAL_TXKEYIX_INVALID; 4605 4606 pktlen += IEEE80211_CRC_LEN; 4607 4608 /* 4609 * Load the DMA map so any coalescing is done. This 4610 * also calculates the number of descriptors we need. 4611 */ 4612 error = ath_tx_dmasetup(sc, bf, m0); 4613 if (error != 0) 4614 return error; 4615 bf->bf_node = ni; /* NB: held reference */ 4616 m0 = bf->bf_m; /* NB: may have changed */ 4617 wh = mtod(m0, struct ieee80211_frame *); 4618 4619 /* setup descriptors */ 4620 ds = bf->bf_desc; 4621 rt = sc->sc_currates; 4622 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 4623 4624 /* 4625 * NB: the 802.11 layer marks whether or not we should 4626 * use short preamble based on the current mode and 4627 * negotiated parameters. 4628 */ 4629 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 4630 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 4631 shortPreamble = AH_TRUE; 4632 sc->sc_stats.ast_tx_shortpre++; 4633 } else { 4634 shortPreamble = AH_FALSE; 4635 } 4636 4637 an = ATH_NODE(ni); 4638 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 4639 ismrr = 0; /* default no multi-rate retry*/ 4640 pri = M_WME_GETAC(m0); /* honor classification */ 4641 /* 4642 * Calculate Atheros packet type from IEEE80211 packet header, 4643 * setup for rate calculations, and select h/w transmit queue. 4644 */ 4645 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 4646 case IEEE80211_FC0_TYPE_MGT: 4647 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4648 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 4649 atype = HAL_PKT_TYPE_BEACON; 4650 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4651 atype = HAL_PKT_TYPE_PROBE_RESP; 4652 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 4653 atype = HAL_PKT_TYPE_ATIM; 4654 else 4655 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 4656 rix = an->an_mgmtrix; 4657 txrate = rt->info[rix].rateCode; 4658 if (shortPreamble) 4659 txrate |= rt->info[rix].shortPreamble; 4660 try0 = ATH_TXMGTTRY; 4661 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4662 break; 4663 case IEEE80211_FC0_TYPE_CTL: 4664 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 4665 rix = an->an_mgmtrix; 4666 txrate = rt->info[rix].rateCode; 4667 if (shortPreamble) 4668 txrate |= rt->info[rix].shortPreamble; 4669 try0 = ATH_TXMGTTRY; 4670 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4671 break; 4672 case IEEE80211_FC0_TYPE_DATA: 4673 atype = HAL_PKT_TYPE_NORMAL; /* default */ 4674 /* 4675 * Data frames: multicast frames go out at a fixed rate, 4676 * otherwise consult the rate control module for the 4677 * rate to use. 4678 */ 4679 if (ismcast) { 4680 rix = an->an_mcastrix; 4681 txrate = rt->info[rix].rateCode; 4682 if (shortPreamble) 4683 txrate |= rt->info[rix].shortPreamble; 4684 try0 = 1; 4685 } else { 4686 ath_rate_findrate(sc, an, shortPreamble, pktlen, 4687 &rix, &try0, &txrate); 4688 sc->sc_txrate = txrate; /* for LED blinking */ 4689 sc->sc_lastdatarix = rix; /* for fast frames */ 4690 if (try0 != ATH_TXMAXTRY) 4691 ismrr = 1; 4692 } 4693 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 4694 flags |= HAL_TXDESC_NOACK; 4695 break; 4696 default: 4697 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 4698 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 4699 /* XXX statistic */ 4700 ath_freetx(m0); 4701 return EIO; 4702 } 4703 txq = sc->sc_ac2q[pri]; 4704 4705 /* 4706 * When servicing one or more stations in power-save mode 4707 * (or) if there is some mcast data waiting on the mcast 4708 * queue (to prevent out of order delivery) multicast 4709 * frames must be buffered until after the beacon. 4710 */ 4711 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 4712 txq = &avp->av_mcastq; 4713 4714 /* 4715 * Calculate miscellaneous flags. 4716 */ 4717 if (ismcast) { 4718 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 4719 } else if (pktlen > vap->iv_rtsthreshold && 4720 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 4721 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 4722 cix = rt->info[rix].controlRate; 4723 sc->sc_stats.ast_tx_rts++; 4724 } 4725 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 4726 sc->sc_stats.ast_tx_noack++; 4727 4728 /* 4729 * If 802.11g protection is enabled, determine whether 4730 * to use RTS/CTS or just CTS. Note that this is only 4731 * done for OFDM unicast frames. 4732 */ 4733 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 4734 rt->info[rix].phy == IEEE80211_T_OFDM && 4735 (flags & HAL_TXDESC_NOACK) == 0) { 4736 /* XXX fragments must use CCK rates w/ protection */ 4737 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4738 flags |= HAL_TXDESC_RTSENA; 4739 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4740 flags |= HAL_TXDESC_CTSENA; 4741 if (isfrag) { 4742 /* 4743 * For frags it would be desirable to use the 4744 * highest CCK rate for RTS/CTS. But stations 4745 * farther away may detect it at a lower CCK rate 4746 * so use the configured protection rate instead 4747 * (for now). 4748 */ 4749 cix = rt->info[sc->sc_protrix].controlRate; 4750 } else 4751 cix = rt->info[sc->sc_protrix].controlRate; 4752 sc->sc_stats.ast_tx_protect++; 4753 } 4754 4755 /* 4756 * Calculate duration. This logically belongs in the 802.11 4757 * layer but it lacks sufficient information to calculate it. 4758 */ 4759 if ((flags & HAL_TXDESC_NOACK) == 0 && 4760 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 4761 u_int16_t dur; 4762 if (shortPreamble) 4763 dur = rt->info[rix].spAckDuration; 4764 else 4765 dur = rt->info[rix].lpAckDuration; 4766 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 4767 dur += dur; /* additional SIFS+ACK */ 4768 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 4769 /* 4770 * Include the size of next fragment so NAV is 4771 * updated properly. The last fragment uses only 4772 * the ACK duration 4773 */ 4774 dur += ath_hal_computetxtime(ah, rt, 4775 m0->m_nextpkt->m_pkthdr.len, 4776 rix, shortPreamble); 4777 } 4778 if (isfrag) { 4779 /* 4780 * Force hardware to use computed duration for next 4781 * fragment by disabling multi-rate retry which updates 4782 * duration based on the multi-rate duration table. 4783 */ 4784 ismrr = 0; 4785 try0 = ATH_TXMGTTRY; /* XXX? */ 4786 } 4787 *(u_int16_t *)wh->i_dur = htole16(dur); 4788 } 4789 4790 /* 4791 * Calculate RTS/CTS rate and duration if needed. 4792 */ 4793 ctsduration = 0; 4794 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 4795 /* 4796 * CTS transmit rate is derived from the transmit rate 4797 * by looking in the h/w rate table. We must also factor 4798 * in whether or not a short preamble is to be used. 4799 */ 4800 /* NB: cix is set above where RTS/CTS is enabled */ 4801 KASSERT(cix != 0xff, ("cix not setup")); 4802 ctsrate = rt->info[cix].rateCode; 4803 /* 4804 * Compute the transmit duration based on the frame 4805 * size and the size of an ACK frame. We call into the 4806 * HAL to do the computation since it depends on the 4807 * characteristics of the actual PHY being used. 4808 * 4809 * NB: CTS is assumed the same size as an ACK so we can 4810 * use the precalculated ACK durations. 4811 */ 4812 if (shortPreamble) { 4813 ctsrate |= rt->info[cix].shortPreamble; 4814 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4815 ctsduration += rt->info[cix].spAckDuration; 4816 ctsduration += ath_hal_computetxtime(ah, 4817 rt, pktlen, rix, AH_TRUE); 4818 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4819 ctsduration += rt->info[rix].spAckDuration; 4820 } else { 4821 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4822 ctsduration += rt->info[cix].lpAckDuration; 4823 ctsduration += ath_hal_computetxtime(ah, 4824 rt, pktlen, rix, AH_FALSE); 4825 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4826 ctsduration += rt->info[rix].lpAckDuration; 4827 } 4828 /* 4829 * Must disable multi-rate retry when using RTS/CTS. 4830 */ 4831 ismrr = 0; 4832 try0 = ATH_TXMGTTRY; /* XXX */ 4833 } else 4834 ctsrate = 0; 4835 4836 /* 4837 * At this point we are committed to sending the frame 4838 * and we don't need to look at m_nextpkt; clear it in 4839 * case this frame is part of frag chain. 4840 */ 4841 m0->m_nextpkt = NULL; 4842 4843 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 4844 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 4845 sc->sc_hwmap[txrate].ieeerate, -1); 4846 4847 if (bpf_peers_present(ifp->if_bpf)) { 4848 u_int64_t tsf = ath_hal_gettsf64(ah); 4849 4850 sc->sc_tx_th.wt_tsf = htole64(tsf); 4851 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 4852 if (iswep) 4853 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4854 if (isfrag) 4855 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 4856 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 4857 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 4858 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 4859 4860 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0); 4861 } 4862 4863 /* 4864 * Determine if a tx interrupt should be generated for 4865 * this descriptor. We take a tx interrupt to reap 4866 * descriptors when the h/w hits an EOL condition or 4867 * when the descriptor is specifically marked to generate 4868 * an interrupt. We periodically mark descriptors in this 4869 * way to insure timely replenishing of the supply needed 4870 * for sending frames. Defering interrupts reduces system 4871 * load and potentially allows more concurrent work to be 4872 * done but if done to aggressively can cause senders to 4873 * backup. 4874 * 4875 * NB: use >= to deal with sc_txintrperiod changing 4876 * dynamically through sysctl. 4877 */ 4878 if (flags & HAL_TXDESC_INTREQ) { 4879 txq->axq_intrcnt = 0; 4880 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 4881 flags |= HAL_TXDESC_INTREQ; 4882 txq->axq_intrcnt = 0; 4883 } 4884 4885 /* 4886 * Formulate first tx descriptor with tx controls. 4887 */ 4888 /* XXX check return value? */ 4889 ath_hal_setuptxdesc(ah, ds 4890 , pktlen /* packet length */ 4891 , hdrlen /* header length */ 4892 , atype /* Atheros packet type */ 4893 , ni->ni_txpower /* txpower */ 4894 , txrate, try0 /* series 0 rate/tries */ 4895 , keyix /* key cache index */ 4896 , sc->sc_txantenna /* antenna mode */ 4897 , flags /* flags */ 4898 , ctsrate /* rts/cts rate */ 4899 , ctsduration /* rts/cts duration */ 4900 ); 4901 bf->bf_flags = flags; 4902 /* 4903 * Setup the multi-rate retry state only when we're 4904 * going to use it. This assumes ath_hal_setuptxdesc 4905 * initializes the descriptors (so we don't have to) 4906 * when the hardware supports multi-rate retry and 4907 * we don't use it. 4908 */ 4909 if (ismrr) 4910 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4911 4912 ath_tx_handoff(sc, txq, bf); 4913 return 0; 4914 } 4915 4916 /* 4917 * Process completed xmit descriptors from the specified queue. 4918 */ 4919 static int 4920 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4921 { 4922 struct ath_hal *ah = sc->sc_ah; 4923 struct ifnet *ifp = sc->sc_ifp; 4924 struct ieee80211com *ic = ifp->if_l2com; 4925 struct ath_buf *bf; 4926 struct ath_desc *ds, *ds0; 4927 struct ath_tx_status *ts; 4928 struct ieee80211_node *ni; 4929 struct ath_node *an; 4930 int sr, lr, pri, nacked; 4931 HAL_STATUS status; 4932 4933 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4934 __func__, txq->axq_qnum, 4935 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4936 txq->axq_link); 4937 nacked = 0; 4938 for (;;) { 4939 ATH_TXQ_LOCK(txq); 4940 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4941 bf = STAILQ_FIRST(&txq->axq_q); 4942 if (bf == NULL) { 4943 ATH_TXQ_UNLOCK(txq); 4944 break; 4945 } 4946 ds0 = &bf->bf_desc[0]; 4947 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4948 ts = &bf->bf_status.ds_txstat; 4949 status = ath_hal_txprocdesc(ah, ds, ts); 4950 #ifdef ATH_DEBUG 4951 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4952 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK); 4953 #endif 4954 if (status == HAL_EINPROGRESS) { 4955 ATH_TXQ_UNLOCK(txq); 4956 break; 4957 } 4958 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4959 if (txq->axq_depth == 0) 4960 txq->axq_link = NULL; 4961 ATH_TXQ_UNLOCK(txq); 4962 4963 ni = bf->bf_node; 4964 if (ni != NULL) { 4965 an = ATH_NODE(ni); 4966 if (ts->ts_status == 0) { 4967 u_int8_t txant = ts->ts_antenna; 4968 sc->sc_stats.ast_ant_tx[txant]++; 4969 sc->sc_ant_tx[txant]++; 4970 if (ts->ts_rate & HAL_TXSTAT_ALTRATE) 4971 sc->sc_stats.ast_tx_altrate++; 4972 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4973 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4974 ts->ts_rssi); 4975 pri = M_WME_GETAC(bf->bf_m); 4976 if (pri >= WME_AC_VO) 4977 ic->ic_wme.wme_hipri_traffic++; 4978 ni->ni_inact = ni->ni_inact_reload; 4979 } else { 4980 if (ts->ts_status & HAL_TXERR_XRETRY) 4981 sc->sc_stats.ast_tx_xretries++; 4982 if (ts->ts_status & HAL_TXERR_FIFO) 4983 sc->sc_stats.ast_tx_fifoerr++; 4984 if (ts->ts_status & HAL_TXERR_FILT) 4985 sc->sc_stats.ast_tx_filtered++; 4986 if (bf->bf_m->m_flags & M_FF) 4987 sc->sc_stats.ast_ff_txerr++; 4988 } 4989 sr = ts->ts_shortretry; 4990 lr = ts->ts_longretry; 4991 sc->sc_stats.ast_tx_shortretry += sr; 4992 sc->sc_stats.ast_tx_longretry += lr; 4993 /* 4994 * Hand the descriptor to the rate control algorithm. 4995 */ 4996 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4997 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 4998 /* 4999 * If frame was ack'd update the last rx time 5000 * used to workaround phantom bmiss interrupts. 5001 */ 5002 if (ts->ts_status == 0) 5003 nacked++; 5004 ath_rate_tx_complete(sc, an, bf); 5005 } 5006 /* 5007 * Do any tx complete callback. Note this must 5008 * be done before releasing the node reference. 5009 */ 5010 if (bf->bf_m->m_flags & M_TXCB) 5011 ieee80211_process_callback(ni, bf->bf_m, 5012 ts->ts_status); 5013 /* 5014 * Reclaim reference to node. 5015 * 5016 * NB: the node may be reclaimed here if, for example 5017 * this is a DEAUTH message that was sent and the 5018 * node was timed out due to inactivity. 5019 */ 5020 ieee80211_free_node(ni); 5021 } 5022 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 5023 BUS_DMASYNC_POSTWRITE); 5024 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5025 5026 m_freem(bf->bf_m); 5027 bf->bf_m = NULL; 5028 bf->bf_node = NULL; 5029 5030 ATH_TXBUF_LOCK(sc); 5031 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5032 ATH_TXBUF_UNLOCK(sc); 5033 } 5034 /* 5035 * Flush fast-frame staging queue when traffic slows. 5036 */ 5037 if (txq->axq_depth <= 1) 5038 ath_ff_stageq_flush(sc, txq, ath_ff_always); 5039 return nacked; 5040 } 5041 5042 static __inline int 5043 txqactive(struct ath_hal *ah, int qnum) 5044 { 5045 u_int32_t txqs = 1<<qnum; 5046 ath_hal_gettxintrtxqs(ah, &txqs); 5047 return (txqs & (1<<qnum)); 5048 } 5049 5050 /* 5051 * Deferred processing of transmit interrupt; special-cased 5052 * for a single hardware transmit queue (e.g. 5210 and 5211). 5053 */ 5054 static void 5055 ath_tx_proc_q0(void *arg, int npending) 5056 { 5057 struct ath_softc *sc = arg; 5058 struct ifnet *ifp = sc->sc_ifp; 5059 5060 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 5061 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5062 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5063 ath_tx_processq(sc, sc->sc_cabq); 5064 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5065 ifp->if_timer = 0; 5066 5067 if (sc->sc_softled) 5068 ath_led_event(sc, ATH_LED_TX); 5069 5070 ath_start(ifp); 5071 } 5072 5073 /* 5074 * Deferred processing of transmit interrupt; special-cased 5075 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 5076 */ 5077 static void 5078 ath_tx_proc_q0123(void *arg, int npending) 5079 { 5080 struct ath_softc *sc = arg; 5081 struct ifnet *ifp = sc->sc_ifp; 5082 int nacked; 5083 5084 /* 5085 * Process each active queue. 5086 */ 5087 nacked = 0; 5088 if (txqactive(sc->sc_ah, 0)) 5089 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 5090 if (txqactive(sc->sc_ah, 1)) 5091 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 5092 if (txqactive(sc->sc_ah, 2)) 5093 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 5094 if (txqactive(sc->sc_ah, 3)) 5095 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 5096 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5097 ath_tx_processq(sc, sc->sc_cabq); 5098 if (nacked) 5099 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5100 5101 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5102 ifp->if_timer = 0; 5103 5104 if (sc->sc_softled) 5105 ath_led_event(sc, ATH_LED_TX); 5106 5107 ath_start(ifp); 5108 } 5109 5110 /* 5111 * Deferred processing of transmit interrupt. 5112 */ 5113 static void 5114 ath_tx_proc(void *arg, int npending) 5115 { 5116 struct ath_softc *sc = arg; 5117 struct ifnet *ifp = sc->sc_ifp; 5118 int i, nacked; 5119 5120 /* 5121 * Process each active queue. 5122 */ 5123 nacked = 0; 5124 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5125 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 5126 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 5127 if (nacked) 5128 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5129 5130 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5131 ifp->if_timer = 0; 5132 5133 if (sc->sc_softled) 5134 ath_led_event(sc, ATH_LED_TX); 5135 5136 ath_start(ifp); 5137 } 5138 5139 static void 5140 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 5141 { 5142 #ifdef ATH_DEBUG 5143 struct ath_hal *ah = sc->sc_ah; 5144 #endif 5145 struct ieee80211_node *ni; 5146 struct ath_buf *bf; 5147 u_int ix; 5148 5149 /* 5150 * NB: this assumes output has been stopped and 5151 * we do not need to block ath_tx_tasklet 5152 */ 5153 for (ix = 0;; ix++) { 5154 ATH_TXQ_LOCK(txq); 5155 bf = STAILQ_FIRST(&txq->axq_q); 5156 if (bf == NULL) { 5157 txq->axq_link = NULL; 5158 ATH_TXQ_UNLOCK(txq); 5159 break; 5160 } 5161 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 5162 ATH_TXQ_UNLOCK(txq); 5163 #ifdef ATH_DEBUG 5164 if (sc->sc_debug & ATH_DEBUG_RESET) { 5165 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5166 5167 ath_printtxbuf(bf, txq->axq_qnum, ix, 5168 ath_hal_txprocdesc(ah, bf->bf_desc, 5169 &bf->bf_status.ds_txstat) == HAL_OK); 5170 ieee80211_dump_pkt(ic, mtod(bf->bf_m, caddr_t), 5171 bf->bf_m->m_len, 0, -1); 5172 } 5173 #endif /* ATH_DEBUG */ 5174 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5175 ni = bf->bf_node; 5176 bf->bf_node = NULL; 5177 if (ni != NULL) { 5178 /* 5179 * Do any callback and reclaim the node reference. 5180 */ 5181 if (bf->bf_m->m_flags & M_TXCB) 5182 ieee80211_process_callback(ni, bf->bf_m, -1); 5183 ieee80211_free_node(ni); 5184 } 5185 m_freem(bf->bf_m); 5186 bf->bf_m = NULL; 5187 5188 ATH_TXBUF_LOCK(sc); 5189 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5190 ATH_TXBUF_UNLOCK(sc); 5191 } 5192 } 5193 5194 static void 5195 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5196 { 5197 struct ath_hal *ah = sc->sc_ah; 5198 5199 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5200 __func__, txq->axq_qnum, 5201 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5202 txq->axq_link); 5203 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5204 } 5205 5206 /* 5207 * Drain the transmit queues and reclaim resources. 5208 */ 5209 static void 5210 ath_draintxq(struct ath_softc *sc) 5211 { 5212 struct ath_hal *ah = sc->sc_ah; 5213 struct ifnet *ifp = sc->sc_ifp; 5214 int i; 5215 5216 /* XXX return value */ 5217 if (!sc->sc_invalid) { 5218 /* don't touch the hardware if marked invalid */ 5219 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5220 __func__, sc->sc_bhalq, 5221 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5222 NULL); 5223 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5224 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5225 if (ATH_TXQ_SETUP(sc, i)) 5226 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5227 } 5228 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5229 if (ATH_TXQ_SETUP(sc, i)) 5230 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5231 #ifdef ATH_DEBUG 5232 if (sc->sc_debug & ATH_DEBUG_RESET) { 5233 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 5234 if (bf != NULL && bf->bf_m != NULL) { 5235 ath_printtxbuf(bf, sc->sc_bhalq, 0, 5236 ath_hal_txprocdesc(ah, bf->bf_desc, 5237 &bf->bf_status.ds_txstat) == HAL_OK); 5238 ieee80211_dump_pkt(ifp->if_l2com, mtod(bf->bf_m, caddr_t), 5239 bf->bf_m->m_len, 0, -1); 5240 } 5241 } 5242 #endif /* ATH_DEBUG */ 5243 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5244 ifp->if_timer = 0; 5245 } 5246 5247 /* 5248 * Disable the receive h/w in preparation for a reset. 5249 */ 5250 static void 5251 ath_stoprecv(struct ath_softc *sc) 5252 { 5253 #define PA2DESC(_sc, _pa) \ 5254 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 5255 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 5256 struct ath_hal *ah = sc->sc_ah; 5257 5258 ath_hal_stoppcurecv(ah); /* disable PCU */ 5259 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 5260 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 5261 DELAY(3000); /* 3ms is long enough for 1 frame */ 5262 #ifdef ATH_DEBUG 5263 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 5264 struct ath_buf *bf; 5265 u_int ix; 5266 5267 printf("%s: rx queue %p, link %p\n", __func__, 5268 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 5269 ix = 0; 5270 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5271 struct ath_desc *ds = bf->bf_desc; 5272 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5273 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 5274 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 5275 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 5276 ath_printrxbuf(bf, ix, status == HAL_OK); 5277 ix++; 5278 } 5279 } 5280 #endif 5281 if (sc->sc_rxpending != NULL) { 5282 m_freem(sc->sc_rxpending); 5283 sc->sc_rxpending = NULL; 5284 } 5285 sc->sc_rxlink = NULL; /* just in case */ 5286 #undef PA2DESC 5287 } 5288 5289 /* 5290 * Enable the receive h/w following a reset. 5291 */ 5292 static int 5293 ath_startrecv(struct ath_softc *sc) 5294 { 5295 struct ath_hal *ah = sc->sc_ah; 5296 struct ath_buf *bf; 5297 5298 sc->sc_rxlink = NULL; 5299 sc->sc_rxpending = NULL; 5300 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5301 int error = ath_rxbuf_init(sc, bf); 5302 if (error != 0) { 5303 DPRINTF(sc, ATH_DEBUG_RECV, 5304 "%s: ath_rxbuf_init failed %d\n", 5305 __func__, error); 5306 return error; 5307 } 5308 } 5309 5310 bf = STAILQ_FIRST(&sc->sc_rxbuf); 5311 ath_hal_putrxbuf(ah, bf->bf_daddr); 5312 ath_hal_rxena(ah); /* enable recv descriptors */ 5313 ath_mode_init(sc); /* set filters, etc. */ 5314 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 5315 return 0; 5316 } 5317 5318 /* 5319 * Update internal state after a channel change. 5320 */ 5321 static void 5322 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5323 { 5324 enum ieee80211_phymode mode; 5325 5326 /* 5327 * Change channels and update the h/w rate map 5328 * if we're switching; e.g. 11a to 11b/g. 5329 */ 5330 if (IEEE80211_IS_CHAN_HALF(chan)) 5331 mode = IEEE80211_MODE_HALF; 5332 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 5333 mode = IEEE80211_MODE_QUARTER; 5334 else 5335 mode = ieee80211_chan2mode(chan); 5336 if (mode != sc->sc_curmode) 5337 ath_setcurmode(sc, mode); 5338 5339 sc->sc_rx_th.wr_chan_flags = htole32(chan->ic_flags); 5340 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags; 5341 sc->sc_rx_th.wr_chan_freq = htole16(chan->ic_freq); 5342 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq; 5343 sc->sc_rx_th.wr_chan_ieee = chan->ic_ieee; 5344 sc->sc_tx_th.wt_chan_ieee = sc->sc_rx_th.wr_chan_ieee; 5345 sc->sc_rx_th.wr_chan_maxpow = chan->ic_maxregpower; 5346 sc->sc_tx_th.wt_chan_maxpow = sc->sc_rx_th.wr_chan_maxpow; 5347 } 5348 5349 /* 5350 * Set/change channels. If the channel is really being changed, 5351 * it's done by reseting the chip. To accomplish this we must 5352 * first cleanup any pending DMA, then restart stuff after a la 5353 * ath_init. 5354 */ 5355 static int 5356 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5357 { 5358 struct ifnet *ifp = sc->sc_ifp; 5359 struct ieee80211com *ic = ifp->if_l2com; 5360 struct ath_hal *ah = sc->sc_ah; 5361 HAL_CHANNEL hchan; 5362 5363 /* 5364 * Convert to a HAL channel description with 5365 * the flags constrained to reflect the current 5366 * operating mode. 5367 */ 5368 ath_mapchan(&hchan, chan); 5369 5370 DPRINTF(sc, ATH_DEBUG_RESET, 5371 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n", 5372 __func__, 5373 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel, 5374 sc->sc_curchan.channelFlags), 5375 sc->sc_curchan.channel, sc->sc_curchan.channelFlags, 5376 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags), 5377 hchan.channel, hchan.channelFlags); 5378 if (hchan.channel != sc->sc_curchan.channel || 5379 hchan.channelFlags != sc->sc_curchan.channelFlags) { 5380 HAL_STATUS status; 5381 5382 /* 5383 * To switch channels clear any pending DMA operations; 5384 * wait long enough for the RX fifo to drain, reset the 5385 * hardware at the new frequency, and then re-enable 5386 * the relevant bits of the h/w. 5387 */ 5388 ath_hal_intrset(ah, 0); /* disable interrupts */ 5389 ath_draintxq(sc); /* clear pending tx frames */ 5390 ath_stoprecv(sc); /* turn off frame recv */ 5391 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) { 5392 if_printf(ifp, "%s: unable to reset " 5393 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x), " 5394 "hal status %u\n", __func__, 5395 ieee80211_chan2ieee(ic, chan), chan->ic_freq, 5396 chan->ic_flags, hchan.channelFlags, status); 5397 return EIO; 5398 } 5399 sc->sc_curchan = hchan; 5400 sc->sc_diversity = ath_hal_getdiversity(ah); 5401 sc->sc_calinterval = 1; 5402 sc->sc_caltries = 0; 5403 5404 /* 5405 * Re-enable rx framework. 5406 */ 5407 if (ath_startrecv(sc) != 0) { 5408 if_printf(ifp, "%s: unable to restart recv logic\n", 5409 __func__); 5410 return EIO; 5411 } 5412 5413 /* 5414 * Change channels and update the h/w rate map 5415 * if we're switching; e.g. 11a to 11b/g. 5416 */ 5417 ath_chan_change(sc, chan); 5418 5419 /* 5420 * Re-enable interrupts. 5421 */ 5422 ath_hal_intrset(ah, sc->sc_imask); 5423 } 5424 return 0; 5425 } 5426 5427 /* 5428 * Periodically recalibrate the PHY to account 5429 * for temperature/environment changes. 5430 */ 5431 static void 5432 ath_calibrate(void *arg) 5433 { 5434 struct ath_softc *sc = arg; 5435 struct ath_hal *ah = sc->sc_ah; 5436 HAL_BOOL iqCalDone; 5437 5438 sc->sc_stats.ast_per_cal++; 5439 5440 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5441 /* 5442 * Rfgain is out of bounds, reset the chip 5443 * to load new gain values. 5444 */ 5445 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5446 "%s: rfgain change\n", __func__); 5447 sc->sc_stats.ast_per_rfgain++; 5448 ath_reset(sc->sc_ifp); 5449 } 5450 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) { 5451 DPRINTF(sc, ATH_DEBUG_ANY, 5452 "%s: calibration of channel %u failed\n", 5453 __func__, sc->sc_curchan.channel); 5454 sc->sc_stats.ast_per_calfail++; 5455 } 5456 /* 5457 * Calibrate noise floor data again in case of change. 5458 */ 5459 ath_hal_process_noisefloor(ah); 5460 /* 5461 * Poll more frequently when the IQ calibration is in 5462 * progress to speedup loading the final settings. 5463 * We temper this aggressive polling with an exponential 5464 * back off after 4 tries up to ath_calinterval. 5465 */ 5466 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) { 5467 sc->sc_caltries = 0; 5468 sc->sc_calinterval = ath_calinterval; 5469 } else if (sc->sc_caltries > 4) { 5470 sc->sc_caltries = 0; 5471 sc->sc_calinterval <<= 1; 5472 if (sc->sc_calinterval > ath_calinterval) 5473 sc->sc_calinterval = ath_calinterval; 5474 } 5475 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval, 5476 ("bad calibration interval %u", sc->sc_calinterval)); 5477 5478 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5479 "%s: next +%u (%siqCalDone tries %u)\n", __func__, 5480 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries); 5481 sc->sc_caltries++; 5482 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 5483 ath_calibrate, sc); 5484 } 5485 5486 static void 5487 ath_scan_start(struct ieee80211com *ic) 5488 { 5489 struct ifnet *ifp = ic->ic_ifp; 5490 struct ath_softc *sc = ifp->if_softc; 5491 struct ath_hal *ah = sc->sc_ah; 5492 u_int32_t rfilt; 5493 5494 /* XXX calibration timer? */ 5495 5496 sc->sc_scanning = 1; 5497 sc->sc_syncbeacon = 0; 5498 rfilt = ath_calcrxfilter(sc); 5499 ath_hal_setrxfilter(ah, rfilt); 5500 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 5501 5502 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5503 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr)); 5504 } 5505 5506 static void 5507 ath_scan_end(struct ieee80211com *ic) 5508 { 5509 struct ifnet *ifp = ic->ic_ifp; 5510 struct ath_softc *sc = ifp->if_softc; 5511 struct ath_hal *ah = sc->sc_ah; 5512 u_int32_t rfilt; 5513 5514 sc->sc_scanning = 0; 5515 rfilt = ath_calcrxfilter(sc); 5516 ath_hal_setrxfilter(ah, rfilt); 5517 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5518 5519 ath_hal_process_noisefloor(ah); 5520 5521 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5522 __func__, rfilt, ether_sprintf(sc->sc_curbssid), 5523 sc->sc_curaid); 5524 } 5525 5526 static void 5527 ath_set_channel(struct ieee80211com *ic) 5528 { 5529 struct ifnet *ifp = ic->ic_ifp; 5530 struct ath_softc *sc = ifp->if_softc; 5531 5532 (void) ath_chan_set(sc, ic->ic_curchan); 5533 /* 5534 * If we are returning to our bss channel then mark state 5535 * so the next recv'd beacon's tsf will be used to sync the 5536 * beacon timers. Note that since we only hear beacons in 5537 * sta/ibss mode this has no effect in other operating modes. 5538 */ 5539 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5540 sc->sc_syncbeacon = 1; 5541 } 5542 5543 /* 5544 * Walk the vap list and check if there any vap's in RUN state. 5545 */ 5546 static int 5547 ath_isanyrunningvaps(struct ieee80211vap *this) 5548 { 5549 struct ieee80211com *ic = this->iv_ic; 5550 struct ieee80211vap *vap; 5551 5552 IEEE80211_LOCK_ASSERT(ic); 5553 5554 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5555 if (vap != this && vap->iv_state == IEEE80211_S_RUN) 5556 return 1; 5557 } 5558 return 0; 5559 } 5560 5561 static int 5562 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5563 { 5564 struct ieee80211com *ic = vap->iv_ic; 5565 struct ath_softc *sc = ic->ic_ifp->if_softc; 5566 struct ath_vap *avp = ATH_VAP(vap); 5567 struct ath_hal *ah = sc->sc_ah; 5568 struct ieee80211_node *ni = NULL; 5569 int i, error, stamode; 5570 u_int32_t rfilt; 5571 static const HAL_LED_STATE leds[] = { 5572 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5573 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5574 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5575 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5576 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5577 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5578 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5579 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5580 }; 5581 5582 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5583 ieee80211_state_name[vap->iv_state], 5584 ieee80211_state_name[nstate]); 5585 5586 callout_stop(&sc->sc_cal_ch); 5587 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5588 5589 if (nstate == IEEE80211_S_SCAN) { 5590 /* 5591 * Scanning: turn off beacon miss and don't beacon. 5592 * Mark beacon state so when we reach RUN state we'll 5593 * [re]setup beacons. Unblock the task q thread so 5594 * deferred interrupt processing is done. 5595 */ 5596 ath_hal_intrset(ah, 5597 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5598 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5599 sc->sc_beacons = 0; 5600 taskqueue_unblock(sc->sc_tq); 5601 } 5602 5603 ni = vap->iv_bss; 5604 rfilt = ath_calcrxfilter(sc); 5605 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5606 vap->iv_opmode == IEEE80211_M_IBSS); 5607 if (stamode && nstate == IEEE80211_S_RUN) { 5608 sc->sc_curaid = ni->ni_associd; 5609 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5610 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5611 } 5612 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5613 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid); 5614 ath_hal_setrxfilter(ah, rfilt); 5615 5616 /* XXX is this to restore keycache on resume? */ 5617 if (vap->iv_opmode != IEEE80211_M_STA && 5618 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5619 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5620 if (ath_hal_keyisvalid(ah, i)) 5621 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5622 } 5623 /* 5624 * Notify the rate control algorithm so rates 5625 * are setup should ath_beacon_alloc be called. 5626 */ 5627 ath_rate_newstate(vap, nstate); 5628 5629 /* 5630 * Invoke the parent method to do net80211 work. 5631 */ 5632 error = avp->av_newstate(vap, nstate, arg); 5633 if (error != 0) 5634 goto bad; 5635 5636 if (nstate == IEEE80211_S_RUN) { 5637 /* NB: collect bss node again, it may have changed */ 5638 ni = vap->iv_bss; 5639 5640 DPRINTF(sc, ATH_DEBUG_STATE, 5641 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5642 "capinfo 0x%04x chan %d\n", __func__, 5643 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid), 5644 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5645 5646 switch (vap->iv_opmode) { 5647 case IEEE80211_M_HOSTAP: 5648 case IEEE80211_M_IBSS: 5649 /* 5650 * Allocate and setup the beacon frame. 5651 * 5652 * Stop any previous beacon DMA. This may be 5653 * necessary, for example, when an ibss merge 5654 * causes reconfiguration; there will be a state 5655 * transition from RUN->RUN that means we may 5656 * be called with beacon transmission active. 5657 */ 5658 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5659 5660 error = ath_beacon_alloc(sc, ni); 5661 if (error != 0) 5662 goto bad; 5663 /* 5664 * If joining an adhoc network defer beacon timer 5665 * configuration to the next beacon frame so we 5666 * have a current TSF to use. Otherwise we're 5667 * starting an ibss/bss so there's no need to delay; 5668 * if this is the first vap moving to RUN state, then 5669 * beacon state needs to be [re]configured. 5670 */ 5671 if (vap->iv_opmode == IEEE80211_M_IBSS && 5672 ni->ni_tstamp.tsf != 0) { 5673 sc->sc_syncbeacon = 1; 5674 } else if (!sc->sc_beacons) { 5675 ath_beacon_config(sc, vap); 5676 sc->sc_beacons = 1; 5677 } 5678 break; 5679 case IEEE80211_M_STA: 5680 /* 5681 * Fakeup since we're not called by net80211. 5682 */ 5683 ath_newassoc(ni, 1); 5684 /* 5685 * Defer beacon timer configuration to the next 5686 * beacon frame so we have a current TSF to use 5687 * (any TSF collected when scanning is likely old). 5688 */ 5689 sc->sc_syncbeacon = 1; 5690 break; 5691 case IEEE80211_M_MONITOR: 5692 /* 5693 * Monitor mode vaps have only INIT->RUN and RUN->RUN 5694 * transitions so we must re-enable interrupts here to 5695 * handle the case of a single monitor mode vap. 5696 */ 5697 ath_hal_intrset(ah, sc->sc_imask); 5698 break; 5699 case IEEE80211_M_WDS: 5700 break; 5701 default: 5702 break; 5703 } 5704 /* 5705 * Let the hal process statistics collected during a 5706 * scan so it can provide calibrated noise floor data. 5707 */ 5708 ath_hal_process_noisefloor(ah); 5709 /* 5710 * Reset rssi stats; maybe not the best place... 5711 */ 5712 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5713 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5714 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5715 /* 5716 * Finally, start any timers and the task q thread 5717 * (in case we didn't go through SCAN state). 5718 */ 5719 if (sc->sc_calinterval != 0) { 5720 /* start periodic recalibration timer */ 5721 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz, 5722 ath_calibrate, sc); 5723 } 5724 taskqueue_unblock(sc->sc_tq); 5725 } else if (nstate == IEEE80211_S_INIT) { 5726 /* 5727 * If there are no vaps left in RUN state then 5728 * shutdown host/driver operation: 5729 * o disable interrupts 5730 * o disable the task queue thread 5731 * o mark beacon processing as stopped 5732 */ 5733 if (!ath_isanyrunningvaps(vap)) { 5734 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5735 /* disable interrupts */ 5736 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5737 taskqueue_block(sc->sc_tq); 5738 sc->sc_beacons = 0; 5739 } 5740 } 5741 bad: 5742 return error; 5743 } 5744 5745 /* 5746 * Allocate a key cache slot to the station so we can 5747 * setup a mapping from key index to node. The key cache 5748 * slot is needed for managing antenna state and for 5749 * compression when stations do not use crypto. We do 5750 * it uniliaterally here; if crypto is employed this slot 5751 * will be reassigned. 5752 */ 5753 static void 5754 ath_setup_stationkey(struct ieee80211_node *ni) 5755 { 5756 struct ieee80211vap *vap = ni->ni_vap; 5757 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5758 ieee80211_keyix keyix, rxkeyix; 5759 5760 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5761 /* 5762 * Key cache is full; we'll fall back to doing 5763 * the more expensive lookup in software. Note 5764 * this also means no h/w compression. 5765 */ 5766 /* XXX msg+statistic */ 5767 } else { 5768 /* XXX locking? */ 5769 ni->ni_ucastkey.wk_keyix = keyix; 5770 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5771 /* NB: this will create a pass-thru key entry */ 5772 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, vap->iv_bss); 5773 } 5774 } 5775 5776 /* 5777 * Setup driver-specific state for a newly associated node. 5778 * Note that we're called also on a re-associate, the isnew 5779 * param tells us if this is the first time or not. 5780 */ 5781 static void 5782 ath_newassoc(struct ieee80211_node *ni, int isnew) 5783 { 5784 struct ath_node *an = ATH_NODE(ni); 5785 struct ieee80211vap *vap = ni->ni_vap; 5786 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5787 const struct ieee80211_txparam *tp; 5788 enum ieee80211_phymode mode; 5789 5790 /* 5791 * Deduce netband of station to simplify setting up xmit 5792 * parameters. Note this allows us to assign different 5793 * parameters to each station in a mixed bss (b/g, n/[abg]). 5794 */ 5795 if (ni->ni_flags & IEEE80211_NODE_HT) { 5796 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) 5797 mode = IEEE80211_MODE_11NA; 5798 else 5799 mode = IEEE80211_MODE_11NG; 5800 } else if (IEEE80211_IS_CHAN_A(ni->ni_chan)) 5801 mode = IEEE80211_MODE_11A; 5802 else if (ni->ni_flags & IEEE80211_NODE_ERP) 5803 mode = IEEE80211_MODE_11G; 5804 else 5805 mode = IEEE80211_MODE_11B; 5806 tp = &vap->iv_txparms[mode]; 5807 an->an_tp = tp; 5808 an->an_mcastrix = ath_tx_findrix(sc->sc_rates[mode], tp->mcastrate); 5809 an->an_mgmtrix = ath_tx_findrix(sc->sc_rates[mode], tp->mgmtrate); 5810 5811 ath_rate_newassoc(sc, an, isnew); 5812 if (isnew && 5813 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 5814 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5815 ath_setup_stationkey(ni); 5816 } 5817 5818 static int 5819 getchannels(struct ath_softc *sc, int *nchans, struct ieee80211_channel chans[], 5820 int cc, int ecm, int outdoor) 5821 { 5822 struct ath_hal *ah = sc->sc_ah; 5823 HAL_CHANNEL *halchans; 5824 int i, nhalchans, error; 5825 5826 halchans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 5827 M_TEMP, M_NOWAIT | M_ZERO); 5828 if (halchans == NULL) { 5829 device_printf(sc->sc_dev, 5830 "%s: unable to allocate channel table\n", __func__); 5831 return ENOMEM; 5832 } 5833 error = 0; 5834 if (!ath_hal_init_channels(ah, halchans, IEEE80211_CHAN_MAX, &nhalchans, 5835 NULL, 0, NULL, CTRY_DEFAULT, HAL_MODE_ALL, AH_FALSE, AH_TRUE)) { 5836 error = EINVAL; 5837 goto done; 5838 } 5839 if (nchans == NULL) /* no table requested */ 5840 goto done; 5841 5842 /* 5843 * Convert HAL channels to ieee80211 ones. 5844 */ 5845 for (i = 0; i < nhalchans; i++) { 5846 HAL_CHANNEL *c = &halchans[i]; 5847 struct ieee80211_channel *ichan = &chans[i]; 5848 5849 ichan->ic_ieee = ath_hal_mhz2ieee(ah, c->channel, 5850 c->channelFlags); 5851 if (bootverbose) 5852 device_printf(sc->sc_dev, "hal channel %u/%x -> %u " 5853 "maxpow %d minpow %d maxreg %d\n", 5854 c->channel, c->channelFlags, ichan->ic_ieee, 5855 c->maxTxPower, c->minTxPower, c->maxRegTxPower); 5856 ichan->ic_freq = c->channel; 5857 5858 if ((c->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) { 5859 /* 5860 * Except for AR5211, HAL's PUREG means mixed 5861 * DSSS and OFDM. 5862 */ 5863 ichan->ic_flags = c->channelFlags &~ CHANNEL_PUREG; 5864 ichan->ic_flags |= IEEE80211_CHAN_G; 5865 } else { 5866 ichan->ic_flags = c->channelFlags; 5867 } 5868 5869 if (ath_hal_isgsmsku(ah)) { 5870 /* remap to true frequencies */ 5871 ichan->ic_freq = 922 + (2422 - ichan->ic_freq); 5872 ichan->ic_flags |= IEEE80211_CHAN_GSM; 5873 ichan->ic_ieee = ieee80211_mhz2ieee(ichan->ic_freq, 5874 ichan->ic_flags); 5875 } 5876 ichan->ic_maxregpower = c->maxRegTxPower; /* dBm */ 5877 /* XXX: old hal's don't provide maxTxPower for some parts */ 5878 ichan->ic_maxpower = (c->maxTxPower != 0) ? 5879 c->maxTxPower : 2*c->maxRegTxPower; /* 1/2 dBm */ 5880 ichan->ic_minpower = c->minTxPower; /* 1/2 dBm */ 5881 } 5882 *nchans = nhalchans; 5883 done: 5884 free(halchans, M_TEMP); 5885 return error; 5886 } 5887 5888 static int 5889 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 5890 int nchans, struct ieee80211_channel chans[]) 5891 { 5892 struct ath_softc *sc = ic->ic_ifp->if_softc; 5893 struct ath_hal *ah = sc->sc_ah; 5894 u_int32_t ord; 5895 int error; 5896 5897 (void) ath_hal_getregdomain(ah, &ord); 5898 /* XXX map sku->rd */ 5899 ath_hal_setregdomain(ah, rd->regdomain); 5900 error = getchannels(sc, &nchans, chans, rd->country, 5901 rd->ecm ? AH_TRUE : AH_FALSE, 5902 rd->location == 'O' ? AH_TRUE : AH_FALSE); 5903 if (error != 0) { 5904 /* 5905 * Restore previous state. 5906 */ 5907 ath_hal_setregdomain(ah, ord); 5908 (void) getchannels(sc, NULL, NULL, ic->ic_regdomain.country, 5909 ic->ic_regdomain.ecm ? AH_TRUE : AH_FALSE, 5910 ic->ic_regdomain.location == 'O' ? AH_TRUE : AH_FALSE); 5911 return error; 5912 } 5913 return 0; 5914 } 5915 5916 static void 5917 ath_getradiocaps(struct ieee80211com *ic, 5918 int *nchans, struct ieee80211_channel chans[]) 5919 { 5920 struct ath_softc *sc = ic->ic_ifp->if_softc; 5921 struct ath_hal *ah = sc->sc_ah; 5922 u_int32_t ord; 5923 5924 (void) ath_hal_getregdomain(ah, &ord); 5925 ath_hal_setregdomain(ah, 0); 5926 /* XXX not quite right but close enough for now */ 5927 getchannels(sc, nchans, chans, CTRY_DEBUG, AH_TRUE, AH_FALSE); 5928 5929 /* NB: restore previous state */ 5930 ath_hal_setregdomain(ah, ord); 5931 (void) getchannels(sc, NULL, NULL, ic->ic_regdomain.country, 5932 ic->ic_regdomain.ecm ? AH_TRUE : AH_FALSE, 5933 ic->ic_regdomain.location == 'O' ? AH_TRUE : AH_FALSE); 5934 } 5935 5936 static int 5937 ath_mapregdomain(struct ath_softc *sc, u_int32_t rd) 5938 { 5939 /* map Atheros rd's to SKU's */ 5940 return rd; 5941 } 5942 5943 static int 5944 ath_getchannels(struct ath_softc *sc) 5945 { 5946 struct ifnet *ifp = sc->sc_ifp; 5947 struct ieee80211com *ic = ifp->if_l2com; 5948 struct ath_hal *ah = sc->sc_ah; 5949 int error; 5950 5951 /* 5952 * Convert HAL channels to ieee80211 ones. 5953 */ 5954 error = getchannels(sc, &ic->ic_nchans, ic->ic_channels, 5955 CTRY_DEFAULT, AH_TRUE, AH_FALSE); 5956 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 5957 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 5958 if (error) { 5959 if_printf(ifp, "%s: unable to collect channel list from hal, " 5960 "error %d\n", __func__, error); 5961 if (error == EINVAL) { 5962 if_printf(ifp, "%s: regdomain likely %u country code %u\n", 5963 __func__, sc->sc_eerd, sc->sc_eecc); 5964 } 5965 return error; 5966 } 5967 ic->ic_regdomain.regdomain = ath_mapregdomain(sc, sc->sc_eerd); 5968 ic->ic_regdomain.country = sc->sc_eecc; 5969 ic->ic_regdomain.ecm = 1; 5970 ic->ic_regdomain.location = 'I'; 5971 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 5972 ic->ic_regdomain.isocc[1] = ' '; 5973 return 0; 5974 } 5975 5976 static void 5977 ath_led_done(void *arg) 5978 { 5979 struct ath_softc *sc = arg; 5980 5981 sc->sc_blinking = 0; 5982 } 5983 5984 /* 5985 * Turn the LED off: flip the pin and then set a timer so no 5986 * update will happen for the specified duration. 5987 */ 5988 static void 5989 ath_led_off(void *arg) 5990 { 5991 struct ath_softc *sc = arg; 5992 5993 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5994 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 5995 } 5996 5997 /* 5998 * Blink the LED according to the specified on/off times. 5999 */ 6000 static void 6001 ath_led_blink(struct ath_softc *sc, int on, int off) 6002 { 6003 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 6004 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 6005 sc->sc_blinking = 1; 6006 sc->sc_ledoff = off; 6007 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 6008 } 6009 6010 static void 6011 ath_led_event(struct ath_softc *sc, int event) 6012 { 6013 6014 sc->sc_ledevent = ticks; /* time of last event */ 6015 if (sc->sc_blinking) /* don't interrupt active blink */ 6016 return; 6017 switch (event) { 6018 case ATH_LED_POLL: 6019 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 6020 sc->sc_hwmap[0].ledoff); 6021 break; 6022 case ATH_LED_TX: 6023 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 6024 sc->sc_hwmap[sc->sc_txrate].ledoff); 6025 break; 6026 case ATH_LED_RX: 6027 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 6028 sc->sc_hwmap[sc->sc_rxrate].ledoff); 6029 break; 6030 } 6031 } 6032 6033 static int 6034 ath_rate_setup(struct ath_softc *sc, u_int mode) 6035 { 6036 struct ath_hal *ah = sc->sc_ah; 6037 const HAL_RATE_TABLE *rt; 6038 6039 switch (mode) { 6040 case IEEE80211_MODE_11A: 6041 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 6042 break; 6043 case IEEE80211_MODE_HALF: 6044 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 6045 break; 6046 case IEEE80211_MODE_QUARTER: 6047 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 6048 break; 6049 case IEEE80211_MODE_11B: 6050 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 6051 break; 6052 case IEEE80211_MODE_11G: 6053 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 6054 break; 6055 case IEEE80211_MODE_TURBO_A: 6056 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 6057 #if HAL_ABI_VERSION < 0x07013100 6058 if (rt == NULL) /* XXX bandaid for old hal's */ 6059 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 6060 #endif 6061 break; 6062 case IEEE80211_MODE_TURBO_G: 6063 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 6064 break; 6065 case IEEE80211_MODE_STURBO_A: 6066 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 6067 break; 6068 case IEEE80211_MODE_11NA: 6069 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 6070 break; 6071 case IEEE80211_MODE_11NG: 6072 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 6073 break; 6074 default: 6075 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 6076 __func__, mode); 6077 return 0; 6078 } 6079 sc->sc_rates[mode] = rt; 6080 return (rt != NULL); 6081 } 6082 6083 static void 6084 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 6085 { 6086 #define N(a) (sizeof(a)/sizeof(a[0])) 6087 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 6088 static const struct { 6089 u_int rate; /* tx/rx 802.11 rate */ 6090 u_int16_t timeOn; /* LED on time (ms) */ 6091 u_int16_t timeOff; /* LED off time (ms) */ 6092 } blinkrates[] = { 6093 { 108, 40, 10 }, 6094 { 96, 44, 11 }, 6095 { 72, 50, 13 }, 6096 { 48, 57, 14 }, 6097 { 36, 67, 16 }, 6098 { 24, 80, 20 }, 6099 { 22, 100, 25 }, 6100 { 18, 133, 34 }, 6101 { 12, 160, 40 }, 6102 { 10, 200, 50 }, 6103 { 6, 240, 58 }, 6104 { 4, 267, 66 }, 6105 { 2, 400, 100 }, 6106 { 0, 500, 130 }, 6107 /* XXX half/quarter rates */ 6108 }; 6109 const HAL_RATE_TABLE *rt; 6110 int i, j; 6111 6112 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 6113 rt = sc->sc_rates[mode]; 6114 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 6115 for (i = 0; i < rt->rateCount; i++) 6116 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 6117 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6118 for (i = 0; i < 32; i++) { 6119 u_int8_t ix = rt->rateCodeToIndex[i]; 6120 if (ix == 0xff) { 6121 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6122 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6123 continue; 6124 } 6125 sc->sc_hwmap[i].ieeerate = 6126 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 6127 if (rt->info[ix].phy == IEEE80211_T_HT) 6128 sc->sc_hwmap[i].ieeerate |= 0x80; /* MCS */ 6129 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6130 if (rt->info[ix].shortPreamble || 6131 rt->info[ix].phy == IEEE80211_T_OFDM) 6132 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6133 /* NB: receive frames include FCS */ 6134 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 6135 IEEE80211_RADIOTAP_F_FCS; 6136 /* setup blink rate table to avoid per-packet lookup */ 6137 for (j = 0; j < N(blinkrates)-1; j++) 6138 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6139 break; 6140 /* NB: this uses the last entry if the rate isn't found */ 6141 /* XXX beware of overlow */ 6142 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6143 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6144 } 6145 sc->sc_currates = rt; 6146 sc->sc_curmode = mode; 6147 /* 6148 * All protection frames are transmited at 2Mb/s for 6149 * 11g, otherwise at 1Mb/s. 6150 */ 6151 if (mode == IEEE80211_MODE_11G) 6152 sc->sc_protrix = ath_tx_findrix(rt, 2*2); 6153 else 6154 sc->sc_protrix = ath_tx_findrix(rt, 2*1); 6155 /* NB: caller is responsible for reseting rate control state */ 6156 #undef N 6157 } 6158 6159 #ifdef ATH_DEBUG 6160 static void 6161 ath_printrxbuf(const struct ath_buf *bf, u_int ix, int done) 6162 { 6163 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 6164 const struct ath_desc *ds; 6165 int i; 6166 6167 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6168 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 6169 " %08x %08x %08x %08x\n", 6170 ix, ds, (const struct ath_desc *)bf->bf_daddr + i, 6171 ds->ds_link, ds->ds_data, 6172 !done ? "" : (rs->rs_status == 0) ? " *" : " !", 6173 ds->ds_ctl0, ds->ds_ctl1, 6174 ds->ds_hw[0], ds->ds_hw[1]); 6175 } 6176 } 6177 6178 static void 6179 ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done) 6180 { 6181 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 6182 const struct ath_desc *ds; 6183 int i; 6184 6185 printf("Q%u[%3u]", qnum, ix); 6186 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6187 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 6188 " %08x %08x %08x %08x %08x %08x\n", 6189 ds, (const struct ath_desc *)bf->bf_daddr + i, 6190 ds->ds_link, ds->ds_data, bf->bf_flags, 6191 !done ? "" : (ts->ts_status == 0) ? " *" : " !", 6192 ds->ds_ctl0, ds->ds_ctl1, 6193 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 6194 } 6195 } 6196 #endif /* ATH_DEBUG */ 6197 6198 static void 6199 ath_watchdog(struct ifnet *ifp) 6200 { 6201 struct ath_softc *sc = ifp->if_softc; 6202 6203 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && !sc->sc_invalid) { 6204 if_printf(ifp, "device timeout\n"); 6205 ath_reset(ifp); 6206 ifp->if_oerrors++; 6207 sc->sc_stats.ast_watchdog++; 6208 } 6209 } 6210 6211 #ifdef ATH_DIAGAPI 6212 /* 6213 * Diagnostic interface to the HAL. This is used by various 6214 * tools to do things like retrieve register contents for 6215 * debugging. The mechanism is intentionally opaque so that 6216 * it can change frequently w/o concern for compatiblity. 6217 */ 6218 static int 6219 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 6220 { 6221 struct ath_hal *ah = sc->sc_ah; 6222 u_int id = ad->ad_id & ATH_DIAG_ID; 6223 void *indata = NULL; 6224 void *outdata = NULL; 6225 u_int32_t insize = ad->ad_in_size; 6226 u_int32_t outsize = ad->ad_out_size; 6227 int error = 0; 6228 6229 if (ad->ad_id & ATH_DIAG_IN) { 6230 /* 6231 * Copy in data. 6232 */ 6233 indata = malloc(insize, M_TEMP, M_NOWAIT); 6234 if (indata == NULL) { 6235 error = ENOMEM; 6236 goto bad; 6237 } 6238 error = copyin(ad->ad_in_data, indata, insize); 6239 if (error) 6240 goto bad; 6241 } 6242 if (ad->ad_id & ATH_DIAG_DYN) { 6243 /* 6244 * Allocate a buffer for the results (otherwise the HAL 6245 * returns a pointer to a buffer where we can read the 6246 * results). Note that we depend on the HAL leaving this 6247 * pointer for us to use below in reclaiming the buffer; 6248 * may want to be more defensive. 6249 */ 6250 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 6251 if (outdata == NULL) { 6252 error = ENOMEM; 6253 goto bad; 6254 } 6255 } 6256 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 6257 if (outsize < ad->ad_out_size) 6258 ad->ad_out_size = outsize; 6259 if (outdata != NULL) 6260 error = copyout(outdata, ad->ad_out_data, 6261 ad->ad_out_size); 6262 } else { 6263 error = EINVAL; 6264 } 6265 bad: 6266 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 6267 free(indata, M_TEMP); 6268 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 6269 free(outdata, M_TEMP); 6270 return error; 6271 } 6272 #endif /* ATH_DIAGAPI */ 6273 6274 static int 6275 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 6276 { 6277 #define IS_RUNNING(ifp) \ 6278 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 6279 struct ath_softc *sc = ifp->if_softc; 6280 struct ieee80211com *ic = ifp->if_l2com; 6281 struct ifreq *ifr = (struct ifreq *)data; 6282 int error = 0; 6283 6284 switch (cmd) { 6285 case SIOCSIFFLAGS: 6286 ATH_LOCK(sc); 6287 if (IS_RUNNING(ifp)) { 6288 /* 6289 * To avoid rescanning another access point, 6290 * do not call ath_init() here. Instead, 6291 * only reflect promisc mode settings. 6292 */ 6293 ath_mode_init(sc); 6294 } else if (ifp->if_flags & IFF_UP) { 6295 /* 6296 * Beware of being called during attach/detach 6297 * to reset promiscuous mode. In that case we 6298 * will still be marked UP but not RUNNING. 6299 * However trying to re-init the interface 6300 * is the wrong thing to do as we've already 6301 * torn down much of our state. There's 6302 * probably a better way to deal with this. 6303 */ 6304 if (!sc->sc_invalid) 6305 ath_init(sc); /* XXX lose error */ 6306 } else 6307 ath_stop_locked(ifp); 6308 ATH_UNLOCK(sc); 6309 break; 6310 case SIOCGIFMEDIA: 6311 case SIOCSIFMEDIA: 6312 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 6313 break; 6314 case SIOCGATHSTATS: 6315 /* NB: embed these numbers to get a consistent view */ 6316 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 6317 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 6318 #if 0 6319 ieee80211_getsignal(ic, &sc->sc_stats.ast_rx_rssi, 6320 &sc->sc_stats.ast_rx_noise); 6321 #endif 6322 sc->sc_stats.ast_tx_rate = sc->sc_hwmap[sc->sc_txrate].ieeerate; 6323 return copyout(&sc->sc_stats, 6324 ifr->ifr_data, sizeof (sc->sc_stats)); 6325 #ifdef ATH_DIAGAPI 6326 case SIOCGATHDIAG: 6327 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 6328 break; 6329 #endif 6330 case SIOCGIFADDR: 6331 error = ether_ioctl(ifp, cmd, data); 6332 break; 6333 default: 6334 error = EINVAL; 6335 break; 6336 } 6337 return error; 6338 #undef IS_RUNNING 6339 } 6340 6341 static int 6342 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 6343 { 6344 struct ath_softc *sc = arg1; 6345 u_int slottime = ath_hal_getslottime(sc->sc_ah); 6346 int error; 6347 6348 error = sysctl_handle_int(oidp, &slottime, 0, req); 6349 if (error || !req->newptr) 6350 return error; 6351 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 6352 } 6353 6354 static int 6355 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 6356 { 6357 struct ath_softc *sc = arg1; 6358 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 6359 int error; 6360 6361 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 6362 if (error || !req->newptr) 6363 return error; 6364 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 6365 } 6366 6367 static int 6368 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 6369 { 6370 struct ath_softc *sc = arg1; 6371 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 6372 int error; 6373 6374 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 6375 if (error || !req->newptr) 6376 return error; 6377 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 6378 } 6379 6380 static int 6381 ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 6382 { 6383 struct ath_softc *sc = arg1; 6384 int softled = sc->sc_softled; 6385 int error; 6386 6387 error = sysctl_handle_int(oidp, &softled, 0, req); 6388 if (error || !req->newptr) 6389 return error; 6390 softled = (softled != 0); 6391 if (softled != sc->sc_softled) { 6392 if (softled) { 6393 /* NB: handle any sc_ledpin change */ 6394 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 6395 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6396 !sc->sc_ledon); 6397 } 6398 sc->sc_softled = softled; 6399 } 6400 return 0; 6401 } 6402 6403 static int 6404 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) 6405 { 6406 struct ath_softc *sc = arg1; 6407 int ledpin = sc->sc_ledpin; 6408 int error; 6409 6410 error = sysctl_handle_int(oidp, &ledpin, 0, req); 6411 if (error || !req->newptr) 6412 return error; 6413 if (ledpin != sc->sc_ledpin) { 6414 sc->sc_ledpin = ledpin; 6415 if (sc->sc_softled) { 6416 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 6417 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6418 !sc->sc_ledon); 6419 } 6420 } 6421 return 0; 6422 } 6423 6424 static int 6425 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) 6426 { 6427 struct ath_softc *sc = arg1; 6428 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah); 6429 int error; 6430 6431 error = sysctl_handle_int(oidp, &txantenna, 0, req); 6432 if (!error && req->newptr) { 6433 /* XXX assumes 2 antenna ports */ 6434 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B) 6435 return EINVAL; 6436 ath_hal_setantennaswitch(sc->sc_ah, txantenna); 6437 /* 6438 * NB: with the switch locked this isn't meaningful, 6439 * but set it anyway so things like radiotap get 6440 * consistent info in their data. 6441 */ 6442 sc->sc_txantenna = txantenna; 6443 } 6444 return error; 6445 } 6446 6447 static int 6448 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 6449 { 6450 struct ath_softc *sc = arg1; 6451 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 6452 int error; 6453 6454 error = sysctl_handle_int(oidp, &defantenna, 0, req); 6455 if (!error && req->newptr) 6456 ath_hal_setdefantenna(sc->sc_ah, defantenna); 6457 return error; 6458 } 6459 6460 static int 6461 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 6462 { 6463 struct ath_softc *sc = arg1; 6464 u_int diversity = ath_hal_getdiversity(sc->sc_ah); 6465 int error; 6466 6467 error = sysctl_handle_int(oidp, &diversity, 0, req); 6468 if (error || !req->newptr) 6469 return error; 6470 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 6471 return EINVAL; 6472 sc->sc_diversity = diversity; 6473 return 0; 6474 } 6475 6476 static int 6477 ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 6478 { 6479 struct ath_softc *sc = arg1; 6480 u_int32_t diag; 6481 int error; 6482 6483 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 6484 return EINVAL; 6485 error = sysctl_handle_int(oidp, &diag, 0, req); 6486 if (error || !req->newptr) 6487 return error; 6488 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 6489 } 6490 6491 static int 6492 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 6493 { 6494 struct ath_softc *sc = arg1; 6495 struct ifnet *ifp = sc->sc_ifp; 6496 u_int32_t scale; 6497 int error; 6498 6499 (void) ath_hal_gettpscale(sc->sc_ah, &scale); 6500 error = sysctl_handle_int(oidp, &scale, 0, req); 6501 if (error || !req->newptr) 6502 return error; 6503 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : 6504 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6505 } 6506 6507 static int 6508 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 6509 { 6510 struct ath_softc *sc = arg1; 6511 u_int tpc = ath_hal_gettpc(sc->sc_ah); 6512 int error; 6513 6514 error = sysctl_handle_int(oidp, &tpc, 0, req); 6515 if (error || !req->newptr) 6516 return error; 6517 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 6518 } 6519 6520 static int 6521 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 6522 { 6523 struct ath_softc *sc = arg1; 6524 struct ifnet *ifp = sc->sc_ifp; 6525 struct ath_hal *ah = sc->sc_ah; 6526 u_int rfkill = ath_hal_getrfkill(ah); 6527 int error; 6528 6529 error = sysctl_handle_int(oidp, &rfkill, 0, req); 6530 if (error || !req->newptr) 6531 return error; 6532 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */ 6533 return 0; 6534 if (!ath_hal_setrfkill(ah, rfkill)) 6535 return EINVAL; 6536 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0; 6537 } 6538 6539 static int 6540 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 6541 { 6542 struct ath_softc *sc = arg1; 6543 u_int rfsilent; 6544 int error; 6545 6546 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 6547 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 6548 if (error || !req->newptr) 6549 return error; 6550 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) 6551 return EINVAL; 6552 sc->sc_rfsilentpin = rfsilent & 0x1c; 6553 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 6554 return 0; 6555 } 6556 6557 static int 6558 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 6559 { 6560 struct ath_softc *sc = arg1; 6561 u_int32_t tpack; 6562 int error; 6563 6564 (void) ath_hal_gettpack(sc->sc_ah, &tpack); 6565 error = sysctl_handle_int(oidp, &tpack, 0, req); 6566 if (error || !req->newptr) 6567 return error; 6568 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0; 6569 } 6570 6571 static int 6572 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 6573 { 6574 struct ath_softc *sc = arg1; 6575 u_int32_t tpcts; 6576 int error; 6577 6578 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts); 6579 error = sysctl_handle_int(oidp, &tpcts, 0, req); 6580 if (error || !req->newptr) 6581 return error; 6582 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0; 6583 } 6584 6585 static void 6586 ath_sysctlattach(struct ath_softc *sc) 6587 { 6588 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 6589 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 6590 struct ath_hal *ah = sc->sc_ah; 6591 6592 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6593 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0, 6594 "EEPROM country code"); 6595 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6596 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0, 6597 "EEPROM regdomain code"); 6598 #ifdef ATH_DEBUG 6599 sc->sc_debug = ath_debug; 6600 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6601 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 6602 "control debugging printfs"); 6603 #endif 6604 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6605 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6606 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 6607 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6608 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6609 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 6610 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6611 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6612 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 6613 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6614 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6615 ath_sysctl_softled, "I", "enable/disable software LED support"); 6616 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6617 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6618 ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); 6619 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6620 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 6621 "setting to turn LED on"); 6622 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6623 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 6624 "idle time for inactivity LED (ticks)"); 6625 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6626 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6627 ath_sysctl_txantenna, "I", "antenna switch"); 6628 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6629 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6630 ath_sysctl_rxantenna, "I", "default/rx antenna"); 6631 if (ath_hal_hasdiversity(ah)) 6632 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6633 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6634 ath_sysctl_diversity, "I", "antenna diversity"); 6635 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 6636 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6637 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 6638 "tx descriptor batching"); 6639 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6640 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6641 ath_sysctl_diag, "I", "h/w diagnostic control"); 6642 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6643 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6644 ath_sysctl_tpscale, "I", "tx power scaling"); 6645 if (ath_hal_hastpc(ah)) { 6646 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6647 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6648 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 6649 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6650 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6651 ath_sysctl_tpack, "I", "tx power for ack frames"); 6652 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6653 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6654 ath_sysctl_tpcts, "I", "tx power for cts frames"); 6655 } 6656 if (ath_hal_hasfastframes(sc->sc_ah)) { 6657 sc->sc_fftxqmin = ATH_FF_TXQMIN; 6658 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6659 "fftxqmin", CTLFLAG_RW, &sc->sc_fftxqmin, 0, 6660 "min frames before fast-frame staging"); 6661 sc->sc_fftxqmax = ATH_FF_TXQMAX; 6662 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6663 "fftxqmax", CTLFLAG_RW, &sc->sc_fftxqmax, 0, 6664 "max queued frames before tail drop"); 6665 } 6666 if (ath_hal_hasrfsilent(ah)) { 6667 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6668 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6669 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 6670 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6671 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6672 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 6673 } 6674 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 6675 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6676 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 6677 "mask of error frames to pass when monitoring"); 6678 } 6679 6680 static void 6681 ath_bpfattach(struct ath_softc *sc) 6682 { 6683 struct ifnet *ifp = sc->sc_ifp; 6684 6685 bpfattach(ifp, DLT_IEEE802_11_RADIO, 6686 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th)); 6687 /* 6688 * Initialize constant fields. 6689 * XXX make header lengths a multiple of 32-bits so subsequent 6690 * headers are properly aligned; this is a kludge to keep 6691 * certain applications happy. 6692 * 6693 * NB: the channel is setup each time we transition to the 6694 * RUN state to avoid filling it in for each frame. 6695 */ 6696 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 6697 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 6698 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 6699 6700 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 6701 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 6702 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 6703 } 6704 6705 static int 6706 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 6707 struct ath_buf *bf, struct mbuf *m0, 6708 const struct ieee80211_bpf_params *params) 6709 { 6710 struct ifnet *ifp = sc->sc_ifp; 6711 struct ieee80211com *ic = ifp->if_l2com; 6712 struct ath_hal *ah = sc->sc_ah; 6713 int error, ismcast, ismrr; 6714 int hdrlen, pktlen, try0, txantenna; 6715 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3; 6716 struct ieee80211_frame *wh; 6717 u_int flags, ctsduration; 6718 HAL_PKT_TYPE atype; 6719 const HAL_RATE_TABLE *rt; 6720 struct ath_desc *ds; 6721 u_int pri; 6722 6723 wh = mtod(m0, struct ieee80211_frame *); 6724 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6725 hdrlen = ieee80211_anyhdrsize(wh); 6726 /* 6727 * Packet length must not include any 6728 * pad bytes; deduct them here. 6729 */ 6730 /* XXX honor IEEE80211_BPF_DATAPAD */ 6731 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 6732 6733 error = ath_tx_dmasetup(sc, bf, m0); 6734 if (error != 0) 6735 return error; 6736 m0 = bf->bf_m; /* NB: may have changed */ 6737 wh = mtod(m0, struct ieee80211_frame *); 6738 bf->bf_node = ni; /* NB: held reference */ 6739 6740 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 6741 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 6742 if (params->ibp_flags & IEEE80211_BPF_RTS) 6743 flags |= HAL_TXDESC_RTSENA; 6744 else if (params->ibp_flags & IEEE80211_BPF_CTS) 6745 flags |= HAL_TXDESC_CTSENA; 6746 /* XXX leave ismcast to injector? */ 6747 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 6748 flags |= HAL_TXDESC_NOACK; 6749 6750 rt = sc->sc_currates; 6751 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 6752 rix = ath_tx_findrix(rt, params->ibp_rate0); 6753 txrate = rt->info[rix].rateCode; 6754 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6755 txrate |= rt->info[rix].shortPreamble; 6756 sc->sc_txrate = txrate; 6757 try0 = params->ibp_try0; 6758 ismrr = (params->ibp_try1 != 0); 6759 txantenna = params->ibp_pri >> 2; 6760 if (txantenna == 0) /* XXX? */ 6761 txantenna = sc->sc_txantenna; 6762 ctsduration = 0; 6763 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { 6764 cix = ath_tx_findrix(rt, params->ibp_ctsrate); 6765 ctsrate = rt->info[cix].rateCode; 6766 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) { 6767 ctsrate |= rt->info[cix].shortPreamble; 6768 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6769 ctsduration += rt->info[cix].spAckDuration; 6770 ctsduration += ath_hal_computetxtime(ah, 6771 rt, pktlen, rix, AH_TRUE); 6772 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6773 ctsduration += rt->info[rix].spAckDuration; 6774 } else { 6775 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6776 ctsduration += rt->info[cix].lpAckDuration; 6777 ctsduration += ath_hal_computetxtime(ah, 6778 rt, pktlen, rix, AH_FALSE); 6779 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6780 ctsduration += rt->info[rix].lpAckDuration; 6781 } 6782 ismrr = 0; /* XXX */ 6783 } else 6784 ctsrate = 0; 6785 pri = params->ibp_pri & 3; 6786 /* 6787 * NB: we mark all packets as type PSPOLL so the h/w won't 6788 * set the sequence number, duration, etc. 6789 */ 6790 atype = HAL_PKT_TYPE_PSPOLL; 6791 6792 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 6793 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 6794 sc->sc_hwmap[txrate].ieeerate, -1); 6795 6796 if (bpf_peers_present(ifp->if_bpf)) { 6797 u_int64_t tsf = ath_hal_gettsf64(ah); 6798 6799 sc->sc_tx_th.wt_tsf = htole64(tsf); 6800 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 6801 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 6802 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6803 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 6804 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 6805 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 6806 6807 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0); 6808 } 6809 6810 /* 6811 * Formulate first tx descriptor with tx controls. 6812 */ 6813 ds = bf->bf_desc; 6814 /* XXX check return value? */ 6815 ath_hal_setuptxdesc(ah, ds 6816 , pktlen /* packet length */ 6817 , hdrlen /* header length */ 6818 , atype /* Atheros packet type */ 6819 , params->ibp_power /* txpower */ 6820 , txrate, try0 /* series 0 rate/tries */ 6821 , HAL_TXKEYIX_INVALID /* key cache index */ 6822 , txantenna /* antenna mode */ 6823 , flags /* flags */ 6824 , ctsrate /* rts/cts rate */ 6825 , ctsduration /* rts/cts duration */ 6826 ); 6827 bf->bf_flags = flags; 6828 6829 if (ismrr) { 6830 rix = ath_tx_findrix(rt, params->ibp_rate1); 6831 rate1 = rt->info[rix].rateCode; 6832 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6833 rate1 |= rt->info[rix].shortPreamble; 6834 if (params->ibp_try2) { 6835 rix = ath_tx_findrix(rt, params->ibp_rate2); 6836 rate2 = rt->info[rix].rateCode; 6837 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6838 rate2 |= rt->info[rix].shortPreamble; 6839 } else 6840 rate2 = 0; 6841 if (params->ibp_try3) { 6842 rix = ath_tx_findrix(rt, params->ibp_rate3); 6843 rate3 = rt->info[rix].rateCode; 6844 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6845 rate3 |= rt->info[rix].shortPreamble; 6846 } else 6847 rate3 = 0; 6848 ath_hal_setupxtxdesc(ah, ds 6849 , rate1, params->ibp_try1 /* series 1 */ 6850 , rate2, params->ibp_try2 /* series 2 */ 6851 , rate3, params->ibp_try3 /* series 3 */ 6852 ); 6853 } 6854 6855 /* NB: no buffered multicast in power save support */ 6856 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf); 6857 return 0; 6858 } 6859 6860 static int 6861 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 6862 const struct ieee80211_bpf_params *params) 6863 { 6864 struct ieee80211com *ic = ni->ni_ic; 6865 struct ifnet *ifp = ic->ic_ifp; 6866 struct ath_softc *sc = ifp->if_softc; 6867 struct ath_buf *bf; 6868 6869 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 6870 ieee80211_free_node(ni); 6871 m_freem(m); 6872 return ENETDOWN; 6873 } 6874 /* 6875 * Grab a TX buffer and associated resources. 6876 */ 6877 ATH_TXBUF_LOCK(sc); 6878 bf = STAILQ_FIRST(&sc->sc_txbuf); 6879 if (bf != NULL) 6880 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 6881 ATH_TXBUF_UNLOCK(sc); 6882 if (bf == NULL) { 6883 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n", 6884 __func__); 6885 sc->sc_stats.ast_tx_qstop++; 6886 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 6887 ieee80211_free_node(ni); 6888 m_freem(m); 6889 return ENOBUFS; 6890 } 6891 6892 ifp->if_opackets++; 6893 sc->sc_stats.ast_tx_raw++; 6894 6895 if (params == NULL) { 6896 /* 6897 * Legacy path; interpret frame contents to decide 6898 * precisely how to send the frame. 6899 */ 6900 if (ath_tx_start(sc, ni, bf, m)) 6901 goto bad; 6902 } else { 6903 /* 6904 * Caller supplied explicit parameters to use in 6905 * sending the frame. 6906 */ 6907 if (ath_tx_raw_start(sc, ni, bf, m, params)) 6908 goto bad; 6909 } 6910 ifp->if_timer = 5; 6911 6912 return 0; 6913 bad: 6914 ifp->if_oerrors++; 6915 ATH_TXBUF_LOCK(sc); 6916 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 6917 ATH_TXBUF_UNLOCK(sc); 6918 ieee80211_free_node(ni); 6919 return EIO; /* XXX */ 6920 } 6921 6922 /* 6923 * Announce various information on device/driver attach. 6924 */ 6925 static void 6926 ath_announce(struct ath_softc *sc) 6927 { 6928 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 6929 struct ifnet *ifp = sc->sc_ifp; 6930 struct ath_hal *ah = sc->sc_ah; 6931 u_int modes, cc; 6932 6933 if_printf(ifp, "mac %d.%d phy %d.%d", 6934 ah->ah_macVersion, ah->ah_macRev, 6935 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 6936 /* 6937 * Print radio revision(s). We check the wireless modes 6938 * to avoid falsely printing revs for inoperable parts. 6939 * Dual-band radio revs are returned in the 5Ghz rev number. 6940 */ 6941 ath_hal_getcountrycode(ah, &cc); 6942 modes = ath_hal_getwirelessmodes(ah, cc); 6943 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 6944 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 6945 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 6946 ah->ah_analog5GhzRev >> 4, 6947 ah->ah_analog5GhzRev & 0xf, 6948 ah->ah_analog2GhzRev >> 4, 6949 ah->ah_analog2GhzRev & 0xf); 6950 else 6951 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 6952 ah->ah_analog5GhzRev & 0xf); 6953 } else 6954 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 6955 ah->ah_analog5GhzRev & 0xf); 6956 printf("\n"); 6957 if (bootverbose) { 6958 int i; 6959 for (i = 0; i <= WME_AC_VO; i++) { 6960 struct ath_txq *txq = sc->sc_ac2q[i]; 6961 if_printf(ifp, "Use hw queue %u for %s traffic\n", 6962 txq->axq_qnum, ieee80211_wme_acnames[i]); 6963 } 6964 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 6965 sc->sc_cabq->axq_qnum); 6966 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 6967 } 6968 if (ath_rxbuf != ATH_RXBUF) 6969 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 6970 if (ath_txbuf != ATH_TXBUF) 6971 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 6972 #undef HAL_MODE_DUALBAND 6973 } 6974