1 /* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 #include "ah_eeprom_9287.h" 27 28 #include "ar9002/ar9280.h" 29 #include "ar9002/ar9287.h" 30 #include "ar5416/ar5416reg.h" 31 #include "ar5416/ar5416phy.h" 32 33 #include "ar9002/ar9287_cal.h" 34 #include "ar9002/ar9287_reset.h" 35 #include "ar9002/ar9287_olc.h" 36 37 #include "ar9002/ar9287.ini" 38 39 static const HAL_PERCAL_DATA ar9287_iq_cal = { /* single sample */ 40 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 41 .calNumSamples = MIN_CAL_SAMPLES, 42 .calCountMax = PER_MAX_LOG_COUNT, 43 .calCollect = ar5416IQCalCollect, 44 .calPostProc = ar5416IQCalibration 45 }; 46 static const HAL_PERCAL_DATA ar9287_adc_gain_cal = { /* single sample */ 47 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 48 .calNumSamples = MIN_CAL_SAMPLES, 49 .calCountMax = PER_MIN_LOG_COUNT, 50 .calCollect = ar5416AdcGainCalCollect, 51 .calPostProc = ar5416AdcGainCalibration 52 }; 53 static const HAL_PERCAL_DATA ar9287_adc_dc_cal = { /* single sample */ 54 .calName = "ADC DC", .calType = ADC_DC_CAL, 55 .calNumSamples = MIN_CAL_SAMPLES, 56 .calCountMax = PER_MIN_LOG_COUNT, 57 .calCollect = ar5416AdcDcCalCollect, 58 .calPostProc = ar5416AdcDcCalibration 59 }; 60 static const HAL_PERCAL_DATA ar9287_adc_init_dc_cal = { 61 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 62 .calNumSamples = MIN_CAL_SAMPLES, 63 .calCountMax = INIT_LOG_COUNT, 64 .calCollect = ar5416AdcDcCalCollect, 65 .calPostProc = ar5416AdcDcCalibration 66 }; 67 68 static void ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 69 static HAL_BOOL ar9287FillCapabilityInfo(struct ath_hal *ah); 70 static void ar9287WriteIni(struct ath_hal *ah, 71 const struct ieee80211_channel *chan); 72 73 static void 74 ar9287AniSetup(struct ath_hal *ah) 75 { 76 /* 77 * These are the parameters from the AR5416 ANI code; 78 * they likely need quite a bit of adjustment for the 79 * AR9280. 80 */ 81 static const struct ar5212AniParams aniparams = { 82 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 83 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 84 .coarseHigh = { -14, -14, -14, -14, -12 }, 85 .coarseLow = { -64, -64, -64, -64, -70 }, 86 .firpwr = { -78, -78, -78, -78, -80 }, 87 .maxSpurImmunityLevel = 2, 88 .cycPwrThr1 = { 2, 4, 6 }, 89 .maxFirstepLevel = 2, /* levels 0..2 */ 90 .firstep = { 0, 4, 8 }, 91 .ofdmTrigHigh = 500, 92 .ofdmTrigLow = 200, 93 .cckTrigHigh = 200, 94 .cckTrigLow = 100, 95 .rssiThrHigh = 40, 96 .rssiThrLow = 7, 97 .period = 100, 98 }; 99 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 100 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 101 102 /* NB: ANI is not enabled yet */ 103 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 104 } 105 106 /* 107 * Attach for an AR9287 part. 108 */ 109 static struct ath_hal * 110 ar9287Attach(uint16_t devid, HAL_SOFTC sc, 111 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 112 HAL_STATUS *status) 113 { 114 struct ath_hal_9287 *ahp9287; 115 struct ath_hal_5212 *ahp; 116 struct ath_hal *ah; 117 uint32_t val; 118 HAL_STATUS ecode; 119 HAL_BOOL rfStatus; 120 int8_t pwr_table_offset; 121 122 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 123 __func__, sc, (void*) st, (void*) sh); 124 125 /* NB: memory is returned zero'd */ 126 ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287)); 127 if (ahp9287 == AH_NULL) { 128 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 129 "%s: cannot allocate memory for state block\n", __func__); 130 *status = HAL_ENOMEM; 131 return AH_NULL; 132 } 133 ahp = AH5212(ahp9287); 134 ah = &ahp->ah_priv.h; 135 136 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 137 138 /* XXX override with 9280 specific state */ 139 /* override 5416 methods for our needs */ 140 ah->ah_setAntennaSwitch = ar9287SetAntennaSwitch; 141 ah->ah_configPCIE = ar9287ConfigPCIE; 142 143 AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal; 144 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal; 145 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal; 146 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal; 147 /* Better performance without ADC Gain Calibration */ 148 AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL; 149 150 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 151 AH5416(ah)->ah_writeIni = ar9287WriteIni; 152 153 ah->ah_setTxPower = ar9287SetTransmitPower; 154 ah->ah_setBoardValues = ar9287SetBoardValues; 155 156 AH5416(ah)->ah_olcInit = ar9287olcInit; 157 AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation; 158 //AH5416(ah)->ah_setPowerCalTable = ar9287SetPowerCalTable; 159 AH5416(ah)->ah_cal_initcal = ar9287InitCalHardware; 160 AH5416(ah)->ah_cal_pacal = ar9287PACal; 161 162 /* XXX NF calibration */ 163 /* XXX Ini override? (IFS vars - since the kiwi mac clock is faster?) */ 164 /* XXX what else is kiwi-specific in the radio/calibration pathway? */ 165 166 AH5416(ah)->ah_rx_chainmask = AR9287_DEFAULT_RXCHAINMASK; 167 AH5416(ah)->ah_tx_chainmask = AR9287_DEFAULT_TXCHAINMASK; 168 169 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 170 /* reset chip */ 171 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 172 __func__); 173 ecode = HAL_EIO; 174 goto bad; 175 } 176 177 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 178 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 179 __func__); 180 ecode = HAL_EIO; 181 goto bad; 182 } 183 /* Read Revisions from Chips before taking out of reset */ 184 val = OS_REG_READ(ah, AR_SREV); 185 HALDEBUG(ah, HAL_DEBUG_ATTACH, 186 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 187 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 188 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 189 /* NB: include chip type to differentiate from pre-Sowl versions */ 190 AH_PRIVATE(ah)->ah_macVersion = 191 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 192 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 193 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 194 195 /* Don't support Kiwi < 1.2; those are pre-release chips */ 196 if (! AR_SREV_KIWI_12_OR_LATER(ah)) { 197 ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n"); 198 ecode = HAL_EIO; 199 goto bad; 200 } 201 202 /* setup common ini data; rf backends handle remainder */ 203 HAL_INI_INIT(&ahp->ah_ini_modes, ar9287Modes_9287_1_1, 6); 204 HAL_INI_INIT(&ahp->ah_ini_common, ar9287Common_9287_1_1, 2); 205 206 /* If pcie_clock_req */ 207 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 208 ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2); 209 210 /* XXX WoW ini values */ 211 212 /* Else */ 213 #if 0 214 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 215 ar9287PciePhy_clkreq_off_L1_9287_1_1, 2); 216 #endif 217 218 /* Initialise Japan arrays */ 219 HAL_INI_INIT(&ahp9287->ah_ini_cckFirNormal, 220 ar9287Common_normal_cck_fir_coeff_9287_1_1, 2); 221 HAL_INI_INIT(&ahp9287->ah_ini_cckFirJapan2484, 222 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2); 223 224 ar5416AttachPCIE(ah); 225 226 ecode = ath_hal_9287EepromAttach(ah); 227 if (ecode != HAL_OK) 228 goto bad; 229 230 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 231 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 232 ecode = HAL_EIO; 233 goto bad; 234 } 235 236 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 237 238 if (!ar5212ChipTest(ah)) { 239 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 240 __func__); 241 ecode = HAL_ESELFTEST; 242 goto bad; 243 } 244 245 /* 246 * Set correct Baseband to analog shift 247 * setting to access analog chips. 248 */ 249 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 250 251 /* Read Radio Chip Rev Extract */ 252 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 253 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 254 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 255 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 256 break; 257 default: 258 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 259 AH_PRIVATE(ah)->ah_analog5GhzRev = 260 AR_RAD5133_SREV_MAJOR; 261 break; 262 } 263 #ifdef AH_DEBUG 264 HALDEBUG(ah, HAL_DEBUG_ANY, 265 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 266 "this driver\n", __func__, 267 AH_PRIVATE(ah)->ah_analog5GhzRev); 268 ecode = HAL_ENOTSUPP; 269 goto bad; 270 #endif 271 } 272 rfStatus = ar9287RfAttach(ah, &ecode); 273 if (!rfStatus) { 274 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 275 __func__, ecode); 276 goto bad; 277 } 278 279 /* 280 * We only implement open-loop TX power control 281 * for the AR9287 in this codebase. 282 */ 283 if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 284 ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control" 285 " isn't supported.\n"); 286 ecode = HAL_ENOTSUPP; 287 goto bad; 288 } 289 290 /* 291 * Check whether the power table offset isn't the default. 292 * This can occur with eeprom minor V21 or greater on Merlin. 293 */ 294 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 295 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 296 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 297 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 298 299 /* setup rxgain table */ 300 HAL_INI_INIT(&ahp9287->ah_ini_rxgain, ar9287Modes_rx_gain_9287_1_1, 6); 301 302 /* setup txgain table */ 303 HAL_INI_INIT(&ahp9287->ah_ini_txgain, ar9287Modes_tx_gain_9287_1_1, 6); 304 305 /* 306 * Got everything we need now to setup the capabilities. 307 */ 308 if (!ar9287FillCapabilityInfo(ah)) { 309 ecode = HAL_EEREAD; 310 goto bad; 311 } 312 313 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 314 if (ecode != HAL_OK) { 315 HALDEBUG(ah, HAL_DEBUG_ANY, 316 "%s: error getting mac address from EEPROM\n", __func__); 317 goto bad; 318 } 319 /* XXX How about the serial number ? */ 320 /* Read Reg Domain */ 321 AH_PRIVATE(ah)->ah_currentRD = 322 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 323 324 /* 325 * ah_miscMode is populated by ar5416FillCapabilityInfo() 326 * starting from griffin. Set here to make sure that 327 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 328 * placed into hardware. 329 */ 330 if (ahp->ah_miscMode != 0) 331 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 332 333 ar9287AniSetup(ah); /* Anti Noise Immunity */ 334 335 /* Setup noise floor min/max/nominal values */ 336 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ; 337 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ; 338 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ; 339 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ; 340 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ; 341 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ; 342 343 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 344 345 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 346 347 return ah; 348 bad: 349 if (ah != AH_NULL) 350 ah->ah_detach(ah); 351 if (status) 352 *status = ecode; 353 return AH_NULL; 354 } 355 356 static void 357 ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 358 { 359 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 360 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 361 OS_DELAY(1000); 362 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 363 OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); /* Yes, Kiwi uses the Kite PCIe PHY WA */ 364 } 365 } 366 367 static void 368 ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 369 { 370 u_int modesIndex, freqIndex; 371 int regWrites = 0; 372 373 /* Setup the indices for the next set of register array writes */ 374 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 375 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 376 freqIndex = 2; 377 if (IEEE80211_IS_CHAN_HT40(chan)) 378 modesIndex = 3; 379 else if (IEEE80211_IS_CHAN_108G(chan)) 380 modesIndex = 5; 381 else 382 modesIndex = 4; 383 } else { 384 freqIndex = 1; 385 if (IEEE80211_IS_CHAN_HT40(chan) || 386 IEEE80211_IS_CHAN_TURBO(chan)) 387 modesIndex = 2; 388 else 389 modesIndex = 1; 390 } 391 392 /* Set correct Baseband to analog shift setting to access analog chips. */ 393 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 394 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 395 396 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites); 397 regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites); 398 regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites); 399 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites); 400 } 401 402 #define AR_BASE_FREQ_2GHZ 2300 403 #define AR_BASE_FREQ_5GHZ 4900 404 #define AR_SPUR_FEEQ_BOUND_HT40 19 405 #define AR_SPUR_FEEQ_BOUND_HT20 10 406 407 408 409 /* 410 * Fill all software cached or static hardware state information. 411 * Return failure if capabilities are to come from EEPROM and 412 * cannot be read. 413 */ 414 static HAL_BOOL 415 ar9287FillCapabilityInfo(struct ath_hal *ah) 416 { 417 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 418 419 if (!ar5416FillCapabilityInfo(ah)) 420 return AH_FALSE; 421 pCap->halNumGpioPins = 10; 422 pCap->halWowSupport = AH_TRUE; 423 pCap->halWowMatchPatternExact = AH_TRUE; 424 #if 0 425 pCap->halWowMatchPatternDword = AH_TRUE; 426 #endif 427 428 pCap->halCSTSupport = AH_TRUE; 429 pCap->halRifsRxSupport = AH_TRUE; 430 pCap->halRifsTxSupport = AH_TRUE; 431 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 432 pCap->halExtChanDfsSupport = AH_TRUE; 433 pCap->halUseCombinedRadarRssi = AH_TRUE; 434 #if 0 435 /* XXX bluetooth */ 436 pCap->halBtCoexSupport = AH_TRUE; 437 #endif 438 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 439 pCap->hal4kbSplitTransSupport = AH_FALSE; 440 /* Disable this so Block-ACK works correctly */ 441 pCap->halHasRxSelfLinkedTail = AH_FALSE; 442 pCap->halPSPollBroken = AH_FALSE; 443 444 /* Hardware supports (at least) single-stream STBC TX/RX */ 445 pCap->halRxStbcSupport = 1; 446 pCap->halTxStbcSupport = 1; 447 448 /* Hardware supports short-GI w/ 20MHz */ 449 pCap->halHTSGI20Support = 1; 450 451 pCap->halEnhancedDfsSupport = AH_TRUE; 452 453 return AH_TRUE; 454 } 455 456 /* 457 * This has been disabled - having the HAL flip chainmasks on/off 458 * when attempting to implement 11n disrupts things. For now, just 459 * leave this flipped off and worry about implementing TX diversity 460 * for legacy and MCS0-7 when 11n is fully functioning. 461 */ 462 HAL_BOOL 463 ar9287SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 464 { 465 return AH_TRUE; 466 } 467 468 static const char* 469 ar9287Probe(uint16_t vendorid, uint16_t devid) 470 { 471 if (vendorid == ATHEROS_VENDOR_ID && 472 (devid == AR9287_DEVID_PCI || devid == AR9287_DEVID_PCIE)) 473 return "Atheros 9287"; 474 return AH_NULL; 475 } 476 AH_CHIP(AR9287, ar9287Probe, ar9287Attach); 477