1 /* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 #include "ah_eeprom_9287.h" 27 28 #include "ar9002/ar9280.h" 29 #include "ar9002/ar9287.h" 30 #include "ar5416/ar5416reg.h" 31 #include "ar5416/ar5416phy.h" 32 33 #include "ar9002/ar9287_cal.h" 34 #include "ar9002/ar9287_reset.h" 35 #include "ar9002/ar9287_olc.h" 36 37 #include "ar9002/ar9287.ini" 38 39 static const HAL_PERCAL_DATA ar9287_iq_cal = { /* single sample */ 40 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 41 .calNumSamples = MIN_CAL_SAMPLES, 42 .calCountMax = PER_MAX_LOG_COUNT, 43 .calCollect = ar5416IQCalCollect, 44 .calPostProc = ar5416IQCalibration 45 }; 46 static const HAL_PERCAL_DATA ar9287_adc_gain_cal = { /* single sample */ 47 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 48 .calNumSamples = MIN_CAL_SAMPLES, 49 .calCountMax = PER_MIN_LOG_COUNT, 50 .calCollect = ar5416AdcGainCalCollect, 51 .calPostProc = ar5416AdcGainCalibration 52 }; 53 static const HAL_PERCAL_DATA ar9287_adc_dc_cal = { /* single sample */ 54 .calName = "ADC DC", .calType = ADC_DC_CAL, 55 .calNumSamples = MIN_CAL_SAMPLES, 56 .calCountMax = PER_MIN_LOG_COUNT, 57 .calCollect = ar5416AdcDcCalCollect, 58 .calPostProc = ar5416AdcDcCalibration 59 }; 60 static const HAL_PERCAL_DATA ar9287_adc_init_dc_cal = { 61 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 62 .calNumSamples = MIN_CAL_SAMPLES, 63 .calCountMax = INIT_LOG_COUNT, 64 .calCollect = ar5416AdcDcCalCollect, 65 .calPostProc = ar5416AdcDcCalibration 66 }; 67 68 static void ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 69 HAL_BOOL power_off); 70 static void ar9287DisablePCIE(struct ath_hal *ah); 71 static HAL_BOOL ar9287FillCapabilityInfo(struct ath_hal *ah); 72 static void ar9287WriteIni(struct ath_hal *ah, 73 const struct ieee80211_channel *chan); 74 75 static void 76 ar9287AniSetup(struct ath_hal *ah) 77 { 78 /* 79 * These are the parameters from the AR5416 ANI code; 80 * they likely need quite a bit of adjustment for the 81 * AR9287. 82 */ 83 static const struct ar5212AniParams aniparams = { 84 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 85 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 86 .coarseHigh = { -14, -14, -14, -14, -12 }, 87 .coarseLow = { -64, -64, -64, -64, -70 }, 88 .firpwr = { -78, -78, -78, -78, -80 }, 89 .maxSpurImmunityLevel = 2, 90 .cycPwrThr1 = { 2, 4, 6 }, 91 .maxFirstepLevel = 2, /* levels 0..2 */ 92 .firstep = { 0, 4, 8 }, 93 .ofdmTrigHigh = 500, 94 .ofdmTrigLow = 200, 95 .cckTrigHigh = 200, 96 .cckTrigLow = 100, 97 .rssiThrHigh = 40, 98 .rssiThrLow = 7, 99 .period = 100, 100 }; 101 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 102 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 103 104 /* NB: ANI is not enabled yet */ 105 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 106 } 107 108 /* 109 * Attach for an AR9287 part. 110 */ 111 static struct ath_hal * 112 ar9287Attach(uint16_t devid, HAL_SOFTC sc, 113 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 114 HAL_STATUS *status) 115 { 116 struct ath_hal_9287 *ahp9287; 117 struct ath_hal_5212 *ahp; 118 struct ath_hal *ah; 119 uint32_t val; 120 HAL_STATUS ecode; 121 HAL_BOOL rfStatus; 122 int8_t pwr_table_offset; 123 124 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 125 __func__, sc, (void*) st, (void*) sh); 126 127 /* NB: memory is returned zero'd */ 128 ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287)); 129 if (ahp9287 == AH_NULL) { 130 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 131 "%s: cannot allocate memory for state block\n", __func__); 132 *status = HAL_ENOMEM; 133 return AH_NULL; 134 } 135 ahp = AH5212(ahp9287); 136 ah = &ahp->ah_priv.h; 137 138 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 139 140 /* XXX override with 9280 specific state */ 141 /* override 5416 methods for our needs */ 142 AH5416(ah)->ah_initPLL = ar9280InitPLL; 143 144 ah->ah_setAntennaSwitch = ar9287SetAntennaSwitch; 145 ah->ah_configPCIE = ar9287ConfigPCIE; 146 ah->ah_disablePCIE = ar9287DisablePCIE; 147 148 AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal; 149 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal; 150 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal; 151 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal; 152 /* Better performance without ADC Gain Calibration */ 153 AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL; 154 155 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 156 AH5416(ah)->ah_writeIni = ar9287WriteIni; 157 158 ah->ah_setTxPower = ar9287SetTransmitPower; 159 ah->ah_setBoardValues = ar9287SetBoardValues; 160 161 AH5416(ah)->ah_olcInit = ar9287olcInit; 162 AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation; 163 //AH5416(ah)->ah_setPowerCalTable = ar9287SetPowerCalTable; 164 AH5416(ah)->ah_cal_initcal = ar9287InitCalHardware; 165 AH5416(ah)->ah_cal_pacal = ar9287PACal; 166 167 /* XXX NF calibration */ 168 /* XXX Ini override? (IFS vars - since the kiwi mac clock is faster?) */ 169 /* XXX what else is kiwi-specific in the radio/calibration pathway? */ 170 171 AH5416(ah)->ah_rx_chainmask = AR9287_DEFAULT_RXCHAINMASK; 172 AH5416(ah)->ah_tx_chainmask = AR9287_DEFAULT_TXCHAINMASK; 173 174 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 175 /* reset chip */ 176 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 177 __func__); 178 ecode = HAL_EIO; 179 goto bad; 180 } 181 182 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 183 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 184 __func__); 185 ecode = HAL_EIO; 186 goto bad; 187 } 188 /* Read Revisions from Chips before taking out of reset */ 189 val = OS_REG_READ(ah, AR_SREV); 190 HALDEBUG(ah, HAL_DEBUG_ATTACH, 191 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 192 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 193 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 194 /* NB: include chip type to differentiate from pre-Sowl versions */ 195 AH_PRIVATE(ah)->ah_macVersion = 196 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 197 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 198 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 199 200 /* Don't support Kiwi < 1.2; those are pre-release chips */ 201 if (! AR_SREV_KIWI_12_OR_LATER(ah)) { 202 ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n"); 203 ecode = HAL_EIO; 204 goto bad; 205 } 206 207 /* setup common ini data; rf backends handle remainder */ 208 HAL_INI_INIT(&ahp->ah_ini_modes, ar9287Modes_9287_1_1, 6); 209 HAL_INI_INIT(&ahp->ah_ini_common, ar9287Common_9287_1_1, 2); 210 211 /* If pcie_clock_req */ 212 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 213 ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2); 214 215 /* XXX WoW ini values */ 216 217 /* Else */ 218 #if 0 219 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 220 ar9287PciePhy_clkreq_off_L1_9287_1_1, 2); 221 #endif 222 223 /* Initialise Japan arrays */ 224 HAL_INI_INIT(&ahp9287->ah_ini_cckFirNormal, 225 ar9287Common_normal_cck_fir_coeff_9287_1_1, 2); 226 HAL_INI_INIT(&ahp9287->ah_ini_cckFirJapan2484, 227 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2); 228 229 ar5416AttachPCIE(ah); 230 231 ecode = ath_hal_9287EepromAttach(ah); 232 if (ecode != HAL_OK) 233 goto bad; 234 235 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 236 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 237 ecode = HAL_EIO; 238 goto bad; 239 } 240 241 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 242 243 if (!ar5212ChipTest(ah)) { 244 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 245 __func__); 246 ecode = HAL_ESELFTEST; 247 goto bad; 248 } 249 250 /* 251 * Set correct Baseband to analog shift 252 * setting to access analog chips. 253 */ 254 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 255 256 /* Read Radio Chip Rev Extract */ 257 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 258 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 259 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 260 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 261 break; 262 default: 263 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 264 AH_PRIVATE(ah)->ah_analog5GhzRev = 265 AR_RAD5133_SREV_MAJOR; 266 break; 267 } 268 #ifdef AH_DEBUG 269 HALDEBUG(ah, HAL_DEBUG_ANY, 270 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 271 "this driver\n", __func__, 272 AH_PRIVATE(ah)->ah_analog5GhzRev); 273 ecode = HAL_ENOTSUPP; 274 goto bad; 275 #endif 276 } 277 rfStatus = ar9287RfAttach(ah, &ecode); 278 if (!rfStatus) { 279 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 280 __func__, ecode); 281 goto bad; 282 } 283 284 /* 285 * We only implement open-loop TX power control 286 * for the AR9287 in this codebase. 287 */ 288 if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 289 ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control" 290 " isn't supported.\n"); 291 ecode = HAL_ENOTSUPP; 292 goto bad; 293 } 294 295 /* 296 * Check whether the power table offset isn't the default. 297 * This can occur with eeprom minor V21 or greater on Merlin. 298 */ 299 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 300 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 301 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 302 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 303 304 /* setup rxgain table */ 305 HAL_INI_INIT(&ahp9287->ah_ini_rxgain, ar9287Modes_rx_gain_9287_1_1, 6); 306 307 /* setup txgain table */ 308 HAL_INI_INIT(&ahp9287->ah_ini_txgain, ar9287Modes_tx_gain_9287_1_1, 6); 309 310 /* 311 * Got everything we need now to setup the capabilities. 312 */ 313 if (!ar9287FillCapabilityInfo(ah)) { 314 ecode = HAL_EEREAD; 315 goto bad; 316 } 317 318 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 319 if (ecode != HAL_OK) { 320 HALDEBUG(ah, HAL_DEBUG_ANY, 321 "%s: error getting mac address from EEPROM\n", __func__); 322 goto bad; 323 } 324 /* XXX How about the serial number ? */ 325 /* Read Reg Domain */ 326 AH_PRIVATE(ah)->ah_currentRD = 327 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 328 AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT; 329 330 /* 331 * ah_miscMode is populated by ar5416FillCapabilityInfo() 332 * starting from griffin. Set here to make sure that 333 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 334 * placed into hardware. 335 */ 336 if (ahp->ah_miscMode != 0) 337 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 338 339 ar9287AniSetup(ah); /* Anti Noise Immunity */ 340 341 /* Setup noise floor min/max/nominal values */ 342 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ; 343 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ; 344 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ; 345 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ; 346 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ; 347 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ; 348 349 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 350 351 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 352 353 return ah; 354 bad: 355 if (ah != AH_NULL) 356 ah->ah_detach(ah); 357 if (status) 358 *status = ecode; 359 return AH_NULL; 360 } 361 362 static void 363 ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 364 { 365 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 366 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 367 OS_DELAY(1000); 368 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 369 /* Yes, Kiwi uses the Kite PCIe PHY WA */ 370 OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); 371 } 372 } 373 374 static void 375 ar9287DisablePCIE(struct ath_hal *ah) 376 { 377 /* XXX TODO */ 378 } 379 380 static void 381 ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 382 { 383 u_int modesIndex, freqIndex; 384 int regWrites = 0; 385 386 /* Setup the indices for the next set of register array writes */ 387 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 388 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 389 freqIndex = 2; 390 if (IEEE80211_IS_CHAN_HT40(chan)) 391 modesIndex = 3; 392 else if (IEEE80211_IS_CHAN_108G(chan)) 393 modesIndex = 5; 394 else 395 modesIndex = 4; 396 } else { 397 freqIndex = 1; 398 if (IEEE80211_IS_CHAN_HT40(chan) || 399 IEEE80211_IS_CHAN_TURBO(chan)) 400 modesIndex = 2; 401 else 402 modesIndex = 1; 403 } 404 405 /* Set correct Baseband to analog shift setting to access analog chips. */ 406 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 407 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 408 409 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites); 410 regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites); 411 regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites); 412 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites); 413 } 414 415 /* 416 * Fill all software cached or static hardware state information. 417 * Return failure if capabilities are to come from EEPROM and 418 * cannot be read. 419 */ 420 static HAL_BOOL 421 ar9287FillCapabilityInfo(struct ath_hal *ah) 422 { 423 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 424 425 if (!ar5416FillCapabilityInfo(ah)) 426 return AH_FALSE; 427 pCap->halNumGpioPins = 10; 428 pCap->halWowSupport = AH_TRUE; 429 pCap->halWowMatchPatternExact = AH_TRUE; 430 #if 0 431 pCap->halWowMatchPatternDword = AH_TRUE; 432 #endif 433 434 pCap->halCSTSupport = AH_TRUE; 435 pCap->halRifsRxSupport = AH_TRUE; 436 pCap->halRifsTxSupport = AH_TRUE; 437 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 438 pCap->halExtChanDfsSupport = AH_TRUE; 439 pCap->halUseCombinedRadarRssi = AH_TRUE; 440 #if 0 441 /* XXX bluetooth */ 442 pCap->halBtCoexSupport = AH_TRUE; 443 #endif 444 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 445 pCap->hal4kbSplitTransSupport = AH_FALSE; 446 /* Disable this so Block-ACK works correctly */ 447 pCap->halHasRxSelfLinkedTail = AH_FALSE; 448 pCap->halPSPollBroken = AH_FALSE; 449 450 /* Hardware supports (at least) single-stream STBC TX/RX */ 451 pCap->halRxStbcSupport = 1; 452 pCap->halTxStbcSupport = 1; 453 454 /* Hardware supports short-GI w/ 20MHz */ 455 pCap->halHTSGI20Support = 1; 456 457 pCap->halEnhancedDfsSupport = AH_TRUE; 458 459 return AH_TRUE; 460 } 461 462 /* 463 * This has been disabled - having the HAL flip chainmasks on/off 464 * when attempting to implement 11n disrupts things. For now, just 465 * leave this flipped off and worry about implementing TX diversity 466 * for legacy and MCS0-15 when 11n is fully functioning. 467 */ 468 HAL_BOOL 469 ar9287SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 470 { 471 return AH_TRUE; 472 } 473 474 static const char* 475 ar9287Probe(uint16_t vendorid, uint16_t devid) 476 { 477 if (vendorid == ATHEROS_VENDOR_ID) { 478 if (devid == AR9287_DEVID_PCI) 479 return "Atheros 9227"; 480 if (devid == AR9287_DEVID_PCIE) 481 return "Atheros 9287"; 482 } 483 return AH_NULL; 484 } 485 AH_CHIP(AR9287, ar9287Probe, ar9287Attach); 486