1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008-2010 Atheros Communications Inc. 5 * Copyright (c) 2010-2011 Adrian Chadd, Xenion Pty Ltd. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 #ifndef __ATH_AR9285PHY_H__ 29 #define __ATH_AR9285PHY_H__ 30 31 #define AR9285_AN_RF2G1 0x7820 32 #define AR9285_AN_RF2G1_ENPACAL 0x00000800 33 #define AR9285_AN_RF2G1_ENPACAL_S 11 34 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000 35 #define AR9285_AN_RF2G1_PDPADRV1_S 25 36 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000 37 #define AR9285_AN_RF2G1_PDPADRV2_S 24 38 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000 39 #define AR9285_AN_RF2G1_PDPAOUT_S 23 40 41 #define AR9285_AN_RF2G2 0x7824 42 #define AR9285_AN_RF2G2_OFFCAL 0x00001000 43 #define AR9285_AN_RF2G2_OFFCAL_S 12 44 45 #define AR9285_AN_RF2G3 0x7828 46 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 47 #define AR9285_AN_RF2G3_PDVCCOMP_S 25 48 #define AR9285_AN_RF2G3_OB_0 0x00E00000 49 #define AR9285_AN_RF2G3_OB_0_S 21 50 #define AR9285_AN_RF2G3_OB_1 0x001C0000 51 #define AR9285_AN_RF2G3_OB_1_S 18 52 #define AR9285_AN_RF2G3_OB_2 0x00038000 53 #define AR9285_AN_RF2G3_OB_2_S 15 54 #define AR9285_AN_RF2G3_OB_3 0x00007000 55 #define AR9285_AN_RF2G3_OB_3_S 12 56 #define AR9285_AN_RF2G3_OB_4 0x00000E00 57 #define AR9285_AN_RF2G3_OB_4_S 9 58 59 #define AR9285_AN_RF2G3_DB1_0 0x000001C0 60 #define AR9285_AN_RF2G3_DB1_0_S 6 61 #define AR9285_AN_RF2G3_DB1_1 0x00000038 62 #define AR9285_AN_RF2G3_DB1_1_S 3 63 #define AR9285_AN_RF2G3_DB1_2 0x00000007 64 #define AR9285_AN_RF2G3_DB1_2_S 0 65 66 #define AR9285_AN_RF2G4 0x782C 67 #define AR9285_AN_RF2G4_DB1_3 0xE0000000 68 #define AR9285_AN_RF2G4_DB1_3_S 29 69 #define AR9285_AN_RF2G4_DB1_4 0x1C000000 70 #define AR9285_AN_RF2G4_DB1_4_S 26 71 72 #define AR9285_AN_RF2G4_DB2_0 0x03800000 73 #define AR9285_AN_RF2G4_DB2_0_S 23 74 #define AR9285_AN_RF2G4_DB2_1 0x00700000 75 #define AR9285_AN_RF2G4_DB2_1_S 20 76 #define AR9285_AN_RF2G4_DB2_2 0x000E0000 77 #define AR9285_AN_RF2G4_DB2_2_S 17 78 #define AR9285_AN_RF2G4_DB2_3 0x0001C000 79 #define AR9285_AN_RF2G4_DB2_3_S 14 80 #define AR9285_AN_RF2G4_DB2_4 0x00003800 81 #define AR9285_AN_RF2G4_DB2_4_S 11 82 83 #define AR9285_RF2G5 0x7830 84 #define AR9285_RF2G5_IC50TX 0xfffff8ff 85 #define AR9285_RF2G5_IC50TX_SET 0x00000400 86 #define AR9285_RF2G5_IC50TX_XE_SET 0x00000500 87 #define AR9285_RF2G5_IC50TX_CLEAR 0x00000700 88 #define AR9285_RF2G5_IC50TX_CLEAR_S 8 89 90 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 91 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 92 #define AR_PHY_TX_GAIN_CLC 0x0000001E 93 #define AR_PHY_TX_GAIN_CLC_S 1 94 #define AR_PHY_TX_GAIN 0x0007F000 95 #define AR_PHY_TX_GAIN_S 12 96 97 #define AR_PHY_CLC_TBL1 0xa35c 98 #define AR_PHY_CLC_I0 0x07ff0000 99 #define AR_PHY_CLC_I0_S 16 100 #define AR_PHY_CLC_Q0 0x0000ffd0 101 #define AR_PHY_CLC_Q0_S 5 102 103 #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 104 #define AR_PHY_9285_FAST_DIV_BIAS 0x00007E00 105 #define AR_PHY_9285_FAST_DIV_BIAS_S 9 106 #define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000 107 #define AR_PHY_9285_ANT_DIV_CTL 0x01000000 108 #define AR_PHY_9285_ANT_DIV_CTL_S 24 109 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000 110 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25 111 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000 112 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27 113 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000 114 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29 115 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000 116 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30 117 #define AR_PHY_9285_ANT_DIV_LNA1 2 118 #define AR_PHY_9285_ANT_DIV_LNA2 1 119 #define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3 120 #define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0 121 #define AR_PHY_9285_ANT_DIV_GAINTB_0 0 122 #define AR_PHY_9285_ANT_DIV_GAINTB_1 1 123 124 /* for AR_PHY_CCK_DETECT */ 125 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 126 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 127 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 128 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 129 130 #endif 131