1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and 22 * supports only 2Ghz operation. 23 */ 24 25 #include "opt_ah.h" 26 27 #include "ah.h" 28 #include "ah_internal.h" 29 #include "ah_devid.h" 30 31 #include "ah_eeprom_v14.h" 32 #include "ah_eeprom_v4k.h" 33 34 #include "ar9002/ar9285.h" 35 #include "ar5416/ar5416.h" 36 #include "ar5416/ar5416reg.h" 37 #include "ar5416/ar5416phy.h" 38 #include "ar9002/ar9002phy.h" 39 #include "ar9002/ar9285phy.h" 40 #include "ar9002/ar9285an.h" 41 #include "ar9002/ar9285_diversity.h" 42 43 /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 44 #define EEP_MINOR(_ah) \ 45 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 46 #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 47 #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 48 49 /* Additional Time delay to wait after activiting the Base band */ 50 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 51 #define PLL_SETTLE_DELAY 300 /* 300 usec */ 52 #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 53 54 static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, 55 struct ar5416eeprom_4k *pEepData, 56 const struct ieee80211_channel *chan, int16_t *ratesArray, 57 uint16_t cfgCtl, uint16_t AntennaReduction, 58 uint16_t twiceMaxRegulatoryPower, 59 uint16_t powerLimit); 60 static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, 61 struct ar5416eeprom_4k *pEepData, 62 const struct ieee80211_channel *chan, 63 int16_t *pTxPowerIndexOffset); 64 static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 65 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, 66 uint8_t * bChans, uint16_t availPiers, 67 uint16_t tPdGainOverlap, int16_t *pMinCalPower, 68 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 69 uint16_t numXpdGains); 70 71 HAL_BOOL 72 ar9285SetTransmitPower(struct ath_hal *ah, 73 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 74 { 75 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 76 #define N(a) (sizeof (a) / sizeof (a[0])) 77 78 MODAL_EEP4K_HEADER *pModal; 79 struct ath_hal_5212 *ahp = AH5212(ah); 80 int16_t txPowerIndexOffset = 0; 81 int i; 82 83 uint16_t cfgCtl; 84 uint16_t powerLimit; 85 uint16_t twiceAntennaReduction; 86 uint16_t twiceMaxRegulatoryPower; 87 int16_t maxPower; 88 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 89 struct ar5416eeprom_4k *pEepData = &ee->ee_base; 90 91 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 92 93 AH5416(ah)->ah_ht40PowerIncForPdadc = 2; 94 95 /* Setup info for the actual eeprom */ 96 OS_MEMZERO(AH5416(ah)->ah_ratesArray, sizeof(AH5416(ah)->ah_ratesArray)); 97 cfgCtl = ath_hal_getctl(ah, chan); 98 powerLimit = chan->ic_maxregpower * 2; 99 twiceAntennaReduction = chan->ic_maxantgain; 100 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 101 pModal = &pEepData->modalHeader; 102 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 103 __func__,chan->ic_freq, cfgCtl ); 104 105 if (IS_EEP_MINOR_V2(ah)) { 106 AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 107 } 108 109 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, 110 &AH5416(ah)->ah_ratesArray[0],cfgCtl, 111 twiceAntennaReduction, 112 twiceMaxRegulatoryPower, powerLimit)) { 113 HALDEBUG(ah, HAL_DEBUG_ANY, 114 "%s: unable to set tx power per rate table\n", __func__); 115 return AH_FALSE; 116 } 117 118 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 119 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 120 __func__); 121 return AH_FALSE; 122 } 123 124 maxPower = AH_MAX(AH5416(ah)->ah_ratesArray[rate6mb], 125 AH5416(ah)->ah_ratesArray[rateHt20_0]); 126 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rate1l]); 127 128 if (IEEE80211_IS_CHAN_HT40(chan)) { 129 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rateHt40_0]); 130 } 131 132 ahp->ah_tx6PowerInHalfDbm = maxPower; 133 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 134 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 135 136 /* 137 * txPowerIndexOffset is set by the SetPowerTable() call - 138 * adjust the rate table (0 offset if rates EEPROM not loaded) 139 */ 140 for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) { 141 AH5416(ah)->ah_ratesArray[i] = (int16_t)(txPowerIndexOffset + AH5416(ah)->ah_ratesArray[i]); 142 /* -5 dBm offset for Merlin and later; this includes Kite */ 143 AH5416(ah)->ah_ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 144 if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER) 145 AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER; 146 if (AH5416(ah)->ah_ratesArray[i] < 0) 147 AH5416(ah)->ah_ratesArray[i] = 0; 148 } 149 150 #ifdef AH_EEPROM_DUMP 151 ar5416PrintPowerPerRate(ah, AH5416(ah)->ah_ratesArray); 152 #endif 153 154 /* 155 * Adjust the HT40 power to meet the correct target TX power 156 * for 40MHz mode, based on TX power curves that are established 157 * for 20MHz mode. 158 * 159 * XXX handle overflow/too high power level? 160 */ 161 if (IEEE80211_IS_CHAN_HT40(chan)) { 162 AH5416(ah)->ah_ratesArray[rateHt40_0] += 163 AH5416(ah)->ah_ht40PowerIncForPdadc; 164 AH5416(ah)->ah_ratesArray[rateHt40_1] += 165 AH5416(ah)->ah_ht40PowerIncForPdadc; 166 AH5416(ah)->ah_ratesArray[rateHt40_2] += 167 AH5416(ah)->ah_ht40PowerIncForPdadc; 168 AH5416(ah)->ah_ratesArray[rateHt40_3] += 169 AH5416(ah)->ah_ht40PowerIncForPdadc; 170 AH5416(ah)->ah_ratesArray[rateHt40_4] += 171 AH5416(ah)->ah_ht40PowerIncForPdadc; 172 AH5416(ah)->ah_ratesArray[rateHt40_5] += 173 AH5416(ah)->ah_ht40PowerIncForPdadc; 174 AH5416(ah)->ah_ratesArray[rateHt40_6] += 175 AH5416(ah)->ah_ht40PowerIncForPdadc; 176 AH5416(ah)->ah_ratesArray[rateHt40_7] += 177 AH5416(ah)->ah_ht40PowerIncForPdadc; 178 } 179 180 /* Write the TX power rate registers */ 181 ar5416WriteTxPowerRateRegisters(ah, chan, AH5416(ah)->ah_ratesArray); 182 183 return AH_TRUE; 184 #undef POW_SM 185 #undef N 186 } 187 188 static void 189 ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal, 190 const struct ar5416eeprom_4k *eep, uint8_t txRxAttenLocal) 191 { 192 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, 193 pModal->antCtrlChain[0]); 194 195 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), 196 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)) & 197 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 198 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 199 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 200 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 201 202 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 203 AR5416_EEP_MINOR_VER_3) { 204 txRxAttenLocal = pModal->txRxAttenCh[0]; 205 206 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 207 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 208 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 209 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 210 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 211 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); 212 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 213 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 214 215 /* Set the block 1 value to block 0 value */ 216 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 217 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 218 pModal->bswMargin[0]); 219 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 220 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 221 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 222 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 223 pModal->xatten2Margin[0]); 224 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 225 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 226 } 227 228 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 229 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 230 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 231 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 232 233 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 234 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 235 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 236 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 237 } 238 239 /* 240 * Read EEPROM header info and program the device for correct operation 241 * given the channel value. 242 */ 243 HAL_BOOL 244 ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 245 { 246 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 247 const struct ar5416eeprom_4k *eep = &ee->ee_base; 248 const MODAL_EEP4K_HEADER *pModal; 249 uint8_t txRxAttenLocal; 250 uint8_t ob[5], db1[5], db2[5]; 251 252 pModal = &eep->modalHeader; 253 txRxAttenLocal = 23; 254 255 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 256 257 /* Single chain for 4K EEPROM*/ 258 ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal); 259 260 /* Initialize Ant Diversity settings if supported */ 261 (void) ar9285SetAntennaSwitch(ah, AH5212(ah)->ah_antControl); 262 263 /* Configure TX power calibration */ 264 if (pModal->version >= 2) { 265 ob[0] = pModal->ob_0; 266 ob[1] = pModal->ob_1; 267 ob[2] = pModal->ob_2; 268 ob[3] = pModal->ob_3; 269 ob[4] = pModal->ob_4; 270 271 db1[0] = pModal->db1_0; 272 db1[1] = pModal->db1_1; 273 db1[2] = pModal->db1_2; 274 db1[3] = pModal->db1_3; 275 db1[4] = pModal->db1_4; 276 277 db2[0] = pModal->db2_0; 278 db2[1] = pModal->db2_1; 279 db2[2] = pModal->db2_2; 280 db2[3] = pModal->db2_3; 281 db2[4] = pModal->db2_4; 282 } else if (pModal->version == 1) { 283 ob[0] = pModal->ob_0; 284 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; 285 db1[0] = pModal->db1_0; 286 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; 287 db2[0] = pModal->db2_0; 288 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; 289 } else { 290 int i; 291 292 for (i = 0; i < 5; i++) { 293 ob[i] = pModal->ob_0; 294 db1[i] = pModal->db1_0; 295 db2[i] = pModal->db1_0; 296 } 297 } 298 299 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_0, ob[0]); 300 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_1, ob[1]); 301 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_2, ob[2]); 302 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_3, ob[3]); 303 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_4, ob[4]); 304 305 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_0, db1[0]); 306 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_1, db1[1]); 307 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_2, db1[2]); 308 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_3, db1[3]); 309 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_4, db1[4]); 310 311 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_0, db2[0]); 312 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_1, db2[1]); 313 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_2, db2[2]); 314 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_3, db2[3]); 315 OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_4, db2[4]); 316 317 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 318 pModal->switchSettling); 319 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 320 pModal->adcDesiredSize); 321 322 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 323 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 324 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 325 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 326 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 327 328 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 329 pModal->txEndToRxOn); 330 331 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 332 pModal->thresh62); 333 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 334 pModal->thresh62); 335 336 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 337 AR5416_EEP_MINOR_VER_2) { 338 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, 339 pModal->txFrameToDataStart); 340 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, 341 pModal->txFrameToPaOn); 342 } 343 344 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 345 AR5416_EEP_MINOR_VER_3) { 346 if (IEEE80211_IS_CHAN_HT40(chan)) 347 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 348 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 349 } 350 351 /* 352 * Program the CCK TX gain factor appropriately if needed. 353 * The AR9285/AR9271 has a non-constant PA tx gain behaviour 354 * for CCK versus OFDM rates; other chips deal with this 355 * differently. 356 * 357 * The mask/shift/multiply hackery is done so place the same 358 * value (bb_desired_scale) into multiple 5-bit fields. 359 * For example, AR_PHY_TX_PWRCTRL9 has bb_desired_scale written 360 * to three fields: (0..4), (5..9) and (10..14). 361 */ 362 if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) { 363 uint8_t bb_desired_scale = (pModal->bb_scale_smrt_antenna & EEP_4K_BB_DESIRED_SCALE_MASK); 364 if ((eep->baseEepHeader.txGainType == 0) && (bb_desired_scale != 0)) { 365 ath_hal_printf(ah, "[ath]: adjusting cck tx gain factor\n"); 366 uint32_t pwrctrl, mask, clr; 367 368 mask = (1<<0) | (1<<5) | (1<<10) | (1<<15) | (1<<20) | (1<<25); 369 pwrctrl = mask * bb_desired_scale; 370 clr = mask * 0x1f; 371 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); 372 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); 373 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); 374 375 mask = (1<<0) | (1<<5) | (1<<15); 376 pwrctrl = mask * bb_desired_scale; 377 clr = mask * 0x1f; 378 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); 379 380 mask = (1<<0) | (1<<5); 381 pwrctrl = mask * bb_desired_scale; 382 clr = mask * 0x1f; 383 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); 384 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); 385 } 386 } 387 388 return AH_TRUE; 389 } 390 391 /* 392 * Helper functions common for AP/CB/XB 393 */ 394 395 static HAL_BOOL 396 ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 397 const struct ieee80211_channel *chan, 398 int16_t *ratesArray, uint16_t cfgCtl, 399 uint16_t AntennaReduction, 400 uint16_t twiceMaxRegulatoryPower, 401 uint16_t powerLimit) 402 { 403 #define N(a) (sizeof(a)/sizeof(a[0])) 404 /* Local defines to distinguish between extension and control CTL's */ 405 #define EXT_ADDITIVE (0x8000) 406 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 407 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 408 409 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 410 int i; 411 int16_t twiceLargestAntenna; 412 CAL_CTL_DATA_4K *rep; 413 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 414 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 415 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 416 int16_t scaledPower, minCtlPower; 417 418 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 419 static const uint16_t ctlModesFor11g[] = { 420 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 421 }; 422 const uint16_t *pCtlMode; 423 uint16_t numCtlModes, ctlMode, freq; 424 CHAN_CENTERS centers; 425 426 ar5416GetChannelCenters(ah, chan, ¢ers); 427 428 /* Compute TxPower reduction due to Antenna Gain */ 429 430 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 431 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 432 433 /* XXX setup for 5212 use (really used?) */ 434 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); 435 436 /* 437 * scaledPower is the minimum of the user input power level and 438 * the regulatory allowed power level 439 */ 440 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 441 442 /* Get target powers from EEPROM - our baseline for TX Power */ 443 /* Setup for CTL modes */ 444 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 445 pCtlMode = ctlModesFor11g; 446 447 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 448 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 449 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 450 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 451 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 452 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 453 454 if (IEEE80211_IS_CHAN_HT40(chan)) { 455 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 456 457 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 458 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 459 /* Get target powers for extension channels */ 460 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 461 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 462 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 463 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 464 } 465 466 /* 467 * For MIMO, need to apply regulatory caps individually across dynamically 468 * running modes: CCK, OFDM, HT20, HT40 469 * 470 * The outer loop walks through each possible applicable runtime mode. 471 * The inner loop walks through each ctlIndex entry in EEPROM. 472 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 473 * 474 */ 475 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 476 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 477 (pCtlMode[ctlMode] == CTL_2GHT40); 478 if (isHt40CtlMode) { 479 freq = centers.ctl_center; 480 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 481 freq = centers.ext_center; 482 } else { 483 freq = centers.ctl_center; 484 } 485 486 /* walk through each CTL index stored in EEPROM */ 487 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 488 uint16_t twiceMinEdgePower; 489 490 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 491 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 492 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 493 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 494 rep = &(pEepData->ctlData[i]); 495 twiceMinEdgePower = ar5416GetMaxEdgePower(freq, 496 rep->ctlEdges[ 497 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], AH_TRUE); 498 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 499 /* Find the minimum of all CTL edge powers that apply to this channel */ 500 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 501 } else { 502 /* specific */ 503 twiceMaxEdgePower = twiceMinEdgePower; 504 break; 505 } 506 } 507 } 508 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 509 /* Apply ctl mode to correct target power set */ 510 switch(pCtlMode[ctlMode]) { 511 case CTL_11B: 512 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 513 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 514 } 515 break; 516 case CTL_11A: 517 case CTL_11G: 518 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 519 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 520 } 521 break; 522 case CTL_5GHT20: 523 case CTL_2GHT20: 524 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 525 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 526 } 527 break; 528 case CTL_11B_EXT: 529 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 530 break; 531 case CTL_11G_EXT: 532 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 533 break; 534 case CTL_5GHT40: 535 case CTL_2GHT40: 536 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 537 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 538 } 539 break; 540 default: 541 return AH_FALSE; 542 break; 543 } 544 } /* end ctl mode checking */ 545 546 /* Set rates Array from collected data */ 547 ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray, 548 &targetPowerCck, 549 &targetPowerCckExt, 550 &targetPowerOfdm, 551 &targetPowerOfdmExt, 552 &targetPowerHt20, 553 &targetPowerHt40); 554 555 return AH_TRUE; 556 #undef EXT_ADDITIVE 557 #undef CTL_11G_EXT 558 #undef CTL_11B_EXT 559 #undef SUB_NUM_CTL_MODES_AT_2G_40 560 #undef N 561 } 562 563 static HAL_BOOL 564 ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, 565 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 566 { 567 CAL_DATA_PER_FREQ_4K *pRawDataset; 568 uint8_t *pCalBChans = AH_NULL; 569 uint16_t pdGainOverlap_t2; 570 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 571 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 572 uint16_t numPiers, i; 573 int16_t tMinCalPower; 574 uint16_t numXpdGain, xpdMask; 575 uint16_t xpdGainValues[4]; /* v4k eeprom has 2; the other two stay 0 */ 576 uint32_t regChainOffset; 577 578 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 579 580 xpdMask = pEepData->modalHeader.xpdGain; 581 582 if (IS_EEP_MINOR_V2(ah)) { 583 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 584 } else { 585 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 586 } 587 588 pCalBChans = pEepData->calFreqPier2G; 589 numPiers = AR5416_4K_NUM_2G_CAL_PIERS; 590 numXpdGain = 0; 591 592 /* Calculate the value of xpdgains from the xpdGain Mask */ 593 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 594 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 595 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { 596 HALASSERT(0); 597 break; 598 } 599 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 600 numXpdGain++; 601 } 602 } 603 604 /* Write the detector gain biases and their number */ 605 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 606 607 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 608 regChainOffset = ar5416GetRegChainOffset(ah, i); 609 if (pEepData->baseEepHeader.txMask & (1 << i)) { 610 pRawDataset = pEepData->calPierData2G[i]; 611 612 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 613 pCalBChans, numPiers, 614 pdGainOverlap_t2, 615 &tMinCalPower, gainBoundaries, 616 pdadcValues, numXpdGain); 617 618 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 619 /* 620 * Note the pdadc table may not start at 0 dBm power, could be 621 * negative or greater than 0. Need to offset the power 622 * values by the amount of minPower for griffin 623 */ 624 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, gainBoundaries); 625 } 626 627 /* Write the power values into the baseband power table */ 628 ar5416WritePdadcValues(ah, i, pdadcValues); 629 } 630 } 631 *pTxPowerIndexOffset = 0; 632 633 return AH_TRUE; 634 } 635 636 static void 637 ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, 638 const struct ieee80211_channel *chan, 639 CAL_DATA_PER_FREQ_4K *pRawDataSet, 640 uint8_t * bChans, uint16_t availPiers, 641 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 642 uint8_t * pPDADCValues, uint16_t numXpdGains) 643 { 644 645 int i, j, k; 646 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 647 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 648 649 /* filled out Vpd table for all pdGains (chanL) */ 650 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 651 652 /* filled out Vpd table for all pdGains (chanR) */ 653 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 654 655 /* filled out Vpd table for all pdGains (interpolated) */ 656 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 657 658 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 659 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; 660 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; 661 int16_t vpdStep; 662 int16_t tmpVal; 663 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 664 HAL_BOOL match; 665 int16_t minDelta = 0; 666 CHAN_CENTERS centers; 667 668 ar5416GetChannelCenters(ah, chan, ¢ers); 669 670 /* Trim numPiers for the number of populated channel Piers */ 671 for (numPiers = 0; numPiers < availPiers; numPiers++) { 672 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 673 break; 674 } 675 } 676 677 /* Find pier indexes around the current channel */ 678 match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 679 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); 680 681 if (match) { 682 /* Directly fill both vpd tables from the matching index */ 683 for (i = 0; i < numXpdGains; i++) { 684 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 685 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 686 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], 687 pRawDataSet[idxL].pwrPdg[i], 688 pRawDataSet[idxL].vpdPdg[i], 689 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 690 } 691 } else { 692 for (i = 0; i < numXpdGains; i++) { 693 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 694 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 695 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 696 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 697 698 /* Start Vpd interpolation from the max of the minimum powers */ 699 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 700 701 /* End Vpd interpolation from the min of the max powers */ 702 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 703 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 704 705 /* Fill pier Vpds */ 706 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, 707 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 708 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, 709 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 710 711 /* Interpolate the final vpd */ 712 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 713 vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, 714 IEEE80211_IS_CHAN_2GHZ(chan)), 715 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 716 } 717 } 718 } 719 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 720 721 k = 0; /* index for the final table */ 722 for (i = 0; i < numXpdGains; i++) { 723 if (i == (numXpdGains - 1)) { 724 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 725 } else { 726 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 727 } 728 729 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 730 731 /* NB: only applies to owl 1.0 */ 732 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) { 733 /* 734 * fix the gain delta, but get a delta that can be applied to min to 735 * keep the upper power values accurate, don't think max needs to 736 * be adjusted because should not be at that area of the table? 737 */ 738 minDelta = pPdGainBoundaries[0] - 23; 739 pPdGainBoundaries[0] = 23; 740 } 741 else { 742 minDelta = 0; 743 } 744 745 /* Find starting index for this pdGain */ 746 if (i == 0) { 747 if (AR_SREV_MERLIN_20_OR_LATER(ah)) 748 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 749 else 750 ss = 0; /* for the first pdGain, start from index 0 */ 751 } else { 752 /* need overlap entries extrapolated below. */ 753 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 754 } 755 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 756 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 757 /* 758 *-ve ss indicates need to extrapolate data below for this pdGain 759 */ 760 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 761 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 762 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 763 ss++; 764 } 765 766 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 767 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 768 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 769 770 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 771 pPDADCValues[k++] = vpdTableI[i][ss++]; 772 } 773 774 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 775 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 776 /* 777 * for last gain, pdGainBoundary == Pmax_t2, so will 778 * have to extrapolate 779 */ 780 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 781 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 782 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 783 (ss - maxIndex +1) * vpdStep)); 784 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 785 ss++; 786 } 787 } /* extrapolated above */ 788 } /* for all pdGainUsed */ 789 790 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 791 while (i < AR5416_PD_GAINS_IN_MASK) { 792 pPdGainBoundaries[i] = AR5416_4K_EEP_PD_GAIN_BOUNDARY_DEFAULT; 793 i++; 794 } 795 796 while (k < AR5416_NUM_PDADC_VALUES) { 797 pPDADCValues[k] = pPDADCValues[k-1]; 798 k++; 799 } 800 return; 801 } 802