1 /* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */ 26 27 #include "ar9002/ar9280.h" 28 #include "ar9002/ar9285.h" 29 #include "ar5416/ar5416reg.h" 30 #include "ar5416/ar5416phy.h" 31 32 #include "ar9002/ar9285.ini" 33 #include "ar9002/ar9285v2.ini" 34 #include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */ 35 36 #include "ar9002/ar9285_cal.h" 37 #include "ar9002/ar9285_phy.h" 38 #include "ar9002/ar9285_diversity.h" 39 40 static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 41 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 42 .calNumSamples = MIN_CAL_SAMPLES, 43 .calCountMax = PER_MAX_LOG_COUNT, 44 .calCollect = ar5416IQCalCollect, 45 .calPostProc = ar5416IQCalibration 46 }; 47 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 48 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 49 .calNumSamples = MIN_CAL_SAMPLES, 50 .calCountMax = PER_MIN_LOG_COUNT, 51 .calCollect = ar5416AdcGainCalCollect, 52 .calPostProc = ar5416AdcGainCalibration 53 }; 54 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 55 .calName = "ADC DC", .calType = ADC_DC_CAL, 56 .calNumSamples = MIN_CAL_SAMPLES, 57 .calCountMax = PER_MIN_LOG_COUNT, 58 .calCollect = ar5416AdcDcCalCollect, 59 .calPostProc = ar5416AdcDcCalibration 60 }; 61 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 62 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 63 .calNumSamples = MIN_CAL_SAMPLES, 64 .calCountMax = INIT_LOG_COUNT, 65 .calCollect = ar5416AdcDcCalCollect, 66 .calPostProc = ar5416AdcDcCalibration 67 }; 68 69 static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 70 static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah); 71 static void ar9285WriteIni(struct ath_hal *ah, 72 const struct ieee80211_channel *chan); 73 74 static void 75 ar9285AniSetup(struct ath_hal *ah) 76 { 77 /* 78 * These are the parameters from the AR5416 ANI code; 79 * they likely need quite a bit of adjustment for the 80 * AR9285. 81 */ 82 static const struct ar5212AniParams aniparams = { 83 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 84 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 85 .coarseHigh = { -14, -14, -14, -14, -12 }, 86 .coarseLow = { -64, -64, -64, -64, -70 }, 87 .firpwr = { -78, -78, -78, -78, -80 }, 88 .maxSpurImmunityLevel = 2, 89 .cycPwrThr1 = { 2, 4, 6 }, 90 .maxFirstepLevel = 2, /* levels 0..2 */ 91 .firstep = { 0, 4, 8 }, 92 .ofdmTrigHigh = 500, 93 .ofdmTrigLow = 200, 94 .cckTrigHigh = 200, 95 .cckTrigLow = 100, 96 .rssiThrHigh = 40, 97 .rssiThrLow = 7, 98 .period = 100, 99 }; 100 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 101 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 102 103 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 104 } 105 106 /* 107 * Attach for an AR9285 part. 108 */ 109 static struct ath_hal * 110 ar9285Attach(uint16_t devid, HAL_SOFTC sc, 111 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 112 HAL_STATUS *status) 113 { 114 struct ath_hal_9285 *ahp9285; 115 struct ath_hal_5212 *ahp; 116 struct ath_hal *ah; 117 uint32_t val; 118 HAL_STATUS ecode; 119 HAL_BOOL rfStatus; 120 121 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 122 __func__, sc, (void*) st, (void*) sh); 123 124 /* NB: memory is returned zero'd */ 125 ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285)); 126 if (ahp9285 == AH_NULL) { 127 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 128 "%s: cannot allocate memory for state block\n", __func__); 129 *status = HAL_ENOMEM; 130 return AH_NULL; 131 } 132 ahp = AH5212(ahp9285); 133 ah = &ahp->ah_priv.h; 134 135 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 136 137 /* XXX override with 9285 specific state */ 138 /* override 5416 methods for our needs */ 139 ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch; 140 ah->ah_configPCIE = ar9285ConfigPCIE; 141 ah->ah_setTxPower = ar9285SetTransmitPower; 142 ah->ah_setBoardValues = ar9285SetBoardValues; 143 144 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 145 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 146 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 147 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 148 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 149 150 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 151 AH5416(ah)->ah_writeIni = ar9285WriteIni; 152 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK; 153 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK; 154 155 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1; 156 157 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 158 /* reset chip */ 159 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 160 __func__); 161 ecode = HAL_EIO; 162 goto bad; 163 } 164 165 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 166 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 167 __func__); 168 ecode = HAL_EIO; 169 goto bad; 170 } 171 /* Read Revisions from Chips before taking out of reset */ 172 val = OS_REG_READ(ah, AR_SREV); 173 HALDEBUG(ah, HAL_DEBUG_ATTACH, 174 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 175 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 176 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 177 /* NB: include chip type to differentiate from pre-Sowl versions */ 178 AH_PRIVATE(ah)->ah_macVersion = 179 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 180 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 181 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 182 183 /* setup common ini data; rf backends handle remainder */ 184 if (AR_SREV_KITE_12_OR_LATER(ah)) { 185 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6); 186 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2); 187 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 188 ar9285PciePhy_clkreq_always_on_L1_v2, 2); 189 } else { 190 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6); 191 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2); 192 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 193 ar9285PciePhy_clkreq_always_on_L1, 2); 194 } 195 ar5416AttachPCIE(ah); 196 197 /* Attach methods that require MAC version/revision info */ 198 if (AR_SREV_KITE_12_OR_LATER(ah)) 199 AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware; 200 if (AR_SREV_KITE_11_OR_LATER(ah)) 201 AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal; 202 203 ecode = ath_hal_v4kEepromAttach(ah); 204 if (ecode != HAL_OK) 205 goto bad; 206 207 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 208 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 209 __func__); 210 ecode = HAL_EIO; 211 goto bad; 212 } 213 214 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 215 216 if (!ar5212ChipTest(ah)) { 217 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 218 __func__); 219 ecode = HAL_ESELFTEST; 220 goto bad; 221 } 222 223 /* 224 * Set correct Baseband to analog shift 225 * setting to access analog chips. 226 */ 227 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 228 229 /* Read Radio Chip Rev Extract */ 230 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 231 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 232 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 233 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 234 break; 235 default: 236 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 237 AH_PRIVATE(ah)->ah_analog5GhzRev = 238 AR_RAD5133_SREV_MAJOR; 239 break; 240 } 241 #ifdef AH_DEBUG 242 HALDEBUG(ah, HAL_DEBUG_ANY, 243 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 244 "this driver\n", __func__, 245 AH_PRIVATE(ah)->ah_analog5GhzRev); 246 ecode = HAL_ENOTSUPP; 247 goto bad; 248 #endif 249 } 250 rfStatus = ar9285RfAttach(ah, &ecode); 251 if (!rfStatus) { 252 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 253 __func__, ecode); 254 goto bad; 255 } 256 257 HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2, 258 6); 259 260 if (AR_SREV_9285E_20(ah)) 261 ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n"); 262 263 /* setup txgain table */ 264 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 265 case AR5416_EEP_TXGAIN_HIGH_POWER: 266 if (AR_SREV_9285E_20(ah)) 267 HAL_INI_INIT(&ahp9285->ah_ini_txgain, 268 ar9285Modes_XE2_0_high_power, 6); 269 else 270 HAL_INI_INIT(&ahp9285->ah_ini_txgain, 271 ar9285Modes_high_power_tx_gain_v2, 6); 272 break; 273 case AR5416_EEP_TXGAIN_ORIG: 274 if (AR_SREV_9285E_20(ah)) 275 HAL_INI_INIT(&ahp9285->ah_ini_txgain, 276 ar9285Modes_XE2_0_normal_power, 6); 277 else 278 HAL_INI_INIT(&ahp9285->ah_ini_txgain, 279 ar9285Modes_original_tx_gain_v2, 6); 280 break; 281 default: 282 HALASSERT(AH_FALSE); 283 goto bad; /* XXX ? try to continue */ 284 } 285 286 /* 287 * Got everything we need now to setup the capabilities. 288 */ 289 if (!ar9285FillCapabilityInfo(ah)) { 290 ecode = HAL_EEREAD; 291 goto bad; 292 } 293 294 /* Print out whether the EEPROM settings enable AR9285 diversity */ 295 if (ar9285_check_div_comb(ah)) { 296 ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n"); 297 ah->ah_rxAntCombDiversity = ar9285_ant_comb_scan; 298 } 299 300 /* Disable 11n for the AR2427 */ 301 if (devid == AR2427_DEVID_PCIE) 302 AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE; 303 304 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 305 if (ecode != HAL_OK) { 306 HALDEBUG(ah, HAL_DEBUG_ANY, 307 "%s: error getting mac address from EEPROM\n", __func__); 308 goto bad; 309 } 310 /* XXX How about the serial number ? */ 311 /* Read Reg Domain */ 312 AH_PRIVATE(ah)->ah_currentRD = 313 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 314 /* 315 * For Kite and later chipsets, the following bits are not 316 * programmed in EEPROM and so are set as enabled always. 317 */ 318 AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT; 319 320 /* 321 * ah_miscMode is populated by ar5416FillCapabilityInfo() 322 * starting from griffin. Set here to make sure that 323 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 324 * placed into hardware. 325 */ 326 if (ahp->ah_miscMode != 0) 327 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 328 329 ar9285AniSetup(ah); /* Anti Noise Immunity */ 330 331 /* Setup noise floor min/max/nominal values */ 332 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ; 333 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ; 334 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ; 335 /* XXX no 5ghz values? */ 336 337 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 338 339 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 340 341 return ah; 342 bad: 343 if (ah != AH_NULL) 344 ah->ah_detach(ah); 345 if (status) 346 *status = ecode; 347 return AH_NULL; 348 } 349 350 static void 351 ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 352 { 353 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 354 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 355 OS_DELAY(1000); 356 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 357 OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); 358 } 359 } 360 361 static void 362 ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 363 { 364 u_int modesIndex, freqIndex; 365 int regWrites = 0; 366 367 /* Setup the indices for the next set of register array writes */ 368 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 369 freqIndex = 2; 370 if (IEEE80211_IS_CHAN_HT40(chan)) 371 modesIndex = 3; 372 else if (IEEE80211_IS_CHAN_108G(chan)) 373 modesIndex = 5; 374 else 375 modesIndex = 4; 376 377 /* Set correct Baseband to analog shift setting to access analog chips. */ 378 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 379 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 380 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 381 modesIndex, regWrites); 382 if (AR_SREV_KITE_12_OR_LATER(ah)) { 383 regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain, 384 modesIndex, regWrites); 385 } 386 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 387 1, regWrites); 388 } 389 390 /* 391 * Fill all software cached or static hardware state information. 392 * Return failure if capabilities are to come from EEPROM and 393 * cannot be read. 394 */ 395 static HAL_BOOL 396 ar9285FillCapabilityInfo(struct ath_hal *ah) 397 { 398 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 399 400 if (!ar5416FillCapabilityInfo(ah)) 401 return AH_FALSE; 402 pCap->halNumGpioPins = 12; 403 pCap->halWowSupport = AH_TRUE; 404 pCap->halWowMatchPatternExact = AH_TRUE; 405 #if 0 406 pCap->halWowMatchPatternDword = AH_TRUE; 407 #endif 408 /* AR9285 has 2 antennas but is a 1x1 stream device */ 409 pCap->halTxStreams = 1; 410 pCap->halRxStreams = 1; 411 412 pCap->halCSTSupport = AH_TRUE; 413 pCap->halRifsRxSupport = AH_TRUE; 414 pCap->halRifsTxSupport = AH_TRUE; 415 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 416 pCap->halExtChanDfsSupport = AH_TRUE; 417 pCap->halUseCombinedRadarRssi = AH_TRUE; 418 #if 0 419 /* XXX bluetooth */ 420 pCap->halBtCoexSupport = AH_TRUE; 421 #endif 422 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 423 pCap->hal4kbSplitTransSupport = AH_FALSE; 424 /* Disable this so Block-ACK works correctly */ 425 pCap->halHasRxSelfLinkedTail = AH_FALSE; 426 pCap->halMbssidAggrSupport = AH_TRUE; 427 pCap->hal4AddrAggrSupport = AH_TRUE; 428 429 if (AR_SREV_KITE_12_OR_LATER(ah)) 430 pCap->halPSPollBroken = AH_FALSE; 431 432 /* Only RX STBC supported */ 433 pCap->halRxStbcSupport = 1; 434 pCap->halTxStbcSupport = 0; 435 436 return AH_TRUE; 437 } 438 439 static const char* 440 ar9285Probe(uint16_t vendorid, uint16_t devid) 441 { 442 if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE) 443 return "Atheros 9285"; 444 if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE)) 445 return "Atheros 2427"; 446 447 return AH_NULL; 448 } 449 AH_CHIP(AR9285, ar9285Probe, ar9285Attach); 450