xref: /freebsd/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c (revision 56961fd7949de755f95a60fe8ac936f81e953f5b)
1 /*
2  * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3  * Copyright (c) 2008 Atheros Communications, Inc.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  *
17  * $FreeBSD$
18  */
19 #include "opt_ah.h"
20 
21 #include "ah.h"
22 #include "ah_internal.h"
23 #include "ah_devid.h"
24 
25 #include "ah_eeprom_v4k.h"		/* XXX for tx/rx gain */
26 
27 #include "ar9002/ar9280.h"
28 #include "ar9002/ar9285.h"
29 #include "ar5416/ar5416reg.h"
30 #include "ar5416/ar5416phy.h"
31 
32 #include "ar9002/ar9285.ini"
33 #include "ar9002/ar9285v2.ini"
34 #include "ar9002/ar9280v2.ini"		/* XXX ini for tx/rx gain */
35 
36 #include "ar9002/ar9285_cal.h"
37 #include "ar9002/ar9285_phy.h"
38 #include "ar9002/ar9285_diversity.h"
39 
40 static const HAL_PERCAL_DATA ar9280_iq_cal = {		/* single sample */
41 	.calName = "IQ", .calType = IQ_MISMATCH_CAL,
42 	.calNumSamples	= MIN_CAL_SAMPLES,
43 	.calCountMax	= PER_MAX_LOG_COUNT,
44 	.calCollect	= ar5416IQCalCollect,
45 	.calPostProc	= ar5416IQCalibration
46 };
47 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = {	/* single sample */
48 	.calName = "ADC Gain", .calType = ADC_GAIN_CAL,
49 	.calNumSamples	= MIN_CAL_SAMPLES,
50 	.calCountMax	= PER_MIN_LOG_COUNT,
51 	.calCollect	= ar5416AdcGainCalCollect,
52 	.calPostProc	= ar5416AdcGainCalibration
53 };
54 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = {	/* single sample */
55 	.calName = "ADC DC", .calType = ADC_DC_CAL,
56 	.calNumSamples	= MIN_CAL_SAMPLES,
57 	.calCountMax	= PER_MIN_LOG_COUNT,
58 	.calCollect	= ar5416AdcDcCalCollect,
59 	.calPostProc	= ar5416AdcDcCalibration
60 };
61 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
62 	.calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
63 	.calNumSamples	= MIN_CAL_SAMPLES,
64 	.calCountMax	= INIT_LOG_COUNT,
65 	.calCollect	= ar5416AdcDcCalCollect,
66 	.calPostProc	= ar5416AdcDcCalibration
67 };
68 
69 static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
70 		HAL_BOOL power_off);
71 static void ar9285DisablePCIE(struct ath_hal *ah);
72 static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
73 static void ar9285WriteIni(struct ath_hal *ah,
74 	const struct ieee80211_channel *chan);
75 
76 static void
77 ar9285AniSetup(struct ath_hal *ah)
78 {
79 	/*
80 	 * These are the parameters from the AR5416 ANI code;
81 	 * they likely need quite a bit of adjustment for the
82 	 * AR9285.
83 	 */
84         static const struct ar5212AniParams aniparams = {
85                 .maxNoiseImmunityLevel  = 4,    /* levels 0..4 */
86                 .totalSizeDesired       = { -55, -55, -55, -55, -62 },
87                 .coarseHigh             = { -14, -14, -14, -14, -12 },
88                 .coarseLow              = { -64, -64, -64, -64, -70 },
89                 .firpwr                 = { -78, -78, -78, -78, -80 },
90                 .maxSpurImmunityLevel   = 7,
91                 .cycPwrThr1             = { 2, 4, 6, 8, 10, 12, 14, 16 },
92                 .maxFirstepLevel        = 2,    /* levels 0..2 */
93                 .firstep                = { 0, 4, 8 },
94                 .ofdmTrigHigh           = 500,
95                 .ofdmTrigLow            = 200,
96                 .cckTrigHigh            = 200,
97                 .cckTrigLow             = 100,
98                 .rssiThrHigh            = 40,
99                 .rssiThrLow             = 7,
100                 .period                 = 100,
101         };
102 	/* NB: disable ANI noise immmunity for reliable RIFS rx */
103 	AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
104 
105         ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
106 }
107 
108 /*
109  * Attach for an AR9285 part.
110  */
111 static struct ath_hal *
112 ar9285Attach(uint16_t devid, HAL_SOFTC sc,
113 	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
114 	HAL_STATUS *status)
115 {
116 	struct ath_hal_9285 *ahp9285;
117 	struct ath_hal_5212 *ahp;
118 	struct ath_hal *ah;
119 	uint32_t val;
120 	HAL_STATUS ecode;
121 	HAL_BOOL rfStatus;
122 
123 	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
124 	    __func__, sc, (void*) st, (void*) sh);
125 
126 	/* NB: memory is returned zero'd */
127 	ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
128 	if (ahp9285 == AH_NULL) {
129 		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
130 		    "%s: cannot allocate memory for state block\n", __func__);
131 		*status = HAL_ENOMEM;
132 		return AH_NULL;
133 	}
134 	ahp = AH5212(ahp9285);
135 	ah = &ahp->ah_priv.h;
136 
137 	ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
138 
139 	/*
140 	 * Use the "local" EEPROM data given to us by the higher layers.
141 	 * This is a private copy out of system flash. The Linux ath9k
142 	 * commit for the initial AR9130 support mentions MMIO flash
143 	 * access is "unreliable." -adrian
144 	 */
145 	if (eepromdata != AH_NULL) {
146 		AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
147 		AH_PRIVATE(ah)->ah_eepromWrite = NULL;
148 		ah->ah_eepromdata = eepromdata;
149 	}
150 
151 	/* override with 9285 specific state */
152 	AH5416(ah)->ah_initPLL = ar9280InitPLL;
153 	AH5416(ah)->ah_btCoexSetDiversity = ar5416BTCoexAntennaDiversity;
154 
155 	ah->ah_setAntennaSwitch		= ar9285SetAntennaSwitch;
156 	ah->ah_configPCIE		= ar9285ConfigPCIE;
157 	ah->ah_disablePCIE		= ar9285DisablePCIE;
158 	ah->ah_setTxPower		= ar9285SetTransmitPower;
159 	ah->ah_setBoardValues		= ar9285SetBoardValues;
160 	ah->ah_btcoexSetParameter	= ar9285BTCoexSetParameter;
161 
162 	AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
163 	AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
164 	AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
165 	AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
166 	AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
167 
168 	AH5416(ah)->ah_spurMitigate	= ar9280SpurMitigate;
169 	AH5416(ah)->ah_writeIni		= ar9285WriteIni;
170 	AH5416(ah)->ah_rx_chainmask	= AR9285_DEFAULT_RXCHAINMASK;
171 	AH5416(ah)->ah_tx_chainmask	= AR9285_DEFAULT_TXCHAINMASK;
172 
173 	ahp->ah_maxTxTrigLev		= MAX_TX_FIFO_THRESHOLD >> 1;
174 
175 	if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
176 		/* reset chip */
177 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
178 		    __func__);
179 		ecode = HAL_EIO;
180 		goto bad;
181 	}
182 
183 	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
184 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
185 		    __func__);
186 		ecode = HAL_EIO;
187 		goto bad;
188 	}
189 	/* Read Revisions from Chips before taking out of reset */
190 	val = OS_REG_READ(ah, AR_SREV);
191 	HALDEBUG(ah, HAL_DEBUG_ATTACH,
192 	    "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
193 	    __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
194 	    MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
195 	/* NB: include chip type to differentiate from pre-Sowl versions */
196 	AH_PRIVATE(ah)->ah_macVersion =
197 	    (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
198 	AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
199 	AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
200 
201 	/* setup common ini data; rf backends handle remainder */
202 	if (AR_SREV_KITE_12_OR_LATER(ah)) {
203 		HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
204 		HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
205 		HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
206 		    ar9285PciePhy_clkreq_always_on_L1_v2, 2);
207 	} else {
208 		HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
209 		HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
210 		HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
211 		    ar9285PciePhy_clkreq_always_on_L1, 2);
212 	}
213 	ar5416AttachPCIE(ah);
214 
215 	/* Attach methods that require MAC version/revision info */
216 	if (AR_SREV_KITE_12_OR_LATER(ah))
217 		AH5416(ah)->ah_cal_initcal      = ar9285InitCalHardware;
218 	if (AR_SREV_KITE_11_OR_LATER(ah))
219 		AH5416(ah)->ah_cal_pacal        = ar9002_hw_pa_cal;
220 
221 	ecode = ath_hal_v4kEepromAttach(ah);
222 	if (ecode != HAL_OK)
223 		goto bad;
224 
225 	if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */
226 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
227 		    __func__);
228 		ecode = HAL_EIO;
229 		goto bad;
230 	}
231 
232 	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
233 
234 	if (!ar5212ChipTest(ah)) {
235 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
236 		    __func__);
237 		ecode = HAL_ESELFTEST;
238 		goto bad;
239 	}
240 
241 	/*
242 	 * Set correct Baseband to analog shift
243 	 * setting to access analog chips.
244 	 */
245 	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
246 
247 	/* Read Radio Chip Rev Extract */
248 	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
249 	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
250         case AR_RAD2133_SREV_MAJOR:	/* Sowl: 2G/3x3 */
251 	case AR_RAD5133_SREV_MAJOR:	/* Sowl: 2+5G/3x3 */
252 		break;
253 	default:
254 		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
255 			AH_PRIVATE(ah)->ah_analog5GhzRev =
256 				AR_RAD5133_SREV_MAJOR;
257 			break;
258 		}
259 #ifdef AH_DEBUG
260 		HALDEBUG(ah, HAL_DEBUG_ANY,
261 		    "%s: 5G Radio Chip Rev 0x%02X is not supported by "
262 		    "this driver\n", __func__,
263 		    AH_PRIVATE(ah)->ah_analog5GhzRev);
264 		ecode = HAL_ENOTSUPP;
265 		goto bad;
266 #endif
267 	}
268 	rfStatus = ar9285RfAttach(ah, &ecode);
269 	if (!rfStatus) {
270 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
271 		    __func__, ecode);
272 		goto bad;
273 	}
274 
275 	HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
276 	    6);
277 
278 	if (AR_SREV_9285E_20(ah))
279 		ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
280 
281 	/* setup txgain table */
282 	switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
283 	case AR5416_EEP_TXGAIN_HIGH_POWER:
284 		if (AR_SREV_9285E_20(ah))
285 			HAL_INI_INIT(&ahp9285->ah_ini_txgain,
286 			    ar9285Modes_XE2_0_high_power, 6);
287 		else
288 			HAL_INI_INIT(&ahp9285->ah_ini_txgain,
289 			    ar9285Modes_high_power_tx_gain_v2, 6);
290 		break;
291 	case AR5416_EEP_TXGAIN_ORIG:
292 		if (AR_SREV_9285E_20(ah))
293 			HAL_INI_INIT(&ahp9285->ah_ini_txgain,
294 			    ar9285Modes_XE2_0_normal_power, 6);
295 		else
296 			HAL_INI_INIT(&ahp9285->ah_ini_txgain,
297 			    ar9285Modes_original_tx_gain_v2, 6);
298 		break;
299 	default:
300 		HALASSERT(AH_FALSE);
301 		goto bad;		/* XXX ? try to continue */
302 	}
303 
304 	/*
305 	 * Got everything we need now to setup the capabilities.
306 	 */
307 	if (!ar9285FillCapabilityInfo(ah)) {
308 		ecode = HAL_EEREAD;
309 		goto bad;
310 	}
311 
312 	/* Print out whether the EEPROM settings enable AR9285 diversity */
313 	if (ar9285_check_div_comb(ah)) {
314 		ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");
315 		ah->ah_rxAntCombDiversity = ar9285_ant_comb_scan;
316 	}
317 
318 	/* Disable 11n for the AR2427 */
319 	if (devid == AR2427_DEVID_PCIE)
320 		AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
321 
322 	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
323 	if (ecode != HAL_OK) {
324 		HALDEBUG(ah, HAL_DEBUG_ANY,
325 		    "%s: error getting mac address from EEPROM\n", __func__);
326 		goto bad;
327         }
328 	/* XXX How about the serial number ? */
329 	/* Read Reg Domain */
330 	AH_PRIVATE(ah)->ah_currentRD =
331 	    ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
332 	/*
333          * For Kite and later chipsets, the following bits are not
334 	 * programmed in EEPROM and so are set as enabled always.
335 	 */
336 	AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;
337 
338 	/*
339 	 * ah_miscMode is populated by ar5416FillCapabilityInfo()
340 	 * starting from griffin. Set here to make sure that
341 	 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
342 	 * placed into hardware.
343 	 */
344 	if (ahp->ah_miscMode != 0)
345 		OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
346 
347 	ar9285AniSetup(ah);			/* Anti Noise Immunity */
348 
349 	/* Setup noise floor min/max/nominal values */
350 	AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
351 	AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
352 	AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
353 	/* XXX no 5ghz values? */
354 
355 	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
356 
357 	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
358 
359 	return ah;
360 bad:
361 	if (ah != AH_NULL)
362 		ah->ah_detach(ah);
363 	if (status)
364 		*status = ecode;
365 	return AH_NULL;
366 }
367 
368 static void
369 ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
370 {
371 	uint32_t val;
372 
373 	/*
374 	 * This workaround needs some integration work with the HAL
375 	 * config parameters and the if_ath_pci.c glue.
376 	 * Specifically, read the value of the PCI register 0x70c
377 	 * (4 byte PCI config space register) and store it in ath_hal_war70c.
378 	 * Then if it's non-zero, the below WAR would override register
379 	 * 0x570c upon suspend/resume.
380 	 */
381 #if 0
382 	if (AR_SREV_9285E_20(ah)) {
383 		val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;
384 		if (val) {
385 			val &= 0xffff00ff;
386 			val |= 0x6f00;
387 			OS_REG_WRITE(ah, 0x570c, val);
388 		}
389 	}
390 #endif
391 
392 	if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
393 		ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
394 		OS_DELAY(1000);
395 	}
396 
397 	/*
398 	 * Set PCIe workaround bits
399 	 *
400 	 * NOTE:
401 	 *
402 	 * In Merlin and Kite, bit 14 in WA register (disable L1) should only
403 	 * be set when device enters D3 and be cleared when device comes back
404 	 * to D0.
405 	 */
406 	if (power_off) {                /* Power-off */
407 		OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
408 
409 		val = OS_REG_READ(ah, AR_WA);
410 
411 		/*
412 		 * Disable bit 6 and 7 before entering D3 to prevent
413 		 * system hang.
414 		 */
415 		val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
416 
417 		/*
418 		 * See above: set AR_WA_D3_L1_DISABLE when entering D3 state.
419 		 *
420 		 * XXX The reference HAL does it this way - it only sets
421 		 * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT,
422 		 * which it (currently) isn't.  So the following statement
423 		 * is currently a NOP.
424 		 */
425 		if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
426 			val |= AR_WA_D3_L1_DISABLE;
427 
428 		if (AR_SREV_9285E_20(ah))
429 			val |= AR_WA_BIT23;
430 
431 		OS_REG_WRITE(ah, AR_WA, val);
432 	} else {			/* Power-on */
433 		val = AR9285_WA_DEFAULT;
434 		/*
435 		 * See note above: make sure L1_DISABLE is not set.
436 		 */
437 		val &= (~AR_WA_D3_L1_DISABLE);
438 
439 		/* Software workaroud for ASPM system hang. */
440 		val |= (AR_WA_BIT6 | AR_WA_BIT7);
441 
442 		if (AR_SREV_9285E_20(ah))
443 			val |= AR_WA_BIT23;
444 
445 		OS_REG_WRITE(ah, AR_WA, val);
446 
447 		/* set bit 19 to allow forcing of pcie core into L1 state */
448 		OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
449 	}
450 }
451 
452 static void
453 ar9285DisablePCIE(struct ath_hal *ah)
454 {
455 }
456 
457 static void
458 ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
459 {
460 	u_int modesIndex, freqIndex;
461 	int regWrites = 0;
462 
463 	/* Setup the indices for the next set of register array writes */
464 	/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
465 	freqIndex = 2;
466 	if (IEEE80211_IS_CHAN_HT40(chan))
467 		modesIndex = 3;
468 	else if (IEEE80211_IS_CHAN_108G(chan))
469 		modesIndex = 5;
470 	else
471 		modesIndex = 4;
472 
473 	/* Set correct Baseband to analog shift setting to access analog chips. */
474 	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
475 	OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
476 	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
477 	    modesIndex, regWrites);
478 	if (AR_SREV_KITE_12_OR_LATER(ah)) {
479 		regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
480 		    modesIndex, regWrites);
481 	}
482 	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
483 	    1, regWrites);
484 }
485 
486 /*
487  * Fill all software cached or static hardware state information.
488  * Return failure if capabilities are to come from EEPROM and
489  * cannot be read.
490  */
491 static HAL_BOOL
492 ar9285FillCapabilityInfo(struct ath_hal *ah)
493 {
494 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
495 
496 	if (!ar5416FillCapabilityInfo(ah))
497 		return AH_FALSE;
498 	pCap->halNumGpioPins = 12;
499 	pCap->halWowSupport = AH_TRUE;
500 	pCap->halWowMatchPatternExact = AH_TRUE;
501 #if 0
502 	pCap->halWowMatchPatternDword = AH_TRUE;
503 #endif
504 	/* AR9285 has 2 antennas but is a 1x1 stream device */
505 	pCap->halTxStreams = 1;
506 	pCap->halRxStreams = 1;
507 
508 	if (ar9285_check_div_comb(ah))
509 		pCap->halAntDivCombSupport = AH_TRUE;
510 
511 	pCap->halCSTSupport = AH_TRUE;
512 	pCap->halRifsRxSupport = AH_TRUE;
513 	pCap->halRifsTxSupport = AH_TRUE;
514 	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
515 	pCap->halExtChanDfsSupport = AH_TRUE;
516 	pCap->halUseCombinedRadarRssi = AH_TRUE;
517 #if 0
518 	/* XXX bluetooth */
519 	pCap->halBtCoexSupport = AH_TRUE;
520 #endif
521 	pCap->halAutoSleepSupport = AH_FALSE;	/* XXX? */
522 	pCap->hal4kbSplitTransSupport = AH_FALSE;
523 	/* Disable this so Block-ACK works correctly */
524 	pCap->halHasRxSelfLinkedTail = AH_FALSE;
525 	pCap->halMbssidAggrSupport = AH_TRUE;
526 	pCap->hal4AddrAggrSupport = AH_TRUE;
527 
528 	if (AR_SREV_KITE_12_OR_LATER(ah))
529 		pCap->halPSPollBroken = AH_FALSE;
530 
531 	/* Only RX STBC supported */
532 	pCap->halRxStbcSupport = 1;
533 	pCap->halTxStbcSupport = 0;
534 
535 	return AH_TRUE;
536 }
537 
538 static const char*
539 ar9285Probe(uint16_t vendorid, uint16_t devid)
540 {
541 	if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
542 		return "Atheros 9285";
543 	if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE))
544 		return "Atheros 2427";
545 
546 	return AH_NULL;
547 }
548 AH_CHIP(AR9285, ar9285Probe, ar9285Attach);
549