1 /* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */ 26 27 #include "ar9002/ar9280.h" 28 #include "ar9002/ar9285.h" 29 #include "ar5416/ar5416reg.h" 30 #include "ar5416/ar5416phy.h" 31 32 #include "ar9002/ar9285.ini" 33 #include "ar9002/ar9285v2.ini" 34 #include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */ 35 36 #include "ar9002/ar9285_cal.h" 37 #include "ar9002/ar9285_phy.h" 38 #include "ar9002/ar9285_diversity.h" 39 40 static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 41 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 42 .calNumSamples = MIN_CAL_SAMPLES, 43 .calCountMax = PER_MAX_LOG_COUNT, 44 .calCollect = ar5416IQCalCollect, 45 .calPostProc = ar5416IQCalibration 46 }; 47 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 48 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 49 .calNumSamples = MIN_CAL_SAMPLES, 50 .calCountMax = PER_MIN_LOG_COUNT, 51 .calCollect = ar5416AdcGainCalCollect, 52 .calPostProc = ar5416AdcGainCalibration 53 }; 54 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 55 .calName = "ADC DC", .calType = ADC_DC_CAL, 56 .calNumSamples = MIN_CAL_SAMPLES, 57 .calCountMax = PER_MIN_LOG_COUNT, 58 .calCollect = ar5416AdcDcCalCollect, 59 .calPostProc = ar5416AdcDcCalibration 60 }; 61 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 62 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 63 .calNumSamples = MIN_CAL_SAMPLES, 64 .calCountMax = INIT_LOG_COUNT, 65 .calCollect = ar5416AdcDcCalCollect, 66 .calPostProc = ar5416AdcDcCalibration 67 }; 68 69 static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 70 HAL_BOOL power_off); 71 static void ar9285DisablePCIE(struct ath_hal *ah); 72 static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah); 73 static void ar9285WriteIni(struct ath_hal *ah, 74 const struct ieee80211_channel *chan); 75 76 static void 77 ar9285AniSetup(struct ath_hal *ah) 78 { 79 /* 80 * These are the parameters from the AR5416 ANI code; 81 * they likely need quite a bit of adjustment for the 82 * AR9285. 83 */ 84 static const struct ar5212AniParams aniparams = { 85 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 86 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 87 .coarseHigh = { -14, -14, -14, -14, -12 }, 88 .coarseLow = { -64, -64, -64, -64, -70 }, 89 .firpwr = { -78, -78, -78, -78, -80 }, 90 .maxSpurImmunityLevel = 7, 91 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 92 .maxFirstepLevel = 2, /* levels 0..2 */ 93 .firstep = { 0, 4, 8 }, 94 .ofdmTrigHigh = 500, 95 .ofdmTrigLow = 200, 96 .cckTrigHigh = 200, 97 .cckTrigLow = 100, 98 .rssiThrHigh = 40, 99 .rssiThrLow = 7, 100 .period = 100, 101 }; 102 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 103 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 104 105 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 106 } 107 108 static const char * ar9285_lna_conf[] = { 109 "LNA1-LNA2", 110 "LNA2", 111 "LNA1", 112 "LNA1+LNA2", 113 }; 114 115 static void 116 ar9285_eeprom_print_diversity_settings(struct ath_hal *ah) 117 { 118 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; 119 const MODAL_EEP4K_HEADER *pModal = &ee->ee_base.modalHeader; 120 121 ath_hal_printf(ah, "[ath] AR9285 Main LNA config: %s\n", 122 ar9285_lna_conf[(pModal->antdiv_ctl2 >> 2) & 0x3]); 123 ath_hal_printf(ah, "[ath] AR9285 Alt LNA config: %s\n", 124 ar9285_lna_conf[pModal->antdiv_ctl2 & 0x3]); 125 ath_hal_printf(ah, "[ath] LNA diversity %s, Diversity %s\n", 126 ((pModal->antdiv_ctl1 & 0x1) ? "enabled" : "disabled"), 127 ((pModal->antdiv_ctl1 & 0x8) ? "enabled" : "disabled")); 128 } 129 130 /* 131 * Attach for an AR9285 part. 132 */ 133 static struct ath_hal * 134 ar9285Attach(uint16_t devid, HAL_SOFTC sc, 135 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 136 HAL_OPS_CONFIG *ah_config, 137 HAL_STATUS *status) 138 { 139 struct ath_hal_9285 *ahp9285; 140 struct ath_hal_5212 *ahp; 141 struct ath_hal *ah; 142 uint32_t val; 143 HAL_STATUS ecode; 144 HAL_BOOL rfStatus; 145 146 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 147 __func__, sc, (void*) st, (void*) sh); 148 149 /* NB: memory is returned zero'd */ 150 ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285)); 151 if (ahp9285 == AH_NULL) { 152 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 153 "%s: cannot allocate memory for state block\n", __func__); 154 *status = HAL_ENOMEM; 155 return AH_NULL; 156 } 157 ahp = AH5212(ahp9285); 158 ah = &ahp->ah_priv.h; 159 160 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 161 162 /* 163 * Use the "local" EEPROM data given to us by the higher layers. 164 * This is a private copy out of system flash. The Linux ath9k 165 * commit for the initial AR9130 support mentions MMIO flash 166 * access is "unreliable." -adrian 167 */ 168 if (eepromdata != AH_NULL) { 169 AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead; 170 AH_PRIVATE(ah)->ah_eepromWrite = NULL; 171 ah->ah_eepromdata = eepromdata; 172 } 173 174 /* override with 9285 specific state */ 175 AH5416(ah)->ah_initPLL = ar9280InitPLL; 176 AH5416(ah)->ah_btCoexSetDiversity = ar9285BTCoexAntennaDiversity; 177 178 ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch; 179 ah->ah_configPCIE = ar9285ConfigPCIE; 180 ah->ah_disablePCIE = ar9285DisablePCIE; 181 ah->ah_setTxPower = ar9285SetTransmitPower; 182 ah->ah_setBoardValues = ar9285SetBoardValues; 183 ah->ah_btCoexSetParameter = ar9285BTCoexSetParameter; 184 ah->ah_divLnaConfGet = ar9285_antdiv_comb_conf_get; 185 ah->ah_divLnaConfSet = ar9285_antdiv_comb_conf_set; 186 187 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 188 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 189 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 190 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 191 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 192 193 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 194 AH5416(ah)->ah_writeIni = ar9285WriteIni; 195 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK; 196 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK; 197 198 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1; 199 200 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 201 /* reset chip */ 202 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 203 __func__); 204 ecode = HAL_EIO; 205 goto bad; 206 } 207 208 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 209 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 210 __func__); 211 ecode = HAL_EIO; 212 goto bad; 213 } 214 /* Read Revisions from Chips before taking out of reset */ 215 val = OS_REG_READ(ah, AR_SREV); 216 HALDEBUG(ah, HAL_DEBUG_ATTACH, 217 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 218 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 219 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 220 /* NB: include chip type to differentiate from pre-Sowl versions */ 221 AH_PRIVATE(ah)->ah_macVersion = 222 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 223 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 224 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 225 226 /* setup common ini data; rf backends handle remainder */ 227 if (AR_SREV_KITE_12_OR_LATER(ah)) { 228 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6); 229 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2); 230 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 231 ar9285PciePhy_clkreq_always_on_L1_v2, 2); 232 } else { 233 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6); 234 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2); 235 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 236 ar9285PciePhy_clkreq_always_on_L1, 2); 237 } 238 ar5416AttachPCIE(ah); 239 240 /* Attach methods that require MAC version/revision info */ 241 if (AR_SREV_KITE_12_OR_LATER(ah)) 242 AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware; 243 if (AR_SREV_KITE_11_OR_LATER(ah)) 244 AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal; 245 246 ecode = ath_hal_v4kEepromAttach(ah); 247 if (ecode != HAL_OK) 248 goto bad; 249 250 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 251 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 252 __func__); 253 ecode = HAL_EIO; 254 goto bad; 255 } 256 257 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 258 259 if (!ar5212ChipTest(ah)) { 260 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 261 __func__); 262 ecode = HAL_ESELFTEST; 263 goto bad; 264 } 265 266 /* 267 * Set correct Baseband to analog shift 268 * setting to access analog chips. 269 */ 270 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 271 272 /* Read Radio Chip Rev Extract */ 273 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 274 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 275 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 276 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 277 break; 278 default: 279 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 280 AH_PRIVATE(ah)->ah_analog5GhzRev = 281 AR_RAD5133_SREV_MAJOR; 282 break; 283 } 284 #ifdef AH_DEBUG 285 HALDEBUG(ah, HAL_DEBUG_ANY, 286 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 287 "this driver\n", __func__, 288 AH_PRIVATE(ah)->ah_analog5GhzRev); 289 ecode = HAL_ENOTSUPP; 290 goto bad; 291 #endif 292 } 293 rfStatus = ar9285RfAttach(ah, &ecode); 294 if (!rfStatus) { 295 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 296 __func__, ecode); 297 goto bad; 298 } 299 300 HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2, 301 6); 302 303 if (AR_SREV_9285E_20(ah)) 304 ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n"); 305 306 /* setup txgain table */ 307 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 308 case AR5416_EEP_TXGAIN_HIGH_POWER: 309 if (AR_SREV_9285E_20(ah)) 310 HAL_INI_INIT(&ahp9285->ah_ini_txgain, 311 ar9285Modes_XE2_0_high_power, 6); 312 else 313 HAL_INI_INIT(&ahp9285->ah_ini_txgain, 314 ar9285Modes_high_power_tx_gain_v2, 6); 315 break; 316 case AR5416_EEP_TXGAIN_ORIG: 317 if (AR_SREV_9285E_20(ah)) 318 HAL_INI_INIT(&ahp9285->ah_ini_txgain, 319 ar9285Modes_XE2_0_normal_power, 6); 320 else 321 HAL_INI_INIT(&ahp9285->ah_ini_txgain, 322 ar9285Modes_original_tx_gain_v2, 6); 323 break; 324 default: 325 HALASSERT(AH_FALSE); 326 goto bad; /* XXX ? try to continue */ 327 } 328 329 /* 330 * Got everything we need now to setup the capabilities. 331 */ 332 if (!ar9285FillCapabilityInfo(ah)) { 333 ecode = HAL_EEREAD; 334 goto bad; 335 } 336 337 /* 338 * Print out the EEPROM antenna configuration mapping. 339 * Some devices have a hard-coded LNA configuration profile; 340 * others enable diversity. 341 */ 342 ar9285_eeprom_print_diversity_settings(ah); 343 344 /* Print out whether the EEPROM settings enable AR9285 diversity */ 345 if (ar9285_check_div_comb(ah)) { 346 ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n"); 347 } 348 349 /* Disable 11n for the AR2427 */ 350 if (devid == AR2427_DEVID_PCIE) 351 AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE; 352 353 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 354 if (ecode != HAL_OK) { 355 HALDEBUG(ah, HAL_DEBUG_ANY, 356 "%s: error getting mac address from EEPROM\n", __func__); 357 goto bad; 358 } 359 /* XXX How about the serial number ? */ 360 /* Read Reg Domain */ 361 AH_PRIVATE(ah)->ah_currentRD = 362 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 363 /* 364 * For Kite and later chipsets, the following bits are not 365 * programmed in EEPROM and so are set as enabled always. 366 */ 367 AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT; 368 369 /* 370 * ah_miscMode is populated by ar5416FillCapabilityInfo() 371 * starting from griffin. Set here to make sure that 372 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 373 * placed into hardware. 374 */ 375 if (ahp->ah_miscMode != 0) 376 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 377 378 ar9285AniSetup(ah); /* Anti Noise Immunity */ 379 380 /* Setup noise floor min/max/nominal values */ 381 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ; 382 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ; 383 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ; 384 /* XXX no 5ghz values? */ 385 386 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 387 388 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 389 390 return ah; 391 bad: 392 if (ah != AH_NULL) 393 ah->ah_detach(ah); 394 if (status) 395 *status = ecode; 396 return AH_NULL; 397 } 398 399 static void 400 ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 401 { 402 uint32_t val; 403 404 /* 405 * This workaround needs some integration work with the HAL 406 * config parameters and the if_ath_pci.c glue. 407 * Specifically, read the value of the PCI register 0x70c 408 * (4 byte PCI config space register) and store it in ath_hal_war70c. 409 * Then if it's non-zero, the below WAR would override register 410 * 0x570c upon suspend/resume. 411 */ 412 #if 0 413 if (AR_SREV_9285E_20(ah)) { 414 val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c; 415 if (val) { 416 val &= 0xffff00ff; 417 val |= 0x6f00; 418 OS_REG_WRITE(ah, 0x570c, val); 419 } 420 } 421 #endif 422 423 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 424 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 425 OS_DELAY(1000); 426 } 427 428 /* 429 * Set PCIe workaround bits 430 * 431 * NOTE: 432 * 433 * In Merlin and Kite, bit 14 in WA register (disable L1) should only 434 * be set when device enters D3 and be cleared when device comes back 435 * to D0. 436 */ 437 if (power_off) { /* Power-off */ 438 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 439 440 val = OS_REG_READ(ah, AR_WA); 441 442 /* 443 * Disable bit 6 and 7 before entering D3 to prevent 444 * system hang. 445 */ 446 val &= ~(AR_WA_BIT6 | AR_WA_BIT7); 447 448 /* 449 * See above: set AR_WA_D3_L1_DISABLE when entering D3 state. 450 * 451 * XXX The reference HAL does it this way - it only sets 452 * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT, 453 * which it (currently) isn't. So the following statement 454 * is currently a NOP. 455 */ 456 if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE) 457 val |= AR_WA_D3_L1_DISABLE; 458 459 if (AR_SREV_9285E_20(ah)) 460 val |= AR_WA_BIT23; 461 462 OS_REG_WRITE(ah, AR_WA, val); 463 } else { /* Power-on */ 464 val = AR9285_WA_DEFAULT; 465 /* 466 * See note above: make sure L1_DISABLE is not set. 467 */ 468 val &= (~AR_WA_D3_L1_DISABLE); 469 470 /* Software workaroud for ASPM system hang. */ 471 val |= (AR_WA_BIT6 | AR_WA_BIT7); 472 473 if (AR_SREV_9285E_20(ah)) 474 val |= AR_WA_BIT23; 475 476 OS_REG_WRITE(ah, AR_WA, val); 477 478 /* set bit 19 to allow forcing of pcie core into L1 state */ 479 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 480 } 481 } 482 483 static void 484 ar9285DisablePCIE(struct ath_hal *ah) 485 { 486 } 487 488 static void 489 ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 490 { 491 u_int modesIndex, freqIndex; 492 int regWrites = 0; 493 494 /* Setup the indices for the next set of register array writes */ 495 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 496 freqIndex = 2; 497 if (IEEE80211_IS_CHAN_HT40(chan)) 498 modesIndex = 3; 499 else if (IEEE80211_IS_CHAN_108G(chan)) 500 modesIndex = 5; 501 else 502 modesIndex = 4; 503 504 /* Set correct Baseband to analog shift setting to access analog chips. */ 505 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 506 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 507 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 508 modesIndex, regWrites); 509 if (AR_SREV_KITE_12_OR_LATER(ah)) { 510 regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain, 511 modesIndex, regWrites); 512 } 513 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 514 1, regWrites); 515 } 516 517 /* 518 * Fill all software cached or static hardware state information. 519 * Return failure if capabilities are to come from EEPROM and 520 * cannot be read. 521 */ 522 static HAL_BOOL 523 ar9285FillCapabilityInfo(struct ath_hal *ah) 524 { 525 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 526 527 if (!ar5416FillCapabilityInfo(ah)) 528 return AH_FALSE; 529 pCap->halNumGpioPins = 12; 530 pCap->halWowSupport = AH_TRUE; 531 pCap->halWowMatchPatternExact = AH_TRUE; 532 #if 0 533 pCap->halWowMatchPatternDword = AH_TRUE; 534 #endif 535 /* AR9285 has 2 antennas but is a 1x1 stream device */ 536 pCap->halTxStreams = 1; 537 pCap->halRxStreams = 1; 538 539 if (ar9285_check_div_comb(ah)) 540 pCap->halAntDivCombSupport = AH_TRUE; 541 542 pCap->halCSTSupport = AH_TRUE; 543 pCap->halRifsRxSupport = AH_TRUE; 544 pCap->halRifsTxSupport = AH_TRUE; 545 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 546 pCap->halExtChanDfsSupport = AH_TRUE; 547 pCap->halUseCombinedRadarRssi = AH_TRUE; 548 #if 1 549 /* XXX bluetooth */ 550 pCap->halBtCoexSupport = AH_TRUE; 551 #endif 552 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 553 pCap->hal4kbSplitTransSupport = AH_FALSE; 554 /* Disable this so Block-ACK works correctly */ 555 pCap->halHasRxSelfLinkedTail = AH_FALSE; 556 pCap->halMbssidAggrSupport = AH_TRUE; 557 pCap->hal4AddrAggrSupport = AH_TRUE; 558 pCap->halSpectralScanSupport = AH_TRUE; 559 pCap->halRxUsingLnaMixing = AH_TRUE; 560 561 if (AR_SREV_KITE_12_OR_LATER(ah)) 562 pCap->halPSPollBroken = AH_FALSE; 563 564 /* Only RX STBC supported */ 565 pCap->halRxStbcSupport = 1; 566 pCap->halTxStbcSupport = 0; 567 568 return AH_TRUE; 569 } 570 571 static const char* 572 ar9285Probe(uint16_t vendorid, uint16_t devid) 573 { 574 if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE) 575 return "Atheros 9285"; 576 if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE)) 577 return "Atheros 2427"; 578 579 return AH_NULL; 580 } 581 AH_CHIP(AR9285, ar9285Probe, ar9285Attach); 582