1 /* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27 #include "ar9002/ar9280.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar9002/ar9280v1.ini" 32 #include "ar9002/ar9280v2.ini" 33 #include "ar9002/ar9280_olc.h" 34 35 static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37 .calNumSamples = MIN_CAL_SAMPLES, 38 .calCountMax = PER_MAX_LOG_COUNT, 39 .calCollect = ar5416IQCalCollect, 40 .calPostProc = ar5416IQCalibration 41 }; 42 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44 .calNumSamples = MIN_CAL_SAMPLES, 45 .calCountMax = PER_MAX_LOG_COUNT, 46 .calCollect = ar5416AdcGainCalCollect, 47 .calPostProc = ar5416AdcGainCalibration 48 }; 49 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50 .calName = "ADC DC", .calType = ADC_DC_CAL, 51 .calNumSamples = MIN_CAL_SAMPLES, 52 .calCountMax = PER_MAX_LOG_COUNT, 53 .calCollect = ar5416AdcDcCalCollect, 54 .calPostProc = ar5416AdcDcCalibration 55 }; 56 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58 .calNumSamples = MIN_CAL_SAMPLES, 59 .calCountMax = INIT_LOG_COUNT, 60 .calCollect = ar5416AdcDcCalCollect, 61 .calPostProc = ar5416AdcDcCalibration 62 }; 63 64 static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 65 HAL_BOOL power_off); 66 static void ar9280DisablePCIE(struct ath_hal *ah); 67 static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 68 static void ar9280WriteIni(struct ath_hal *ah, 69 const struct ieee80211_channel *chan); 70 71 static void 72 ar9280AniSetup(struct ath_hal *ah) 73 { 74 /* 75 * These are the parameters from the AR5416 ANI code; 76 * they likely need quite a bit of adjustment for the 77 * AR9280. 78 */ 79 static const struct ar5212AniParams aniparams = { 80 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 81 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 82 .coarseHigh = { -14, -14, -14, -14, -12 }, 83 .coarseLow = { -64, -64, -64, -64, -70 }, 84 .firpwr = { -78, -78, -78, -78, -80 }, 85 .maxSpurImmunityLevel = 2, 86 .cycPwrThr1 = { 2, 4, 6 }, 87 .maxFirstepLevel = 2, /* levels 0..2 */ 88 .firstep = { 0, 4, 8 }, 89 .ofdmTrigHigh = 500, 90 .ofdmTrigLow = 200, 91 .cckTrigHigh = 200, 92 .cckTrigLow = 100, 93 .rssiThrHigh = 40, 94 .rssiThrLow = 7, 95 .period = 100, 96 }; 97 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 98 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 99 100 /* NB: ANI is not enabled yet */ 101 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 102 } 103 104 void 105 ar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 106 { 107 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 108 109 if (AR_SREV_MERLIN_20(ah) && 110 chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 111 /* 112 * PLL WAR for Merlin 2.0/2.1 113 * When doing fast clock, set PLL to 0x142c 114 * Else, set PLL to 0x2850 to prevent reset-to-reset variation 115 */ 116 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 117 } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 118 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 119 if (chan != AH_NULL) { 120 if (IEEE80211_IS_CHAN_HALF(chan)) 121 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 122 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 123 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 124 if (IEEE80211_IS_CHAN_5GHZ(chan)) 125 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 126 else 127 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 128 } else 129 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 130 } 131 132 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 133 OS_DELAY(RTC_PLL_SETTLE_DELAY); 134 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 135 } 136 137 /* XXX shouldn't be here! */ 138 #define EEP_MINOR(_ah) \ 139 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 140 141 /* 142 * Attach for an AR9280 part. 143 */ 144 static struct ath_hal * 145 ar9280Attach(uint16_t devid, HAL_SOFTC sc, 146 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 147 HAL_STATUS *status) 148 { 149 struct ath_hal_9280 *ahp9280; 150 struct ath_hal_5212 *ahp; 151 struct ath_hal *ah; 152 uint32_t val; 153 HAL_STATUS ecode; 154 HAL_BOOL rfStatus; 155 int8_t pwr_table_offset; 156 uint8_t pwr; 157 158 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 159 __func__, sc, (void*) st, (void*) sh); 160 161 /* NB: memory is returned zero'd */ 162 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 163 if (ahp9280 == AH_NULL) { 164 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 165 "%s: cannot allocate memory for state block\n", __func__); 166 *status = HAL_ENOMEM; 167 return AH_NULL; 168 } 169 ahp = AH5212(ahp9280); 170 ah = &ahp->ah_priv.h; 171 172 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 173 174 /* 175 * Use the "local" EEPROM data given to us by the higher layers. 176 * This is a private copy out of system flash. The Linux ath9k 177 * commit for the initial AR9130 support mentions MMIO flash 178 * access is "unreliable." -adrian 179 */ 180 if (eepromdata != AH_NULL) { 181 AH_PRIVATE((ah))->ah_eepromRead = ath_hal_EepromDataRead; 182 AH_PRIVATE((ah))->ah_eepromWrite = NULL; 183 ah->ah_eepromdata = eepromdata; 184 } 185 186 /* XXX override with 9280 specific state */ 187 /* override 5416 methods for our needs */ 188 AH5416(ah)->ah_initPLL = ar9280InitPLL; 189 190 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 191 ah->ah_configPCIE = ar9280ConfigPCIE; 192 ah->ah_disablePCIE = ar9280DisablePCIE; 193 194 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 195 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 196 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 197 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 198 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 199 200 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 201 AH5416(ah)->ah_writeIni = ar9280WriteIni; 202 AH5416(ah)->ah_olcInit = ar9280olcInit; 203 AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 204 AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 205 206 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 207 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 208 209 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 210 /* reset chip */ 211 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 212 __func__); 213 ecode = HAL_EIO; 214 goto bad; 215 } 216 217 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 218 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 219 __func__); 220 ecode = HAL_EIO; 221 goto bad; 222 } 223 /* Read Revisions from Chips before taking out of reset */ 224 val = OS_REG_READ(ah, AR_SREV); 225 HALDEBUG(ah, HAL_DEBUG_ATTACH, 226 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 227 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 228 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 229 /* NB: include chip type to differentiate from pre-Sowl versions */ 230 AH_PRIVATE(ah)->ah_macVersion = 231 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 232 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 233 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 234 235 /* setup common ini data; rf backends handle remainder */ 236 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 237 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 238 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 239 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 240 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 241 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 242 ar9280Modes_fast_clock_v2, 3); 243 } else { 244 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 245 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 246 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 247 ar9280PciePhy_v1, 2); 248 } 249 ar5416AttachPCIE(ah); 250 251 ecode = ath_hal_v14EepromAttach(ah); 252 if (ecode != HAL_OK) 253 goto bad; 254 255 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 256 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 257 ecode = HAL_EIO; 258 goto bad; 259 } 260 261 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 262 263 if (!ar5212ChipTest(ah)) { 264 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 265 __func__); 266 ecode = HAL_ESELFTEST; 267 goto bad; 268 } 269 270 /* 271 * Set correct Baseband to analog shift 272 * setting to access analog chips. 273 */ 274 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 275 276 /* Read Radio Chip Rev Extract */ 277 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 278 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 279 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 280 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 281 break; 282 default: 283 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 284 AH_PRIVATE(ah)->ah_analog5GhzRev = 285 AR_RAD5133_SREV_MAJOR; 286 break; 287 } 288 #ifdef AH_DEBUG 289 HALDEBUG(ah, HAL_DEBUG_ANY, 290 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 291 "this driver\n", __func__, 292 AH_PRIVATE(ah)->ah_analog5GhzRev); 293 ecode = HAL_ENOTSUPP; 294 goto bad; 295 #endif 296 } 297 rfStatus = ar9280RfAttach(ah, &ecode); 298 if (!rfStatus) { 299 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 300 __func__, ecode); 301 goto bad; 302 } 303 304 /* Enable fixup for AR_AN_TOP2 if necessary */ 305 /* 306 * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 307 * by the EEPROM version. 308 * 309 * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 310 * the abstracted EEPROM access layer. 311 */ 312 ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 313 if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 314 printf("[ath] enabling AN_TOP2_FIXUP\n"); 315 AH5416(ah)->ah_need_an_top2_fixup = 1; 316 } 317 318 /* 319 * Check whether the power table offset isn't the default. 320 * This can occur with eeprom minor V21 or greater on Merlin. 321 */ 322 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 323 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 324 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 325 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 326 327 /* XXX check for >= minor ver 17 */ 328 if (AR_SREV_MERLIN_20(ah)) { 329 /* setup rxgain table */ 330 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 331 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 332 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 333 ar9280Modes_backoff_13db_rxgain_v2, 6); 334 break; 335 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 336 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 337 ar9280Modes_backoff_23db_rxgain_v2, 6); 338 break; 339 case AR5416_EEP_RXGAIN_ORIG: 340 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 341 ar9280Modes_original_rxgain_v2, 6); 342 break; 343 default: 344 HALASSERT(AH_FALSE); 345 goto bad; /* XXX ? try to continue */ 346 } 347 } 348 349 /* XXX check for >= minor ver 19 */ 350 if (AR_SREV_MERLIN_20(ah)) { 351 /* setp txgain table */ 352 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 353 case AR5416_EEP_TXGAIN_HIGH_POWER: 354 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 355 ar9280Modes_high_power_tx_gain_v2, 6); 356 break; 357 case AR5416_EEP_TXGAIN_ORIG: 358 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 359 ar9280Modes_original_tx_gain_v2, 6); 360 break; 361 default: 362 HALASSERT(AH_FALSE); 363 goto bad; /* XXX ? try to continue */ 364 } 365 } 366 367 /* 368 * Got everything we need now to setup the capabilities. 369 */ 370 if (!ar9280FillCapabilityInfo(ah)) { 371 ecode = HAL_EEREAD; 372 goto bad; 373 } 374 375 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 376 if (ecode != HAL_OK) { 377 HALDEBUG(ah, HAL_DEBUG_ANY, 378 "%s: error getting mac address from EEPROM\n", __func__); 379 goto bad; 380 } 381 /* XXX How about the serial number ? */ 382 /* Read Reg Domain */ 383 AH_PRIVATE(ah)->ah_currentRD = 384 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 385 AH_PRIVATE(ah)->ah_currentRDext = 386 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 387 388 /* 389 * ah_miscMode is populated by ar5416FillCapabilityInfo() 390 * starting from griffin. Set here to make sure that 391 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 392 * placed into hardware. 393 */ 394 if (ahp->ah_miscMode != 0) 395 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 396 397 ar9280AniSetup(ah); /* Anti Noise Immunity */ 398 399 /* Setup noise floor min/max/nominal values */ 400 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 401 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 402 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 403 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 404 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 405 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 406 407 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 408 409 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 410 411 return ah; 412 bad: 413 if (ah != AH_NULL) 414 ah->ah_detach(ah); 415 if (status) 416 *status = ecode; 417 return AH_NULL; 418 } 419 420 static void 421 ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 422 { 423 uint32_t val; 424 425 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 426 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 427 OS_DELAY(1000); 428 } 429 430 431 /* 432 * Set PCIe workaround bits 433 * 434 * NOTE: 435 * 436 * In Merlin and Kite, bit 14 in WA register (disable L1) should only 437 * be set when device enters D3 and be cleared when device comes back 438 * to D0. 439 */ 440 if (power_off) { /* Power-off */ 441 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 442 443 val = OS_REG_READ(ah, AR_WA); 444 445 /* 446 * Disable bit 6 and 7 before entering D3 to prevent 447 * system hang. 448 */ 449 val &= ~(AR_WA_BIT6 | AR_WA_BIT7); 450 451 /* 452 * XXX Not sure, is specified in the reference HAL. 453 */ 454 val |= AR_WA_BIT22; 455 456 /* 457 * See above: set AR_WA_D3_L1_DISABLE when entering D3 state. 458 * 459 * XXX The reference HAL does it this way - it only sets 460 * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT, 461 * which it (currently) isn't. So the following statement 462 * is currently a NOP. 463 */ 464 if (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE) 465 val |= AR_WA_D3_L1_DISABLE; 466 467 OS_REG_WRITE(ah, AR_WA, val); 468 } else { /* Power-on */ 469 val = AR9280_WA_DEFAULT; 470 471 /* 472 * See note above: make sure L1_DISABLE is not set. 473 */ 474 val &= (~AR_WA_D3_L1_DISABLE); 475 OS_REG_WRITE(ah, AR_WA, val); 476 477 /* set bit 19 to allow forcing of pcie core into L1 state */ 478 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 479 } 480 } 481 482 static void 483 ar9280DisablePCIE(struct ath_hal *ah) 484 { 485 } 486 487 static void 488 ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 489 { 490 u_int modesIndex, freqIndex; 491 int regWrites = 0; 492 int i; 493 const HAL_INI_ARRAY *ia; 494 495 /* Setup the indices for the next set of register array writes */ 496 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 497 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 498 freqIndex = 2; 499 if (IEEE80211_IS_CHAN_HT40(chan)) 500 modesIndex = 3; 501 else if (IEEE80211_IS_CHAN_108G(chan)) 502 modesIndex = 5; 503 else 504 modesIndex = 4; 505 } else { 506 freqIndex = 1; 507 if (IEEE80211_IS_CHAN_HT40(chan) || 508 IEEE80211_IS_CHAN_TURBO(chan)) 509 modesIndex = 2; 510 else 511 modesIndex = 1; 512 } 513 514 /* Set correct Baseband to analog shift setting to access analog chips. */ 515 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 516 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 517 518 /* 519 * This is unwound because at the moment, there's a requirement 520 * for Merlin (and later, perhaps) to have a specific bit fixed 521 * in the AR_AN_TOP2 register before writing it. 522 */ 523 ia = &AH5212(ah)->ah_ini_modes; 524 #if 0 525 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 526 modesIndex, regWrites); 527 #endif 528 HALASSERT(modesIndex < ia->cols); 529 for (i = 0; i < ia->rows; i++) { 530 uint32_t reg = HAL_INI_VAL(ia, i, 0); 531 uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 532 533 if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 534 val &= ~AR_AN_TOP2_PWDCLKIND; 535 536 OS_REG_WRITE(ah, reg, val); 537 538 /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 539 if (reg >= 0x7800 && reg < 0x7900) 540 OS_DELAY(100); 541 542 DMA_YIELD(regWrites); 543 } 544 545 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 546 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 547 modesIndex, regWrites); 548 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 549 modesIndex, regWrites); 550 } 551 /* XXX Merlin 100us delay for shift registers */ 552 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 553 1, regWrites); 554 555 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 556 /* 5GHz channels w/ Fast Clock use different modal values */ 557 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 558 modesIndex, regWrites); 559 } 560 } 561 562 #define AR_BASE_FREQ_2GHZ 2300 563 #define AR_BASE_FREQ_5GHZ 4900 564 #define AR_SPUR_FEEQ_BOUND_HT40 19 565 #define AR_SPUR_FEEQ_BOUND_HT20 10 566 567 void 568 ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 569 { 570 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 571 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 572 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 573 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 574 static int inc[4] = { 0, 100, 0, 0 }; 575 576 int bb_spur = AR_NO_SPUR; 577 int freq; 578 int bin, cur_bin; 579 int bb_spur_off, spur_subchannel_sd; 580 int spur_freq_sd; 581 int spur_delta_phase; 582 int denominator; 583 int upper, lower, cur_vit_mask; 584 int tmp, newVal; 585 int i; 586 CHAN_CENTERS centers; 587 588 int8_t mask_m[123]; 589 int8_t mask_p[123]; 590 int8_t mask_amt; 591 int tmp_mask; 592 int cur_bb_spur; 593 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 594 595 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 596 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 597 598 ar5416GetChannelCenters(ah, chan, ¢ers); 599 freq = centers.synth_center; 600 601 /* 602 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 603 * otherwise spur is out-of-band and can be ignored. 604 */ 605 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 606 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 607 /* Get actual spur freq in MHz from EEPROM read value */ 608 if (is2GHz) { 609 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 610 } else { 611 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 612 } 613 614 if (AR_NO_SPUR == cur_bb_spur) 615 break; 616 cur_bb_spur = cur_bb_spur - freq; 617 618 if (IEEE80211_IS_CHAN_HT40(chan)) { 619 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 620 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 621 bb_spur = cur_bb_spur; 622 break; 623 } 624 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 625 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 626 bb_spur = cur_bb_spur; 627 break; 628 } 629 } 630 631 if (AR_NO_SPUR == bb_spur) { 632 #if 1 633 /* 634 * MRC CCK can interfere with beacon detection and cause deaf/mute. 635 * Disable MRC CCK for now. 636 */ 637 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 638 #else 639 /* Enable MRC CCK if no spur is found in this channel. */ 640 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 641 #endif 642 return; 643 } else { 644 /* 645 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 646 * is found in this channel. 647 */ 648 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 649 } 650 651 bin = bb_spur * 320; 652 653 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 654 655 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 656 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 657 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 658 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 659 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 660 661 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 662 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 663 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 664 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 665 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 666 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 667 668 /* Pick control or extn channel to cancel the spur */ 669 if (IEEE80211_IS_CHAN_HT40(chan)) { 670 if (bb_spur < 0) { 671 spur_subchannel_sd = 1; 672 bb_spur_off = bb_spur + 10; 673 } else { 674 spur_subchannel_sd = 0; 675 bb_spur_off = bb_spur - 10; 676 } 677 } else { 678 spur_subchannel_sd = 0; 679 bb_spur_off = bb_spur; 680 } 681 682 /* 683 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 684 * /80 for dyn2040. 685 */ 686 if (IEEE80211_IS_CHAN_HT40(chan)) 687 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 688 else 689 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 690 691 /* 692 * in 11A mode the denominator of spur_freq_sd should be 40 and 693 * it should be 44 in 11G 694 */ 695 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 696 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 697 698 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 699 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 700 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 701 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 702 703 /* Choose to cancel between control and extension channels */ 704 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 705 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 706 707 /* 708 * ============================================ 709 * Set Pilot and Channel Masks 710 * 711 * pilot mask 1 [31:0] = +6..-26, no 0 bin 712 * pilot mask 2 [19:0] = +26..+7 713 * 714 * channel mask 1 [31:0] = +6..-26, no 0 bin 715 * channel mask 2 [19:0] = +26..+7 716 */ 717 cur_bin = -6000; 718 upper = bin + 100; 719 lower = bin - 100; 720 721 for (i = 0; i < 4; i++) { 722 int pilot_mask = 0; 723 int chan_mask = 0; 724 int bp = 0; 725 for (bp = 0; bp < 30; bp++) { 726 if ((cur_bin > lower) && (cur_bin < upper)) { 727 pilot_mask = pilot_mask | 0x1 << bp; 728 chan_mask = chan_mask | 0x1 << bp; 729 } 730 cur_bin += 100; 731 } 732 cur_bin += inc[i]; 733 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 734 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 735 } 736 737 /* ================================================= 738 * viterbi mask 1 based on channel magnitude 739 * four levels 0-3 740 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 741 * [1 2 2 1] for -9.6 or [1 2 1] for +16 742 * - enable_mask_ppm, all bins move with freq 743 * 744 * - mask_select, 8 bits for rates (reg 67,0x990c) 745 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 746 * choose which mask to use mask or mask2 747 */ 748 749 /* 750 * viterbi mask 2 2nd set for per data rate puncturing 751 * four levels 0-3 752 * - mask_select, 8 bits for rates (reg 67) 753 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 754 * [1 2 2 1] for -9.6 or [1 2 1] for +16 755 */ 756 cur_vit_mask = 6100; 757 upper = bin + 120; 758 lower = bin - 120; 759 760 for (i = 0; i < 123; i++) { 761 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 762 if ((abs(cur_vit_mask - bin)) < 75) { 763 mask_amt = 1; 764 } else { 765 mask_amt = 0; 766 } 767 if (cur_vit_mask < 0) { 768 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 769 } else { 770 mask_p[cur_vit_mask / 100] = mask_amt; 771 } 772 } 773 cur_vit_mask -= 100; 774 } 775 776 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 777 | (mask_m[48] << 26) | (mask_m[49] << 24) 778 | (mask_m[50] << 22) | (mask_m[51] << 20) 779 | (mask_m[52] << 18) | (mask_m[53] << 16) 780 | (mask_m[54] << 14) | (mask_m[55] << 12) 781 | (mask_m[56] << 10) | (mask_m[57] << 8) 782 | (mask_m[58] << 6) | (mask_m[59] << 4) 783 | (mask_m[60] << 2) | (mask_m[61] << 0); 784 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 785 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 786 787 tmp_mask = (mask_m[31] << 28) 788 | (mask_m[32] << 26) | (mask_m[33] << 24) 789 | (mask_m[34] << 22) | (mask_m[35] << 20) 790 | (mask_m[36] << 18) | (mask_m[37] << 16) 791 | (mask_m[48] << 14) | (mask_m[39] << 12) 792 | (mask_m[40] << 10) | (mask_m[41] << 8) 793 | (mask_m[42] << 6) | (mask_m[43] << 4) 794 | (mask_m[44] << 2) | (mask_m[45] << 0); 795 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 796 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 797 798 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 799 | (mask_m[18] << 26) | (mask_m[18] << 24) 800 | (mask_m[20] << 22) | (mask_m[20] << 20) 801 | (mask_m[22] << 18) | (mask_m[22] << 16) 802 | (mask_m[24] << 14) | (mask_m[24] << 12) 803 | (mask_m[25] << 10) | (mask_m[26] << 8) 804 | (mask_m[27] << 6) | (mask_m[28] << 4) 805 | (mask_m[29] << 2) | (mask_m[30] << 0); 806 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 807 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 808 809 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 810 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 811 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 812 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 813 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 814 | (mask_m[10] << 10) | (mask_m[11] << 8) 815 | (mask_m[12] << 6) | (mask_m[13] << 4) 816 | (mask_m[14] << 2) | (mask_m[15] << 0); 817 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 818 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 819 820 tmp_mask = (mask_p[15] << 28) 821 | (mask_p[14] << 26) | (mask_p[13] << 24) 822 | (mask_p[12] << 22) | (mask_p[11] << 20) 823 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 824 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 825 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 826 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 827 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 828 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 829 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 830 831 tmp_mask = (mask_p[30] << 28) 832 | (mask_p[29] << 26) | (mask_p[28] << 24) 833 | (mask_p[27] << 22) | (mask_p[26] << 20) 834 | (mask_p[25] << 18) | (mask_p[24] << 16) 835 | (mask_p[23] << 14) | (mask_p[22] << 12) 836 | (mask_p[21] << 10) | (mask_p[20] << 8) 837 | (mask_p[19] << 6) | (mask_p[18] << 4) 838 | (mask_p[17] << 2) | (mask_p[16] << 0); 839 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 840 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 841 842 tmp_mask = (mask_p[45] << 28) 843 | (mask_p[44] << 26) | (mask_p[43] << 24) 844 | (mask_p[42] << 22) | (mask_p[41] << 20) 845 | (mask_p[40] << 18) | (mask_p[39] << 16) 846 | (mask_p[38] << 14) | (mask_p[37] << 12) 847 | (mask_p[36] << 10) | (mask_p[35] << 8) 848 | (mask_p[34] << 6) | (mask_p[33] << 4) 849 | (mask_p[32] << 2) | (mask_p[31] << 0); 850 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 851 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 852 853 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 854 | (mask_p[59] << 26) | (mask_p[58] << 24) 855 | (mask_p[57] << 22) | (mask_p[56] << 20) 856 | (mask_p[55] << 18) | (mask_p[54] << 16) 857 | (mask_p[53] << 14) | (mask_p[52] << 12) 858 | (mask_p[51] << 10) | (mask_p[50] << 8) 859 | (mask_p[49] << 6) | (mask_p[48] << 4) 860 | (mask_p[47] << 2) | (mask_p[46] << 0); 861 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 862 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 863 } 864 865 /* 866 * Fill all software cached or static hardware state information. 867 * Return failure if capabilities are to come from EEPROM and 868 * cannot be read. 869 */ 870 static HAL_BOOL 871 ar9280FillCapabilityInfo(struct ath_hal *ah) 872 { 873 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 874 875 if (!ar5416FillCapabilityInfo(ah)) 876 return AH_FALSE; 877 pCap->halNumGpioPins = 10; 878 pCap->halWowSupport = AH_TRUE; 879 pCap->halWowMatchPatternExact = AH_TRUE; 880 #if 0 881 pCap->halWowMatchPatternDword = AH_TRUE; 882 #endif 883 pCap->halCSTSupport = AH_TRUE; 884 pCap->halRifsRxSupport = AH_TRUE; 885 pCap->halRifsTxSupport = AH_TRUE; 886 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 887 pCap->halExtChanDfsSupport = AH_TRUE; 888 pCap->halUseCombinedRadarRssi = AH_TRUE; 889 #if 0 890 /* XXX bluetooth */ 891 pCap->halBtCoexSupport = AH_TRUE; 892 #endif 893 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 894 pCap->hal4kbSplitTransSupport = AH_FALSE; 895 /* Disable this so Block-ACK works correctly */ 896 pCap->halHasRxSelfLinkedTail = AH_FALSE; 897 pCap->halMbssidAggrSupport = AH_TRUE; 898 pCap->hal4AddrAggrSupport = AH_TRUE; 899 900 if (AR_SREV_MERLIN_20(ah)) { 901 pCap->halPSPollBroken = AH_FALSE; 902 /* 903 * This just enables the support; it doesn't 904 * state 5ghz fast clock will always be used. 905 */ 906 pCap->halSupportsFastClock5GHz = AH_TRUE; 907 } 908 pCap->halRxStbcSupport = 1; 909 pCap->halTxStbcSupport = 1; 910 pCap->halEnhancedDfsSupport = AH_TRUE; 911 912 return AH_TRUE; 913 } 914 915 /* 916 * This has been disabled - having the HAL flip chainmasks on/off 917 * when attempting to implement 11n disrupts things. For now, just 918 * leave this flipped off and worry about implementing TX diversity 919 * for legacy and MCS0-7 when 11n is fully functioning. 920 */ 921 HAL_BOOL 922 ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 923 { 924 #define ANTENNA0_CHAINMASK 0x1 925 #define ANTENNA1_CHAINMASK 0x2 926 #if 0 927 struct ath_hal_5416 *ahp = AH5416(ah); 928 929 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 930 switch (settings) { 931 case HAL_ANT_FIXED_A: 932 /* Enable first antenna only */ 933 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 934 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 935 break; 936 case HAL_ANT_FIXED_B: 937 /* Enable second antenna only, after checking capability */ 938 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 939 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 940 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 941 break; 942 case HAL_ANT_VARIABLE: 943 /* Restore original chainmask settings */ 944 /* XXX */ 945 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 946 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 947 break; 948 } 949 950 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 951 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 952 953 #endif 954 return AH_TRUE; 955 #undef ANTENNA0_CHAINMASK 956 #undef ANTENNA1_CHAINMASK 957 } 958 959 static const char* 960 ar9280Probe(uint16_t vendorid, uint16_t devid) 961 { 962 if (vendorid == ATHEROS_VENDOR_ID) { 963 if (devid == AR9280_DEVID_PCI) 964 return "Atheros 9220"; 965 if (devid == AR9280_DEVID_PCIE) 966 return "Atheros 9280"; 967 } 968 return AH_NULL; 969 } 970 AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 971