1 /* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 /* 22 * NB: Merlin and later have a simpler RF backend. 23 */ 24 #include "ah.h" 25 #include "ah_internal.h" 26 27 #include "ah_eeprom_v14.h" 28 29 #include "ar9002/ar9280.h" 30 #include "ar5416/ar5416reg.h" 31 #include "ar5416/ar5416phy.h" 32 33 #define N(a) (sizeof(a)/sizeof(a[0])) 34 35 struct ar9280State { 36 RF_HAL_FUNCS base; /* public state, must be first */ 37 uint16_t pcdacTable[1]; /* XXX */ 38 }; 39 #define AR9280(ah) ((struct ar9280State *) AH5212(ah)->ah_rfHal) 40 41 static HAL_BOOL ar9280GetChannelMaxMinPower(struct ath_hal *, 42 const struct ieee80211_channel *, int16_t *maxPow,int16_t *minPow); 43 int16_t ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c); 44 45 static void 46 ar9280WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex, 47 int writes) 48 { 49 (void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain, 50 freqIndex, writes); 51 } 52 53 /* 54 * Take the MHz channel value and set the Channel value 55 * 56 * ASSUMES: Writes enabled to analog bus 57 * 58 * Actual Expression, 59 * 60 * For 2GHz channel, 61 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 62 * (freq_ref = 40MHz) 63 * 64 * For 5GHz channel, 65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) 66 * (freq_ref = 40MHz/(24>>amodeRefSel)) 67 * 68 * For 5GHz channels which are 5MHz spaced, 69 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 70 * (freq_ref = 40MHz) 71 */ 72 static HAL_BOOL 73 ar9280SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 74 { 75 uint16_t bMode, fracMode, aModeRefSel = 0; 76 uint32_t freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; 77 CHAN_CENTERS centers; 78 uint32_t refDivA = 24; 79 uint8_t frac_n_5g; 80 81 OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq); 82 83 ar5416GetChannelCenters(ah, chan, ¢ers); 84 freq = centers.synth_center; 85 86 reg32 = OS_REG_READ(ah, AR_PHY_SYNTH_CONTROL); 87 reg32 &= 0xc0000000; 88 89 if (ath_hal_eepromGet(ah, AR_EEP_FRAC_N_5G, &frac_n_5g) != HAL_OK) 90 frac_n_5g = 0; 91 92 if (freq < 4800) { /* 2 GHz, fractional mode */ 93 uint32_t txctl; 94 95 bMode = 1; 96 fracMode = 1; 97 aModeRefSel = 0; 98 channelSel = (freq * 0x10000)/15; 99 100 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL); 101 if (freq == 2484) { 102 /* Enable channel spreading for channel 14 */ 103 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 104 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 105 } else { 106 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 107 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN); 108 } 109 } else { 110 bMode = 0; 111 fracMode = 0; 112 113 switch (frac_n_5g) { 114 case 0: 115 if ((freq % 20) == 0) { 116 aModeRefSel = 3; 117 } else if ((freq % 10) == 0) { 118 aModeRefSel = 2; 119 } 120 if (aModeRefSel) break; 121 case 1: 122 default: 123 aModeRefSel = 0; 124 /* Enable 2G (fractional) mode for channels which are 5MHz spaced */ 125 fracMode = 1; 126 refDivA = 1; 127 channelSel = (freq * 0x8000)/15; 128 129 /* RefDivA setting */ 130 OS_A_REG_RMW_FIELD(ah, AR_AN_SYNTH9, 131 AR_AN_SYNTH9_REFDIVA, refDivA); 132 } 133 134 if (!fracMode) { 135 ndiv = (freq * (refDivA >> aModeRefSel))/60; 136 channelSel = ndiv & 0x1ff; 137 channelFrac = (ndiv & 0xfffffe00) * 2; 138 channelSel = (channelSel << 17) | channelFrac; 139 } 140 } 141 142 reg32 = reg32 | (bMode << 29) | (fracMode << 28) | 143 (aModeRefSel << 26) | (channelSel); 144 145 OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 146 147 AH_PRIVATE(ah)->ah_curchan = chan; 148 149 return AH_TRUE; 150 } 151 152 /* 153 * Return a reference to the requested RF Bank. 154 */ 155 static uint32_t * 156 ar9280GetRfBank(struct ath_hal *ah, int bank) 157 { 158 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n", 159 __func__, bank); 160 return AH_NULL; 161 } 162 163 /* 164 * Reads EEPROM header info from device structure and programs 165 * all rf registers 166 */ 167 static HAL_BOOL 168 ar9280SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan, 169 uint16_t modesIndex, uint16_t *rfXpdGain) 170 { 171 return AH_TRUE; /* nothing to do */ 172 } 173 174 /* 175 * Read the transmit power levels from the structures taken from EEPROM 176 * Interpolate read transmit power values for this channel 177 * Organize the transmit power values into a table for writing into the hardware 178 */ 179 180 static HAL_BOOL 181 ar9280SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax, 182 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 183 { 184 return AH_TRUE; 185 } 186 187 #if 0 188 static int16_t 189 ar9280GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data) 190 { 191 int i, minIndex; 192 int16_t minGain,minPwr,minPcdac,retVal; 193 194 /* Assume NUM_POINTS_XPD0 > 0 */ 195 minGain = data->pDataPerXPD[0].xpd_gain; 196 for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) { 197 if (data->pDataPerXPD[i].xpd_gain < minGain) { 198 minIndex = i; 199 minGain = data->pDataPerXPD[i].xpd_gain; 200 } 201 } 202 minPwr = data->pDataPerXPD[minIndex].pwr_t4[0]; 203 minPcdac = data->pDataPerXPD[minIndex].pcdac[0]; 204 for (i=1; i<NUM_POINTS_XPD0; i++) { 205 if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) { 206 minPwr = data->pDataPerXPD[minIndex].pwr_t4[i]; 207 minPcdac = data->pDataPerXPD[minIndex].pcdac[i]; 208 } 209 } 210 retVal = minPwr - (minPcdac*2); 211 return(retVal); 212 } 213 #endif 214 215 static HAL_BOOL 216 ar9280GetChannelMaxMinPower(struct ath_hal *ah, 217 const struct ieee80211_channel *chan, 218 int16_t *maxPow, int16_t *minPow) 219 { 220 #if 0 221 struct ath_hal_5212 *ahp = AH5212(ah); 222 int numChannels=0,i,last; 223 int totalD, totalF,totalMin; 224 EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL; 225 EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL; 226 227 *maxPow = 0; 228 if (IS_CHAN_A(chan)) { 229 powerArray = ahp->ah_modePowerArray5112; 230 data = powerArray[headerInfo11A].pDataPerChannel; 231 numChannels = powerArray[headerInfo11A].numChannels; 232 } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) { 233 /* XXX - is this correct? Should we also use the same power for turbo G? */ 234 powerArray = ahp->ah_modePowerArray5112; 235 data = powerArray[headerInfo11G].pDataPerChannel; 236 numChannels = powerArray[headerInfo11G].numChannels; 237 } else if (IS_CHAN_B(chan)) { 238 powerArray = ahp->ah_modePowerArray5112; 239 data = powerArray[headerInfo11B].pDataPerChannel; 240 numChannels = powerArray[headerInfo11B].numChannels; 241 } else { 242 return (AH_TRUE); 243 } 244 /* Make sure the channel is in the range of the TP values 245 * (freq piers) 246 */ 247 if ((numChannels < 1) || 248 (chan->channel < data[0].channelValue) || 249 (chan->channel > data[numChannels-1].channelValue)) 250 return(AH_FALSE); 251 252 /* Linearly interpolate the power value now */ 253 for (last=0,i=0; 254 (i<numChannels) && (chan->channel > data[i].channelValue); 255 last=i++); 256 totalD = data[i].channelValue - data[last].channelValue; 257 if (totalD > 0) { 258 totalF = data[i].maxPower_t4 - data[last].maxPower_t4; 259 *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD); 260 261 totalMin = ar9280GetMinPower(ah,&data[i]) - ar9280GetMinPower(ah, &data[last]); 262 *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar9280GetMinPower(ah, &data[last])*totalD)/totalD); 263 return (AH_TRUE); 264 } else { 265 if (chan->channel == data[i].channelValue) { 266 *maxPow = data[i].maxPower_t4; 267 *minPow = ar9280GetMinPower(ah, &data[i]); 268 return(AH_TRUE); 269 } else 270 return(AH_FALSE); 271 } 272 #else 273 *maxPow = *minPow = 0; 274 return AH_FALSE; 275 #endif 276 } 277 278 /* 279 * The ordering of nfarray is thus: 280 * 281 * nfarray[0]: Chain 0 ctl 282 * nfarray[1]: Chain 1 ctl 283 * nfarray[2]: Chain 2 ctl 284 * nfarray[3]: Chain 0 ext 285 * nfarray[4]: Chain 1 ext 286 * nfarray[5]: Chain 2 ext 287 */ 288 static void 289 ar9280GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[]) 290 { 291 int16_t nf; 292 293 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); 294 if (nf & 0x100) 295 nf = 0 - ((nf ^ 0x1ff) + 1); 296 HALDEBUG(ah, HAL_DEBUG_NFCAL, 297 "NF calibrated [ctl] [chain 0] is %d\n", nf); 298 nfarray[0] = nf; 299 300 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); 301 if (nf & 0x100) 302 nf = 0 - ((nf ^ 0x1ff) + 1); 303 HALDEBUG(ah, HAL_DEBUG_NFCAL, 304 "NF calibrated [ctl] [chain 1] is %d\n", nf); 305 nfarray[1] = nf; 306 307 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); 308 if (nf & 0x100) 309 nf = 0 - ((nf ^ 0x1ff) + 1); 310 HALDEBUG(ah, HAL_DEBUG_NFCAL, 311 "NF calibrated [ext] [chain 0] is %d\n", nf); 312 nfarray[3] = nf; 313 314 nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); 315 if (nf & 0x100) 316 nf = 0 - ((nf ^ 0x1ff) + 1); 317 HALDEBUG(ah, HAL_DEBUG_NFCAL, 318 "NF calibrated [ext] [chain 1] is %d\n", nf); 319 nfarray[4] = nf; 320 321 /* Chain 2 - invalid */ 322 nfarray[2] = 0; 323 nfarray[5] = 0; 324 325 } 326 327 /* 328 * Adjust NF based on statistical values for 5GHz frequencies. 329 * Stubbed:Not used by Fowl 330 */ 331 int16_t 332 ar9280GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 333 { 334 return 0; 335 } 336 337 /* 338 * Free memory for analog bank scratch buffers 339 */ 340 static void 341 ar9280RfDetach(struct ath_hal *ah) 342 { 343 struct ath_hal_5212 *ahp = AH5212(ah); 344 345 HALASSERT(ahp->ah_rfHal != AH_NULL); 346 ath_hal_free(ahp->ah_rfHal); 347 ahp->ah_rfHal = AH_NULL; 348 } 349 350 HAL_BOOL 351 ar9280RfAttach(struct ath_hal *ah, HAL_STATUS *status) 352 { 353 struct ath_hal_5212 *ahp = AH5212(ah); 354 struct ar9280State *priv; 355 356 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR9280 radio\n", __func__); 357 358 HALASSERT(ahp->ah_rfHal == AH_NULL); 359 priv = ath_hal_malloc(sizeof(struct ar9280State)); 360 if (priv == AH_NULL) { 361 HALDEBUG(ah, HAL_DEBUG_ANY, 362 "%s: cannot allocate private state\n", __func__); 363 *status = HAL_ENOMEM; /* XXX */ 364 return AH_FALSE; 365 } 366 priv->base.rfDetach = ar9280RfDetach; 367 priv->base.writeRegs = ar9280WriteRegs; 368 priv->base.getRfBank = ar9280GetRfBank; 369 priv->base.setChannel = ar9280SetChannel; 370 priv->base.setRfRegs = ar9280SetRfRegs; 371 priv->base.setPowerTable = ar9280SetPowerTable; 372 priv->base.getChannelMaxMinPower = ar9280GetChannelMaxMinPower; 373 priv->base.getNfAdjust = ar9280GetNfAdjust; 374 375 ahp->ah_pcdacTable = priv->pcdacTable; 376 ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable); 377 ahp->ah_rfHal = &priv->base; 378 /* 379 * Set noise floor adjust method; we arrange a 380 * direct call instead of thunking. 381 */ 382 AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust; 383 AH_PRIVATE(ah)->ah_getNoiseFloor = ar9280GetNoiseFloor; 384 385 return AH_TRUE; 386 } 387