1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #ifndef _DEV_ATH_AR5416REG_H 20 #define _DEV_ATH_AR5416REG_H 21 22 #include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23 24 /* 25 * Register added starting with the AR5416 26 */ 27 #define AR_MIRT 0x0020 /* interrupt rate threshold */ 28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30 #define AR_GTXTO 0x0064 /* global transmit timeout */ 31 #define AR_GTTM 0x0068 /* global transmit timeout mode */ 32 #define AR_CST 0x006C /* carrier sense timeout */ 33 #define AR_MAC_LED 0x1f04 /* LED control */ 34 #define AR_WA 0x4004 /* PCIE work-arounds */ 35 #define AR_PCIE_PM_CTRL 0x4014 36 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37 #define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38 #define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39 #define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40 #define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41 #define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42 #define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43 #define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 44 #define AR5416_PCIE_SERDES 0x4040 45 #define AR5416_PCIE_SERDES2 0x4044 46 #define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 47 #define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 48 #define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 49 #define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 50 #define AR_GPIO_INPUT_MUX1 0x4058 51 #define AR_GPIO_INPUT_MUX2 0x405c 52 #define AR_GPIO_OUTPUT_MUX1 0x4060 53 #define AR_GPIO_OUTPUT_MUX2 0x4064 54 #define AR_GPIO_OUTPUT_MUX3 0x4068 55 #define AR_EEPROM_STATUS_DATA 0x407c 56 #define AR_OBS 0x4080 57 #define AR_RTC_RC 0x7000 /* reset control */ 58 #define AR_RTC_PLL_CONTROL 0x7014 59 #define AR_RTC_RESET 0x7040 /* RTC reset register */ 60 #define AR_RTC_STATUS 0x7044 /* system sleep status */ 61 #define AR_RTC_SLEEP_CLK 0x7048 62 #define AR_RTC_FORCE_WAKE 0x704c /* control MAC force wake */ 63 #define AR_RTC_INTR_CAUSE 0x7050 /* RTC interrupt cause/clear */ 64 #define AR_RTC_INTR_ENABLE 0x7054 /* RTC interrupt enable */ 65 #define AR_RTC_INTR_MASK 0x7058 /* RTC interrupt mask */ 66 /* AR9280: rf long shift registers */ 67 #define AR_AN_RF2G1_CH0 0x7810 68 #define AR_AN_RF5G1_CH0 0x7818 69 #define AR_AN_RF2G1_CH1 0x7834 70 #define AR_AN_RF5G1_CH1 0x783C 71 #define AR_AN_TOP2 0x7894 72 #define AR_AN_SYNTH9 0x7868 73 #define AR9285_AN_RF2G1 0x7820 74 #define AR9285_AN_RF2G2 0x7824 75 #define AR9285_AN_RF2G3 0x7828 76 #define AR9285_AN_RF2G4 0x782C 77 #define AR9285_AN_RF2G6 0x7834 78 #define AR9285_AN_RF2G7 0x7838 79 #define AR9285_AN_RF2G8 0x783C 80 #define AR9285_AN_RF2G9 0x7840 81 #define AR9285_AN_RXTXBB1 0x7854 82 #define AR9285_AN_TOP2 0x7868 83 #define AR9285_AN_TOP3 0x786c 84 #define AR9285_AN_TOP4 0x7870 85 #define AR9285_AN_TOP4_DEFAULT 0x10142c00 86 87 #define AR_RESET_TSF 0x8020 88 #define AR_RXFIFO_CFG 0x8114 89 #define AR_PHY_ERR_1 0x812c 90 #define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 91 #define AR_PHY_ERR_2 0x8134 92 #define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 93 #define AR_TSFOOR_THRESHOLD 0x813c 94 #define AR_PHY_ERR_3 0x8168 95 #define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 96 #define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 97 #define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 98 #define AR_TXOP_4_7 0x81f4 99 #define AR_TXOP_8_11 0x81f8 100 #define AR_TXOP_12_15 0x81fc 101 /* generic timers based on tsf - all uS */ 102 #define AR_NEXT_TBTT 0x8200 103 #define AR_NEXT_DBA 0x8204 104 #define AR_NEXT_SWBA 0x8208 105 #define AR_NEXT_CFP 0x8208 106 #define AR_NEXT_HCF 0x820C 107 #define AR_NEXT_TIM 0x8210 108 #define AR_NEXT_DTIM 0x8214 109 #define AR_NEXT_QUIET 0x8218 110 #define AR_NEXT_NDP 0x821C 111 #define AR5416_BEACON_PERIOD 0x8220 112 #define AR_DBA_PERIOD 0x8224 113 #define AR_SWBA_PERIOD 0x8228 114 #define AR_HCF_PERIOD 0x822C 115 #define AR_TIM_PERIOD 0x8230 116 #define AR_DTIM_PERIOD 0x8234 117 #define AR_QUIET_PERIOD 0x8238 118 #define AR_NDP_PERIOD 0x823C 119 #define AR_TIMER_MODE 0x8240 120 #define AR_SLP32_MODE 0x8244 121 #define AR_SLP32_WAKE 0x8248 122 #define AR_SLP32_INC 0x824c 123 #define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 124 #define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 125 #define AR_SLP_MIB_CTRL 0x8258 126 #define AR_2040_MODE 0x8318 127 #define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 128 #define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 129 #define AR_PCU_TXBUF_CTRL 0x8340 130 131 /* DMA & PCI Registers in PCI space (usable during sleep)*/ 132 #define AR_RC_AHB 0x00000001 /* AHB reset */ 133 #define AR_RC_APB 0x00000002 /* APB reset */ 134 #define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 135 136 #define AR_MIRT_VAL 0x0000ffff /* in uS */ 137 #define AR_MIRT_VAL_S 16 138 139 #define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 140 #define AR_TIMT_LAST_S 0 141 #define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 142 #define AR_TIMT_FIRST_S 16 143 144 #define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 145 #define AR_RIMT_LAST_S 0 146 #define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 147 #define AR_RIMT_FIRST_S 16 148 149 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 150 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 151 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 152 153 #define AR_GTTM_USEC 0x00000001 // usec strobe 154 #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 155 #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 156 #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 157 158 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 159 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 160 #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 161 162 /* MAC tx DMA size config */ 163 #define AR_TXCFG_DMASZ_MASK 0x00000003 164 #define AR_TXCFG_DMASZ_4B 0 165 #define AR_TXCFG_DMASZ_8B 1 166 #define AR_TXCFG_DMASZ_16B 2 167 #define AR_TXCFG_DMASZ_32B 3 168 #define AR_TXCFG_DMASZ_64B 4 169 #define AR_TXCFG_DMASZ_128B 5 170 #define AR_TXCFG_DMASZ_256B 6 171 #define AR_TXCFG_DMASZ_512B 7 172 #define AR_TXCFG_ATIM_TXPOLICY 0x00000800 173 174 /* MAC rx DMA size config */ 175 #define AR_RXCFG_DMASZ_MASK 0x00000007 176 #define AR_RXCFG_DMASZ_4B 0 177 #define AR_RXCFG_DMASZ_8B 1 178 #define AR_RXCFG_DMASZ_16B 2 179 #define AR_RXCFG_DMASZ_32B 3 180 #define AR_RXCFG_DMASZ_64B 4 181 #define AR_RXCFG_DMASZ_128B 5 182 #define AR_RXCFG_DMASZ_256B 6 183 #define AR_RXCFG_DMASZ_512B 7 184 185 /* MAC Led registers */ 186 #define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 187 #define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 188 #define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 189 #define AR_MAC_LED_MODE_S 7 190 #define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 191 #define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 192 #define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 193 #define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 194 #define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 195 #define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 196 #define AR_MAC_LED_ASSOC 0x00000c00 197 #define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 198 #define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 199 #define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 200 #define AR_MAC_LED_ASSOC_S 10 201 202 #define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 203 #define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 204 #define AR_WA_ANALOG_SHIFT 0x00100000 205 #define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 206 207 #define AR_WA_DEFAULT 0x0000073f 208 #define AR9280_WA_DEFAULT 0x0040073f 209 #define AR9285_WA_DEFAULT 0x004a05cb 210 211 #define AR_PCIE_PM_CTRL_ENA 0x00080000 212 213 #define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 214 #define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 215 #define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 216 #define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 217 #define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 218 #define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 219 #define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 220 #define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 221 222 /* MAC PCU Registers */ 223 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 224 225 /* Extended PCU DIAG_SW control fields */ 226 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 227 #define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 228 #define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 229 #define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 230 #define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 231 #define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 232 233 #define AR_TXOP_X_VAL 0x000000FF 234 235 #define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 236 237 /* Interrupts */ 238 #define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 239 #define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 240 #define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 241 #define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 242 243 #define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 244 #define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 245 #define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 246 247 #define AR_INTR_SPURIOUS 0xffffffff 248 #define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 249 #define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 250 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 251 #define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 252 #define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 253 254 /* Interrupt Mask Registers */ 255 #define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 256 #define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 257 #define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 258 #define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 259 260 #define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 261 #define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 262 263 /* synchronous interrupt signals */ 264 #define AR_INTR_SYNC_RTC_IRQ 0x00000001 265 #define AR_INTR_SYNC_MAC_IRQ 0x00000002 266 #define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 267 #define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 268 #define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 269 #define AR_INTR_SYNC_HOST1_FATAL 0x00000020 270 #define AR_INTR_SYNC_HOST1_PERR 0x00000040 271 #define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 272 #define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 273 #define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 274 #define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 275 #define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 276 #define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 277 #define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 278 #define AR_INTR_SYNC_PM_ACCESS 0x00004000 279 #define AR_INTR_SYNC_MAC_AWAKE 0x00008000 280 #define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 281 #define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 282 #define AR_INTR_SYNC_ALL 0x0003FFFF 283 284 /* default synchronous interrupt signals enabled */ 285 #define AR_INTR_SYNC_DEFAULT \ 286 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 287 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 288 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 289 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 290 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 291 292 #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 293 #define AR_INTR_SYNC_MASK_GPIO_S 18 294 295 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 296 #define AR_INTR_SYNC_ENABLE_GPIO_S 18 297 298 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 299 #define AR_INTR_ASYNC_MASK_GPIO_S 18 300 301 #define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 302 #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 303 304 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 305 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 306 307 /* RTC registers */ 308 #define AR_RTC_RC_M 0x00000003 309 #define AR_RTC_RC_MAC_WARM 0x00000001 310 #define AR_RTC_RC_MAC_COLD 0x00000002 311 #define AR_RTC_PLL_DIV 0x0000001f 312 #define AR_RTC_PLL_DIV_S 0 313 #define AR_RTC_PLL_DIV2 0x00000020 314 #define AR_RTC_PLL_REFDIV_5 0x000000c0 315 316 #define AR_RTC_SOWL_PLL_DIV 0x000003ff 317 #define AR_RTC_SOWL_PLL_DIV_S 0 318 #define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 319 #define AR_RTC_SOWL_PLL_REFDIV_S 10 320 #define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 321 #define AR_RTC_SOWL_PLL_CLKSEL_S 14 322 323 #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 324 325 #define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 326 #define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 327 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 328 #define AR_RTC_STATUS_ON 0x00000002 329 #define AR_RTC_STATUS_SLEEP 0x00000004 330 #define AR_RTC_STATUS_WAKEUP 0x00000008 331 #define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 332 #define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 333 334 #define AR_RTC_SLEEP_DERIVED_CLK 0x2 335 336 #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 337 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 338 339 #define AR_RTC_PLL_CLKSEL 0x00000300 340 #define AR_RTC_PLL_CLKSEL_S 8 341 342 /* AR9280: rf long shift registers */ 343 #define AR_AN_RF2G1_CH0_OB 0x03800000 344 #define AR_AN_RF2G1_CH0_OB_S 23 345 #define AR_AN_RF2G1_CH0_DB 0x1C000000 346 #define AR_AN_RF2G1_CH0_DB_S 26 347 348 #define AR_AN_RF5G1_CH0_OB5 0x00070000 349 #define AR_AN_RF5G1_CH0_OB5_S 16 350 #define AR_AN_RF5G1_CH0_DB5 0x00380000 351 #define AR_AN_RF5G1_CH0_DB5_S 19 352 353 #define AR_AN_RF2G1_CH1_OB 0x03800000 354 #define AR_AN_RF2G1_CH1_OB_S 23 355 #define AR_AN_RF2G1_CH1_DB 0x1C000000 356 #define AR_AN_RF2G1_CH1_DB_S 26 357 358 #define AR_AN_RF5G1_CH1_OB5 0x00070000 359 #define AR_AN_RF5G1_CH1_OB5_S 16 360 #define AR_AN_RF5G1_CH1_DB5 0x00380000 361 #define AR_AN_RF5G1_CH1_DB5_S 19 362 363 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 364 #define AR_AN_TOP2_XPABIAS_LVL_S 30 365 #define AR_AN_TOP2_LOCALBIAS 0x00200000 366 #define AR_AN_TOP2_LOCALBIAS_S 21 367 #define AR_AN_TOP2_PWDCLKIND 0x00400000 368 #define AR_AN_TOP2_PWDCLKIND_S 22 369 370 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 371 #define AR_AN_SYNTH9_REFDIVA_S 27 372 373 /* AR9285 Analog registers */ 374 #define AR9285_AN_RF2G1_ENPACAL 0x00000800 375 #define AR9285_AN_RF2G1_ENPACAL_S 11 376 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000 377 #define AR9285_AN_RF2G1_PDPADRV1_S 25 378 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000 379 #define AR9285_AN_RF2G1_PDPADRV2_S 24 380 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000 381 #define AR9285_AN_RF2G1_PDPAOUT_S 23 382 383 #define AR9285_AN_RF2G2_OFFCAL 0x00001000 384 #define AR9285_AN_RF2G2_OFFCAL_S 12 385 386 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 387 #define AR9285_AN_RF2G3_PDVCCOMP_S 25 388 #define AR9285_AN_RF2G3_OB_0 0x00E00000 389 #define AR9285_AN_RF2G3_OB_0_S 21 390 #define AR9285_AN_RF2G3_OB_1 0x001C0000 391 #define AR9285_AN_RF2G3_OB_1_S 18 392 #define AR9285_AN_RF2G3_OB_2 0x00038000 393 #define AR9285_AN_RF2G3_OB_2_S 15 394 #define AR9285_AN_RF2G3_OB_3 0x00007000 395 #define AR9285_AN_RF2G3_OB_3_S 12 396 #define AR9285_AN_RF2G3_OB_4 0x00000E00 397 #define AR9285_AN_RF2G3_OB_4_S 9 398 399 #define AR9285_AN_RF2G3_DB1_0 0x000001C0 400 #define AR9285_AN_RF2G3_DB1_0_S 6 401 #define AR9285_AN_RF2G3_DB1_1 0x00000038 402 #define AR9285_AN_RF2G3_DB1_1_S 3 403 #define AR9285_AN_RF2G3_DB1_2 0x00000007 404 #define AR9285_AN_RF2G3_DB1_2_S 0 405 406 #define AR9285_AN_RF2G4_DB1_3 0xE0000000 407 #define AR9285_AN_RF2G4_DB1_3_S 29 408 #define AR9285_AN_RF2G4_DB1_4 0x1C000000 409 #define AR9285_AN_RF2G4_DB1_4_S 26 410 411 #define AR9285_AN_RF2G4_DB2_0 0x03800000 412 #define AR9285_AN_RF2G4_DB2_0_S 23 413 #define AR9285_AN_RF2G4_DB2_1 0x00700000 414 #define AR9285_AN_RF2G4_DB2_1_S 20 415 #define AR9285_AN_RF2G4_DB2_2 0x000E0000 416 #define AR9285_AN_RF2G4_DB2_2_S 17 417 #define AR9285_AN_RF2G4_DB2_3 0x0001C000 418 #define AR9285_AN_RF2G4_DB2_3_S 14 419 #define AR9285_AN_RF2G4_DB2_4 0x00003800 420 #define AR9285_AN_RF2G4_DB2_4_S 11 421 422 #define AR9285_AN_RF2G6_CCOMP 0x00007800 423 #define AR9285_AN_RF2G6_CCOMP_S 11 424 #define AR9285_AN_RF2G6_OFFS 0x03f00000 425 #define AR9285_AN_RF2G6_OFFS_S 20 426 427 #define AR9271_AN_RF2G6_OFFS 0x07f00000 428 #define AR9271_AN_RF2G6_OFFS_S 20 429 430 #define AR9285_AN_RF2G7_PWDDB 0x00000002 431 #define AR9285_AN_RF2G7_PWDDB_S 1 432 #define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 433 #define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 434 435 #define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 436 #define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 437 438 #define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 439 #define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 440 #define AR9285_AN_RXTXBB1_PDV2I 0x00000080 441 #define AR9285_AN_RXTXBB1_PDV2I_S 7 442 #define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 443 #define AR9285_AN_RXTXBB1_PDDACIF_S 8 444 #define AR9285_AN_RXTXBB1_SPARE9 0x00000001 445 #define AR9285_AN_RXTXBB1_SPARE9_S 0 446 447 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 448 #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 449 #define AR9285_AN_TOP3_PWDDAC 0x00800000 450 #define AR9285_AN_TOP3_PWDDAC_S 23 451 452 /* Sleep control */ 453 #define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 454 #define AR5416_SLEEP1_CAB_TIMEOUT_S 22 455 456 #define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 457 #define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 458 459 /* Sleep Registers */ 460 #define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 461 #define AR_SLP32_ENA 0x00100000 462 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 463 464 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 465 466 #define AR_SLP32_TST_INC 0x000FFFFF 467 468 #define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 469 #define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 470 471 #define AR_TIMER_MODE_TBTT 0x00000001 472 #define AR_TIMER_MODE_DBA 0x00000002 473 #define AR_TIMER_MODE_SWBA 0x00000004 474 #define AR_TIMER_MODE_HCF 0x00000008 475 #define AR_TIMER_MODE_TIM 0x00000010 476 #define AR_TIMER_MODE_DTIM 0x00000020 477 #define AR_TIMER_MODE_QUIET 0x00000040 478 #define AR_TIMER_MODE_NDP 0x00000080 479 #define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 480 #define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 481 #define AR_TIMER_MODE_THRESH 0xFFFFF000 482 #define AR_TIMER_MODE_THRESH_S 12 483 484 /* PCU Misc modes */ 485 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 486 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 487 #define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 488 #define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 489 #define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 490 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 491 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 492 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 493 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 494 #define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 495 #define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 496 #define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 497 498 /* GPIO Interrupt */ 499 #define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 500 #define AR_INTR_GPIO_S 20 501 502 #define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 503 #define AR_GPIO_OUT_VAL 0x000FFC00 504 #define AR_GPIO_OUT_VAL_S 10 505 #define AR_GPIO_INTR_CTRL 0x3FF00000 506 #define AR_GPIO_INTR_CTRL_S 20 507 508 #define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 509 #define AR_GPIO_IN_VAL_S 14 510 #define AR928X_GPIO_IN_VAL 0x000FFC00 511 #define AR928X_GPIO_IN_VAL_S 10 512 #define AR9285_GPIO_IN_VAL 0x00FFF000 513 #define AR9285_GPIO_IN_VAL_S 12 514 515 #define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 516 #define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 517 #define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 518 #define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 519 #define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 520 521 #define AR_GPIO_INTR_POL_VAL 0x1FFF 522 #define AR_GPIO_INTR_POL_VAL_S 0 523 524 #define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 525 526 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 527 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 528 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 529 530 /* Eeprom defines */ 531 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 532 #define AR_EEPROM_STATUS_DATA_VAL_S 0 533 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 534 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 535 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 536 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 537 538 #define AR_SREV_REVISION_OWL_10 0x08 539 #define AR_SREV_REVISION_OWL_20 0x09 540 #define AR_SREV_REVISION_OWL_22 0x0a 541 542 #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 543 #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 544 #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 545 #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 546 547 /* Test macro for owl 1.0 */ 548 #define IS_5416V1(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10) 549 #define IS_5416V2(_ah) ((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20) 550 #define IS_5416V2_2(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22) 551 552 /* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 553 #define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 554 #define AR_XSREV_ID_S 0 555 #define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 556 #define AR_XSREV_VERSION_S 18 557 #define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 558 #define AR_XSREV_TYPE_S 12 559 #define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 560 * 0:2 chains) */ 561 #define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 562 #define AR_XSREV_REVISION 0x00000F00 563 #define AR_XSREV_REVISION_S 8 564 565 #define AR_XSREV_VERSION_OWL_PCI 0x0D 566 #define AR_XSREV_VERSION_OWL_PCIE 0x0C 567 #define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 568 #define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 569 #define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 570 #define AR_XSREV_VERSION_SOWL 0x40 571 #define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 572 #define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 573 #define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 574 #define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 575 #define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 576 #define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 577 #define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 578 #define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 579 #define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 580 #define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 581 582 #define AR_SREV_OWL_20_OR_LATER(_ah) \ 583 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \ 584 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20) 585 #define AR_SREV_OWL_22_OR_LATER(_ah) \ 586 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \ 587 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22) 588 589 #define AR_SREV_SOWL(_ah) \ 590 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 591 #define AR_SREV_SOWL_10_OR_LATER(_ah) \ 592 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 593 #define AR_SREV_SOWL_11(_ah) \ 594 (AR_SREV_SOWL(_ah) && \ 595 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 596 597 #define AR_SREV_MERLIN(_ah) \ 598 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 599 #define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 600 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 601 #define AR_SREV_MERLIN_20(_ah) \ 602 (AR_SREV_MERLIN(_ah) && \ 603 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_MERLIN_20) 604 #define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 605 (AR_SREV_MERLIN_20(_ah) || \ 606 AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) 607 608 #define AR_SREV_KITE(_ah) \ 609 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 610 #define AR_SREV_KITE_10_OR_LATER(_ah) \ 611 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 612 #define AR_SREV_KITE_11(_ah) \ 613 (AR_SREV_KITE(ah) && \ 614 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 615 #define AR_SREV_KITE_11_OR_LATER(_ah) \ 616 (AR_SREV_KITE_11(_ah) || \ 617 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11) 618 #define AR_SREV_KITE_12(_ah) \ 619 (AR_SREV_KITE(ah) && \ 620 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 621 #define AR_SREV_KITE_12_OR_LATER(_ah) \ 622 (AR_SREV_KITE_12(_ah) || \ 623 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12) 624 #endif /* _DEV_ATH_AR5416REG_H */ 625