1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_desc.h" 25 #include "ah_internal.h" 26 27 #include "ar5416/ar5416.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 #include "ar5416/ar5416desc.h" 31 32 /* 33 * Stop transmit on the specified queue 34 */ 35 HAL_BOOL 36 ar5416StopTxDma(struct ath_hal *ah, u_int q) 37 { 38 #define STOP_DMA_TIMEOUT 4000 /* us */ 39 #define STOP_DMA_ITER 100 /* us */ 40 u_int i; 41 42 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 43 44 HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 45 46 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); 47 for (i = STOP_DMA_TIMEOUT/STOP_DMA_ITER; i != 0; i--) { 48 if (ar5212NumTxPending(ah, q) == 0) 49 break; 50 OS_DELAY(STOP_DMA_ITER); 51 } 52 #ifdef AH_DEBUG 53 if (i == 0) { 54 HALDEBUG(ah, HAL_DEBUG_ANY, 55 "%s: queue %u DMA did not stop in 400 msec\n", __func__, q); 56 HALDEBUG(ah, HAL_DEBUG_ANY, 57 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", __func__, 58 OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE), 59 OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q))); 60 HALDEBUG(ah, HAL_DEBUG_ANY, 61 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", 62 __func__, OS_REG_READ(ah, AR_QMISC(q)), 63 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), 64 OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); 65 } 66 #endif /* AH_DEBUG */ 67 68 /* ar5416 and up can kill packets at the PCU level */ 69 if (ar5212NumTxPending(ah, q)) { 70 uint32_t j; 71 72 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, 73 "%s: Num of pending TX Frames %d on Q %d\n", 74 __func__, ar5212NumTxPending(ah, q), q); 75 76 /* Kill last PCU Tx Frame */ 77 /* TODO - save off and restore current values of Q1/Q2? */ 78 for (j = 0; j < 2; j++) { 79 uint32_t tsfLow = OS_REG_READ(ah, AR_TSF_L32); 80 OS_REG_WRITE(ah, AR_QUIET2, 81 SM(10, AR_QUIET2_QUIET_DUR)); 82 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); 83 OS_REG_WRITE(ah, AR_NEXT_QUIET, tsfLow >> 10); 84 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 85 86 if ((OS_REG_READ(ah, AR_TSF_L32)>>10) == (tsfLow>>10)) 87 break; 88 89 HALDEBUG(ah, HAL_DEBUG_ANY, 90 "%s: TSF moved while trying to set quiet time " 91 "TSF: 0x%08x\n", __func__, tsfLow); 92 HALASSERT(j < 1); /* TSF shouldn't count twice or reg access is taking forever */ 93 } 94 95 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE); 96 97 /* Allow the quiet mechanism to do its work */ 98 OS_DELAY(200); 99 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 100 101 /* Verify the transmit q is empty */ 102 for (i = STOP_DMA_TIMEOUT/STOP_DMA_ITER; i != 0; i--) { 103 if (ar5212NumTxPending(ah, q) == 0) 104 break; 105 OS_DELAY(STOP_DMA_ITER); 106 } 107 if (i == 0) { 108 HALDEBUG(ah, HAL_DEBUG_ANY, 109 "%s: Failed to stop Tx DMA in %d msec after killing" 110 " last frame\n", __func__, STOP_DMA_TIMEOUT / 1000); 111 } 112 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE); 113 } 114 115 OS_REG_WRITE(ah, AR_Q_TXD, 0); 116 return (i != 0); 117 #undef STOP_DMA_ITER 118 #undef STOP_DMA_TIMEOUT 119 } 120 121 #define VALID_KEY_TYPES \ 122 ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\ 123 (1 << HAL_KEY_TYPE_AES) | (1 << HAL_KEY_TYPE_TKIP)) 124 #define isValidKeyType(_t) ((1 << (_t)) & VALID_KEY_TYPES) 125 126 #define set11nTries(_series, _index) \ 127 (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) 128 129 #define set11nRate(_series, _index) \ 130 (SM((_series)[_index].Rate, AR_XmitRate##_index)) 131 132 #define set11nPktDurRTSCTS(_series, _index) \ 133 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\ 134 ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\ 135 AR_RTSCTSQual##_index : 0)) 136 137 #define set11nRateFlags(_series, _index) \ 138 ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \ 139 |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_GI##_index : 0) \ 140 |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_STBC##_index : 0) \ 141 |SM((_series)[_index].ChSel, AR_ChainSel##_index) 142 143 /* 144 * Descriptor Access Functions 145 */ 146 147 #define VALID_PKT_TYPES \ 148 ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\ 149 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\ 150 (1<<HAL_PKT_TYPE_BEACON)|(1<<HAL_PKT_TYPE_AMPDU)) 151 #define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES) 152 #define VALID_TX_RATES \ 153 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\ 154 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\ 155 (1<<0x1d)|(1<<0x18)|(1<<0x1c)|(1<<0x01)|(1<<0x02)|(1<<0x03)|\ 156 (1<<0x04)|(1<<0x05)|(1<<0x06)|(1<<0x07)|(1<<0x00)) 157 /* NB: accept HT rates */ 158 #define isValidTxRate(_r) ((1<<((_r) & 0x7f)) & VALID_TX_RATES) 159 160 static inline int 161 ar5416RateToRateTable(struct ath_hal *ah, uint8_t rate, HAL_BOOL is_ht40) 162 { 163 164 /* 165 * Handle the non-MCS rates 166 */ 167 switch (rate) { 168 case /* 1 Mb */ 0x1b: 169 case /* 1 MbS*/ 0x1b | 0x4: 170 return (AH5416(ah)->ah_ratesArray[rate1l]); 171 case /* 2 Mb */ 0x1a: 172 return (AH5416(ah)->ah_ratesArray[rate2l]); 173 case /* 2 MbS*/ 0x1a | 0x4: 174 return (AH5416(ah)->ah_ratesArray[rate2s]); 175 case /* 5.5 Mb */ 0x19: 176 return (AH5416(ah)->ah_ratesArray[rate5_5l]); 177 case /* 5.5 MbS*/ 0x19 | 0x4: 178 return (AH5416(ah)->ah_ratesArray[rate5_5s]); 179 case /* 11 Mb */ 0x18: 180 return (AH5416(ah)->ah_ratesArray[rate11l]); 181 case /* 11 MbS*/ 0x18 | 0x4: 182 return (AH5416(ah)->ah_ratesArray[rate11s]); 183 } 184 185 /* OFDM rates */ 186 switch (rate) { 187 case /* 6 Mb */ 0x0b: 188 return (AH5416(ah)->ah_ratesArray[rate6mb]); 189 case /* 9 Mb */ 0x0f: 190 return (AH5416(ah)->ah_ratesArray[rate9mb]); 191 case /* 12 Mb */ 0x0a: 192 return (AH5416(ah)->ah_ratesArray[rate12mb]); 193 case /* 18 Mb */ 0x0e: 194 return (AH5416(ah)->ah_ratesArray[rate18mb]); 195 case /* 24 Mb */ 0x09: 196 return (AH5416(ah)->ah_ratesArray[rate24mb]); 197 case /* 36 Mb */ 0x0d: 198 return (AH5416(ah)->ah_ratesArray[rate36mb]); 199 case /* 48 Mb */ 0x08: 200 return (AH5416(ah)->ah_ratesArray[rate48mb]); 201 case /* 54 Mb */ 0x0c: 202 return (AH5416(ah)->ah_ratesArray[rate54mb]); 203 } 204 205 /* 206 * Handle HT20/HT40 - we only have to do MCS0-7; 207 * there's no stream differences. 208 */ 209 if ((rate & 0x80) && is_ht40) { 210 return (AH5416(ah)->ah_ratesArray[rateHt40_0 + (rate & 0x7)]); 211 } else if (rate & 0x80) { 212 return (AH5416(ah)->ah_ratesArray[rateHt20_0 + (rate & 0x7)]); 213 } 214 215 /* XXX default (eg XR, bad bad person!) */ 216 return (AH5416(ah)->ah_ratesArray[rate6mb]); 217 } 218 219 /* 220 * Return the TX power to be used for the given rate/chains/TX power. 221 * 222 * There are a bunch of tweaks to make to a given TX power based on 223 * the current configuration, so... 224 */ 225 static uint16_t 226 ar5416GetTxRatePower(struct ath_hal *ah, uint8_t rate, uint8_t tx_chainmask, 227 uint16_t txPower, HAL_BOOL is_ht40) 228 { 229 int n_txpower, max_txpower; 230 const int cck_ofdm_delta = 2; 231 #define EEP_MINOR(_ah) \ 232 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 233 #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 234 235 /* Take a copy ; we may underflow and thus need to clamp things */ 236 n_txpower = txPower; 237 238 /* HT40? Need to adjust the TX power by this */ 239 if (is_ht40) 240 n_txpower += AH5416(ah)->ah_ht40PowerIncForPdadc; 241 242 /* 243 * Merlin? Offset the target TX power offset - it defaults to 244 * starting at -5.0dBm, but that can change! 245 * 246 * Kiwi/Kite? Always -5.0dBm offset. 247 */ 248 if (AR_SREV_KIWI_10_OR_LATER(ah)) { 249 n_txpower -= (AR5416_PWR_TABLE_OFFSET_DB * 2); 250 } else if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 251 int8_t pwr_table_offset = 0; 252 /* This is in dBm, convert to 1/2 dBm */ 253 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, 254 &pwr_table_offset); 255 n_txpower -= (pwr_table_offset * 2); 256 } 257 258 /* 259 * If Open-loop TX power control is used, the CCK rates need 260 * to be offset by that. 261 * 262 * Rates: 2S, 2L, 1S, 1L, 5.5S, 5.5L 263 * 264 * XXX Odd, we don't have a PHY table entry for long preamble 265 * 1mbit CCK? 266 */ 267 if (AR_SREV_MERLIN_20_OR_LATER(ah) && 268 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 269 270 if (rate == 0x19 || rate == 0x1a || rate == 0x1b || 271 rate == (0x19 | 0x04) || rate == (0x1a | 0x04) || 272 rate == (0x1b | 0x04)) { 273 n_txpower -= cck_ofdm_delta; 274 } 275 } 276 277 /* 278 * We're now offset by the same amount that the static maximum 279 * PHY power tables are. So, clamp the value based on that rate. 280 */ 281 max_txpower = ar5416RateToRateTable(ah, rate, is_ht40); 282 #if 0 283 ath_hal_printf(ah, "%s: n_txpower = %d, max_txpower = %d, " 284 "rate = 0x%x , is_ht40 = %d\n", 285 __func__, 286 n_txpower, 287 max_txpower, 288 rate, 289 is_ht40); 290 #endif 291 n_txpower = MIN(max_txpower, n_txpower); 292 293 /* 294 * We don't have to offset the TX power for two or three 295 * chain operation here - it's done by the AR_PHY_POWER_TX_SUB 296 * register setting via the EEPROM. 297 * 298 * So for vendors that programmed the maximum target power assuming 299 * that 2/3 chains are always on, things will just plain work. 300 * (They won't reach that target power if only one chain is on, but 301 * that's a different problem.) 302 */ 303 304 /* Over/underflow? Adjust */ 305 if (n_txpower < 0) 306 n_txpower = 0; 307 else if (n_txpower > 63) 308 n_txpower = 63; 309 310 /* 311 * For some odd reason the AR9160 with txpower=0 results in a 312 * much higher (max?) TX power. So, if it's a chipset before 313 * AR9220/AR9280, just clamp the minimum value at 1. 314 */ 315 if ((! AR_SREV_MERLIN_10_OR_LATER(ah)) && (n_txpower == 0)) 316 n_txpower = 1; 317 318 return (n_txpower); 319 #undef EEP_MINOR 320 #undef IS_EEP_MINOR_V2 321 } 322 323 HAL_BOOL 324 ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 325 u_int pktLen, 326 u_int hdrLen, 327 HAL_PKT_TYPE type, 328 u_int txPower, 329 u_int txRate0, u_int txTries0, 330 u_int keyIx, 331 u_int antMode, 332 u_int flags, 333 u_int rtsctsRate, 334 u_int rtsctsDuration, 335 u_int compicvLen, 336 u_int compivLen, 337 u_int comp) 338 { 339 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) 340 struct ar5416_desc *ads = AR5416DESC(ds); 341 struct ath_hal_5416 *ahp = AH5416(ah); 342 343 (void) hdrLen; 344 345 HALASSERT(txTries0 != 0); 346 HALASSERT(isValidPktType(type)); 347 HALASSERT(isValidTxRate(txRate0)); 348 HALASSERT((flags & RTSCTS) != RTSCTS); 349 /* XXX validate antMode */ 350 351 txPower = (txPower + AH5212(ah)->ah_txPowerIndexOffset); 352 if (txPower > 63) 353 txPower = 63; 354 355 /* 356 * XXX For now, just assume that this isn't a HT40 frame. 357 * It'll get over-ridden by the multi-rate TX power setup. 358 */ 359 if (AH5212(ah)->ah_tpcEnabled) { 360 txPower = ar5416GetTxRatePower(ah, txRate0, 361 ahp->ah_tx_chainmask, 362 txPower, 363 AH_FALSE); 364 } 365 366 ads->ds_ctl0 = (pktLen & AR_FrameLen) 367 | (txPower << AR_XmitPower_S) 368 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0) 369 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) 370 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0) 371 ; 372 ads->ds_ctl1 = (type << AR_FrameType_S) 373 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0) 374 | (flags & HAL_TXDESC_HWTS ? AR_InsertTS : 0) 375 ; 376 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0) 377 | (flags & HAL_TXDESC_DURENA ? AR_DurUpdateEn : 0) 378 ; 379 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S) 380 ; 381 ads->ds_ctl4 = 0; 382 ads->ds_ctl5 = 0; 383 ads->ds_ctl6 = 0; 384 ads->ds_ctl7 = SM(ahp->ah_tx_chainmask, AR_ChainSel0) 385 | SM(ahp->ah_tx_chainmask, AR_ChainSel1) 386 | SM(ahp->ah_tx_chainmask, AR_ChainSel2) 387 | SM(ahp->ah_tx_chainmask, AR_ChainSel3) 388 ; 389 ads->ds_ctl8 = SM(0, AR_AntCtl0); 390 ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(txPower, AR_XmitPower1); 391 ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(txPower, AR_XmitPower2); 392 ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(txPower, AR_XmitPower3); 393 394 if (keyIx != HAL_TXKEYIX_INVALID) { 395 /* XXX validate key index */ 396 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx); 397 ads->ds_ctl0 |= AR_DestIdxValid; 398 ads->ds_ctl6 |= SM(ahp->ah_keytype[keyIx], AR_EncrType); 399 } 400 if (flags & RTSCTS) { 401 if (!isValidTxRate(rtsctsRate)) { 402 HALDEBUG(ah, HAL_DEBUG_ANY, 403 "%s: invalid rts/cts rate 0x%x\n", 404 __func__, rtsctsRate); 405 return AH_FALSE; 406 } 407 /* XXX validate rtsctsDuration */ 408 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0) 409 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0) 410 ; 411 ads->ds_ctl7 |= (rtsctsRate << AR_RTSCTSRate_S); 412 } 413 414 /* 415 * Set the TX antenna to 0 for Kite 416 * To preserve existing behaviour, also set the TPC bits to 0; 417 * when TPC is enabled these should be filled in appropriately. 418 * 419 * XXX TODO: when doing TPC, set the TX power up appropriately? 420 */ 421 if (AR_SREV_KITE(ah)) { 422 ads->ds_ctl8 = SM(0, AR_AntCtl0); 423 ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(0, AR_XmitPower1); 424 ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(0, AR_XmitPower2); 425 ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(0, AR_XmitPower3); 426 } 427 return AH_TRUE; 428 #undef RTSCTS 429 } 430 431 HAL_BOOL 432 ar5416SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds, 433 u_int txRate1, u_int txTries1, 434 u_int txRate2, u_int txTries2, 435 u_int txRate3, u_int txTries3) 436 { 437 struct ar5416_desc *ads = AR5416DESC(ds); 438 439 if (txTries1) { 440 HALASSERT(isValidTxRate(txRate1)); 441 ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1); 442 ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S); 443 } 444 if (txTries2) { 445 HALASSERT(isValidTxRate(txRate2)); 446 ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2); 447 ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S); 448 } 449 if (txTries3) { 450 HALASSERT(isValidTxRate(txRate3)); 451 ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3); 452 ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S); 453 } 454 return AH_TRUE; 455 } 456 457 /* 458 * XXX TODO: Figure out if AR_InsertTS is required on all sub-frames 459 * of a TX descriptor. 460 */ 461 HAL_BOOL 462 ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 463 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int descId, 464 u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 465 const struct ath_desc *ds0) 466 { 467 struct ar5416_desc *ads = AR5416DESC(ds); 468 uint32_t segLen = segLenList[0]; 469 470 HALASSERT((segLen &~ AR_BufLen) == 0); 471 472 ds->ds_data = bufAddrList[0]; 473 474 if (firstSeg) { 475 /* 476 * First descriptor, don't clobber xmit control data 477 * setup by ar5212SetupTxDesc. 478 */ 479 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore); 480 } else if (lastSeg) { /* !firstSeg && lastSeg */ 481 /* 482 * Last descriptor in a multi-descriptor frame, 483 * copy the multi-rate transmit parameters from 484 * the first frame for processing on completion. 485 */ 486 ads->ds_ctl1 = segLen; 487 #ifdef AH_NEED_DESC_SWAP 488 ads->ds_ctl0 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl0) 489 & AR_TxIntrReq; 490 ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2); 491 ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3); 492 /* ctl6 - we only need encrtype; the rest are blank */ 493 ads->ds_ctl6 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl6 & AR_EncrType); 494 #else 495 ads->ds_ctl0 = AR5416DESC_CONST(ds0)->ds_ctl0 & AR_TxIntrReq; 496 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2; 497 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3; 498 /* ctl6 - we only need encrtype; the rest are blank */ 499 ads->ds_ctl6 = AR5416DESC_CONST(ds0)->ds_ctl6 & AR_EncrType; 500 #endif 501 } else { /* !firstSeg && !lastSeg */ 502 /* 503 * Intermediate descriptor in a multi-descriptor frame. 504 */ 505 #ifdef AH_NEED_DESC_SWAP 506 ads->ds_ctl0 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl0) 507 & AR_TxIntrReq; 508 ads->ds_ctl6 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl6 & AR_EncrType); 509 #else 510 ads->ds_ctl0 = AR5416DESC_CONST(ds0)->ds_ctl0 & AR_TxIntrReq; 511 ads->ds_ctl6 = AR5416DESC_CONST(ds0)->ds_ctl6 & AR_EncrType; 512 #endif 513 ads->ds_ctl1 = segLen | AR_TxMore; 514 ads->ds_ctl2 = 0; 515 ads->ds_ctl3 = 0; 516 } 517 /* XXX only on last descriptor? */ 518 OS_MEMZERO(ads->u.tx.status, sizeof(ads->u.tx.status)); 519 return AH_TRUE; 520 } 521 522 /* 523 * NB: cipher is no longer used, it's calculated. 524 */ 525 HAL_BOOL 526 ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds, 527 HAL_DMA_ADDR *bufAddrList, 528 uint32_t *segLenList, 529 u_int pktLen, 530 u_int hdrLen, 531 HAL_PKT_TYPE type, 532 u_int keyIx, 533 HAL_CIPHER cipher, 534 uint8_t delims, 535 HAL_BOOL firstSeg, 536 HAL_BOOL lastSeg, 537 HAL_BOOL lastAggr) 538 { 539 struct ar5416_desc *ads = AR5416DESC(ds); 540 uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads); 541 struct ath_hal_5416 *ahp = AH5416(ah); 542 u_int segLen = segLenList[0]; 543 544 int isaggr = 0; 545 uint32_t last_aggr = 0; 546 547 (void) hdrLen; 548 (void) ah; 549 550 HALASSERT((segLen &~ AR_BufLen) == 0); 551 ds->ds_data = bufAddrList[0]; 552 553 HALASSERT(isValidPktType(type)); 554 if (type == HAL_PKT_TYPE_AMPDU) { 555 type = HAL_PKT_TYPE_NORMAL; 556 isaggr = 1; 557 if (lastAggr == AH_FALSE) 558 last_aggr = AR_MoreAggr; 559 } 560 561 /* 562 * Since this function is called before any of the other 563 * descriptor setup functions (at least in this particular 564 * 802.11n aggregation implementation), always bzero() the 565 * descriptor. Previously this would be done for all but 566 * the first segment. 567 * XXX TODO: figure out why; perhaps I'm using this slightly 568 * XXX incorrectly. 569 */ 570 OS_MEMZERO(ds->ds_hw, AR5416_DESC_TX_CTL_SZ); 571 572 /* 573 * Note: VEOL should only be for the last descriptor in the chain. 574 */ 575 ads->ds_ctl0 = (pktLen & AR_FrameLen); 576 577 /* 578 * For aggregates: 579 * + IsAggr must be set for all descriptors of all subframes of 580 * the aggregate 581 * + MoreAggr must be set for all descriptors of all subframes 582 * of the aggregate EXCEPT the last subframe; 583 * + MoreAggr must be _CLEAR_ for all descrpitors of the last 584 * subframe of the aggregate. 585 */ 586 ads->ds_ctl1 = (type << AR_FrameType_S) 587 | (isaggr ? (AR_IsAggr | last_aggr) : 0); 588 589 ads->ds_ctl2 = 0; 590 ads->ds_ctl3 = 0; 591 if (keyIx != HAL_TXKEYIX_INVALID) { 592 /* XXX validate key index */ 593 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx); 594 ads->ds_ctl0 |= AR_DestIdxValid; 595 } 596 597 ads->ds_ctl6 |= SM(ahp->ah_keytype[keyIx], AR_EncrType); 598 if (isaggr) { 599 ads->ds_ctl6 |= SM(delims, AR_PadDelim); 600 } 601 602 if (firstSeg) { 603 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore); 604 } else if (lastSeg) { /* !firstSeg && lastSeg */ 605 ads->ds_ctl0 = 0; 606 ads->ds_ctl1 |= segLen; 607 } else { /* !firstSeg && !lastSeg */ 608 /* 609 * Intermediate descriptor in a multi-descriptor frame. 610 */ 611 ads->ds_ctl0 = 0; 612 ads->ds_ctl1 |= segLen | AR_TxMore; 613 } 614 ds_txstatus[0] = ds_txstatus[1] = 0; 615 ds_txstatus[9] &= ~AR_TxDone; 616 617 return AH_TRUE; 618 } 619 620 HAL_BOOL 621 ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds, 622 u_int aggrLen, u_int flags, u_int txPower, 623 u_int txRate0, u_int txTries0, u_int antMode, 624 u_int rtsctsRate, u_int rtsctsDuration) 625 { 626 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) 627 struct ar5416_desc *ads = AR5416DESC(ds); 628 struct ath_hal_5212 *ahp = AH5212(ah); 629 630 HALASSERT(txTries0 != 0); 631 HALASSERT(isValidTxRate(txRate0)); 632 HALASSERT((flags & RTSCTS) != RTSCTS); 633 /* XXX validate antMode */ 634 635 txPower = (txPower + ahp->ah_txPowerIndexOffset ); 636 if(txPower > 63) txPower=63; 637 638 ads->ds_ctl0 |= (txPower << AR_XmitPower_S) 639 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0) 640 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) 641 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0); 642 ads->ds_ctl1 |= (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0); 643 ads->ds_ctl2 |= SM(txTries0, AR_XmitDataTries0); 644 ads->ds_ctl3 |= (txRate0 << AR_XmitRate0_S); 645 ads->ds_ctl7 = SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel0) 646 | SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel1) 647 | SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel2) 648 | SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel3); 649 650 /* NB: no V1 WAR */ 651 ads->ds_ctl8 = SM(0, AR_AntCtl0); 652 ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(txPower, AR_XmitPower1); 653 ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(txPower, AR_XmitPower2); 654 ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(txPower, AR_XmitPower3); 655 656 ads->ds_ctl6 &= ~(0xffff); 657 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); 658 659 if (flags & RTSCTS) { 660 /* XXX validate rtsctsDuration */ 661 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0) 662 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0); 663 } 664 665 /* 666 * Set the TX antenna to 0 for Kite 667 * To preserve existing behaviour, also set the TPC bits to 0; 668 * when TPC is enabled these should be filled in appropriately. 669 */ 670 if (AR_SREV_KITE(ah)) { 671 ads->ds_ctl8 = SM(0, AR_AntCtl0); 672 ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(0, AR_XmitPower1); 673 ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(0, AR_XmitPower2); 674 ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(0, AR_XmitPower3); 675 } 676 677 return AH_TRUE; 678 #undef RTSCTS 679 } 680 681 HAL_BOOL 682 ar5416SetupLastTxDesc(struct ath_hal *ah, struct ath_desc *ds, 683 const struct ath_desc *ds0) 684 { 685 struct ar5416_desc *ads = AR5416DESC(ds); 686 687 ads->ds_ctl1 &= ~AR_MoreAggr; 688 ads->ds_ctl6 &= ~AR_PadDelim; 689 690 /* hack to copy rate info to last desc for later processing */ 691 #ifdef AH_NEED_DESC_SWAP 692 ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2); 693 ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3); 694 #else 695 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2; 696 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3; 697 #endif 698 return AH_TRUE; 699 } 700 701 #ifdef AH_NEED_DESC_SWAP 702 /* Swap transmit descriptor */ 703 static __inline void 704 ar5416SwapTxDesc(struct ath_desc *ds) 705 { 706 ds->ds_data = __bswap32(ds->ds_data); 707 ds->ds_ctl0 = __bswap32(ds->ds_ctl0); 708 ds->ds_ctl1 = __bswap32(ds->ds_ctl1); 709 ds->ds_hw[0] = __bswap32(ds->ds_hw[0]); 710 ds->ds_hw[1] = __bswap32(ds->ds_hw[1]); 711 ds->ds_hw[2] = __bswap32(ds->ds_hw[2]); 712 ds->ds_hw[3] = __bswap32(ds->ds_hw[3]); 713 } 714 #endif 715 716 /* 717 * Processing of HW TX descriptor. 718 */ 719 HAL_STATUS 720 ar5416ProcTxDesc(struct ath_hal *ah, 721 struct ath_desc *ds, struct ath_tx_status *ts) 722 { 723 struct ar5416_desc *ads = AR5416DESC(ds); 724 uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads); 725 726 #ifdef AH_NEED_DESC_SWAP 727 if ((ds_txstatus[9] & __bswap32(AR_TxDone)) == 0) 728 return HAL_EINPROGRESS; 729 ar5416SwapTxDesc(ds); 730 #else 731 if ((ds_txstatus[9] & AR_TxDone) == 0) 732 return HAL_EINPROGRESS; 733 #endif 734 735 /* Update software copies of the HW status */ 736 ts->ts_seqnum = MS(ds_txstatus[9], AR_SeqNum); 737 ts->ts_tstamp = AR_SendTimestamp(ds_txstatus); 738 ts->ts_tid = MS(ds_txstatus[9], AR_TxTid); 739 740 ts->ts_status = 0; 741 if (ds_txstatus[1] & AR_ExcessiveRetries) 742 ts->ts_status |= HAL_TXERR_XRETRY; 743 if (ds_txstatus[1] & AR_Filtered) 744 ts->ts_status |= HAL_TXERR_FILT; 745 if (ds_txstatus[1] & AR_FIFOUnderrun) 746 ts->ts_status |= HAL_TXERR_FIFO; 747 if (ds_txstatus[9] & AR_TxOpExceeded) 748 ts->ts_status |= HAL_TXERR_XTXOP; 749 if (ds_txstatus[1] & AR_TxTimerExpired) 750 ts->ts_status |= HAL_TXERR_TIMER_EXPIRED; 751 752 ts->ts_flags = 0; 753 if (ds_txstatus[0] & AR_TxBaStatus) { 754 ts->ts_flags |= HAL_TX_BA; 755 ts->ts_ba_low = AR_BaBitmapLow(ds_txstatus); 756 ts->ts_ba_high = AR_BaBitmapHigh(ds_txstatus); 757 } 758 if (ds->ds_ctl1 & AR_IsAggr) 759 ts->ts_flags |= HAL_TX_AGGR; 760 if (ds_txstatus[1] & AR_DescCfgErr) 761 ts->ts_flags |= HAL_TX_DESC_CFG_ERR; 762 if (ds_txstatus[1] & AR_TxDataUnderrun) 763 ts->ts_flags |= HAL_TX_DATA_UNDERRUN; 764 if (ds_txstatus[1] & AR_TxDelimUnderrun) 765 ts->ts_flags |= HAL_TX_DELIM_UNDERRUN; 766 767 /* 768 * Extract the transmit rate used and mark the rate as 769 * ``alternate'' if it wasn't the series 0 rate. 770 */ 771 ts->ts_finaltsi = MS(ds_txstatus[9], AR_FinalTxIdx); 772 switch (ts->ts_finaltsi) { 773 case 0: 774 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0); 775 break; 776 case 1: 777 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1); 778 break; 779 case 2: 780 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2); 781 break; 782 case 3: 783 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3); 784 break; 785 } 786 787 ts->ts_rssi = MS(ds_txstatus[5], AR_TxRSSICombined); 788 ts->ts_rssi_ctl[0] = MS(ds_txstatus[0], AR_TxRSSIAnt00); 789 ts->ts_rssi_ctl[1] = MS(ds_txstatus[0], AR_TxRSSIAnt01); 790 ts->ts_rssi_ctl[2] = MS(ds_txstatus[0], AR_TxRSSIAnt02); 791 ts->ts_rssi_ext[0] = MS(ds_txstatus[5], AR_TxRSSIAnt10); 792 ts->ts_rssi_ext[1] = MS(ds_txstatus[5], AR_TxRSSIAnt11); 793 ts->ts_rssi_ext[2] = MS(ds_txstatus[5], AR_TxRSSIAnt12); 794 ts->ts_evm0 = AR_TxEVM0(ds_txstatus); 795 ts->ts_evm1 = AR_TxEVM1(ds_txstatus); 796 ts->ts_evm2 = AR_TxEVM2(ds_txstatus); 797 798 ts->ts_shortretry = MS(ds_txstatus[1], AR_RTSFailCnt); 799 ts->ts_longretry = MS(ds_txstatus[1], AR_DataFailCnt); 800 /* 801 * The retry count has the number of un-acked tries for the 802 * final series used. When doing multi-rate retry we must 803 * fixup the retry count by adding in the try counts for 804 * each series that was fully-processed. Beware that this 805 * takes values from the try counts in the final descriptor. 806 * These are not required by the hardware. We assume they 807 * are placed there by the driver as otherwise we have no 808 * access and the driver can't do the calculation because it 809 * doesn't know the descriptor format. 810 */ 811 switch (ts->ts_finaltsi) { 812 case 3: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries2); 813 case 2: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries1); 814 case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0); 815 } 816 817 /* 818 * These fields are not used. Zero these to preserve compatibility 819 * with existing drivers. 820 */ 821 ts->ts_virtcol = MS(ads->ds_ctl1, AR_VirtRetryCnt); 822 ts->ts_antenna = 0; /* We don't switch antennas on Owl*/ 823 824 /* handle tx trigger level changes internally */ 825 if ((ts->ts_status & HAL_TXERR_FIFO) || 826 (ts->ts_flags & (HAL_TX_DATA_UNDERRUN | HAL_TX_DELIM_UNDERRUN))) 827 ar5212UpdateTxTrigLevel(ah, AH_TRUE); 828 829 return HAL_OK; 830 } 831 832 HAL_BOOL 833 ar5416SetGlobalTxTimeout(struct ath_hal *ah, u_int tu) 834 { 835 struct ath_hal_5416 *ahp = AH5416(ah); 836 837 if (tu > 0xFFFF) { 838 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad global tx timeout %u\n", 839 __func__, tu); 840 /* restore default handling */ 841 ahp->ah_globaltxtimeout = (u_int) -1; 842 return AH_FALSE; 843 } 844 OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 845 ahp->ah_globaltxtimeout = tu; 846 return AH_TRUE; 847 } 848 849 u_int 850 ar5416GetGlobalTxTimeout(struct ath_hal *ah) 851 { 852 return MS(OS_REG_READ(ah, AR_GTXTO), AR_GTXTO_TIMEOUT_LIMIT); 853 } 854 855 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) 856 static const u_int8_t baDurationDelta[] = { 857 24, // 0: BPSK 858 12, // 1: QPSK 1/2 859 12, // 2: QPSK 3/4 860 4, // 3: 16-QAM 1/2 861 4, // 4: 16-QAM 3/4 862 4, // 5: 64-QAM 2/3 863 4, // 6: 64-QAM 3/4 864 4, // 7: 64-QAM 5/6 865 24, // 8: BPSK 866 12, // 9: QPSK 1/2 867 12, // 10: QPSK 3/4 868 4, // 11: 16-QAM 1/2 869 4, // 12: 16-QAM 3/4 870 4, // 13: 64-QAM 2/3 871 4, // 14: 64-QAM 3/4 872 4, // 15: 64-QAM 5/6 873 }; 874 875 void 876 ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds, 877 u_int durUpdateEn, u_int rtsctsRate, 878 HAL_11N_RATE_SERIES series[], u_int nseries, u_int flags) 879 { 880 struct ar5416_desc *ads = AR5416DESC(ds); 881 uint32_t ds_ctl0; 882 883 HALASSERT(nseries == 4); 884 (void)nseries; 885 886 /* 887 * Only one of RTS and CTS enable must be set. 888 * If a frame has both set, just do RTS protection - 889 * that's enough to satisfy legacy protection. 890 */ 891 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { 892 ds_ctl0 = ads->ds_ctl0; 893 894 if (flags & HAL_TXDESC_RTSENA) { 895 ds_ctl0 &= ~AR_CTSEnable; 896 ds_ctl0 |= AR_RTSEnable; 897 } else { 898 ds_ctl0 &= ~AR_RTSEnable; 899 ds_ctl0 |= AR_CTSEnable; 900 } 901 902 ads->ds_ctl0 = ds_ctl0; 903 } else { 904 ads->ds_ctl0 = 905 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); 906 } 907 908 ads->ds_ctl2 = set11nTries(series, 0) 909 | set11nTries(series, 1) 910 | set11nTries(series, 2) 911 | set11nTries(series, 3) 912 | (durUpdateEn ? AR_DurUpdateEn : 0); 913 914 ads->ds_ctl3 = set11nRate(series, 0) 915 | set11nRate(series, 1) 916 | set11nRate(series, 2) 917 | set11nRate(series, 3); 918 919 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) 920 | set11nPktDurRTSCTS(series, 1); 921 922 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) 923 | set11nPktDurRTSCTS(series, 3); 924 925 ads->ds_ctl7 = set11nRateFlags(series, 0) 926 | set11nRateFlags(series, 1) 927 | set11nRateFlags(series, 2) 928 | set11nRateFlags(series, 3) 929 | SM(rtsctsRate, AR_RTSCTSRate); 930 931 /* 932 * Doing per-packet TPC - update the TX power for the first 933 * field; program in the other series. 934 */ 935 if (AH5212(ah)->ah_tpcEnabled) { 936 uint32_t ds_ctl0; 937 uint16_t txPower; 938 939 /* Modify the tx power field for rate 0 */ 940 txPower = ar5416GetTxRatePower(ah, series[0].Rate, 941 series[0].ChSel, 942 series[0].tx_power_cap, 943 !! (series[0].RateFlags & HAL_RATESERIES_2040)); 944 ds_ctl0 = ads->ds_ctl0 & ~AR_XmitPower; 945 ds_ctl0 |= (txPower << AR_XmitPower_S); 946 ads->ds_ctl0 = ds_ctl0; 947 948 /* 949 * Override the whole descriptor field for each TX power. 950 * 951 * This will need changing if we ever support antenna control 952 * programming. 953 */ 954 txPower = ar5416GetTxRatePower(ah, series[1].Rate, 955 series[1].ChSel, 956 series[1].tx_power_cap, 957 !! (series[1].RateFlags & HAL_RATESERIES_2040)); 958 ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(txPower, AR_XmitPower1); 959 960 txPower = ar5416GetTxRatePower(ah, series[2].Rate, 961 series[2].ChSel, 962 series[2].tx_power_cap, 963 !! (series[2].RateFlags & HAL_RATESERIES_2040)); 964 ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(txPower, AR_XmitPower2); 965 966 txPower = ar5416GetTxRatePower(ah, series[3].Rate, 967 series[3].ChSel, 968 series[3].tx_power_cap, 969 !! (series[3].RateFlags & HAL_RATESERIES_2040)); 970 ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(txPower, AR_XmitPower3); 971 } 972 } 973 974 /* 975 * Note: this should be called before calling ar5416SetBurstDuration() 976 * (if it is indeed called) in order to ensure that the burst duration 977 * is correctly updated with the BA delta workaround. 978 */ 979 void 980 ar5416Set11nAggrFirst(struct ath_hal *ah, struct ath_desc *ds, u_int aggrLen, 981 u_int numDelims) 982 { 983 struct ar5416_desc *ads = AR5416DESC(ds); 984 uint32_t flags; 985 uint32_t burstDur; 986 uint8_t rate; 987 988 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); 989 990 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim); 991 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); 992 ads->ds_ctl6 |= SM(numDelims, AR_PadDelim); 993 994 if (! AR_SREV_MERLIN_10_OR_LATER(ah)) { 995 /* 996 * XXX It'd be nice if I were passed in the rate scenario 997 * at this point.. 998 */ 999 rate = MS(ads->ds_ctl3, AR_XmitRate0); 1000 flags = ads->ds_ctl0 & (AR_CTSEnable | AR_RTSEnable); 1001 /* 1002 * WAR - MAC assumes normal ACK time instead of 1003 * block ACK while computing packet duration. 1004 * Add this delta to the burst duration in the descriptor. 1005 */ 1006 if (flags && (ads->ds_ctl1 & AR_IsAggr)) { 1007 burstDur = baDurationDelta[HT_RC_2_MCS(rate)]; 1008 ads->ds_ctl2 &= ~(AR_BurstDur); 1009 ads->ds_ctl2 |= SM(burstDur, AR_BurstDur); 1010 } 1011 } 1012 } 1013 1014 void 1015 ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims) 1016 { 1017 struct ar5416_desc *ads = AR5416DESC(ds); 1018 uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads); 1019 1020 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); 1021 1022 ads->ds_ctl6 &= ~AR_PadDelim; 1023 ads->ds_ctl6 |= SM(numDelims, AR_PadDelim); 1024 ads->ds_ctl6 &= ~AR_AggrLen; 1025 1026 /* 1027 * Clear the TxDone status here, may need to change 1028 * func name to reflect this 1029 */ 1030 ds_txstatus[9] &= ~AR_TxDone; 1031 } 1032 1033 void 1034 ar5416Set11nAggrLast(struct ath_hal *ah, struct ath_desc *ds) 1035 { 1036 struct ar5416_desc *ads = AR5416DESC(ds); 1037 1038 ads->ds_ctl1 |= AR_IsAggr; 1039 ads->ds_ctl1 &= ~AR_MoreAggr; 1040 ads->ds_ctl6 &= ~AR_PadDelim; 1041 } 1042 1043 void 1044 ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds) 1045 { 1046 struct ar5416_desc *ads = AR5416DESC(ds); 1047 1048 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); 1049 ads->ds_ctl6 &= ~AR_PadDelim; 1050 ads->ds_ctl6 &= ~AR_AggrLen; 1051 } 1052 1053 void 1054 ar5416Set11nVirtualMoreFrag(struct ath_hal *ah, struct ath_desc *ds, 1055 u_int vmf) 1056 { 1057 struct ar5416_desc *ads = AR5416DESC(ds); 1058 if (vmf) 1059 ads->ds_ctl0 |= AR_VirtMoreFrag; 1060 else 1061 ads->ds_ctl0 &= ~AR_VirtMoreFrag; 1062 } 1063 1064 /* 1065 * Program the burst duration, with the included BA delta if it's 1066 * applicable. 1067 */ 1068 void 1069 ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds, 1070 u_int burstDuration) 1071 { 1072 struct ar5416_desc *ads = AR5416DESC(ds); 1073 uint32_t burstDur = 0; 1074 uint8_t rate; 1075 1076 if (! AR_SREV_MERLIN_10_OR_LATER(ah)) { 1077 /* 1078 * XXX It'd be nice if I were passed in the rate scenario 1079 * at this point.. 1080 */ 1081 rate = MS(ads->ds_ctl3, AR_XmitDataTries0); 1082 /* 1083 * WAR - MAC assumes normal ACK time instead of 1084 * block ACK while computing packet duration. 1085 * Add this delta to the burst duration in the descriptor. 1086 */ 1087 if (ads->ds_ctl1 & AR_IsAggr) { 1088 burstDur = baDurationDelta[HT_RC_2_MCS(rate)]; 1089 } 1090 } 1091 1092 ads->ds_ctl2 &= ~AR_BurstDur; 1093 ads->ds_ctl2 |= SM(burstDur + burstDuration, AR_BurstDur); 1094 } 1095 1096 /* 1097 * Retrieve the rate table from the given TX completion descriptor 1098 */ 1099 HAL_BOOL 1100 ar5416GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries) 1101 { 1102 const struct ar5416_desc *ads = AR5416DESC_CONST(ds0); 1103 1104 rates[0] = MS(ads->ds_ctl3, AR_XmitRate0); 1105 rates[1] = MS(ads->ds_ctl3, AR_XmitRate1); 1106 rates[2] = MS(ads->ds_ctl3, AR_XmitRate2); 1107 rates[3] = MS(ads->ds_ctl3, AR_XmitRate3); 1108 1109 tries[0] = MS(ads->ds_ctl2, AR_XmitDataTries0); 1110 tries[1] = MS(ads->ds_ctl2, AR_XmitDataTries1); 1111 tries[2] = MS(ads->ds_ctl2, AR_XmitDataTries2); 1112 tries[3] = MS(ads->ds_ctl2, AR_XmitDataTries3); 1113 1114 return AH_TRUE; 1115 } 1116 1117 1118 /* 1119 * TX queue management routines - AR5416 and later chipsets 1120 */ 1121 1122 /* 1123 * Allocate and initialize a tx DCU/QCU combination. 1124 */ 1125 int 1126 ar5416SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 1127 const HAL_TXQ_INFO *qInfo) 1128 { 1129 struct ath_hal_5212 *ahp = AH5212(ah); 1130 HAL_TX_QUEUE_INFO *qi; 1131 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 1132 int q, defqflags; 1133 1134 /* by default enable OK+ERR+DESC+URN interrupts */ 1135 defqflags = HAL_TXQ_TXOKINT_ENABLE 1136 | HAL_TXQ_TXERRINT_ENABLE 1137 | HAL_TXQ_TXDESCINT_ENABLE 1138 | HAL_TXQ_TXURNINT_ENABLE; 1139 /* XXX move queue assignment to driver */ 1140 switch (type) { 1141 case HAL_TX_QUEUE_BEACON: 1142 q = pCap->halTotalQueues-1; /* highest priority */ 1143 defqflags |= HAL_TXQ_DBA_GATED 1144 | HAL_TXQ_CBR_DIS_QEMPTY 1145 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 1146 | HAL_TXQ_BACKOFF_DISABLE; 1147 break; 1148 case HAL_TX_QUEUE_CAB: 1149 q = pCap->halTotalQueues-2; /* next highest priority */ 1150 defqflags |= HAL_TXQ_DBA_GATED 1151 | HAL_TXQ_CBR_DIS_QEMPTY 1152 | HAL_TXQ_CBR_DIS_BEMPTY 1153 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 1154 | HAL_TXQ_BACKOFF_DISABLE; 1155 break; 1156 case HAL_TX_QUEUE_PSPOLL: 1157 q = 1; /* lowest priority */ 1158 defqflags |= HAL_TXQ_DBA_GATED 1159 | HAL_TXQ_CBR_DIS_QEMPTY 1160 | HAL_TXQ_CBR_DIS_BEMPTY 1161 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 1162 | HAL_TXQ_BACKOFF_DISABLE; 1163 break; 1164 case HAL_TX_QUEUE_UAPSD: 1165 q = pCap->halTotalQueues-3; /* nextest highest priority */ 1166 if (ahp->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE) { 1167 HALDEBUG(ah, HAL_DEBUG_ANY, 1168 "%s: no available UAPSD tx queue\n", __func__); 1169 return -1; 1170 } 1171 break; 1172 case HAL_TX_QUEUE_DATA: 1173 for (q = 0; q < pCap->halTotalQueues; q++) 1174 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) 1175 break; 1176 if (q == pCap->halTotalQueues) { 1177 HALDEBUG(ah, HAL_DEBUG_ANY, 1178 "%s: no available tx queue\n", __func__); 1179 return -1; 1180 } 1181 break; 1182 default: 1183 HALDEBUG(ah, HAL_DEBUG_ANY, 1184 "%s: bad tx queue type %u\n", __func__, type); 1185 return -1; 1186 } 1187 1188 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q); 1189 1190 qi = &ahp->ah_txq[q]; 1191 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) { 1192 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n", 1193 __func__, q); 1194 return -1; 1195 } 1196 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO)); 1197 qi->tqi_type = type; 1198 if (qInfo == AH_NULL) { 1199 qi->tqi_qflags = defqflags; 1200 qi->tqi_aifs = INIT_AIFS; 1201 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */ 1202 qi->tqi_cwmax = INIT_CWMAX; 1203 qi->tqi_shretry = INIT_SH_RETRY; 1204 qi->tqi_lgretry = INIT_LG_RETRY; 1205 qi->tqi_physCompBuf = 0; 1206 } else { 1207 qi->tqi_physCompBuf = qInfo->tqi_compBuf; 1208 (void) ar5212SetTxQueueProps(ah, q, qInfo); 1209 } 1210 /* NB: must be followed by ar5212ResetTxQueue */ 1211 return q; 1212 } 1213 1214 /* 1215 * Update the h/w interrupt registers to reflect a tx q's configuration. 1216 */ 1217 static void 1218 setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi) 1219 { 1220 struct ath_hal_5212 *ahp = AH5212(ah); 1221 1222 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, 1223 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__, 1224 ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask, 1225 ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask, 1226 ahp->ah_txUrnInterruptMask); 1227 1228 OS_REG_WRITE(ah, AR_IMR_S0, 1229 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) 1230 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC) 1231 ); 1232 OS_REG_WRITE(ah, AR_IMR_S1, 1233 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) 1234 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL) 1235 ); 1236 OS_REG_RMW_FIELD(ah, AR_IMR_S2, 1237 AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); 1238 } 1239 1240 /* 1241 * Set the retry, aifs, cwmin/max, readyTime regs for specified queue 1242 * Assumes: 1243 * phwChannel has been set to point to the current channel 1244 */ 1245 #define TU_TO_USEC(_tu) ((_tu) << 10) 1246 HAL_BOOL 1247 ar5416ResetTxQueue(struct ath_hal *ah, u_int q) 1248 { 1249 struct ath_hal_5212 *ahp = AH5212(ah); 1250 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 1251 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1252 HAL_TX_QUEUE_INFO *qi; 1253 uint32_t cwMin, chanCwMin, qmisc, dmisc; 1254 1255 if (q >= pCap->halTotalQueues) { 1256 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n", 1257 __func__, q); 1258 return AH_FALSE; 1259 } 1260 qi = &ahp->ah_txq[q]; 1261 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { 1262 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n", 1263 __func__, q); 1264 return AH_TRUE; /* XXX??? */ 1265 } 1266 1267 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: reset queue %u\n", __func__, q); 1268 1269 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) { 1270 /* 1271 * Select cwmin according to channel type. 1272 * NB: chan can be NULL during attach 1273 */ 1274 if (chan && IEEE80211_IS_CHAN_B(chan)) 1275 chanCwMin = INIT_CWMIN_11B; 1276 else 1277 chanCwMin = INIT_CWMIN; 1278 /* make sure that the CWmin is of the form (2^n - 1) */ 1279 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1) 1280 ; 1281 } else 1282 cwMin = qi->tqi_cwmin; 1283 1284 /* set cwMin/Max and AIFS values */ 1285 OS_REG_WRITE(ah, AR_DLCL_IFS(q), 1286 SM(cwMin, AR_D_LCL_IFS_CWMIN) 1287 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) 1288 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 1289 1290 /* Set retry limit values */ 1291 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), 1292 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) 1293 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) 1294 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG) 1295 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH) 1296 ); 1297 1298 /* NB: always enable early termination on the QCU */ 1299 qmisc = AR_Q_MISC_DCU_EARLY_TERM_REQ 1300 | SM(AR_Q_MISC_FSP_ASAP, AR_Q_MISC_FSP); 1301 1302 /* NB: always enable DCU to wait for next fragment from QCU */ 1303 dmisc = AR_D_MISC_FRAG_WAIT_EN; 1304 1305 /* Enable exponential backoff window */ 1306 dmisc |= AR_D_MISC_BKOFF_PERSISTENCE; 1307 1308 /* 1309 * The chip reset default is to use a DCU backoff threshold of 0x2. 1310 * Restore this when programming the DCU MISC register. 1311 */ 1312 dmisc |= 0x2; 1313 1314 /* multiqueue support */ 1315 if (qi->tqi_cbrPeriod) { 1316 OS_REG_WRITE(ah, AR_QCBRCFG(q), 1317 SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL) 1318 | SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH)); 1319 qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_CBR; 1320 if (qi->tqi_cbrOverflowLimit) 1321 qmisc |= AR_Q_MISC_CBR_EXP_CNTR_LIMIT; 1322 } 1323 1324 if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) { 1325 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 1326 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) 1327 | AR_Q_RDYTIMECFG_ENA); 1328 } 1329 1330 OS_REG_WRITE(ah, AR_DCHNTIME(q), 1331 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) 1332 | (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); 1333 1334 if (qi->tqi_readyTime && 1335 (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE)) 1336 qmisc |= AR_Q_MISC_RDYTIME_EXP_POLICY; 1337 if (qi->tqi_qflags & HAL_TXQ_DBA_GATED) 1338 qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_DBA_GATED; 1339 if (MS(qmisc, AR_Q_MISC_FSP) != AR_Q_MISC_FSP_ASAP) { 1340 /* 1341 * These are meangingful only when not scheduled asap. 1342 */ 1343 if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY) 1344 qmisc |= AR_Q_MISC_CBR_INCR_DIS0; 1345 else 1346 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS0; 1347 if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY) 1348 qmisc |= AR_Q_MISC_CBR_INCR_DIS1; 1349 else 1350 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS1; 1351 } 1352 1353 if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) 1354 dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS; 1355 if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) 1356 dmisc |= AR_D_MISC_FRAG_BKOFF_EN; 1357 if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL) 1358 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 1359 AR_D_MISC_ARB_LOCKOUT_CNTRL); 1360 else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA) 1361 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR, 1362 AR_D_MISC_ARB_LOCKOUT_CNTRL); 1363 if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL) 1364 dmisc |= SM(AR_D_MISC_VIR_COL_HANDLING_IGNORE, 1365 AR_D_MISC_VIR_COL_HANDLING); 1366 if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS) 1367 dmisc |= AR_D_MISC_SEQ_NUM_INCR_DIS; 1368 1369 /* 1370 * Fillin type-dependent bits. Most of this can be 1371 * removed by specifying the queue parameters in the 1372 * driver; it's here for backwards compatibility. 1373 */ 1374 switch (qi->tqi_type) { 1375 case HAL_TX_QUEUE_BEACON: /* beacon frames */ 1376 qmisc |= AR_Q_MISC_FSP_DBA_GATED 1377 | AR_Q_MISC_BEACON_USE 1378 | AR_Q_MISC_CBR_INCR_DIS1; 1379 1380 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 1381 AR_D_MISC_ARB_LOCKOUT_CNTRL) 1382 | AR_D_MISC_BEACON_USE 1383 | AR_D_MISC_POST_FR_BKOFF_DIS; 1384 break; 1385 case HAL_TX_QUEUE_CAB: /* CAB frames */ 1386 /* 1387 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY, 1388 * There is an issue with the CAB Queue 1389 * not properly refreshing the Tx descriptor if 1390 * the TXE clear setting is used. 1391 */ 1392 qmisc |= AR_Q_MISC_FSP_DBA_GATED 1393 | AR_Q_MISC_CBR_INCR_DIS1 1394 | AR_Q_MISC_CBR_INCR_DIS0; 1395 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: CAB: tqi_readyTime = %d\n", 1396 __func__, qi->tqi_readyTime); 1397 if (qi->tqi_readyTime) { 1398 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, 1399 "%s: using tqi_readyTime\n", __func__); 1400 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 1401 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) | 1402 AR_Q_RDYTIMECFG_ENA); 1403 } else { 1404 int value; 1405 /* 1406 * NB: don't set default ready time if driver 1407 * has explicitly specified something. This is 1408 * here solely for backwards compatibility. 1409 */ 1410 /* 1411 * XXX for now, hard-code a CAB interval of 70% 1412 * XXX of the total beacon interval. 1413 * 1414 * XXX This keeps Merlin and later based MACs 1415 * XXX quite a bit happier (stops stuck beacons, 1416 * XXX which I gather is because of such a long 1417 * XXX cabq time.) 1418 */ 1419 value = (ahp->ah_beaconInterval * 50 / 100) 1420 - ah->ah_config.ah_additional_swba_backoff 1421 - ah->ah_config.ah_sw_beacon_response_time 1422 + ah->ah_config.ah_dma_beacon_response_time; 1423 /* 1424 * XXX Ensure it isn't too low - nothing lower 1425 * XXX than 10 TU 1426 */ 1427 if (value < 10) 1428 value = 10; 1429 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, 1430 "%s: defaulting to rdytime = %d uS\n", 1431 __func__, value); 1432 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 1433 SM(TU_TO_USEC(value), AR_Q_RDYTIMECFG_INT) | 1434 AR_Q_RDYTIMECFG_ENA); 1435 } 1436 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 1437 AR_D_MISC_ARB_LOCKOUT_CNTRL); 1438 break; 1439 case HAL_TX_QUEUE_PSPOLL: 1440 qmisc |= AR_Q_MISC_CBR_INCR_DIS1; 1441 break; 1442 case HAL_TX_QUEUE_UAPSD: 1443 dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS; 1444 break; 1445 default: /* NB: silence compiler */ 1446 break; 1447 } 1448 1449 OS_REG_WRITE(ah, AR_QMISC(q), qmisc); 1450 OS_REG_WRITE(ah, AR_DMISC(q), dmisc); 1451 1452 /* Setup compression scratchpad buffer */ 1453 /* 1454 * XXX: calling this asynchronously to queue operation can 1455 * cause unexpected behavior!!! 1456 */ 1457 if (qi->tqi_physCompBuf) { 1458 HALASSERT(qi->tqi_type == HAL_TX_QUEUE_DATA || 1459 qi->tqi_type == HAL_TX_QUEUE_UAPSD); 1460 OS_REG_WRITE(ah, AR_Q_CBBS, (80 + 2*q)); 1461 OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf); 1462 OS_REG_WRITE(ah, AR_Q_CBC, HAL_COMP_BUF_MAX_SIZE/1024); 1463 OS_REG_WRITE(ah, AR_Q0_MISC + 4*q, 1464 OS_REG_READ(ah, AR_Q0_MISC + 4*q) 1465 | AR_Q_MISC_QCU_COMP_EN); 1466 } 1467 1468 /* 1469 * Always update the secondary interrupt mask registers - this 1470 * could be a new queue getting enabled in a running system or 1471 * hw getting re-initialized during a reset! 1472 * 1473 * Since we don't differentiate between tx interrupts corresponding 1474 * to individual queues - secondary tx mask regs are always unmasked; 1475 * tx interrupts are enabled/disabled for all queues collectively 1476 * using the primary mask reg 1477 */ 1478 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) 1479 ahp->ah_txOkInterruptMask |= 1 << q; 1480 else 1481 ahp->ah_txOkInterruptMask &= ~(1 << q); 1482 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) 1483 ahp->ah_txErrInterruptMask |= 1 << q; 1484 else 1485 ahp->ah_txErrInterruptMask &= ~(1 << q); 1486 if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE) 1487 ahp->ah_txDescInterruptMask |= 1 << q; 1488 else 1489 ahp->ah_txDescInterruptMask &= ~(1 << q); 1490 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) 1491 ahp->ah_txEolInterruptMask |= 1 << q; 1492 else 1493 ahp->ah_txEolInterruptMask &= ~(1 << q); 1494 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) 1495 ahp->ah_txUrnInterruptMask |= 1 << q; 1496 else 1497 ahp->ah_txUrnInterruptMask &= ~(1 << q); 1498 setTxQInterrupts(ah, qi); 1499 1500 return AH_TRUE; 1501 } 1502 #undef TU_TO_USEC 1503