xref: /freebsd/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c (revision 273c26a3c3bea87a241d6879abd4f991db180bf0)
1 /*
2  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  *
17  * $FreeBSD$
18  */
19 #include "opt_ah.h"
20 
21 #include "ah.h"
22 #include "ah_desc.h"
23 #include "ah_internal.h"
24 
25 #include "ar5416/ar5416.h"
26 #include "ar5416/ar5416reg.h"
27 #include "ar5416/ar5416phy.h"
28 #include "ar5416/ar5416desc.h"
29 
30 /*
31  * Stop transmit on the specified queue
32  */
33 HAL_BOOL
34 ar5416StopTxDma(struct ath_hal *ah, u_int q)
35 {
36 #define	STOP_DMA_TIMEOUT	4000	/* us */
37 #define	STOP_DMA_ITER		100	/* us */
38 	u_int i;
39 
40 	HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
41 
42 	HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
43 
44 	OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
45 	for (i = STOP_DMA_TIMEOUT/STOP_DMA_ITER; i != 0; i--) {
46 		if (ar5212NumTxPending(ah, q) == 0)
47 			break;
48 		OS_DELAY(STOP_DMA_ITER);
49 	}
50 #ifdef AH_DEBUG
51 	if (i == 0) {
52 		HALDEBUG(ah, HAL_DEBUG_ANY,
53 		    "%s: queue %u DMA did not stop in 400 msec\n", __func__, q);
54 		HALDEBUG(ah, HAL_DEBUG_ANY,
55 		    "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", __func__,
56 		    OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE),
57 		    OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q)));
58 		HALDEBUG(ah, HAL_DEBUG_ANY,
59 		    "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
60 		    __func__, OS_REG_READ(ah, AR_QMISC(q)),
61 		    OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
62 		    OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
63 	}
64 #endif /* AH_DEBUG */
65 
66 	/* ar5416 and up can kill packets at the PCU level */
67 	if (ar5212NumTxPending(ah, q)) {
68 		uint32_t j;
69 
70 		HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
71 		    "%s: Num of pending TX Frames %d on Q %d\n",
72 		    __func__, ar5212NumTxPending(ah, q), q);
73 
74 		/* Kill last PCU Tx Frame */
75 		/* TODO - save off and restore current values of Q1/Q2? */
76 		for (j = 0; j < 2; j++) {
77 			uint32_t tsfLow = OS_REG_READ(ah, AR_TSF_L32);
78 			OS_REG_WRITE(ah, AR_QUIET2,
79 			    SM(10, AR_QUIET2_QUIET_DUR));
80 			OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100);
81 			OS_REG_WRITE(ah, AR_NEXT_QUIET, tsfLow >> 10);
82 			OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);
83 
84 			if ((OS_REG_READ(ah, AR_TSF_L32)>>10) == (tsfLow>>10))
85 				break;
86 
87 			HALDEBUG(ah, HAL_DEBUG_ANY,
88 			    "%s: TSF moved while trying to set quiet time "
89 			    "TSF: 0x%08x\n", __func__, tsfLow);
90 			HALASSERT(j < 1); /* TSF shouldn't count twice or reg access is taking forever */
91 		}
92 
93 		OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
94 
95 		/* Allow the quiet mechanism to do its work */
96 		OS_DELAY(200);
97 		OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);
98 
99 		/* Verify the transmit q is empty */
100 		for (i = STOP_DMA_TIMEOUT/STOP_DMA_ITER; i != 0; i--) {
101 			if (ar5212NumTxPending(ah, q) == 0)
102 				break;
103 			OS_DELAY(STOP_DMA_ITER);
104 		}
105 		if (i == 0) {
106 			HALDEBUG(ah, HAL_DEBUG_ANY,
107 			    "%s: Failed to stop Tx DMA in %d msec after killing"
108 			    " last frame\n", __func__, STOP_DMA_TIMEOUT / 1000);
109 		}
110 		OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
111 	}
112 
113 	OS_REG_WRITE(ah, AR_Q_TXD, 0);
114 	return (i != 0);
115 #undef STOP_DMA_ITER
116 #undef STOP_DMA_TIMEOUT
117 }
118 
119 #define VALID_KEY_TYPES \
120         ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\
121          (1 << HAL_KEY_TYPE_AES)   | (1 << HAL_KEY_TYPE_TKIP))
122 #define isValidKeyType(_t)      ((1 << (_t)) & VALID_KEY_TYPES)
123 
124 #define set11nTries(_series, _index) \
125         (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
126 
127 #define set11nRate(_series, _index) \
128         (SM((_series)[_index].Rate, AR_XmitRate##_index))
129 
130 #define set11nPktDurRTSCTS(_series, _index) \
131         (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\
132          ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS   ?\
133          AR_RTSCTSQual##_index : 0))
134 
135 #define set11nRateFlags(_series, _index) \
136         ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \
137         |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_GI##_index : 0) \
138         |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_STBC##_index : 0) \
139         |SM((_series)[_index].ChSel, AR_ChainSel##_index)
140 
141 /*
142  * Descriptor Access Functions
143  */
144 
145 #define VALID_PKT_TYPES \
146         ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
147          (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
148          (1<<HAL_PKT_TYPE_BEACON)|(1<<HAL_PKT_TYPE_AMPDU))
149 #define isValidPktType(_t)      ((1<<(_t)) & VALID_PKT_TYPES)
150 #define VALID_TX_RATES \
151         ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
152          (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
153 	 (1<<0x1d)|(1<<0x18)|(1<<0x1c)|(1<<0x01)|(1<<0x02)|(1<<0x03)|\
154 	 (1<<0x04)|(1<<0x05)|(1<<0x06)|(1<<0x07)|(1<<0x00))
155 /* NB: accept HT rates */
156 #define	isValidTxRate(_r)	((1<<((_r) & 0x7f)) & VALID_TX_RATES)
157 
158 static inline int
159 ar5416RateToRateTable(struct ath_hal *ah, uint8_t rate, HAL_BOOL is_ht40)
160 {
161 
162 	/*
163 	 * Handle the non-MCS rates
164 	 */
165 	switch (rate) {
166 	case /*   1 Mb */ 0x1b:
167 	case /*   1 MbS*/ 0x1b | 0x4:
168 		return (AH5416(ah)->ah_ratesArray[rate1l]);
169 	case /*   2 Mb */ 0x1a:
170 		return (AH5416(ah)->ah_ratesArray[rate2l]);
171 	case /*   2 MbS*/ 0x1a | 0x4:
172 		return (AH5416(ah)->ah_ratesArray[rate2s]);
173 	case /* 5.5 Mb */ 0x19:
174 		return (AH5416(ah)->ah_ratesArray[rate5_5l]);
175 	case /* 5.5 MbS*/ 0x19 | 0x4:
176 		return (AH5416(ah)->ah_ratesArray[rate5_5s]);
177 	case /*  11 Mb */ 0x18:
178 		return (AH5416(ah)->ah_ratesArray[rate11l]);
179 	case /*  11 MbS*/ 0x18 | 0x4:
180 		return (AH5416(ah)->ah_ratesArray[rate11s]);
181 	}
182 
183 	/* OFDM rates */
184 	switch (rate) {
185 	case /*   6 Mb */ 0x0b:
186 		return (AH5416(ah)->ah_ratesArray[rate6mb]);
187 	case /*   9 Mb */ 0x0f:
188 		return (AH5416(ah)->ah_ratesArray[rate9mb]);
189 	case /*  12 Mb */ 0x0a:
190 		return (AH5416(ah)->ah_ratesArray[rate12mb]);
191 	case /*  18 Mb */ 0x0e:
192 		return (AH5416(ah)->ah_ratesArray[rate18mb]);
193 	case /*  24 Mb */ 0x09:
194 		return (AH5416(ah)->ah_ratesArray[rate24mb]);
195 	case /*  36 Mb */ 0x0d:
196 		return (AH5416(ah)->ah_ratesArray[rate36mb]);
197 	case /*  48 Mb */ 0x08:
198 		return (AH5416(ah)->ah_ratesArray[rate48mb]);
199 	case /*  54 Mb */ 0x0c:
200 		return (AH5416(ah)->ah_ratesArray[rate54mb]);
201 	}
202 
203 	/*
204 	 * Handle HT20/HT40 - we only have to do MCS0-7;
205 	 * there's no stream differences.
206 	 */
207 	if ((rate & 0x80) && is_ht40) {
208 		return (AH5416(ah)->ah_ratesArray[rateHt40_0 + (rate & 0x7)]);
209 	} else if (rate & 0x80) {
210 		return (AH5416(ah)->ah_ratesArray[rateHt20_0 + (rate & 0x7)]);
211 	}
212 
213 	/* XXX default (eg XR, bad bad person!) */
214 	return (AH5416(ah)->ah_ratesArray[rate6mb]);
215 }
216 
217 /*
218  * Return the TX power to be used for the given rate/chains/TX power.
219  *
220  * There are a bunch of tweaks to make to a given TX power based on
221  * the current configuration, so...
222  */
223 static uint16_t
224 ar5416GetTxRatePower(struct ath_hal *ah, uint8_t rate, uint8_t tx_chainmask,
225     uint16_t txPower, HAL_BOOL is_ht40)
226 {
227 	int n_txpower, max_txpower;
228 	const int cck_ofdm_delta = 2;
229 #define	EEP_MINOR(_ah) \
230 	(AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
231 #define	IS_EEP_MINOR_V2(_ah)	(EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
232 
233 	/* Take a copy ; we may underflow and thus need to clamp things */
234 	n_txpower = txPower;
235 
236 	/* HT40? Need to adjust the TX power by this */
237 	if (is_ht40)
238 		n_txpower += AH5416(ah)->ah_ht40PowerIncForPdadc;
239 
240 	/*
241 	 * Merlin? Offset the target TX power offset - it defaults to
242 	 * starting at -5.0dBm, but that can change!
243 	 *
244 	 * Kiwi/Kite? Always -5.0dBm offset.
245 	 */
246 	if (AR_SREV_KIWI_10_OR_LATER(ah)) {
247 		n_txpower -= (AR5416_PWR_TABLE_OFFSET_DB * 2);
248 	} else if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
249 		int8_t pwr_table_offset = 0;
250 		/* This is in dBm, convert to 1/2 dBm */
251 		(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET,
252 		    &pwr_table_offset);
253 		n_txpower -= (pwr_table_offset * 2);
254 	}
255 
256 	/*
257 	 * If Open-loop TX power control is used, the CCK rates need
258 	 * to be offset by that.
259 	 *
260 	 * Rates: 2S, 2L, 1S, 1L, 5.5S, 5.5L
261 	 *
262 	 * XXX Odd, we don't have a PHY table entry for long preamble
263 	 * 1mbit CCK?
264 	 */
265 	if (AR_SREV_MERLIN_20_OR_LATER(ah) &&
266 	    ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
267 
268 		if (rate == 0x19 || rate == 0x1a || rate == 0x1b ||
269 		    rate == (0x19 | 0x04) || rate == (0x1a | 0x04) ||
270 		    rate == (0x1b | 0x04)) {
271 			n_txpower -= cck_ofdm_delta;
272 		}
273 	}
274 
275 	/*
276 	 * We're now offset by the same amount that the static maximum
277 	 * PHY power tables are.  So, clamp the value based on that rate.
278 	 */
279 	max_txpower = ar5416RateToRateTable(ah, rate, is_ht40);
280 #if 0
281 	ath_hal_printf(ah, "%s: n_txpower = %d, max_txpower = %d, "
282 	    "rate = 0x%x , is_ht40 = %d\n",
283 	    __func__,
284 	    n_txpower,
285 	    max_txpower,
286 	    rate,
287 	    is_ht40);
288 #endif
289 	n_txpower = MIN(max_txpower, n_txpower);
290 
291 	/*
292 	 * We don't have to offset the TX power for two or three
293 	 * chain operation here - it's done by the AR_PHY_POWER_TX_SUB
294 	 * register setting via the EEPROM.
295 	 *
296 	 * So for vendors that programmed the maximum target power assuming
297 	 * that 2/3 chains are always on, things will just plain work.
298 	 * (They won't reach that target power if only one chain is on, but
299 	 * that's a different problem.)
300 	 */
301 
302 	/* Over/underflow? Adjust */
303 	if (n_txpower < 0)
304 		n_txpower = 0;
305 	else if (n_txpower > 63)
306 		n_txpower = 63;
307 
308 	/*
309 	 * For some odd reason the AR9160 with txpower=0 results in a
310 	 * much higher (max?) TX power.  So, if it's a chipset before
311 	 * AR9220/AR9280, just clamp the minimum value at 1.
312 	 */
313 	if ((! AR_SREV_MERLIN_10_OR_LATER(ah)) && (n_txpower == 0))
314 		n_txpower = 1;
315 
316 	return (n_txpower);
317 #undef	EEP_MINOR
318 #undef	IS_EEP_MINOR_V2
319 }
320 
321 HAL_BOOL
322 ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
323 	u_int pktLen,
324 	u_int hdrLen,
325 	HAL_PKT_TYPE type,
326 	u_int txPower,
327 	u_int txRate0, u_int txTries0,
328 	u_int keyIx,
329 	u_int antMode,
330 	u_int flags,
331 	u_int rtsctsRate,
332 	u_int rtsctsDuration,
333 	u_int compicvLen,
334 	u_int compivLen,
335 	u_int comp)
336 {
337 #define	RTSCTS	(HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
338 	struct ar5416_desc *ads = AR5416DESC(ds);
339 	struct ath_hal_5416 *ahp = AH5416(ah);
340 
341 	(void) hdrLen;
342 
343 	HALASSERT(txTries0 != 0);
344 	HALASSERT(isValidPktType(type));
345 	HALASSERT(isValidTxRate(txRate0));
346 	HALASSERT((flags & RTSCTS) != RTSCTS);
347 	/* XXX validate antMode */
348 
349         txPower = (txPower + AH5212(ah)->ah_txPowerIndexOffset);
350         if (txPower > 63)
351 		txPower = 63;
352 
353 	/*
354 	 * XXX For now, just assume that this isn't a HT40 frame.
355 	 * It'll get over-ridden by the multi-rate TX power setup.
356 	 */
357 	if (AH5212(ah)->ah_tpcEnabled) {
358 		txPower = ar5416GetTxRatePower(ah, txRate0,
359 		    ahp->ah_tx_chainmask,
360 		    txPower,
361 		    AH_FALSE);
362 	}
363 
364 	ads->ds_ctl0 = (pktLen & AR_FrameLen)
365 		     | (txPower << AR_XmitPower_S)
366 		     | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
367 		     | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
368 		     | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
369 		     ;
370 	ads->ds_ctl1 = (type << AR_FrameType_S)
371 		     | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
372 		     | (flags & HAL_TXDESC_HWTS ? AR_InsertTS : 0)
373                      ;
374 	ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0)
375 		     | (flags & HAL_TXDESC_DURENA ? AR_DurUpdateEn : 0)
376 		     ;
377 	ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S)
378 		     ;
379 	ads->ds_ctl4 = 0;
380 	ads->ds_ctl5 = 0;
381 	ads->ds_ctl6 = 0;
382 	ads->ds_ctl7 = SM(ahp->ah_tx_chainmask, AR_ChainSel0)
383 		     | SM(ahp->ah_tx_chainmask, AR_ChainSel1)
384 		     | SM(ahp->ah_tx_chainmask, AR_ChainSel2)
385 		     | SM(ahp->ah_tx_chainmask, AR_ChainSel3)
386 		     ;
387 	ads->ds_ctl8 = SM(0, AR_AntCtl0);
388 	ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(txPower, AR_XmitPower1);
389 	ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(txPower, AR_XmitPower2);
390 	ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(txPower, AR_XmitPower3);
391 
392 	if (keyIx != HAL_TXKEYIX_INVALID) {
393 		/* XXX validate key index */
394 		ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
395 		ads->ds_ctl0 |= AR_DestIdxValid;
396 		ads->ds_ctl6 |= SM(ahp->ah_keytype[keyIx], AR_EncrType);
397 	}
398 	if (flags & RTSCTS) {
399 		if (!isValidTxRate(rtsctsRate)) {
400 			HALDEBUG(ah, HAL_DEBUG_ANY,
401 			    "%s: invalid rts/cts rate 0x%x\n",
402 			    __func__, rtsctsRate);
403 			return AH_FALSE;
404 		}
405 		/* XXX validate rtsctsDuration */
406 		ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
407 			     | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
408 			     ;
409 		ads->ds_ctl7 |= (rtsctsRate << AR_RTSCTSRate_S);
410 	}
411 
412 	/*
413 	 * Set the TX antenna to 0 for Kite
414 	 * To preserve existing behaviour, also set the TPC bits to 0;
415 	 * when TPC is enabled these should be filled in appropriately.
416 	 *
417 	 * XXX TODO: when doing TPC, set the TX power up appropriately?
418 	 */
419 	if (AR_SREV_KITE(ah)) {
420 		ads->ds_ctl8 = SM(0, AR_AntCtl0);
421 		ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(0, AR_XmitPower1);
422 		ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(0, AR_XmitPower2);
423 		ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(0, AR_XmitPower3);
424 	}
425 	return AH_TRUE;
426 #undef RTSCTS
427 }
428 
429 HAL_BOOL
430 ar5416SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
431 	u_int txRate1, u_int txTries1,
432 	u_int txRate2, u_int txTries2,
433 	u_int txRate3, u_int txTries3)
434 {
435 	struct ar5416_desc *ads = AR5416DESC(ds);
436 
437 	if (txTries1) {
438 		HALASSERT(isValidTxRate(txRate1));
439 		ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1);
440 		ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
441 	}
442 	if (txTries2) {
443 		HALASSERT(isValidTxRate(txRate2));
444 		ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2);
445 		ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
446 	}
447 	if (txTries3) {
448 		HALASSERT(isValidTxRate(txRate3));
449 		ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3);
450 		ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
451 	}
452 	return AH_TRUE;
453 }
454 
455 /*
456  * XXX TODO: Figure out if AR_InsertTS is required on all sub-frames
457  * of a TX descriptor.
458  */
459 HAL_BOOL
460 ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
461 	HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int descId,
462 	u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
463 	const struct ath_desc *ds0)
464 {
465 	struct ar5416_desc *ads = AR5416DESC(ds);
466 	uint32_t segLen = segLenList[0];
467 
468 	HALASSERT((segLen &~ AR_BufLen) == 0);
469 
470 	ds->ds_data = bufAddrList[0];
471 
472 	if (firstSeg) {
473 		/*
474 		 * First descriptor, don't clobber xmit control data
475 		 * setup by ar5212SetupTxDesc.
476 		 */
477 		ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
478 	} else if (lastSeg) {		/* !firstSeg && lastSeg */
479 		/*
480 		 * Last descriptor in a multi-descriptor frame,
481 		 * copy the multi-rate transmit parameters from
482 		 * the first frame for processing on completion.
483 		 */
484 		ads->ds_ctl1 = segLen;
485 #ifdef AH_NEED_DESC_SWAP
486 		ads->ds_ctl0 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl0)
487 		    & AR_TxIntrReq;
488 		ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2);
489 		ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3);
490 		/* ctl6 - we only need encrtype; the rest are blank */
491 		ads->ds_ctl6 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl6 & AR_EncrType);
492 #else
493 		ads->ds_ctl0 = AR5416DESC_CONST(ds0)->ds_ctl0 & AR_TxIntrReq;
494 		ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
495 		ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
496 		/* ctl6 - we only need encrtype; the rest are blank */
497 		ads->ds_ctl6 = AR5416DESC_CONST(ds0)->ds_ctl6 & AR_EncrType;
498 #endif
499 	} else {			/* !firstSeg && !lastSeg */
500 		/*
501 		 * Intermediate descriptor in a multi-descriptor frame.
502 		 */
503 #ifdef AH_NEED_DESC_SWAP
504 		ads->ds_ctl0 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl0)
505 		    & AR_TxIntrReq;
506 		ads->ds_ctl6 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl6 & AR_EncrType);
507 #else
508 		ads->ds_ctl0 = AR5416DESC_CONST(ds0)->ds_ctl0 & AR_TxIntrReq;
509 		ads->ds_ctl6 = AR5416DESC_CONST(ds0)->ds_ctl6 & AR_EncrType;
510 #endif
511 		ads->ds_ctl1 = segLen | AR_TxMore;
512 		ads->ds_ctl2 = 0;
513 		ads->ds_ctl3 = 0;
514 	}
515 	/* XXX only on last descriptor? */
516 	OS_MEMZERO(ads->u.tx.status, sizeof(ads->u.tx.status));
517 	return AH_TRUE;
518 }
519 
520 /*
521  * NB: cipher is no longer used, it's calculated.
522  */
523 HAL_BOOL
524 ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds,
525 	HAL_DMA_ADDR *bufAddrList,
526 	uint32_t *segLenList,
527 	u_int pktLen,
528 	u_int hdrLen,
529 	HAL_PKT_TYPE type,
530 	u_int keyIx,
531 	HAL_CIPHER cipher,
532 	uint8_t delims,
533 	HAL_BOOL firstSeg,
534 	HAL_BOOL lastSeg,
535 	HAL_BOOL lastAggr)
536 {
537 	struct ar5416_desc *ads = AR5416DESC(ds);
538 	uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);
539 	struct ath_hal_5416 *ahp = AH5416(ah);
540 	u_int segLen = segLenList[0];
541 
542 	int isaggr = 0;
543 	uint32_t last_aggr = 0;
544 
545 	(void) hdrLen;
546 	(void) ah;
547 
548 	HALASSERT((segLen &~ AR_BufLen) == 0);
549 	ds->ds_data = bufAddrList[0];
550 
551 	HALASSERT(isValidPktType(type));
552 	if (type == HAL_PKT_TYPE_AMPDU) {
553 		type = HAL_PKT_TYPE_NORMAL;
554 		isaggr = 1;
555 		if (lastAggr == AH_FALSE)
556 			last_aggr = AR_MoreAggr;
557 	}
558 
559 	/*
560 	 * Since this function is called before any of the other
561 	 * descriptor setup functions (at least in this particular
562 	 * 802.11n aggregation implementation), always bzero() the
563 	 * descriptor. Previously this would be done for all but
564 	 * the first segment.
565 	 * XXX TODO: figure out why; perhaps I'm using this slightly
566 	 * XXX incorrectly.
567 	 */
568 	OS_MEMZERO(ds->ds_hw, AR5416_DESC_TX_CTL_SZ);
569 
570 	/*
571 	 * Note: VEOL should only be for the last descriptor in the chain.
572 	 */
573 	ads->ds_ctl0 = (pktLen & AR_FrameLen);
574 
575 	/*
576 	 * For aggregates:
577 	 * + IsAggr must be set for all descriptors of all subframes of
578 	 *   the aggregate
579 	 * + MoreAggr must be set for all descriptors of all subframes
580 	 *   of the aggregate EXCEPT the last subframe;
581 	 * + MoreAggr must be _CLEAR_ for all descrpitors of the last
582 	 *   subframe of the aggregate.
583 	 */
584 	ads->ds_ctl1 = (type << AR_FrameType_S)
585 			| (isaggr ? (AR_IsAggr | last_aggr) : 0);
586 
587 	ads->ds_ctl2 = 0;
588 	ads->ds_ctl3 = 0;
589 	if (keyIx != HAL_TXKEYIX_INVALID) {
590 		/* XXX validate key index */
591 		ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
592 		ads->ds_ctl0 |= AR_DestIdxValid;
593 	}
594 
595 	ads->ds_ctl6 |= SM(ahp->ah_keytype[keyIx], AR_EncrType);
596 	if (isaggr) {
597 		ads->ds_ctl6 |= SM(delims, AR_PadDelim);
598 	}
599 
600 	if (firstSeg) {
601 		ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
602 	} else if (lastSeg) {           /* !firstSeg && lastSeg */
603 		ads->ds_ctl0 = 0;
604 		ads->ds_ctl1 |= segLen;
605 	} else {                        /* !firstSeg && !lastSeg */
606 		/*
607 		 * Intermediate descriptor in a multi-descriptor frame.
608 		 */
609 		ads->ds_ctl0 = 0;
610 		ads->ds_ctl1 |= segLen | AR_TxMore;
611 	}
612 	ds_txstatus[0] = ds_txstatus[1] = 0;
613 	ds_txstatus[9] &= ~AR_TxDone;
614 
615 	return AH_TRUE;
616 }
617 
618 HAL_BOOL
619 ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds,
620 	u_int aggrLen, u_int flags, u_int txPower,
621 	u_int txRate0, u_int txTries0, u_int antMode,
622 	u_int rtsctsRate, u_int rtsctsDuration)
623 {
624 #define RTSCTS  (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
625 	struct ar5416_desc *ads = AR5416DESC(ds);
626 	struct ath_hal_5212 *ahp = AH5212(ah);
627 
628 	HALASSERT(txTries0 != 0);
629 	HALASSERT(isValidTxRate(txRate0));
630 	HALASSERT((flags & RTSCTS) != RTSCTS);
631 	/* XXX validate antMode */
632 
633 	txPower = (txPower + ahp->ah_txPowerIndexOffset );
634 	if(txPower > 63)  txPower=63;
635 
636 	ads->ds_ctl0 |= (txPower << AR_XmitPower_S)
637 		| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
638 		| (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
639 		| (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
640 	ads->ds_ctl1 |= (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
641 	ads->ds_ctl2 |= SM(txTries0, AR_XmitDataTries0);
642 	ads->ds_ctl3 |= (txRate0 << AR_XmitRate0_S);
643 	ads->ds_ctl7 = SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel0)
644 		| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel1)
645 		| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel2)
646 		| SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel3);
647 
648 	/* NB: no V1 WAR */
649 	ads->ds_ctl8 = SM(0, AR_AntCtl0);
650 	ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(txPower, AR_XmitPower1);
651 	ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(txPower, AR_XmitPower2);
652 	ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(txPower, AR_XmitPower3);
653 
654 	ads->ds_ctl6 &= ~(0xffff);
655 	ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
656 
657 	if (flags & RTSCTS) {
658 		/* XXX validate rtsctsDuration */
659 		ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
660 			| (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
661 	}
662 
663 	/*
664 	 * Set the TX antenna to 0 for Kite
665 	 * To preserve existing behaviour, also set the TPC bits to 0;
666 	 * when TPC is enabled these should be filled in appropriately.
667 	 */
668 	if (AR_SREV_KITE(ah)) {
669 		ads->ds_ctl8 = SM(0, AR_AntCtl0);
670 		ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(0, AR_XmitPower1);
671 		ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(0, AR_XmitPower2);
672 		ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(0, AR_XmitPower3);
673 	}
674 
675 	return AH_TRUE;
676 #undef RTSCTS
677 }
678 
679 HAL_BOOL
680 ar5416SetupLastTxDesc(struct ath_hal *ah, struct ath_desc *ds,
681 		const struct ath_desc *ds0)
682 {
683 	struct ar5416_desc *ads = AR5416DESC(ds);
684 
685 	ads->ds_ctl1 &= ~AR_MoreAggr;
686 	ads->ds_ctl6 &= ~AR_PadDelim;
687 
688 	/* hack to copy rate info to last desc for later processing */
689 #ifdef AH_NEED_DESC_SWAP
690 	ads->ds_ctl2 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl2);
691 	ads->ds_ctl3 = __bswap32(AR5416DESC_CONST(ds0)->ds_ctl3);
692 #else
693 	ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
694 	ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
695 #endif
696 	return AH_TRUE;
697 }
698 
699 #ifdef AH_NEED_DESC_SWAP
700 /* Swap transmit descriptor */
701 static __inline void
702 ar5416SwapTxDesc(struct ath_desc *ds)
703 {
704 	ds->ds_data = __bswap32(ds->ds_data);
705 	ds->ds_ctl0 = __bswap32(ds->ds_ctl0);
706 	ds->ds_ctl1 = __bswap32(ds->ds_ctl1);
707 	ds->ds_hw[0] = __bswap32(ds->ds_hw[0]);
708 	ds->ds_hw[1] = __bswap32(ds->ds_hw[1]);
709 	ds->ds_hw[2] = __bswap32(ds->ds_hw[2]);
710 	ds->ds_hw[3] = __bswap32(ds->ds_hw[3]);
711 }
712 #endif
713 
714 /*
715  * Processing of HW TX descriptor.
716  */
717 HAL_STATUS
718 ar5416ProcTxDesc(struct ath_hal *ah,
719 	struct ath_desc *ds, struct ath_tx_status *ts)
720 {
721 	struct ar5416_desc *ads = AR5416DESC(ds);
722 	uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);
723 
724 #ifdef AH_NEED_DESC_SWAP
725 	if ((ds_txstatus[9] & __bswap32(AR_TxDone)) == 0)
726 		return HAL_EINPROGRESS;
727 	ar5416SwapTxDesc(ds);
728 #else
729 	if ((ds_txstatus[9] & AR_TxDone) == 0)
730 		return HAL_EINPROGRESS;
731 #endif
732 
733 	/* Update software copies of the HW status */
734 	ts->ts_seqnum = MS(ds_txstatus[9], AR_SeqNum);
735 	ts->ts_tstamp = AR_SendTimestamp(ds_txstatus);
736 	ts->ts_tid = MS(ds_txstatus[9], AR_TxTid);
737 
738 	ts->ts_status = 0;
739 	if (ds_txstatus[1] & AR_ExcessiveRetries)
740 		ts->ts_status |= HAL_TXERR_XRETRY;
741 	if (ds_txstatus[1] & AR_Filtered)
742 		ts->ts_status |= HAL_TXERR_FILT;
743 	if (ds_txstatus[1] & AR_FIFOUnderrun)
744 		ts->ts_status |= HAL_TXERR_FIFO;
745 	if (ds_txstatus[9] & AR_TxOpExceeded)
746 		ts->ts_status |= HAL_TXERR_XTXOP;
747 	if (ds_txstatus[1] & AR_TxTimerExpired)
748 		ts->ts_status |= HAL_TXERR_TIMER_EXPIRED;
749 
750 	ts->ts_flags  = 0;
751 	if (ds_txstatus[0] & AR_TxBaStatus) {
752 		ts->ts_flags |= HAL_TX_BA;
753 		ts->ts_ba_low = AR_BaBitmapLow(ds_txstatus);
754 		ts->ts_ba_high = AR_BaBitmapHigh(ds_txstatus);
755 	}
756 	if (ds->ds_ctl1 & AR_IsAggr)
757 		ts->ts_flags |= HAL_TX_AGGR;
758 	if (ds_txstatus[1] & AR_DescCfgErr)
759 		ts->ts_flags |= HAL_TX_DESC_CFG_ERR;
760 	if (ds_txstatus[1] & AR_TxDataUnderrun)
761 		ts->ts_flags |= HAL_TX_DATA_UNDERRUN;
762 	if (ds_txstatus[1] & AR_TxDelimUnderrun)
763 		ts->ts_flags |= HAL_TX_DELIM_UNDERRUN;
764 
765 	/*
766 	 * Extract the transmit rate used and mark the rate as
767 	 * ``alternate'' if it wasn't the series 0 rate.
768 	 */
769 	ts->ts_finaltsi =  MS(ds_txstatus[9], AR_FinalTxIdx);
770 	switch (ts->ts_finaltsi) {
771 	case 0:
772 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
773 		break;
774 	case 1:
775 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1);
776 		break;
777 	case 2:
778 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2);
779 		break;
780 	case 3:
781 		ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3);
782 		break;
783 	}
784 
785 	ts->ts_rssi = MS(ds_txstatus[5], AR_TxRSSICombined);
786 	ts->ts_rssi_ctl[0] = MS(ds_txstatus[0], AR_TxRSSIAnt00);
787 	ts->ts_rssi_ctl[1] = MS(ds_txstatus[0], AR_TxRSSIAnt01);
788 	ts->ts_rssi_ctl[2] = MS(ds_txstatus[0], AR_TxRSSIAnt02);
789 	ts->ts_rssi_ext[0] = MS(ds_txstatus[5], AR_TxRSSIAnt10);
790 	ts->ts_rssi_ext[1] = MS(ds_txstatus[5], AR_TxRSSIAnt11);
791 	ts->ts_rssi_ext[2] = MS(ds_txstatus[5], AR_TxRSSIAnt12);
792 	ts->ts_evm0 = AR_TxEVM0(ds_txstatus);
793 	ts->ts_evm1 = AR_TxEVM1(ds_txstatus);
794 	ts->ts_evm2 = AR_TxEVM2(ds_txstatus);
795 
796 	ts->ts_shortretry = MS(ds_txstatus[1], AR_RTSFailCnt);
797 	ts->ts_longretry = MS(ds_txstatus[1], AR_DataFailCnt);
798 	/*
799 	 * The retry count has the number of un-acked tries for the
800 	 * final series used.  When doing multi-rate retry we must
801 	 * fixup the retry count by adding in the try counts for
802 	 * each series that was fully-processed.  Beware that this
803 	 * takes values from the try counts in the final descriptor.
804 	 * These are not required by the hardware.  We assume they
805 	 * are placed there by the driver as otherwise we have no
806 	 * access and the driver can't do the calculation because it
807 	 * doesn't know the descriptor format.
808 	 */
809 	switch (ts->ts_finaltsi) {
810 	case 3: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries2);
811 	case 2: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries1);
812 	case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0);
813 	}
814 
815 	/*
816 	 * These fields are not used. Zero these to preserve compatibility
817 	 * with existing drivers.
818 	 */
819 	ts->ts_virtcol = MS(ads->ds_ctl1, AR_VirtRetryCnt);
820 	ts->ts_antenna = 0; /* We don't switch antennas on Owl*/
821 
822 	/* handle tx trigger level changes internally */
823 	if ((ts->ts_status & HAL_TXERR_FIFO) ||
824 	    (ts->ts_flags & (HAL_TX_DATA_UNDERRUN | HAL_TX_DELIM_UNDERRUN)))
825 		ar5212UpdateTxTrigLevel(ah, AH_TRUE);
826 
827 	return HAL_OK;
828 }
829 
830 HAL_BOOL
831 ar5416SetGlobalTxTimeout(struct ath_hal *ah, u_int tu)
832 {
833 	struct ath_hal_5416 *ahp = AH5416(ah);
834 
835 	if (tu > 0xFFFF) {
836 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad global tx timeout %u\n",
837 		    __func__, tu);
838 		/* restore default handling */
839 		ahp->ah_globaltxtimeout = (u_int) -1;
840 		return AH_FALSE;
841 	}
842 	OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
843 	ahp->ah_globaltxtimeout = tu;
844 	return AH_TRUE;
845 }
846 
847 u_int
848 ar5416GetGlobalTxTimeout(struct ath_hal *ah)
849 {
850 	return MS(OS_REG_READ(ah, AR_GTXTO), AR_GTXTO_TIMEOUT_LIMIT);
851 }
852 
853 #define	HT_RC_2_MCS(_rc)	((_rc) & 0x0f)
854 static const u_int8_t baDurationDelta[] = {
855 	24,	//  0: BPSK
856 	12,	//  1: QPSK 1/2
857 	12,	//  2: QPSK 3/4
858 	4,	//  3: 16-QAM 1/2
859 	4,	//  4: 16-QAM 3/4
860 	4,	//  5: 64-QAM 2/3
861 	4,	//  6: 64-QAM 3/4
862 	4,	//  7: 64-QAM 5/6
863 	24,	//  8: BPSK
864 	12,	//  9: QPSK 1/2
865 	12,	// 10: QPSK 3/4
866 	4,	// 11: 16-QAM 1/2
867 	4,	// 12: 16-QAM 3/4
868 	4,	// 13: 64-QAM 2/3
869 	4,	// 14: 64-QAM 3/4
870 	4,	// 15: 64-QAM 5/6
871 };
872 
873 void
874 ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds,
875         u_int durUpdateEn, u_int rtsctsRate,
876 	HAL_11N_RATE_SERIES series[], u_int nseries, u_int flags)
877 {
878 	struct ar5416_desc *ads = AR5416DESC(ds);
879 	uint32_t ds_ctl0;
880 
881 	HALASSERT(nseries == 4);
882 	(void)nseries;
883 
884 	/*
885 	 * Only one of RTS and CTS enable must be set.
886 	 * If a frame has both set, just do RTS protection -
887 	 * that's enough to satisfy legacy protection.
888 	 */
889 	if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
890 		ds_ctl0 = ads->ds_ctl0;
891 
892 		if (flags & HAL_TXDESC_RTSENA) {
893 			ds_ctl0 &= ~AR_CTSEnable;
894 			ds_ctl0 |= AR_RTSEnable;
895 		} else {
896 			ds_ctl0 &= ~AR_RTSEnable;
897 			ds_ctl0 |= AR_CTSEnable;
898 		}
899 
900 		ads->ds_ctl0 = ds_ctl0;
901 	} else {
902 		ads->ds_ctl0 =
903 		    (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
904 	}
905 
906 	ads->ds_ctl2 = set11nTries(series, 0)
907 		     | set11nTries(series, 1)
908 		     | set11nTries(series, 2)
909 		     | set11nTries(series, 3)
910 		     | (durUpdateEn ? AR_DurUpdateEn : 0);
911 
912 	ads->ds_ctl3 = set11nRate(series, 0)
913 		     | set11nRate(series, 1)
914 		     | set11nRate(series, 2)
915 		     | set11nRate(series, 3);
916 
917 	ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
918 		     | set11nPktDurRTSCTS(series, 1);
919 
920 	ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
921 		     | set11nPktDurRTSCTS(series, 3);
922 
923 	ads->ds_ctl7 = set11nRateFlags(series, 0)
924 		     | set11nRateFlags(series, 1)
925 		     | set11nRateFlags(series, 2)
926 		     | set11nRateFlags(series, 3)
927 		     | SM(rtsctsRate, AR_RTSCTSRate);
928 
929 	/*
930 	 * Doing per-packet TPC - update the TX power for the first
931 	 * field; program in the other series.
932 	 */
933 	if (AH5212(ah)->ah_tpcEnabled) {
934 		uint32_t ds_ctl0;
935 		uint16_t txPower;
936 
937 		/* Modify the tx power field for rate 0 */
938 		txPower = ar5416GetTxRatePower(ah, series[0].Rate,
939 		    series[0].ChSel,
940 		    series[0].tx_power_cap,
941 		    !! (series[0].RateFlags & HAL_RATESERIES_2040));
942 		ds_ctl0 = ads->ds_ctl0 & ~AR_XmitPower;
943 		ds_ctl0 |= (txPower << AR_XmitPower_S);
944 		ads->ds_ctl0 = ds_ctl0;
945 
946 		/*
947 		 * Override the whole descriptor field for each TX power.
948 		 *
949 		 * This will need changing if we ever support antenna control
950 		 * programming.
951 		 */
952 		txPower = ar5416GetTxRatePower(ah, series[1].Rate,
953 		    series[1].ChSel,
954 		    series[1].tx_power_cap,
955 		    !! (series[1].RateFlags & HAL_RATESERIES_2040));
956 		ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(txPower, AR_XmitPower1);
957 
958 		txPower = ar5416GetTxRatePower(ah, series[2].Rate,
959 		    series[2].ChSel,
960 		    series[2].tx_power_cap,
961 		    !! (series[2].RateFlags & HAL_RATESERIES_2040));
962 		ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(txPower, AR_XmitPower2);
963 
964 		txPower = ar5416GetTxRatePower(ah, series[3].Rate,
965 		    series[3].ChSel,
966 		    series[3].tx_power_cap,
967 		    !! (series[3].RateFlags & HAL_RATESERIES_2040));
968 		ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(txPower, AR_XmitPower3);
969 	}
970 }
971 
972 /*
973  * Note: this should be called before calling ar5416SetBurstDuration()
974  * (if it is indeed called) in order to ensure that the burst duration
975  * is correctly updated with the BA delta workaround.
976  */
977 void
978 ar5416Set11nAggrFirst(struct ath_hal *ah, struct ath_desc *ds, u_int aggrLen,
979     u_int numDelims)
980 {
981 	struct ar5416_desc *ads = AR5416DESC(ds);
982 	uint32_t flags;
983 	uint32_t burstDur;
984 	uint8_t rate;
985 
986 	ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
987 
988 	ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
989 	ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
990 	ads->ds_ctl6 |= SM(numDelims, AR_PadDelim);
991 
992 	if (! AR_SREV_MERLIN_10_OR_LATER(ah)) {
993 		/*
994 		 * XXX It'd be nice if I were passed in the rate scenario
995 		 * at this point..
996 		 */
997 		rate = MS(ads->ds_ctl3, AR_XmitRate0);
998 		flags = ads->ds_ctl0 & (AR_CTSEnable | AR_RTSEnable);
999 		/*
1000 		 * WAR - MAC assumes normal ACK time instead of
1001 		 * block ACK while computing packet duration.
1002 		 * Add this delta to the burst duration in the descriptor.
1003 		 */
1004 		if (flags && (ads->ds_ctl1 & AR_IsAggr)) {
1005 			burstDur = baDurationDelta[HT_RC_2_MCS(rate)];
1006 			ads->ds_ctl2 &= ~(AR_BurstDur);
1007 			ads->ds_ctl2 |= SM(burstDur, AR_BurstDur);
1008 		}
1009 	}
1010 }
1011 
1012 void
1013 ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims)
1014 {
1015 	struct ar5416_desc *ads = AR5416DESC(ds);
1016 	uint32_t *ds_txstatus = AR5416_DS_TXSTATUS(ah,ads);
1017 
1018 	ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1019 
1020 	ads->ds_ctl6 &= ~AR_PadDelim;
1021 	ads->ds_ctl6 |= SM(numDelims, AR_PadDelim);
1022 	ads->ds_ctl6 &= ~AR_AggrLen;
1023 
1024 	/*
1025 	 * Clear the TxDone status here, may need to change
1026 	 * func name to reflect this
1027 	 */
1028 	ds_txstatus[9] &= ~AR_TxDone;
1029 }
1030 
1031 void
1032 ar5416Set11nAggrLast(struct ath_hal *ah, struct ath_desc *ds)
1033 {
1034 	struct ar5416_desc *ads = AR5416DESC(ds);
1035 
1036 	ads->ds_ctl1 |= AR_IsAggr;
1037 	ads->ds_ctl1 &= ~AR_MoreAggr;
1038 	ads->ds_ctl6 &= ~AR_PadDelim;
1039 }
1040 
1041 void
1042 ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds)
1043 {
1044 	struct ar5416_desc *ads = AR5416DESC(ds);
1045 
1046 	ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1047 	ads->ds_ctl6 &= ~AR_PadDelim;
1048 	ads->ds_ctl6 &= ~AR_AggrLen;
1049 }
1050 
1051 void
1052 ar5416Set11nVirtualMoreFrag(struct ath_hal *ah, struct ath_desc *ds,
1053     u_int vmf)
1054 {
1055 	struct ar5416_desc *ads = AR5416DESC(ds);
1056 	if (vmf)
1057 		ads->ds_ctl0 |= AR_VirtMoreFrag;
1058 	else
1059 		ads->ds_ctl0 &= ~AR_VirtMoreFrag;
1060 }
1061 
1062 /*
1063  * Program the burst duration, with the included BA delta if it's
1064  * applicable.
1065  */
1066 void
1067 ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds,
1068                                                   u_int burstDuration)
1069 {
1070 	struct ar5416_desc *ads = AR5416DESC(ds);
1071 	uint32_t burstDur = 0;
1072 	uint8_t rate;
1073 
1074 	if (! AR_SREV_MERLIN_10_OR_LATER(ah)) {
1075 		/*
1076 		 * XXX It'd be nice if I were passed in the rate scenario
1077 		 * at this point..
1078 		 */
1079 		rate = MS(ads->ds_ctl3, AR_XmitDataTries0);
1080 		/*
1081 		 * WAR - MAC assumes normal ACK time instead of
1082 		 * block ACK while computing packet duration.
1083 		 * Add this delta to the burst duration in the descriptor.
1084 		 */
1085 		if (ads->ds_ctl1 & AR_IsAggr) {
1086 			burstDur = baDurationDelta[HT_RC_2_MCS(rate)];
1087 		}
1088 	}
1089 
1090 	ads->ds_ctl2 &= ~AR_BurstDur;
1091 	ads->ds_ctl2 |= SM(burstDur + burstDuration, AR_BurstDur);
1092 }
1093 
1094 /*
1095  * Retrieve the rate table from the given TX completion descriptor
1096  */
1097 HAL_BOOL
1098 ar5416GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)
1099 {
1100 	const struct ar5416_desc *ads = AR5416DESC_CONST(ds0);
1101 
1102 	rates[0] = MS(ads->ds_ctl3, AR_XmitRate0);
1103 	rates[1] = MS(ads->ds_ctl3, AR_XmitRate1);
1104 	rates[2] = MS(ads->ds_ctl3, AR_XmitRate2);
1105 	rates[3] = MS(ads->ds_ctl3, AR_XmitRate3);
1106 
1107 	tries[0] = MS(ads->ds_ctl2, AR_XmitDataTries0);
1108 	tries[1] = MS(ads->ds_ctl2, AR_XmitDataTries1);
1109 	tries[2] = MS(ads->ds_ctl2, AR_XmitDataTries2);
1110 	tries[3] = MS(ads->ds_ctl2, AR_XmitDataTries3);
1111 
1112 	return AH_TRUE;
1113 }
1114 
1115 
1116 /*
1117  * TX queue management routines - AR5416 and later chipsets
1118  */
1119 
1120 /*
1121  * Allocate and initialize a tx DCU/QCU combination.
1122  */
1123 int
1124 ar5416SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
1125 	const HAL_TXQ_INFO *qInfo)
1126 {
1127 	struct ath_hal_5212 *ahp = AH5212(ah);
1128 	HAL_TX_QUEUE_INFO *qi;
1129 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
1130 	int q, defqflags;
1131 
1132 	/* by default enable OK+ERR+DESC+URN interrupts */
1133 	defqflags = HAL_TXQ_TXOKINT_ENABLE
1134 		  | HAL_TXQ_TXERRINT_ENABLE
1135 		  | HAL_TXQ_TXDESCINT_ENABLE
1136 		  | HAL_TXQ_TXURNINT_ENABLE;
1137 	/* XXX move queue assignment to driver */
1138 	switch (type) {
1139 	case HAL_TX_QUEUE_BEACON:
1140 		q = pCap->halTotalQueues-1;	/* highest priority */
1141 		defqflags |= HAL_TXQ_DBA_GATED
1142 		       | HAL_TXQ_CBR_DIS_QEMPTY
1143 		       | HAL_TXQ_ARB_LOCKOUT_GLOBAL
1144 		       | HAL_TXQ_BACKOFF_DISABLE;
1145 		break;
1146 	case HAL_TX_QUEUE_CAB:
1147 		q = pCap->halTotalQueues-2;	/* next highest priority */
1148 		defqflags |= HAL_TXQ_DBA_GATED
1149 		       | HAL_TXQ_CBR_DIS_QEMPTY
1150 		       | HAL_TXQ_CBR_DIS_BEMPTY
1151 		       | HAL_TXQ_ARB_LOCKOUT_GLOBAL
1152 		       | HAL_TXQ_BACKOFF_DISABLE;
1153 		break;
1154 	case HAL_TX_QUEUE_PSPOLL:
1155 		q = 1;				/* lowest priority */
1156 		defqflags |= HAL_TXQ_DBA_GATED
1157 		       | HAL_TXQ_CBR_DIS_QEMPTY
1158 		       | HAL_TXQ_CBR_DIS_BEMPTY
1159 		       | HAL_TXQ_ARB_LOCKOUT_GLOBAL
1160 		       | HAL_TXQ_BACKOFF_DISABLE;
1161 		break;
1162 	case HAL_TX_QUEUE_UAPSD:
1163 		q = pCap->halTotalQueues-3;	/* nextest highest priority */
1164 		if (ahp->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE) {
1165 			HALDEBUG(ah, HAL_DEBUG_ANY,
1166 			    "%s: no available UAPSD tx queue\n", __func__);
1167 			return -1;
1168 		}
1169 		break;
1170 	case HAL_TX_QUEUE_DATA:
1171 		for (q = 0; q < pCap->halTotalQueues; q++)
1172 			if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE)
1173 				break;
1174 		if (q == pCap->halTotalQueues) {
1175 			HALDEBUG(ah, HAL_DEBUG_ANY,
1176 			    "%s: no available tx queue\n", __func__);
1177 			return -1;
1178 		}
1179 		break;
1180 	default:
1181 		HALDEBUG(ah, HAL_DEBUG_ANY,
1182 		    "%s: bad tx queue type %u\n", __func__, type);
1183 		return -1;
1184 	}
1185 
1186 	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
1187 
1188 	qi = &ahp->ah_txq[q];
1189 	if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
1190 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
1191 		    __func__, q);
1192 		return -1;
1193 	}
1194 	OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
1195 	qi->tqi_type = type;
1196 	if (qInfo == AH_NULL) {
1197 		qi->tqi_qflags = defqflags;
1198 		qi->tqi_aifs = INIT_AIFS;
1199 		qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;	/* NB: do at reset */
1200 		qi->tqi_cwmax = INIT_CWMAX;
1201 		qi->tqi_shretry = INIT_SH_RETRY;
1202 		qi->tqi_lgretry = INIT_LG_RETRY;
1203 		qi->tqi_physCompBuf = 0;
1204 	} else {
1205 		qi->tqi_physCompBuf = qInfo->tqi_compBuf;
1206 		(void) ar5212SetTxQueueProps(ah, q, qInfo);
1207 	}
1208 	/* NB: must be followed by ar5212ResetTxQueue */
1209 	return q;
1210 }
1211 
1212 /*
1213  * Update the h/w interrupt registers to reflect a tx q's configuration.
1214  */
1215 static void
1216 setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
1217 {
1218 	struct ath_hal_5212 *ahp = AH5212(ah);
1219 
1220 	HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
1221 	    "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__,
1222 	    ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask,
1223 	    ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask,
1224 	    ahp->ah_txUrnInterruptMask);
1225 
1226 	OS_REG_WRITE(ah, AR_IMR_S0,
1227 		  SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
1228 		| SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
1229 	);
1230 	OS_REG_WRITE(ah, AR_IMR_S1,
1231 		  SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
1232 		| SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
1233 	);
1234 	OS_REG_RMW_FIELD(ah, AR_IMR_S2,
1235 		AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
1236 }
1237 
1238 /*
1239  * Set the retry, aifs, cwmin/max, readyTime regs for specified queue
1240  * Assumes:
1241  *  phwChannel has been set to point to the current channel
1242  */
1243 #define	TU_TO_USEC(_tu)		((_tu) << 10)
1244 HAL_BOOL
1245 ar5416ResetTxQueue(struct ath_hal *ah, u_int q)
1246 {
1247 	struct ath_hal_5212 *ahp = AH5212(ah);
1248 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
1249 	const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1250 	HAL_TX_QUEUE_INFO *qi;
1251 	uint32_t cwMin, chanCwMin, qmisc, dmisc;
1252 
1253 	if (q >= pCap->halTotalQueues) {
1254 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
1255 		    __func__, q);
1256 		return AH_FALSE;
1257 	}
1258 	qi = &ahp->ah_txq[q];
1259 	if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
1260 		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
1261 		    __func__, q);
1262 		return AH_TRUE;		/* XXX??? */
1263 	}
1264 
1265 	HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: reset queue %u\n", __func__, q);
1266 
1267 	if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
1268 		/*
1269 		 * Select cwmin according to channel type.
1270 		 * NB: chan can be NULL during attach
1271 		 */
1272 		if (chan && IEEE80211_IS_CHAN_B(chan))
1273 			chanCwMin = INIT_CWMIN_11B;
1274 		else
1275 			chanCwMin = INIT_CWMIN;
1276 		/* make sure that the CWmin is of the form (2^n - 1) */
1277 		for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1)
1278 			;
1279 	} else
1280 		cwMin = qi->tqi_cwmin;
1281 
1282 	/* set cwMin/Max and AIFS values */
1283 	OS_REG_WRITE(ah, AR_DLCL_IFS(q),
1284 		  SM(cwMin, AR_D_LCL_IFS_CWMIN)
1285 		| SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
1286 		| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
1287 
1288 	/* Set retry limit values */
1289 	OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
1290 		   SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
1291 		 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
1292 		 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
1293 		 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
1294 	);
1295 
1296 	/* NB: always enable early termination on the QCU */
1297 	qmisc = AR_Q_MISC_DCU_EARLY_TERM_REQ
1298 	      | SM(AR_Q_MISC_FSP_ASAP, AR_Q_MISC_FSP);
1299 
1300 	/* NB: always enable DCU to wait for next fragment from QCU */
1301 	dmisc = AR_D_MISC_FRAG_WAIT_EN;
1302 
1303 	/* Enable exponential backoff window */
1304 	dmisc |= AR_D_MISC_BKOFF_PERSISTENCE;
1305 
1306 	/*
1307 	 * The chip reset default is to use a DCU backoff threshold of 0x2.
1308 	 * Restore this when programming the DCU MISC register.
1309 	 */
1310 	dmisc |= 0x2;
1311 
1312 	/* multiqueue support */
1313 	if (qi->tqi_cbrPeriod) {
1314 		OS_REG_WRITE(ah, AR_QCBRCFG(q),
1315 			  SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
1316 			| SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
1317 		qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_CBR;
1318 		if (qi->tqi_cbrOverflowLimit)
1319 			qmisc |= AR_Q_MISC_CBR_EXP_CNTR_LIMIT;
1320 	}
1321 
1322 	if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
1323 		OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
1324 			  SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT)
1325 			| AR_Q_RDYTIMECFG_ENA);
1326 	}
1327 
1328 	OS_REG_WRITE(ah, AR_DCHNTIME(q),
1329 		  SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR)
1330 		| (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
1331 
1332 	if (qi->tqi_readyTime &&
1333 	    (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
1334 		qmisc |= AR_Q_MISC_RDYTIME_EXP_POLICY;
1335 	if (qi->tqi_qflags & HAL_TXQ_DBA_GATED)
1336 		qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_DBA_GATED;
1337 	if (MS(qmisc, AR_Q_MISC_FSP) != AR_Q_MISC_FSP_ASAP) {
1338 		/*
1339 		 * These are meangingful only when not scheduled asap.
1340 		 */
1341 		if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY)
1342 			qmisc |= AR_Q_MISC_CBR_INCR_DIS0;
1343 		else
1344 			qmisc &= ~AR_Q_MISC_CBR_INCR_DIS0;
1345 		if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY)
1346 			qmisc |= AR_Q_MISC_CBR_INCR_DIS1;
1347 		else
1348 			qmisc &= ~AR_Q_MISC_CBR_INCR_DIS1;
1349 	}
1350 
1351 	if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE)
1352 		dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS;
1353 	if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE)
1354 		dmisc |= AR_D_MISC_FRAG_BKOFF_EN;
1355 	if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL)
1356 		dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
1357 			    AR_D_MISC_ARB_LOCKOUT_CNTRL);
1358 	else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA)
1359 		dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR,
1360 			    AR_D_MISC_ARB_LOCKOUT_CNTRL);
1361 	if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL)
1362 		dmisc |= SM(AR_D_MISC_VIR_COL_HANDLING_IGNORE,
1363 			    AR_D_MISC_VIR_COL_HANDLING);
1364 	if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS)
1365 		dmisc |= AR_D_MISC_SEQ_NUM_INCR_DIS;
1366 
1367 	/*
1368 	 * Fillin type-dependent bits.  Most of this can be
1369 	 * removed by specifying the queue parameters in the
1370 	 * driver; it's here for backwards compatibility.
1371 	 */
1372 	switch (qi->tqi_type) {
1373 	case HAL_TX_QUEUE_BEACON:		/* beacon frames */
1374 		qmisc |= AR_Q_MISC_FSP_DBA_GATED
1375 		      |  AR_Q_MISC_BEACON_USE
1376 		      |  AR_Q_MISC_CBR_INCR_DIS1;
1377 
1378 		dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
1379 			    AR_D_MISC_ARB_LOCKOUT_CNTRL)
1380 		      |  AR_D_MISC_BEACON_USE
1381 		      |  AR_D_MISC_POST_FR_BKOFF_DIS;
1382 		break;
1383 	case HAL_TX_QUEUE_CAB:			/* CAB  frames */
1384 		/*
1385 		 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY,
1386 		 * There is an issue with the CAB Queue
1387 		 * not properly refreshing the Tx descriptor if
1388 		 * the TXE clear setting is used.
1389 		 */
1390 		qmisc |= AR_Q_MISC_FSP_DBA_GATED
1391 		      |  AR_Q_MISC_CBR_INCR_DIS1
1392 		      |  AR_Q_MISC_CBR_INCR_DIS0;
1393 		HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: CAB: tqi_readyTime = %d\n",
1394 		    __func__, qi->tqi_readyTime);
1395 		if (qi->tqi_readyTime) {
1396 			HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
1397 			    "%s: using tqi_readyTime\n", __func__);
1398 			OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
1399 			    SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) |
1400 			    AR_Q_RDYTIMECFG_ENA);
1401 		} else {
1402 			int value;
1403 			/*
1404 			 * NB: don't set default ready time if driver
1405 			 * has explicitly specified something.  This is
1406 			 * here solely for backwards compatibility.
1407 			 */
1408 			/*
1409 			 * XXX for now, hard-code a CAB interval of 70%
1410 			 * XXX of the total beacon interval.
1411 			 *
1412 			 * XXX This keeps Merlin and later based MACs
1413 			 * XXX quite a bit happier (stops stuck beacons,
1414 			 * XXX which I gather is because of such a long
1415 			 * XXX cabq time.)
1416 			 */
1417 			value = (ahp->ah_beaconInterval * 50 / 100)
1418 				- ah->ah_config.ah_additional_swba_backoff
1419 				- ah->ah_config.ah_sw_beacon_response_time
1420 				+ ah->ah_config.ah_dma_beacon_response_time;
1421 			/*
1422 			 * XXX Ensure it isn't too low - nothing lower
1423 			 * XXX than 10 TU
1424 			 */
1425 			if (value < 10)
1426 				value = 10;
1427 			HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
1428 			    "%s: defaulting to rdytime = %d uS\n",
1429 			    __func__, value);
1430 			OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
1431 			    SM(TU_TO_USEC(value), AR_Q_RDYTIMECFG_INT) |
1432 			    AR_Q_RDYTIMECFG_ENA);
1433 		}
1434 		dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
1435 			    AR_D_MISC_ARB_LOCKOUT_CNTRL);
1436 		break;
1437 	case HAL_TX_QUEUE_PSPOLL:
1438 		qmisc |= AR_Q_MISC_CBR_INCR_DIS1;
1439 		break;
1440 	case HAL_TX_QUEUE_UAPSD:
1441 		dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS;
1442 		break;
1443 	default:			/* NB: silence compiler */
1444 		break;
1445 	}
1446 
1447 	OS_REG_WRITE(ah, AR_QMISC(q), qmisc);
1448 	OS_REG_WRITE(ah, AR_DMISC(q), dmisc);
1449 
1450 	/* Setup compression scratchpad buffer */
1451 	/*
1452 	 * XXX: calling this asynchronously to queue operation can
1453 	 *      cause unexpected behavior!!!
1454 	 */
1455 	if (qi->tqi_physCompBuf) {
1456 		HALASSERT(qi->tqi_type == HAL_TX_QUEUE_DATA ||
1457 			  qi->tqi_type == HAL_TX_QUEUE_UAPSD);
1458 		OS_REG_WRITE(ah, AR_Q_CBBS, (80 + 2*q));
1459 		OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf);
1460 		OS_REG_WRITE(ah, AR_Q_CBC,  HAL_COMP_BUF_MAX_SIZE/1024);
1461 		OS_REG_WRITE(ah, AR_Q0_MISC + 4*q,
1462 			     OS_REG_READ(ah, AR_Q0_MISC + 4*q)
1463 			     | AR_Q_MISC_QCU_COMP_EN);
1464 	}
1465 
1466 	/*
1467 	 * Always update the secondary interrupt mask registers - this
1468 	 * could be a new queue getting enabled in a running system or
1469 	 * hw getting re-initialized during a reset!
1470 	 *
1471 	 * Since we don't differentiate between tx interrupts corresponding
1472 	 * to individual queues - secondary tx mask regs are always unmasked;
1473 	 * tx interrupts are enabled/disabled for all queues collectively
1474 	 * using the primary mask reg
1475 	 */
1476 	if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
1477 		ahp->ah_txOkInterruptMask |= 1 << q;
1478 	else
1479 		ahp->ah_txOkInterruptMask &= ~(1 << q);
1480 	if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
1481 		ahp->ah_txErrInterruptMask |= 1 << q;
1482 	else
1483 		ahp->ah_txErrInterruptMask &= ~(1 << q);
1484 	if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
1485 		ahp->ah_txDescInterruptMask |= 1 << q;
1486 	else
1487 		ahp->ah_txDescInterruptMask &= ~(1 << q);
1488 	if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
1489 		ahp->ah_txEolInterruptMask |= 1 << q;
1490 	else
1491 		ahp->ah_txEolInterruptMask &= ~(1 << q);
1492 	if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
1493 		ahp->ah_txUrnInterruptMask |= 1 << q;
1494 	else
1495 		ahp->ah_txUrnInterruptMask &= ~(1 << q);
1496 	setTxQInterrupts(ah, qi);
1497 
1498 	return AH_TRUE;
1499 }
1500 #undef	TU_TO_USEC
1501