1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" 26 27 #include "ar5416/ar5416.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 32 #define EEP_MINOR(_ah) \ 33 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 34 #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 35 #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 36 37 /* Additional Time delay to wait after activiting the Base band */ 38 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 39 #define PLL_SETTLE_DELAY 300 /* 300 usec */ 40 #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 41 42 static void ar5416InitDMA(struct ath_hal *ah); 43 static void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *); 44 static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode); 45 static void ar5416InitQoS(struct ath_hal *ah); 46 static void ar5416InitUserSettings(struct ath_hal *ah); 47 static void ar5416UpdateChainMasks(struct ath_hal *ah, HAL_BOOL is_ht); 48 static void ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *); 49 50 #if 0 51 static HAL_BOOL ar5416ChannelChange(struct ath_hal *, const struct ieee80211_channel *); 52 #endif 53 static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *); 54 55 static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah); 56 static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type); 57 static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah, 58 struct ar5416eeprom *pEepData, 59 const struct ieee80211_channel *chan, int16_t *ratesArray, 60 uint16_t cfgCtl, uint16_t AntennaReduction, 61 uint16_t twiceMaxRegulatoryPower, 62 uint16_t powerLimit); 63 static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan); 64 static void ar5416MarkPhyInactive(struct ath_hal *ah); 65 66 /* 67 * Places the device in and out of reset and then places sane 68 * values in the registers based on EEPROM config, initialization 69 * vectors (as determined by the mode), and station configuration 70 * 71 * bChannelChange is used to preserve DMA/PCU registers across 72 * a HW Reset during channel change. 73 */ 74 HAL_BOOL 75 ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, 76 struct ieee80211_channel *chan, 77 HAL_BOOL bChannelChange, HAL_STATUS *status) 78 { 79 #define N(a) (sizeof (a) / sizeof (a[0])) 80 #define FAIL(_code) do { ecode = _code; goto bad; } while (0) 81 struct ath_hal_5212 *ahp = AH5212(ah); 82 HAL_CHANNEL_INTERNAL *ichan; 83 uint32_t saveDefAntenna, saveLedState; 84 uint32_t macStaId1; 85 uint16_t rfXpdGain[2]; 86 HAL_STATUS ecode; 87 uint32_t powerVal, rssiThrReg; 88 uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 89 int i; 90 uint64_t tsf = 0; 91 92 OS_MARK(ah, AH_MARK_RESET, bChannelChange); 93 94 /* Bring out of sleep mode */ 95 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 96 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 97 __func__); 98 FAIL(HAL_EIO); 99 } 100 101 /* 102 * Map public channel to private. 103 */ 104 ichan = ath_hal_checkchannel(ah, chan); 105 if (ichan == AH_NULL) 106 FAIL(HAL_EINVAL); 107 switch (opmode) { 108 case HAL_M_STA: 109 case HAL_M_IBSS: 110 case HAL_M_HOSTAP: 111 case HAL_M_MONITOR: 112 break; 113 default: 114 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 115 __func__, opmode); 116 FAIL(HAL_EINVAL); 117 break; 118 } 119 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 120 121 /* XXX Turn on fast channel change for 5416 */ 122 /* 123 * Preserve the bmiss rssi threshold and count threshold 124 * across resets 125 */ 126 rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR); 127 /* If reg is zero, first time thru set to default val */ 128 if (rssiThrReg == 0) 129 rssiThrReg = INIT_RSSI_THR; 130 131 /* 132 * Preserve the antenna on a channel change 133 */ 134 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 135 if (saveDefAntenna == 0) /* XXX magic constants */ 136 saveDefAntenna = 1; 137 138 /* Save hardware flag before chip reset clears the register */ 139 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 140 (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 141 142 /* Save led state from pci config register */ 143 saveLedState = OS_REG_READ(ah, AR_MAC_LED) & 144 (AR_MAC_LED_ASSOC | AR_MAC_LED_MODE | 145 AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW); 146 147 /* For chips on which the RTC reset is done, save TSF before it gets cleared */ 148 if (AR_SREV_HOWL(ah) || 149 (AR_SREV_MERLIN(ah) && 150 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) || 151 (ah->ah_config.ah_force_full_reset)) 152 tsf = ar5416GetTsf64(ah); 153 154 /* Mark PHY as inactive; marked active in ar5416InitBB() */ 155 ar5416MarkPhyInactive(ah); 156 157 if (!ar5416ChipReset(ah, chan)) { 158 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 159 FAIL(HAL_EIO); 160 } 161 162 /* Restore TSF */ 163 if (tsf) 164 ar5416SetTsf64(ah, tsf); 165 166 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 167 if (AR_SREV_MERLIN_10_OR_LATER(ah)) 168 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 169 170 AH5416(ah)->ah_writeIni(ah, chan); 171 172 if(AR_SREV_KIWI_13_OR_LATER(ah) ) { 173 /* Enable ASYNC FIFO */ 174 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 175 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); 176 OS_REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); 177 OS_REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 178 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 179 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 180 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 181 } 182 183 /* Override ini values (that can be overriden in this fashion) */ 184 ar5416OverrideIni(ah, chan); 185 186 /* Setup 11n MAC/Phy mode registers */ 187 ar5416Set11nRegs(ah, chan); 188 189 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 190 191 /* 192 * Some AR91xx SoC devices frequently fail to accept TSF writes 193 * right after the chip reset. When that happens, write a new 194 * value after the initvals have been applied, with an offset 195 * based on measured time difference 196 */ 197 if (AR_SREV_HOWL(ah) && (ar5416GetTsf64(ah) < tsf)) { 198 tsf += 1500; 199 ar5416SetTsf64(ah, tsf); 200 } 201 202 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n", 203 __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK)); 204 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n", 205 __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL)); 206 207 /* 208 * Setup ah_tx_chainmask / ah_rx_chainmask before we fiddle 209 * with enabling the TX/RX radio chains. 210 */ 211 ar5416UpdateChainMasks(ah, IEEE80211_IS_CHAN_HT(chan)); 212 /* 213 * This routine swaps the analog chains - it should be done 214 * before any radio register twiddling is done. 215 */ 216 ar5416InitChainMasks(ah); 217 218 /* Setup the open-loop power calibration if required */ 219 if (ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 220 AH5416(ah)->ah_olcInit(ah); 221 AH5416(ah)->ah_olcTempCompensation(ah); 222 } 223 224 /* Setup the transmit power values. */ 225 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) { 226 HALDEBUG(ah, HAL_DEBUG_ANY, 227 "%s: error init'ing transmit power\n", __func__); 228 FAIL(HAL_EIO); 229 } 230 231 /* Write the analog registers */ 232 if (!ahp->ah_rfHal->setRfRegs(ah, chan, 233 IEEE80211_IS_CHAN_2GHZ(chan) ? 2: 1, rfXpdGain)) { 234 HALDEBUG(ah, HAL_DEBUG_ANY, 235 "%s: ar5212SetRfRegs failed\n", __func__); 236 FAIL(HAL_EIO); 237 } 238 239 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 240 if (IEEE80211_IS_CHAN_OFDM(chan)|| IEEE80211_IS_CHAN_HT(chan)) 241 ar5416SetDeltaSlope(ah, chan); 242 243 AH5416(ah)->ah_spurMitigate(ah, chan); 244 245 /* Setup board specific options for EEPROM version 3 */ 246 if (!ah->ah_setBoardValues(ah, chan)) { 247 HALDEBUG(ah, HAL_DEBUG_ANY, 248 "%s: error setting board options\n", __func__); 249 FAIL(HAL_EIO); 250 } 251 252 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 253 254 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 255 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 256 | macStaId1 257 | AR_STA_ID1_RTS_USE_DEF 258 | ahp->ah_staId1Defaults 259 ); 260 ar5212SetOperatingMode(ah, opmode); 261 262 /* Set Venice BSSID mask according to current state */ 263 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 264 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 265 266 /* Restore previous led state */ 267 if (AR_SREV_HOWL(ah)) 268 OS_REG_WRITE(ah, AR_MAC_LED, 269 AR_MAC_LED_ASSOC_ACTIVE | AR_CFG_SCLK_32KHZ); 270 else 271 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | 272 saveLedState); 273 274 /* Start TSF2 for generic timer 8-15 */ 275 #ifdef NOTYET 276 if (AR_SREV_KIWI(ah)) 277 ar5416StartTsf2(ah); 278 #endif 279 280 /* Restore previous antenna */ 281 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 282 283 /* then our BSSID and associate id */ 284 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 285 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 286 (ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S); 287 288 /* Restore bmiss rssi & count thresholds */ 289 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 290 291 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 292 293 /* Restore bmiss rssi & count thresholds */ 294 OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); 295 296 if (!ar5212SetChannel(ah, chan)) 297 FAIL(HAL_EIO); 298 299 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 300 301 /* Set 1:1 QCU to DCU mapping for all queues */ 302 for (i = 0; i < AR_NUM_DCU; i++) 303 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 304 305 ahp->ah_intrTxqs = 0; 306 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 307 ah->ah_resetTxQueue(ah, i); 308 309 ar5416InitIMR(ah, opmode); 310 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 311 ar5416InitQoS(ah); 312 /* This may override the AR_DIAG_SW register */ 313 ar5416InitUserSettings(ah); 314 315 if (AR_SREV_KIWI_13_OR_LATER(ah)) { 316 /* 317 * Enable ASYNC FIFO 318 * 319 * If Async FIFO is enabled, the following counters change 320 * as MAC now runs at 117 Mhz instead of 88/44MHz when 321 * async FIFO is disabled. 322 * 323 * Overwrite the delay/timeouts initialized in ProcessIni() 324 * above. 325 */ 326 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 327 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 328 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 329 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); 330 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 331 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); 332 333 OS_REG_WRITE(ah, AR_TIME_OUT, 334 AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); 335 OS_REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); 336 337 OS_REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 338 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 339 OS_REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 340 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 341 } 342 343 if (AR_SREV_KIWI_13_OR_LATER(ah)) { 344 /* Enable AGGWEP to accelerate encryption engine */ 345 OS_REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 346 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 347 } 348 349 350 /* 351 * disable seq number generation in hw 352 */ 353 OS_REG_WRITE(ah, AR_STA_ID1, 354 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 355 356 ar5416InitDMA(ah); 357 358 /* 359 * program OBS bus to see MAC interrupts 360 */ 361 OS_REG_WRITE(ah, AR_OBS, 8); 362 363 /* 364 * Disable the "general" TX/RX mitigation timers. 365 */ 366 OS_REG_WRITE(ah, AR_MIRT, 0); 367 368 #ifdef AH_AR5416_INTERRUPT_MITIGATION 369 /* 370 * This initialises the RX interrupt mitigation timers. 371 * 372 * The mitigation timers begin at idle and are triggered 373 * upon the RXOK of a single frame (or sub-frame, for A-MPDU.) 374 * Then, the RX mitigation interrupt will fire: 375 * 376 * + 250uS after the last RX'ed frame, or 377 * + 700uS after the first RX'ed frame 378 * 379 * Thus, the LAST field dictates the extra latency 380 * induced by the RX mitigation method and the FIRST 381 * field dictates how long to delay before firing an 382 * RX mitigation interrupt. 383 * 384 * Please note this only seems to be for RXOK frames; 385 * not CRC or PHY error frames. 386 * 387 */ 388 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 250); 389 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 700); 390 #endif 391 ar5416InitBB(ah, chan); 392 393 /* Setup compression registers */ 394 ar5212SetCompRegs(ah); /* XXX not needed? */ 395 396 /* 397 * 5416 baseband will check the per rate power table 398 * and select the lower of the two 399 */ 400 ackTpcPow = 63; 401 ctsTpcPow = 63; 402 chirpTpcPow = 63; 403 powerVal = SM(ackTpcPow, AR_TPC_ACK) | 404 SM(ctsTpcPow, AR_TPC_CTS) | 405 SM(chirpTpcPow, AR_TPC_CHIRP); 406 OS_REG_WRITE(ah, AR_TPC, powerVal); 407 408 if (!ar5416InitCal(ah, chan)) 409 FAIL(HAL_ESELFTEST); 410 411 ar5416RestoreChainMask(ah); 412 413 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 414 415 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 416 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 417 418 if (AR_SREV_HOWL(ah)) { 419 /* 420 * Enable the MBSSID block-ack fix for HOWL. 421 * This feature is only supported on Howl 1.4, but it is safe to 422 * set bit 22 of STA_ID1 on other Howl revisions (1.1, 1.2, 1.3), 423 * since bit 22 is unused in those Howl revisions. 424 */ 425 unsigned int reg; 426 reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22)); 427 OS_REG_WRITE(ah,AR_STA_ID1, reg); 428 ath_hal_printf(ah, "MBSSID Set bit 22 of AR_STA_ID 0x%x\n", reg); 429 } 430 431 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 432 433 OS_MARK(ah, AH_MARK_RESET_DONE, 0); 434 435 return AH_TRUE; 436 bad: 437 OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 438 if (status != AH_NULL) 439 *status = ecode; 440 return AH_FALSE; 441 #undef FAIL 442 #undef N 443 } 444 445 #if 0 446 /* 447 * This channel change evaluates whether the selected hardware can 448 * perform a synthesizer-only channel change (no reset). If the 449 * TX is not stopped, or the RFBus cannot be granted in the given 450 * time, the function returns false as a reset is necessary 451 */ 452 HAL_BOOL 453 ar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan) 454 { 455 uint32_t ulCount; 456 uint32_t data, synthDelay, qnum; 457 uint16_t rfXpdGain[4]; 458 struct ath_hal_5212 *ahp = AH5212(ah); 459 HAL_CHANNEL_INTERNAL *ichan; 460 461 /* 462 * Map public channel to private. 463 */ 464 ichan = ath_hal_checkchannel(ah, chan); 465 466 /* TX must be stopped or RF Bus grant will not work */ 467 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 468 if (ar5212NumTxPending(ah, qnum)) { 469 HALDEBUG(ah, HAL_DEBUG_ANY, 470 "%s: frames pending on queue %d\n", __func__, qnum); 471 return AH_FALSE; 472 } 473 } 474 475 /* 476 * Kill last Baseband Rx Frame - Request analog bus grant 477 */ 478 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); 479 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) { 480 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n", 481 __func__); 482 return AH_FALSE; 483 } 484 485 ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */ 486 487 /* Change the synth */ 488 if (!ar5212SetChannel(ah, chan)) 489 return AH_FALSE; 490 491 /* Setup the transmit power values. */ 492 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) { 493 HALDEBUG(ah, HAL_DEBUG_ANY, 494 "%s: error init'ing transmit power\n", __func__); 495 return AH_FALSE; 496 } 497 498 /* 499 * Wait for the frequency synth to settle (synth goes on 500 * via PHY_ACTIVE_EN). Read the phy active delay register. 501 * Value is in 100ns increments. 502 */ 503 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 504 if (IS_CHAN_CCK(ichan)) { 505 synthDelay = (4 * data) / 22; 506 } else { 507 synthDelay = data / 10; 508 } 509 510 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 511 512 /* Release the RFBus Grant */ 513 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 514 515 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 516 if (IEEE80211_IS_CHAN_OFDM(ichan)|| IEEE80211_IS_CHAN_HT(chan)) { 517 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3); 518 ar5212SetSpurMitigation(ah, chan); 519 ar5416SetDeltaSlope(ah, chan); 520 } 521 522 /* XXX spur mitigation for Melin */ 523 524 if (!IEEE80211_IS_CHAN_DFS(chan)) 525 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 526 527 ichan->channel_time = 0; 528 ichan->tsf_last = ar5416GetTsf64(ah); 529 ar5212TxEnable(ah, AH_TRUE); 530 return AH_TRUE; 531 } 532 #endif 533 534 static void 535 ar5416InitDMA(struct ath_hal *ah) 536 { 537 struct ath_hal_5212 *ahp = AH5212(ah); 538 539 /* 540 * set AHB_MODE not to do cacheline prefetches 541 */ 542 OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 543 544 /* 545 * let mac dma reads be in 128 byte chunks 546 */ 547 OS_REG_WRITE(ah, AR_TXCFG, 548 (OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B); 549 550 /* 551 * let mac dma writes be in 128 byte chunks 552 */ 553 OS_REG_WRITE(ah, AR_RXCFG, 554 (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B); 555 556 /* restore TX trigger level */ 557 OS_REG_WRITE(ah, AR_TXCFG, 558 (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) | 559 SM(ahp->ah_txTrigLev, AR_FTRIG)); 560 561 /* 562 * Setup receive FIFO threshold to hold off TX activities 563 */ 564 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 565 566 /* 567 * reduce the number of usable entries in PCU TXBUF to avoid 568 * wrap around. 569 */ 570 if (AR_SREV_KITE(ah)) 571 /* 572 * For AR9285 the number of Fifos are reduced to half. 573 * So set the usable tx buf size also to half to 574 * avoid data/delimiter underruns 575 */ 576 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 577 else 578 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE); 579 } 580 581 static void 582 ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan) 583 { 584 uint32_t synthDelay; 585 586 /* 587 * Wait for the frequency synth to settle (synth goes on 588 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 589 * Value is in 100ns increments. 590 */ 591 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 592 if (IEEE80211_IS_CHAN_CCK(chan)) { 593 synthDelay = (4 * synthDelay) / 22; 594 } else { 595 synthDelay /= 10; 596 } 597 598 /* Turn on PLL on 5416 */ 599 HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n", 600 __func__, IEEE80211_IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz"); 601 602 /* Activate the PHY (includes baseband activate and synthesizer on) */ 603 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 604 605 /* 606 * If the AP starts the calibration before the base band timeout 607 * completes we could get rx_clear false triggering. Add an 608 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 609 * does not happen. 610 */ 611 if (IEEE80211_IS_CHAN_HALF(chan)) { 612 OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 613 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 614 OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 615 } else { 616 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 617 } 618 } 619 620 static void 621 ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode) 622 { 623 struct ath_hal_5212 *ahp = AH5212(ah); 624 625 /* 626 * Setup interrupt handling. Note that ar5212ResetTxQueue 627 * manipulates the secondary IMR's as queues are enabled 628 * and disabled. This is done with RMW ops to insure the 629 * settings we make here are preserved. 630 */ 631 ahp->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN 632 | AR_IMR_RXERR | AR_IMR_RXORN 633 | AR_IMR_BCNMISC; 634 635 #ifdef AH_AR5416_INTERRUPT_MITIGATION 636 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 637 #else 638 ahp->ah_maskReg |= AR_IMR_RXOK; 639 #endif 640 ahp->ah_maskReg |= AR_IMR_TXOK; 641 642 if (opmode == HAL_M_HOSTAP) 643 ahp->ah_maskReg |= AR_IMR_MIB; 644 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 645 646 #ifdef ADRIAN_NOTYET 647 /* This is straight from ath9k */ 648 if (! AR_SREV_HOWL(ah)) { 649 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 650 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 651 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 652 } 653 #endif 654 655 /* Enable bus errors that are OR'd to set the HIUERR bit */ 656 #if 0 657 OS_REG_WRITE(ah, AR_IMR_S2, 658 OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST); 659 #endif 660 } 661 662 static void 663 ar5416InitQoS(struct ath_hal *ah) 664 { 665 /* QoS support */ 666 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 667 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 668 669 /* Turn on NOACK Support for QoS packets */ 670 OS_REG_WRITE(ah, AR_NOACK, 671 SM(2, AR_NOACK_2BIT_VALUE) | 672 SM(5, AR_NOACK_BIT_OFFSET) | 673 SM(0, AR_NOACK_BYTE_OFFSET)); 674 675 /* 676 * initialize TXOP for all TIDs 677 */ 678 OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 679 OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 680 OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 681 OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 682 OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 683 } 684 685 static void 686 ar5416InitUserSettings(struct ath_hal *ah) 687 { 688 struct ath_hal_5212 *ahp = AH5212(ah); 689 690 /* Restore user-specified settings */ 691 if (ahp->ah_miscMode != 0) 692 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 693 if (ahp->ah_sifstime != (u_int) -1) 694 ar5212SetSifsTime(ah, ahp->ah_sifstime); 695 if (ahp->ah_slottime != (u_int) -1) 696 ar5212SetSlotTime(ah, ahp->ah_slottime); 697 if (ahp->ah_acktimeout != (u_int) -1) 698 ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 699 if (ahp->ah_ctstimeout != (u_int) -1) 700 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 701 if (AH_PRIVATE(ah)->ah_diagreg != 0) 702 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 703 if (AH5416(ah)->ah_globaltxtimeout != (u_int) -1) 704 ar5416SetGlobalTxTimeout(ah, AH5416(ah)->ah_globaltxtimeout); 705 } 706 707 static void 708 ar5416SetRfMode(struct ath_hal *ah, const struct ieee80211_channel *chan) 709 { 710 uint32_t rfMode; 711 712 if (chan == AH_NULL) 713 return; 714 715 /* treat channel B as channel G , no B mode suport in owl */ 716 rfMode = IEEE80211_IS_CHAN_CCK(chan) ? 717 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 718 719 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 720 /* phy mode bits for 5GHz channels require Fast Clock */ 721 rfMode |= AR_PHY_MODE_DYNAMIC 722 | AR_PHY_MODE_DYN_CCK_DISABLE; 723 } else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) { 724 rfMode |= IEEE80211_IS_CHAN_5GHZ(chan) ? 725 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 726 } 727 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 728 } 729 730 /* 731 * Places the hardware into reset and then pulls it out of reset 732 */ 733 HAL_BOOL 734 ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 735 { 736 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 737 /* 738 * Warm reset is optimistic for open-loop TX power control. 739 */ 740 if (AR_SREV_MERLIN(ah) && 741 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 742 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) 743 return AH_FALSE; 744 } else if (ah->ah_config.ah_force_full_reset) { 745 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) 746 return AH_FALSE; 747 } else { 748 if (!ar5416SetResetReg(ah, HAL_RESET_WARM)) 749 return AH_FALSE; 750 } 751 752 /* Bring out of sleep mode (AGAIN) */ 753 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 754 return AH_FALSE; 755 756 #ifdef notyet 757 ahp->ah_chipFullSleep = AH_FALSE; 758 #endif 759 760 AH5416(ah)->ah_initPLL(ah, chan); 761 762 /* 763 * Perform warm reset before the mode/PLL/turbo registers 764 * are changed in order to deactivate the radio. Mode changes 765 * with an active radio can result in corrupted shifts to the 766 * radio device. 767 */ 768 ar5416SetRfMode(ah, chan); 769 770 return AH_TRUE; 771 } 772 773 /* 774 * Delta slope coefficient computation. 775 * Required for OFDM operation. 776 */ 777 static void 778 ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled, 779 uint32_t *coef_mantissa, uint32_t *coef_exponent) 780 { 781 #define COEF_SCALE_S 24 782 uint32_t coef_exp, coef_man; 783 /* 784 * ALGO -> coef_exp = 14-floor(log2(coef)); 785 * floor(log2(x)) is the highest set bit position 786 */ 787 for (coef_exp = 31; coef_exp > 0; coef_exp--) 788 if ((coef_scaled >> coef_exp) & 0x1) 789 break; 790 /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 791 HALASSERT(coef_exp); 792 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 793 794 /* 795 * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 796 * The coefficient is already shifted up for scaling 797 */ 798 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 799 800 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 801 *coef_exponent = coef_exp - 16; 802 803 #undef COEF_SCALE_S 804 } 805 806 void 807 ar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 808 { 809 #define INIT_CLOCKMHZSCALED 0x64000000 810 uint32_t coef_scaled, ds_coef_exp, ds_coef_man; 811 uint32_t clockMhzScaled; 812 813 CHAN_CENTERS centers; 814 815 /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 816 /* scale for selected channel bandwidth */ 817 clockMhzScaled = INIT_CLOCKMHZSCALED; 818 if (IEEE80211_IS_CHAN_TURBO(chan)) 819 clockMhzScaled <<= 1; 820 else if (IEEE80211_IS_CHAN_HALF(chan)) 821 clockMhzScaled >>= 1; 822 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 823 clockMhzScaled >>= 2; 824 825 /* 826 * ALGO -> coef = 1e8/fcarrier*fclock/40; 827 * scaled coef to provide precision for this floating calculation 828 */ 829 ar5416GetChannelCenters(ah, chan, ¢ers); 830 coef_scaled = clockMhzScaled / centers.synth_center; 831 832 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 833 834 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 835 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 836 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 837 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 838 839 /* 840 * For Short GI, 841 * scaled coeff is 9/10 that of normal coeff 842 */ 843 coef_scaled = (9 * coef_scaled)/10; 844 845 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 846 847 /* for short gi */ 848 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 849 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 850 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 851 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 852 #undef INIT_CLOCKMHZSCALED 853 } 854 855 /* 856 * Set a limit on the overall output power. Used for dynamic 857 * transmit power control and the like. 858 * 859 * NB: limit is in units of 0.5 dbM. 860 */ 861 HAL_BOOL 862 ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 863 { 864 uint16_t dummyXpdGains[2]; 865 866 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 867 return ah->ah_setTxPower(ah, AH_PRIVATE(ah)->ah_curchan, 868 dummyXpdGains); 869 } 870 871 HAL_BOOL 872 ar5416GetChipPowerLimits(struct ath_hal *ah, 873 struct ieee80211_channel *chan) 874 { 875 struct ath_hal_5212 *ahp = AH5212(ah); 876 int16_t minPower, maxPower; 877 878 /* 879 * Get Pier table max and min powers. 880 */ 881 if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 882 /* NB: rf code returns 1/4 dBm units, convert */ 883 chan->ic_maxpower = maxPower / 2; 884 chan->ic_minpower = minPower / 2; 885 } else { 886 HALDEBUG(ah, HAL_DEBUG_ANY, 887 "%s: no min/max power for %u/0x%x\n", 888 __func__, chan->ic_freq, chan->ic_flags); 889 chan->ic_maxpower = AR5416_MAX_RATE_POWER; 890 chan->ic_minpower = 0; 891 } 892 HALDEBUG(ah, HAL_DEBUG_RESET, 893 "Chan %d: MaxPow = %d MinPow = %d\n", 894 chan->ic_freq, chan->ic_maxpower, chan->ic_minpower); 895 return AH_TRUE; 896 } 897 898 /************************************************************** 899 * ar5416WriteTxPowerRateRegisters 900 * 901 * Write the TX power rate registers from the raw values given 902 * in ratesArray[]. 903 * 904 * The CCK and HT40 rate registers are only written if needed. 905 * HT20 and 11g/11a OFDM rate registers are always written. 906 * 907 * The values written are raw values which should be written 908 * to the registers - so it's up to the caller to pre-adjust 909 * them (eg CCK power offset value, or Merlin TX power offset, 910 * etc.) 911 */ 912 void 913 ar5416WriteTxPowerRateRegisters(struct ath_hal *ah, 914 const struct ieee80211_channel *chan, const int16_t ratesArray[]) 915 { 916 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 917 918 /* Write the OFDM power per rate set */ 919 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 920 POW_SM(ratesArray[rate18mb], 24) 921 | POW_SM(ratesArray[rate12mb], 16) 922 | POW_SM(ratesArray[rate9mb], 8) 923 | POW_SM(ratesArray[rate6mb], 0) 924 ); 925 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 926 POW_SM(ratesArray[rate54mb], 24) 927 | POW_SM(ratesArray[rate48mb], 16) 928 | POW_SM(ratesArray[rate36mb], 8) 929 | POW_SM(ratesArray[rate24mb], 0) 930 ); 931 932 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 933 /* Write the CCK power per rate set */ 934 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 935 POW_SM(ratesArray[rate2s], 24) 936 | POW_SM(ratesArray[rate2l], 16) 937 | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 938 | POW_SM(ratesArray[rate1l], 0) 939 ); 940 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 941 POW_SM(ratesArray[rate11s], 24) 942 | POW_SM(ratesArray[rate11l], 16) 943 | POW_SM(ratesArray[rate5_5s], 8) 944 | POW_SM(ratesArray[rate5_5l], 0) 945 ); 946 HALDEBUG(ah, HAL_DEBUG_RESET, 947 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 948 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 949 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 950 } 951 952 /* Write the HT20 power per rate set */ 953 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 954 POW_SM(ratesArray[rateHt20_3], 24) 955 | POW_SM(ratesArray[rateHt20_2], 16) 956 | POW_SM(ratesArray[rateHt20_1], 8) 957 | POW_SM(ratesArray[rateHt20_0], 0) 958 ); 959 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 960 POW_SM(ratesArray[rateHt20_7], 24) 961 | POW_SM(ratesArray[rateHt20_6], 16) 962 | POW_SM(ratesArray[rateHt20_5], 8) 963 | POW_SM(ratesArray[rateHt20_4], 0) 964 ); 965 966 if (IEEE80211_IS_CHAN_HT40(chan)) { 967 /* Write the HT40 power per rate set */ 968 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 969 POW_SM(ratesArray[rateHt40_3], 24) 970 | POW_SM(ratesArray[rateHt40_2], 16) 971 | POW_SM(ratesArray[rateHt40_1], 8) 972 | POW_SM(ratesArray[rateHt40_0], 0) 973 ); 974 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 975 POW_SM(ratesArray[rateHt40_7], 24) 976 | POW_SM(ratesArray[rateHt40_6], 16) 977 | POW_SM(ratesArray[rateHt40_5], 8) 978 | POW_SM(ratesArray[rateHt40_4], 0) 979 ); 980 /* Write the Dup/Ext 40 power per rate set */ 981 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 982 POW_SM(ratesArray[rateExtOfdm], 24) 983 | POW_SM(ratesArray[rateExtCck], 16) 984 | POW_SM(ratesArray[rateDupOfdm], 8) 985 | POW_SM(ratesArray[rateDupCck], 0) 986 ); 987 } 988 } 989 990 991 /************************************************************** 992 * ar5416SetTransmitPower 993 * 994 * Set the transmit power in the baseband for the given 995 * operating channel and mode. 996 */ 997 HAL_BOOL 998 ar5416SetTransmitPower(struct ath_hal *ah, 999 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 1000 { 1001 #define N(a) (sizeof (a) / sizeof (a[0])) 1002 1003 MODAL_EEP_HEADER *pModal; 1004 struct ath_hal_5212 *ahp = AH5212(ah); 1005 int16_t ratesArray[Ar5416RateSize]; 1006 int16_t txPowerIndexOffset = 0; 1007 uint8_t ht40PowerIncForPdadc = 2; 1008 int i; 1009 1010 uint16_t cfgCtl; 1011 uint16_t powerLimit; 1012 uint16_t twiceAntennaReduction; 1013 uint16_t twiceMaxRegulatoryPower; 1014 int16_t maxPower; 1015 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 1016 struct ar5416eeprom *pEepData = &ee->ee_base; 1017 1018 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 1019 1020 /* Setup info for the actual eeprom */ 1021 OS_MEMZERO(ratesArray, sizeof(ratesArray)); 1022 cfgCtl = ath_hal_getctl(ah, chan); 1023 powerLimit = chan->ic_maxregpower * 2; 1024 twiceAntennaReduction = chan->ic_maxantgain; 1025 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 1026 pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 1027 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 1028 __func__,chan->ic_freq, cfgCtl ); 1029 1030 if (IS_EEP_MINOR_V2(ah)) { 1031 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 1032 } 1033 1034 if (!ar5416SetPowerPerRateTable(ah, pEepData, chan, 1035 &ratesArray[0],cfgCtl, 1036 twiceAntennaReduction, 1037 twiceMaxRegulatoryPower, powerLimit)) { 1038 HALDEBUG(ah, HAL_DEBUG_ANY, 1039 "%s: unable to set tx power per rate table\n", __func__); 1040 return AH_FALSE; 1041 } 1042 1043 if (!AH5416(ah)->ah_setPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 1044 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 1045 __func__); 1046 return AH_FALSE; 1047 } 1048 1049 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 1050 1051 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1052 maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 1053 } 1054 1055 if (IEEE80211_IS_CHAN_HT40(chan)) { 1056 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 1057 } 1058 1059 ahp->ah_tx6PowerInHalfDbm = maxPower; 1060 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 1061 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 1062 1063 /* 1064 * txPowerIndexOffset is set by the SetPowerTable() call - 1065 * adjust the rate table (0 offset if rates EEPROM not loaded) 1066 */ 1067 for (i = 0; i < N(ratesArray); i++) { 1068 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 1069 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 1070 ratesArray[i] = AR5416_MAX_RATE_POWER; 1071 } 1072 1073 #ifdef AH_EEPROM_DUMP 1074 /* 1075 * Dump the rate array whilst it represents the intended dBm*2 1076 * values versus what's being adjusted before being programmed 1077 * in. Keep this in mind if you code up this function and enable 1078 * this debugging; the values won't necessarily be what's being 1079 * programmed into the hardware. 1080 */ 1081 ar5416PrintPowerPerRate(ah, ratesArray); 1082 #endif 1083 1084 /* 1085 * Merlin and later have a power offset, so subtract 1086 * pwr_table_offset * 2 from each value. The default 1087 * power offset is -5 dBm - ie, a register value of 0 1088 * equates to a TX power of -5 dBm. 1089 */ 1090 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 1091 int8_t pwr_table_offset; 1092 1093 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, 1094 &pwr_table_offset); 1095 /* Underflow power gets clamped at raw value 0 */ 1096 /* Overflow power gets camped at AR5416_MAX_RATE_POWER */ 1097 for (i = 0; i < N(ratesArray); i++) { 1098 /* 1099 * + pwr_table_offset is in dBm 1100 * + ratesArray is in 1/2 dBm 1101 */ 1102 ratesArray[i] -= (pwr_table_offset * 2); 1103 if (ratesArray[i] < 0) 1104 ratesArray[i] = 0; 1105 else if (ratesArray[i] > AR5416_MAX_RATE_POWER) 1106 ratesArray[i] = AR5416_MAX_RATE_POWER; 1107 } 1108 } 1109 1110 /* 1111 * Adjust rates for OLC where needed 1112 * 1113 * The following CCK rates need adjusting when doing 2.4ghz 1114 * CCK transmission. 1115 * 1116 * + rate2s, rate2l, rate1l, rate11s, rate11l, rate5_5s, rate5_5l 1117 * + rateExtCck, rateDupCck 1118 * 1119 * They're adjusted here regardless. The hardware then gets 1120 * programmed as needed. 5GHz operation doesn't program in CCK 1121 * rates for legacy mode but they seem to be initialised for 1122 * HT40 regardless of channel type. 1123 */ 1124 if (AR_SREV_MERLIN_20_OR_LATER(ah) && 1125 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 1126 int adj[] = { 1127 rate2s, rate2l, rate1l, rate11s, rate11l, 1128 rate5_5s, rate5_5l, rateExtCck, rateDupCck 1129 }; 1130 int cck_ofdm_delta = 2; 1131 int i; 1132 for (i = 0; i < N(adj); i++) { 1133 ratesArray[adj[i]] -= cck_ofdm_delta; 1134 if (ratesArray[adj[i]] < 0) 1135 ratesArray[adj[i]] = 0; 1136 } 1137 } 1138 1139 /* 1140 * Adjust the HT40 power to meet the correct target TX power 1141 * for 40MHz mode, based on TX power curves that are established 1142 * for 20MHz mode. 1143 * 1144 * XXX handle overflow/too high power level? 1145 */ 1146 if (IEEE80211_IS_CHAN_HT40(chan)) { 1147 ratesArray[rateHt40_0] += ht40PowerIncForPdadc; 1148 ratesArray[rateHt40_1] += ht40PowerIncForPdadc; 1149 ratesArray[rateHt40_2] += ht40PowerIncForPdadc; 1150 ratesArray[rateHt40_3] += ht40PowerIncForPdadc; 1151 ratesArray[rateHt40_4] += ht40PowerIncForPdadc; 1152 ratesArray[rateHt40_5] += ht40PowerIncForPdadc; 1153 ratesArray[rateHt40_6] += ht40PowerIncForPdadc; 1154 ratesArray[rateHt40_7] += ht40PowerIncForPdadc; 1155 } 1156 1157 /* Write the TX power rate registers */ 1158 ar5416WriteTxPowerRateRegisters(ah, chan, ratesArray); 1159 1160 /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */ 1161 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 1162 POW_SM(pModal->pwrDecreaseFor3Chain, 6) 1163 | POW_SM(pModal->pwrDecreaseFor2Chain, 0) 1164 ); 1165 return AH_TRUE; 1166 #undef POW_SM 1167 #undef N 1168 } 1169 1170 /* 1171 * Exported call to check for a recent gain reading and return 1172 * the current state of the thermal calibration gain engine. 1173 */ 1174 HAL_RFGAIN 1175 ar5416GetRfgain(struct ath_hal *ah) 1176 { 1177 return HAL_RFGAIN_INACTIVE; 1178 } 1179 1180 /* 1181 * Places all of hardware into reset 1182 */ 1183 HAL_BOOL 1184 ar5416Disable(struct ath_hal *ah) 1185 { 1186 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 1187 return AH_FALSE; 1188 if (! ar5416SetResetReg(ah, HAL_RESET_COLD)) 1189 return AH_FALSE; 1190 1191 AH5416(ah)->ah_initPLL(ah, AH_NULL); 1192 return AH_TRUE; 1193 } 1194 1195 /* 1196 * Places the PHY and Radio chips into reset. A full reset 1197 * must be called to leave this state. The PCI/MAC/PCU are 1198 * not placed into reset as we must receive interrupt to 1199 * re-enable the hardware. 1200 */ 1201 HAL_BOOL 1202 ar5416PhyDisable(struct ath_hal *ah) 1203 { 1204 if (! ar5416SetResetReg(ah, HAL_RESET_WARM)) 1205 return AH_FALSE; 1206 1207 AH5416(ah)->ah_initPLL(ah, AH_NULL); 1208 return AH_TRUE; 1209 } 1210 1211 /* 1212 * Write the given reset bit mask into the reset register 1213 */ 1214 HAL_BOOL 1215 ar5416SetResetReg(struct ath_hal *ah, uint32_t type) 1216 { 1217 /* 1218 * Set force wake 1219 */ 1220 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1221 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1222 1223 switch (type) { 1224 case HAL_RESET_POWER_ON: 1225 return ar5416SetResetPowerOn(ah); 1226 case HAL_RESET_WARM: 1227 case HAL_RESET_COLD: 1228 return ar5416SetReset(ah, type); 1229 default: 1230 HALASSERT(AH_FALSE); 1231 return AH_FALSE; 1232 } 1233 } 1234 1235 static HAL_BOOL 1236 ar5416SetResetPowerOn(struct ath_hal *ah) 1237 { 1238 /* Power On Reset (Hard Reset) */ 1239 1240 /* 1241 * Set force wake 1242 * 1243 * If the MAC was running, previously calling 1244 * reset will wake up the MAC but it may go back to sleep 1245 * before we can start polling. 1246 * Set force wake stops that 1247 * This must be called before initiating a hard reset. 1248 */ 1249 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1250 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1251 1252 /* 1253 * PowerOn reset can be used in open loop power control or failure recovery. 1254 * If we do RTC reset while DMA is still running, hardware may corrupt memory. 1255 * Therefore, we need to reset AHB first to stop DMA. 1256 */ 1257 if (! AR_SREV_HOWL(ah)) 1258 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1259 /* 1260 * RTC reset and clear 1261 */ 1262 OS_REG_WRITE(ah, AR_RTC_RESET, 0); 1263 OS_DELAY(20); 1264 1265 if (! AR_SREV_HOWL(ah)) 1266 OS_REG_WRITE(ah, AR_RC, 0); 1267 1268 OS_REG_WRITE(ah, AR_RTC_RESET, 1); 1269 1270 /* 1271 * Poll till RTC is ON 1272 */ 1273 if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) { 1274 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__); 1275 return AH_FALSE; 1276 } 1277 1278 return ar5416SetReset(ah, HAL_RESET_COLD); 1279 } 1280 1281 static HAL_BOOL 1282 ar5416SetReset(struct ath_hal *ah, int type) 1283 { 1284 uint32_t tmpReg, mask; 1285 uint32_t rst_flags; 1286 1287 #ifdef AH_SUPPORT_AR9130 /* Because of the AR9130 specific registers */ 1288 if (AR_SREV_HOWL(ah)) { 1289 HALDEBUG(ah, HAL_DEBUG_ANY, "[ath] HOWL: Fiddling with derived clk!\n"); 1290 uint32_t val = OS_REG_READ(ah, AR_RTC_DERIVED_CLK); 1291 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 1292 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 1293 OS_REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 1294 (void) OS_REG_READ(ah, AR_RTC_DERIVED_CLK); 1295 } 1296 #endif /* AH_SUPPORT_AR9130 */ 1297 1298 /* 1299 * Force wake 1300 */ 1301 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1302 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1303 1304 #ifdef AH_SUPPORT_AR9130 1305 if (AR_SREV_HOWL(ah)) { 1306 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1307 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1308 } else { 1309 #endif /* AH_SUPPORT_AR9130 */ 1310 /* 1311 * Reset AHB 1312 * 1313 * (In case the last interrupt source was a bus timeout.) 1314 * XXX TODO: this is not the way to do it! It should be recorded 1315 * XXX by the interrupt handler and passed _into_ the 1316 * XXX reset path routine so this occurs. 1317 */ 1318 tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 1319 if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1320 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1321 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF); 1322 } else { 1323 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1324 } 1325 rst_flags = AR_RTC_RC_MAC_WARM; 1326 if (type == HAL_RESET_COLD) 1327 rst_flags |= AR_RTC_RC_MAC_COLD; 1328 #ifdef AH_SUPPORT_AR9130 1329 } 1330 #endif /* AH_SUPPORT_AR9130 */ 1331 1332 OS_REG_WRITE(ah, AR_RTC_RC, rst_flags); 1333 1334 if (AR_SREV_HOWL(ah)) 1335 OS_DELAY(10000); 1336 else 1337 OS_DELAY(100); 1338 1339 /* 1340 * Clear resets and force wakeup 1341 */ 1342 OS_REG_WRITE(ah, AR_RTC_RC, 0); 1343 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) { 1344 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__); 1345 return AH_FALSE; 1346 } 1347 1348 /* Clear AHB reset */ 1349 if (! AR_SREV_HOWL(ah)) 1350 OS_REG_WRITE(ah, AR_RC, 0); 1351 1352 if (AR_SREV_HOWL(ah)) 1353 OS_DELAY(50); 1354 1355 if (AR_SREV_HOWL(ah)) { 1356 uint32_t mask; 1357 mask = OS_REG_READ(ah, AR_CFG); 1358 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1359 HALDEBUG(ah, HAL_DEBUG_RESET, 1360 "CFG Byte Swap Set 0x%x\n", mask); 1361 } else { 1362 mask = 1363 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1364 OS_REG_WRITE(ah, AR_CFG, mask); 1365 HALDEBUG(ah, HAL_DEBUG_RESET, 1366 "Setting CFG 0x%x\n", OS_REG_READ(ah, AR_CFG)); 1367 } 1368 } else { 1369 if (type == HAL_RESET_COLD) { 1370 if (isBigEndian()) { 1371 /* 1372 * Set CFG, little-endian for register 1373 * and descriptor accesses. 1374 */ 1375 mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; 1376 #ifndef AH_NEED_DESC_SWAP 1377 mask |= AR_CFG_SWTD; 1378 #endif 1379 HALDEBUG(ah, HAL_DEBUG_RESET, 1380 "%s Applying descriptor swap\n", __func__); 1381 OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); 1382 } else 1383 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 1384 } 1385 } 1386 1387 return AH_TRUE; 1388 } 1389 1390 void 1391 ar5416InitChainMasks(struct ath_hal *ah) 1392 { 1393 int rx_chainmask = AH5416(ah)->ah_rx_chainmask; 1394 1395 /* Flip this for this chainmask regardless of chip */ 1396 if (rx_chainmask == 0x5) 1397 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1398 1399 /* 1400 * Workaround for OWL 1.0 calibration failure; enable multi-chain; 1401 * then set true mask after calibration. 1402 */ 1403 if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) { 1404 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 1405 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 1406 } else { 1407 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 1408 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 1409 } 1410 OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask); 1411 1412 if (AH5416(ah)->ah_tx_chainmask == 0x5) 1413 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 1414 1415 if (AR_SREV_HOWL(ah)) { 1416 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 1417 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1418 } 1419 } 1420 1421 /* 1422 * Work-around for Owl 1.0 calibration failure. 1423 * 1424 * ar5416InitChainMasks sets the RX chainmask to 0x7 if it's Owl 1.0 1425 * due to init calibration failures. ar5416RestoreChainMask restores 1426 * these registers to the correct setting. 1427 */ 1428 void 1429 ar5416RestoreChainMask(struct ath_hal *ah) 1430 { 1431 int rx_chainmask = AH5416(ah)->ah_rx_chainmask; 1432 1433 if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) { 1434 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1435 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1436 } 1437 } 1438 1439 /* 1440 * Update the chainmask based on the current channel configuration. 1441 * 1442 * XXX ath9k checks bluetooth co-existence here 1443 * XXX ath9k checks whether the current state is "off-channel". 1444 * XXX ath9k sticks the hardware into 1x1 mode for legacy; 1445 * we're going to leave multi-RX on for multi-path cancellation. 1446 */ 1447 static void 1448 ar5416UpdateChainMasks(struct ath_hal *ah, HAL_BOOL is_ht) 1449 { 1450 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 1451 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 1452 1453 if (is_ht) { 1454 AH5416(ah)->ah_tx_chainmask = pCap->halTxChainMask; 1455 } else { 1456 AH5416(ah)->ah_tx_chainmask = 1; 1457 } 1458 AH5416(ah)->ah_rx_chainmask = pCap->halRxChainMask; 1459 HALDEBUG(ah, HAL_DEBUG_RESET, "TX chainmask: 0x%x; RX chainmask: 0x%x\n", 1460 AH5416(ah)->ah_tx_chainmask, 1461 AH5416(ah)->ah_rx_chainmask); 1462 } 1463 1464 void 1465 ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 1466 { 1467 uint32_t pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 1468 if (chan != AH_NULL) { 1469 if (IEEE80211_IS_CHAN_HALF(chan)) 1470 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1471 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1472 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1473 1474 if (IEEE80211_IS_CHAN_5GHZ(chan)) 1475 pll |= SM(0xa, AR_RTC_PLL_DIV); 1476 else 1477 pll |= SM(0xb, AR_RTC_PLL_DIV); 1478 } else 1479 pll |= SM(0xb, AR_RTC_PLL_DIV); 1480 1481 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1482 1483 /* TODO: 1484 * For multi-band owl, switch between bands by reiniting the PLL. 1485 */ 1486 1487 OS_DELAY(RTC_PLL_SETTLE_DELAY); 1488 1489 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 1490 } 1491 1492 static void 1493 ar5416SetDefGainValues(struct ath_hal *ah, 1494 const MODAL_EEP_HEADER *pModal, 1495 const struct ar5416eeprom *eep, 1496 uint8_t txRxAttenLocal, int regChainOffset, int i) 1497 { 1498 if (IS_EEP_MINOR_V3(ah)) { 1499 txRxAttenLocal = pModal->txRxAttenCh[i]; 1500 1501 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1502 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1503 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 1504 pModal->bswMargin[i]); 1505 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1506 AR_PHY_GAIN_2GHZ_XATTEN1_DB, 1507 pModal->bswAtten[i]); 1508 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1509 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 1510 pModal->xatten2Margin[i]); 1511 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1512 AR_PHY_GAIN_2GHZ_XATTEN2_DB, 1513 pModal->xatten2Db[i]); 1514 } else { 1515 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1516 AR_PHY_GAIN_2GHZ_BSW_MARGIN, 1517 pModal->bswMargin[i]); 1518 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1519 AR_PHY_GAIN_2GHZ_BSW_ATTEN, 1520 pModal->bswAtten[i]); 1521 } 1522 } 1523 1524 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1525 OS_REG_RMW_FIELD(ah, 1526 AR_PHY_RXGAIN + regChainOffset, 1527 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1528 OS_REG_RMW_FIELD(ah, 1529 AR_PHY_RXGAIN + regChainOffset, 1530 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]); 1531 } else { 1532 OS_REG_RMW_FIELD(ah, 1533 AR_PHY_RXGAIN + regChainOffset, 1534 AR_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1535 OS_REG_RMW_FIELD(ah, 1536 AR_PHY_GAIN_2GHZ + regChainOffset, 1537 AR_PHY_GAIN_2GHZ_RXTX_MARGIN, pModal->rxTxMarginCh[i]); 1538 } 1539 } 1540 1541 /* 1542 * Get the register chain offset for the given chain. 1543 * 1544 * Take into account the register chain swapping with AR5416 v2.0. 1545 * 1546 * XXX make sure that the reg chain swapping is only done for 1547 * XXX AR5416 v2.0 or greater, and not later chips? 1548 */ 1549 int 1550 ar5416GetRegChainOffset(struct ath_hal *ah, int i) 1551 { 1552 int regChainOffset; 1553 1554 if (AR_SREV_5416_V20_OR_LATER(ah) && 1555 (AH5416(ah)->ah_rx_chainmask == 0x5 || 1556 AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { 1557 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 1558 * only chains 0 and 2 populated 1559 */ 1560 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1561 } else { 1562 regChainOffset = i * 0x1000; 1563 } 1564 1565 return regChainOffset; 1566 } 1567 1568 /* 1569 * Read EEPROM header info and program the device for correct operation 1570 * given the channel value. 1571 */ 1572 HAL_BOOL 1573 ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1574 { 1575 const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 1576 const struct ar5416eeprom *eep = &ee->ee_base; 1577 const MODAL_EEP_HEADER *pModal; 1578 int i, regChainOffset; 1579 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */ 1580 1581 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 1582 pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 1583 1584 /* NB: workaround for eeprom versions <= 14.2 */ 1585 txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44; 1586 1587 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 1588 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1589 if (AR_SREV_MERLIN(ah)) { 1590 if (i >= 2) break; 1591 } 1592 regChainOffset = ar5416GetRegChainOffset(ah, i); 1593 1594 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]); 1595 1596 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, 1597 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) & 1598 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1599 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 1600 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1601 1602 /* 1603 * Large signal upgrade, 1604 * If 14.3 or later EEPROM, use 1605 * txRxAttenLocal = pModal->txRxAttenCh[i] 1606 * else txRxAttenLocal is fixed value above. 1607 */ 1608 1609 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) 1610 ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i); 1611 1612 } 1613 1614 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1615 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1616 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob); 1617 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db); 1618 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_OB, pModal->ob_ch1); 1619 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_DB, pModal->db_ch1); 1620 } else { 1621 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_OB5, pModal->ob); 1622 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_DB5, pModal->db); 1623 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_OB5, pModal->ob_ch1); 1624 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_DB5, pModal->db_ch1); 1625 } 1626 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl); 1627 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_LOCALBIAS, 1628 !!(pModal->flagBits & AR5416_EEP_FLAG_LOCALBIAS)); 1629 OS_A_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, 1630 !!(pModal->flagBits & AR5416_EEP_FLAG_FORCEXPAON)); 1631 } 1632 1633 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling); 1634 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); 1635 1636 if (! AR_SREV_MERLIN_10_OR_LATER(ah)) 1637 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize); 1638 1639 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 1640 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 1641 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 1642 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) 1643 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 1644 1645 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1646 pModal->txEndToRxOn); 1647 1648 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1649 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1650 pModal->thresh62); 1651 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1652 pModal->thresh62); 1653 } else { 1654 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, 1655 pModal->thresh62); 1656 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, 1657 pModal->thresh62); 1658 } 1659 1660 /* Minor Version Specific application */ 1661 if (IS_EEP_MINOR_V2(ah)) { 1662 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, 1663 pModal->txFrameToDataStart); 1664 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, 1665 pModal->txFrameToPaOn); 1666 } 1667 1668 if (IS_EEP_MINOR_V3(ah) && IEEE80211_IS_CHAN_HT40(chan)) 1669 /* Overwrite switch settling with HT40 value */ 1670 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 1671 pModal->swSettleHt40); 1672 1673 if (AR_SREV_MERLIN_20_OR_LATER(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_19) 1674 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits); 1675 1676 if (AR_SREV_MERLIN_20(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_20) { 1677 if (IEEE80211_IS_CHAN_2GHZ(chan)) 1678 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 1679 eep->baseEepHeader.dacLpMode); 1680 else if (eep->baseEepHeader.dacHiPwrMode_5G) 1681 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); 1682 else 1683 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 1684 eep->baseEepHeader.dacLpMode); 1685 1686 OS_DELAY(100); 1687 1688 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, 1689 pModal->miscBits >> 2); 1690 OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_DESIRED_SCALE_CCK, 1691 eep->baseEepHeader.desiredScaleCCK); 1692 } 1693 1694 return AH_TRUE; 1695 } 1696 1697 /* 1698 * Helper functions common for AP/CB/XB 1699 */ 1700 1701 /* 1702 * Set the target power array "ratesArray" from the 1703 * given set of target powers. 1704 * 1705 * This is used by the various chipset/EEPROM TX power 1706 * setup routines. 1707 */ 1708 void 1709 ar5416SetRatesArrayFromTargetPower(struct ath_hal *ah, 1710 const struct ieee80211_channel *chan, 1711 int16_t *ratesArray, 1712 const CAL_TARGET_POWER_LEG *targetPowerCck, 1713 const CAL_TARGET_POWER_LEG *targetPowerCckExt, 1714 const CAL_TARGET_POWER_LEG *targetPowerOfdm, 1715 const CAL_TARGET_POWER_LEG *targetPowerOfdmExt, 1716 const CAL_TARGET_POWER_HT *targetPowerHt20, 1717 const CAL_TARGET_POWER_HT *targetPowerHt40) 1718 { 1719 #define N(a) (sizeof(a)/sizeof(a[0])) 1720 int i; 1721 1722 /* Blank the rates array, to be consistent */ 1723 for (i = 0; i < Ar5416RateSize; i++) 1724 ratesArray[i] = 0; 1725 1726 /* Set rates Array from collected data */ 1727 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = 1728 ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm->tPow2x[0]; 1729 ratesArray[rate36mb] = targetPowerOfdm->tPow2x[1]; 1730 ratesArray[rate48mb] = targetPowerOfdm->tPow2x[2]; 1731 ratesArray[rate54mb] = targetPowerOfdm->tPow2x[3]; 1732 ratesArray[rateXr] = targetPowerOfdm->tPow2x[0]; 1733 1734 for (i = 0; i < N(targetPowerHt20->tPow2x); i++) { 1735 ratesArray[rateHt20_0 + i] = targetPowerHt20->tPow2x[i]; 1736 } 1737 1738 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1739 ratesArray[rate1l] = targetPowerCck->tPow2x[0]; 1740 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck->tPow2x[1]; 1741 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck->tPow2x[2]; 1742 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck->tPow2x[3]; 1743 } 1744 if (IEEE80211_IS_CHAN_HT40(chan)) { 1745 for (i = 0; i < N(targetPowerHt40->tPow2x); i++) { 1746 ratesArray[rateHt40_0 + i] = targetPowerHt40->tPow2x[i]; 1747 } 1748 ratesArray[rateDupOfdm] = targetPowerHt40->tPow2x[0]; 1749 ratesArray[rateDupCck] = targetPowerHt40->tPow2x[0]; 1750 ratesArray[rateExtOfdm] = targetPowerOfdmExt->tPow2x[0]; 1751 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1752 ratesArray[rateExtCck] = targetPowerCckExt->tPow2x[0]; 1753 } 1754 } 1755 #undef N 1756 } 1757 1758 /* 1759 * ar5416SetPowerPerRateTable 1760 * 1761 * Sets the transmit power in the baseband for the given 1762 * operating channel and mode. 1763 */ 1764 static HAL_BOOL 1765 ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 1766 const struct ieee80211_channel *chan, 1767 int16_t *ratesArray, uint16_t cfgCtl, 1768 uint16_t AntennaReduction, 1769 uint16_t twiceMaxRegulatoryPower, 1770 uint16_t powerLimit) 1771 { 1772 #define N(a) (sizeof(a)/sizeof(a[0])) 1773 /* Local defines to distinguish between extension and control CTL's */ 1774 #define EXT_ADDITIVE (0x8000) 1775 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 1776 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 1777 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 1778 1779 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1780 int i; 1781 int16_t twiceLargestAntenna; 1782 CAL_CTL_DATA *rep; 1783 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 1784 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 1785 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 1786 int16_t scaledPower, minCtlPower; 1787 1788 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 1789 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 1790 static const uint16_t ctlModesFor11a[] = { 1791 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 1792 }; 1793 static const uint16_t ctlModesFor11g[] = { 1794 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 1795 }; 1796 const uint16_t *pCtlMode; 1797 uint16_t numCtlModes, ctlMode, freq; 1798 CHAN_CENTERS centers; 1799 1800 ar5416GetChannelCenters(ah, chan, ¢ers); 1801 1802 /* Compute TxPower reduction due to Antenna Gain */ 1803 1804 twiceLargestAntenna = AH_MAX(AH_MAX( 1805 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0], 1806 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]), 1807 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1808 #if 0 1809 /* Turn it back on if we need to calculate per chain antenna gain reduction */ 1810 /* Use only if the expected gain > 6dbi */ 1811 /* Chain 0 is always used */ 1812 twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0]; 1813 1814 /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */ 1815 if (ahp->ah_tx_chainmask & 0x2) 1816 twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1817 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]); 1818 1819 if (ahp->ah_tx_chainmask & 0x4) 1820 twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1821 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1822 #endif 1823 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 1824 1825 /* XXX setup for 5212 use (really used?) */ 1826 ath_hal_eepromSet(ah, 1827 IEEE80211_IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5, 1828 twiceLargestAntenna); 1829 1830 /* 1831 * scaledPower is the minimum of the user input power level and 1832 * the regulatory allowed power level 1833 */ 1834 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 1835 1836 /* Reduce scaled Power by number of chains active to get to per chain tx power level */ 1837 /* TODO: better value than these? */ 1838 switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) { 1839 case 1: 1840 break; 1841 case 2: 1842 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain; 1843 break; 1844 case 3: 1845 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain; 1846 break; 1847 default: 1848 return AH_FALSE; /* Unsupported number of chains */ 1849 } 1850 1851 scaledPower = AH_MAX(0, scaledPower); 1852 1853 /* Get target powers from EEPROM - our baseline for TX Power */ 1854 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1855 /* Setup for CTL modes */ 1856 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 1857 pCtlMode = ctlModesFor11g; 1858 1859 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1860 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 1861 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1862 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1863 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 1864 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1865 1866 if (IEEE80211_IS_CHAN_HT40(chan)) { 1867 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 1868 1869 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 1870 AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1871 /* Get target powers for extension channels */ 1872 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1873 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 1874 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1875 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1876 } 1877 } else { 1878 /* Setup for CTL modes */ 1879 numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */ 1880 pCtlMode = ctlModesFor11a; 1881 1882 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1883 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1884 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20, 1885 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1886 1887 if (IEEE80211_IS_CHAN_HT40(chan)) { 1888 numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */ 1889 1890 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40, 1891 AR5416_NUM_5G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1892 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1893 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1894 } 1895 } 1896 1897 /* 1898 * For MIMO, need to apply regulatory caps individually across dynamically 1899 * running modes: CCK, OFDM, HT20, HT40 1900 * 1901 * The outer loop walks through each possible applicable runtime mode. 1902 * The inner loop walks through each ctlIndex entry in EEPROM. 1903 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 1904 * 1905 */ 1906 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 1907 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 1908 (pCtlMode[ctlMode] == CTL_2GHT40); 1909 if (isHt40CtlMode) { 1910 freq = centers.ctl_center; 1911 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 1912 freq = centers.ext_center; 1913 } else { 1914 freq = centers.ctl_center; 1915 } 1916 1917 /* walk through each CTL index stored in EEPROM */ 1918 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 1919 uint16_t twiceMinEdgePower; 1920 1921 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 1922 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 1923 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 1924 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 1925 rep = &(pEepData->ctlData[i]); 1926 twiceMinEdgePower = ar5416GetMaxEdgePower(freq, 1927 rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], 1928 IEEE80211_IS_CHAN_2GHZ(chan)); 1929 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 1930 /* Find the minimum of all CTL edge powers that apply to this channel */ 1931 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 1932 } else { 1933 /* specific */ 1934 twiceMaxEdgePower = twiceMinEdgePower; 1935 break; 1936 } 1937 } 1938 } 1939 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 1940 /* Apply ctl mode to correct target power set */ 1941 switch(pCtlMode[ctlMode]) { 1942 case CTL_11B: 1943 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 1944 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 1945 } 1946 break; 1947 case CTL_11A: 1948 case CTL_11G: 1949 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 1950 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 1951 } 1952 break; 1953 case CTL_5GHT20: 1954 case CTL_2GHT20: 1955 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 1956 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 1957 } 1958 break; 1959 case CTL_11B_EXT: 1960 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 1961 break; 1962 case CTL_11A_EXT: 1963 case CTL_11G_EXT: 1964 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 1965 break; 1966 case CTL_5GHT40: 1967 case CTL_2GHT40: 1968 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 1969 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 1970 } 1971 break; 1972 default: 1973 return AH_FALSE; 1974 break; 1975 } 1976 } /* end ctl mode checking */ 1977 1978 /* Set rates Array from collected data */ 1979 ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray, 1980 &targetPowerCck, 1981 &targetPowerCckExt, 1982 &targetPowerOfdm, 1983 &targetPowerOfdmExt, 1984 &targetPowerHt20, 1985 &targetPowerHt40); 1986 return AH_TRUE; 1987 #undef EXT_ADDITIVE 1988 #undef CTL_11A_EXT 1989 #undef CTL_11G_EXT 1990 #undef CTL_11B_EXT 1991 #undef SUB_NUM_CTL_MODES_AT_5G_40 1992 #undef SUB_NUM_CTL_MODES_AT_2G_40 1993 #undef N 1994 } 1995 1996 /************************************************************************** 1997 * fbin2freq 1998 * 1999 * Get channel value from binary representation held in eeprom 2000 * RETURNS: the frequency in MHz 2001 */ 2002 static uint16_t 2003 fbin2freq(uint8_t fbin, HAL_BOOL is2GHz) 2004 { 2005 /* 2006 * Reserved value 0xFF provides an empty definition both as 2007 * an fbin and as a frequency - do not convert 2008 */ 2009 if (fbin == AR5416_BCHAN_UNUSED) { 2010 return fbin; 2011 } 2012 2013 return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 2014 } 2015 2016 /* 2017 * ar5416GetMaxEdgePower 2018 * 2019 * Find the maximum conformance test limit for the given channel and CTL info 2020 */ 2021 uint16_t 2022 ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz) 2023 { 2024 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 2025 int i; 2026 2027 /* Get the edge power */ 2028 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { 2029 /* 2030 * If there's an exact channel match or an inband flag set 2031 * on the lower channel use the given rdEdgePower 2032 */ 2033 if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { 2034 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); 2035 break; 2036 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) { 2037 if (fbin2freq(pRdEdgesPower[i - 1].bChannel, is2GHz) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { 2038 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); 2039 } 2040 /* Leave loop - no more affecting edges possible in this monotonic increasing list */ 2041 break; 2042 } 2043 } 2044 HALASSERT(twiceMaxEdgePower > 0); 2045 return twiceMaxEdgePower; 2046 } 2047 2048 /************************************************************** 2049 * ar5416GetTargetPowers 2050 * 2051 * Return the rates of target power for the given target power table 2052 * channel, and number of channels 2053 */ 2054 void 2055 ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 2056 CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels, 2057 CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates, 2058 HAL_BOOL isHt40Target) 2059 { 2060 uint16_t clo, chi; 2061 int i; 2062 int matchIndex = -1, lowIndex = -1; 2063 uint16_t freq; 2064 CHAN_CENTERS centers; 2065 2066 ar5416GetChannelCenters(ah, chan, ¢ers); 2067 freq = isHt40Target ? centers.synth_center : centers.ctl_center; 2068 2069 /* Copy the target powers into the temp channel list */ 2070 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2071 matchIndex = 0; 2072 } else { 2073 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 2074 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2075 matchIndex = i; 2076 break; 2077 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 2078 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 2079 { 2080 lowIndex = i - 1; 2081 break; 2082 } 2083 } 2084 if ((matchIndex == -1) && (lowIndex == -1)) { 2085 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 2086 matchIndex = i - 1; 2087 } 2088 } 2089 2090 if (matchIndex != -1) { 2091 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 2092 } else { 2093 HALASSERT(lowIndex != -1); 2094 /* 2095 * Get the lower and upper channels, target powers, 2096 * and interpolate between them. 2097 */ 2098 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2099 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2100 2101 for (i = 0; i < numRates; i++) { 2102 pNewPower->tPow2x[i] = (uint8_t)ath_ee_interpolate(freq, clo, chi, 2103 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 2104 } 2105 } 2106 } 2107 /************************************************************** 2108 * ar5416GetTargetPowersLeg 2109 * 2110 * Return the four rates of target power for the given target power table 2111 * channel, and number of channels 2112 */ 2113 void 2114 ar5416GetTargetPowersLeg(struct ath_hal *ah, 2115 const struct ieee80211_channel *chan, 2116 CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels, 2117 CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates, 2118 HAL_BOOL isExtTarget) 2119 { 2120 uint16_t clo, chi; 2121 int i; 2122 int matchIndex = -1, lowIndex = -1; 2123 uint16_t freq; 2124 CHAN_CENTERS centers; 2125 2126 ar5416GetChannelCenters(ah, chan, ¢ers); 2127 freq = (isExtTarget) ? centers.ext_center :centers.ctl_center; 2128 2129 /* Copy the target powers into the temp channel list */ 2130 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2131 matchIndex = 0; 2132 } else { 2133 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 2134 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 2135 matchIndex = i; 2136 break; 2137 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 2138 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 2139 { 2140 lowIndex = i - 1; 2141 break; 2142 } 2143 } 2144 if ((matchIndex == -1) && (lowIndex == -1)) { 2145 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 2146 matchIndex = i - 1; 2147 } 2148 } 2149 2150 if (matchIndex != -1) { 2151 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 2152 } else { 2153 HALASSERT(lowIndex != -1); 2154 /* 2155 * Get the lower and upper channels, target powers, 2156 * and interpolate between them. 2157 */ 2158 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2159 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 2160 2161 for (i = 0; i < numRates; i++) { 2162 pNewPower->tPow2x[i] = (uint8_t)ath_ee_interpolate(freq, clo, chi, 2163 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 2164 } 2165 } 2166 } 2167 2168 /* 2169 * Set the gain boundaries for the given radio chain. 2170 * 2171 * The gain boundaries tell the hardware at what point in the 2172 * PDADC array to "switch over" from one PD gain setting 2173 * to another. There's also a gain overlap between two 2174 * PDADC array gain curves where there's valid PD values 2175 * for 2 gain settings. 2176 * 2177 * The hardware uses the gain overlap and gain boundaries 2178 * to determine which gain curve to use for the given 2179 * target TX power. 2180 */ 2181 void 2182 ar5416SetGainBoundariesClosedLoop(struct ath_hal *ah, int i, 2183 uint16_t pdGainOverlap_t2, uint16_t gainBoundaries[]) 2184 { 2185 int regChainOffset; 2186 2187 regChainOffset = ar5416GetRegChainOffset(ah, i); 2188 2189 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: chain %d: gainOverlap_t2: %d," 2190 " gainBoundaries: %d, %d, %d, %d\n", __func__, i, pdGainOverlap_t2, 2191 gainBoundaries[0], gainBoundaries[1], gainBoundaries[2], 2192 gainBoundaries[3]); 2193 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 2194 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 2195 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | 2196 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | 2197 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | 2198 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 2199 } 2200 2201 /* 2202 * Get the gain values and the number of gain levels given 2203 * in xpdMask. 2204 * 2205 * The EEPROM xpdMask determines which power detector gain 2206 * levels were used during calibration. Each of these mask 2207 * bits maps to a fixed gain level in hardware. 2208 */ 2209 uint16_t 2210 ar5416GetXpdGainValues(struct ath_hal *ah, uint16_t xpdMask, 2211 uint16_t xpdGainValues[]) 2212 { 2213 int i; 2214 uint16_t numXpdGain = 0; 2215 2216 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 2217 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 2218 if (numXpdGain >= AR5416_NUM_PD_GAINS) { 2219 HALASSERT(0); 2220 break; 2221 } 2222 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 2223 numXpdGain++; 2224 } 2225 } 2226 return numXpdGain; 2227 } 2228 2229 /* 2230 * Write the detector gain and biases. 2231 * 2232 * There are four power detector gain levels. The xpdMask in the EEPROM 2233 * determines which power detector gain levels have TX power calibration 2234 * data associated with them. This function writes the number of 2235 * PD gain levels and their values into the hardware. 2236 * 2237 * This is valid for all TX chains - the calibration data itself however 2238 * will likely differ per-chain. 2239 */ 2240 void 2241 ar5416WriteDetectorGainBiases(struct ath_hal *ah, uint16_t numXpdGain, 2242 uint16_t xpdGainValues[]) 2243 { 2244 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: numXpdGain: %d," 2245 " xpdGainValues: %d, %d, %d\n", __func__, numXpdGain, 2246 xpdGainValues[0], xpdGainValues[1], xpdGainValues[2]); 2247 2248 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & 2249 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | 2250 AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | 2251 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | 2252 SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) | 2253 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | 2254 SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3)); 2255 } 2256 2257 /* 2258 * Write the PDADC array to the given radio chain i. 2259 * 2260 * The 32 PDADC registers are written without any care about 2261 * their contents - so if various chips treat values as "special", 2262 * this routine will not care. 2263 */ 2264 void 2265 ar5416WritePdadcValues(struct ath_hal *ah, int i, uint8_t pdadcValues[]) 2266 { 2267 int regOffset, regChainOffset; 2268 int j; 2269 int reg32; 2270 2271 regChainOffset = ar5416GetRegChainOffset(ah, i); 2272 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 2273 2274 for (j = 0; j < 32; j++) { 2275 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) | 2276 ((pdadcValues[4*j + 1] & 0xFF) << 8) | 2277 ((pdadcValues[4*j + 2] & 0xFF) << 16) | 2278 ((pdadcValues[4*j + 3] & 0xFF) << 24) ; 2279 OS_REG_WRITE(ah, regOffset, reg32); 2280 HALDEBUG(ah, HAL_DEBUG_EEPROM, "PDADC: Chain %d |" 2281 " PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d" 2282 " Value %3d | PDADC %3d Value %3d |\n", 2283 i, 2284 4*j, pdadcValues[4*j], 2285 4*j+1, pdadcValues[4*j + 1], 2286 4*j+2, pdadcValues[4*j + 2], 2287 4*j+3, pdadcValues[4*j + 3]); 2288 regOffset += 4; 2289 } 2290 } 2291 2292 /************************************************************** 2293 * ar5416SetPowerCalTable 2294 * 2295 * Pull the PDADC piers from cal data and interpolate them across the given 2296 * points as well as from the nearest pier(s) to get a power detector 2297 * linear voltage to power level table. 2298 */ 2299 HAL_BOOL 2300 ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 2301 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 2302 { 2303 CAL_DATA_PER_FREQ *pRawDataset; 2304 uint8_t *pCalBChans = AH_NULL; 2305 uint16_t pdGainOverlap_t2; 2306 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 2307 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 2308 uint16_t numPiers, i; 2309 int16_t tMinCalPower; 2310 uint16_t numXpdGain, xpdMask; 2311 uint16_t xpdGainValues[AR5416_NUM_PD_GAINS]; 2312 uint32_t regChainOffset; 2313 2314 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 2315 2316 xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain; 2317 2318 if (IS_EEP_MINOR_V2(ah)) { 2319 pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap; 2320 } else { 2321 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 2322 } 2323 2324 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2325 pCalBChans = pEepData->calFreqPier2G; 2326 numPiers = AR5416_NUM_2G_CAL_PIERS; 2327 } else { 2328 pCalBChans = pEepData->calFreqPier5G; 2329 numPiers = AR5416_NUM_5G_CAL_PIERS; 2330 } 2331 2332 /* Calculate the value of xpdgains from the xpdGain Mask */ 2333 numXpdGain = ar5416GetXpdGainValues(ah, xpdMask, xpdGainValues); 2334 2335 /* Write the detector gain biases and their number */ 2336 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); 2337 2338 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2339 regChainOffset = ar5416GetRegChainOffset(ah, i); 2340 2341 if (pEepData->baseEepHeader.txMask & (1 << i)) { 2342 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2343 pRawDataset = pEepData->calPierData2G[i]; 2344 } else { 2345 pRawDataset = pEepData->calPierData5G[i]; 2346 } 2347 2348 /* Fetch the gain boundaries and the PDADC values */ 2349 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 2350 pCalBChans, numPiers, 2351 pdGainOverlap_t2, 2352 &tMinCalPower, gainBoundaries, 2353 pdadcValues, numXpdGain); 2354 2355 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 2356 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, 2357 gainBoundaries); 2358 } 2359 2360 /* Write the power values into the baseband power table */ 2361 ar5416WritePdadcValues(ah, i, pdadcValues); 2362 } 2363 } 2364 *pTxPowerIndexOffset = 0; 2365 2366 return AH_TRUE; 2367 } 2368 2369 /************************************************************** 2370 * ar5416GetGainBoundariesAndPdadcs 2371 * 2372 * Uses the data points read from EEPROM to reconstruct the pdadc power table 2373 * Called by ar5416SetPowerCalTable only. 2374 */ 2375 void 2376 ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 2377 const struct ieee80211_channel *chan, 2378 CAL_DATA_PER_FREQ *pRawDataSet, 2379 uint8_t * bChans, uint16_t availPiers, 2380 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 2381 uint8_t * pPDADCValues, uint16_t numXpdGains) 2382 { 2383 2384 int i, j, k; 2385 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 2386 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 2387 2388 /* filled out Vpd table for all pdGains (chanL) */ 2389 static uint8_t vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2390 2391 /* filled out Vpd table for all pdGains (chanR) */ 2392 static uint8_t vpdTableR[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2393 2394 /* filled out Vpd table for all pdGains (interpolated) */ 2395 static uint8_t vpdTableI[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 2396 2397 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 2398 uint8_t minPwrT4[AR5416_NUM_PD_GAINS]; 2399 uint8_t maxPwrT4[AR5416_NUM_PD_GAINS]; 2400 int16_t vpdStep; 2401 int16_t tmpVal; 2402 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 2403 HAL_BOOL match; 2404 int16_t minDelta = 0; 2405 CHAN_CENTERS centers; 2406 2407 ar5416GetChannelCenters(ah, chan, ¢ers); 2408 2409 /* Trim numPiers for the number of populated channel Piers */ 2410 for (numPiers = 0; numPiers < availPiers; numPiers++) { 2411 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 2412 break; 2413 } 2414 } 2415 2416 /* Find pier indexes around the current channel */ 2417 match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, 2418 IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); 2419 2420 if (match) { 2421 /* Directly fill both vpd tables from the matching index */ 2422 for (i = 0; i < numXpdGains; i++) { 2423 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 2424 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 2425 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i], 2426 pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 2427 } 2428 } else { 2429 for (i = 0; i < numXpdGains; i++) { 2430 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 2431 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 2432 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 2433 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 2434 2435 /* Start Vpd interpolation from the max of the minimum powers */ 2436 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 2437 2438 /* End Vpd interpolation from the min of the max powers */ 2439 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 2440 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 2441 2442 /* Fill pier Vpds */ 2443 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 2444 ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 2445 2446 /* Interpolate the final vpd */ 2447 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 2448 vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, 2449 IEEE80211_IS_CHAN_2GHZ(chan)), 2450 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 2451 } 2452 } 2453 } 2454 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 2455 2456 k = 0; /* index for the final table */ 2457 for (i = 0; i < numXpdGains; i++) { 2458 if (i == (numXpdGains - 1)) { 2459 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 2460 } else { 2461 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 2462 } 2463 2464 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 2465 2466 /* NB: only applies to owl 1.0 */ 2467 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) { 2468 /* 2469 * fix the gain delta, but get a delta that can be applied to min to 2470 * keep the upper power values accurate, don't think max needs to 2471 * be adjusted because should not be at that area of the table? 2472 */ 2473 minDelta = pPdGainBoundaries[0] - 23; 2474 pPdGainBoundaries[0] = 23; 2475 } 2476 else { 2477 minDelta = 0; 2478 } 2479 2480 /* Find starting index for this pdGain */ 2481 if (i == 0) { 2482 if (AR_SREV_MERLIN_10_OR_LATER(ah)) 2483 ss = (int16_t)(0 - (minPwrT4[i] / 2)); 2484 else 2485 ss = 0; /* for the first pdGain, start from index 0 */ 2486 } else { 2487 /* need overlap entries extrapolated below. */ 2488 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 2489 } 2490 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 2491 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 2492 /* 2493 *-ve ss indicates need to extrapolate data below for this pdGain 2494 */ 2495 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2496 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 2497 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 2498 ss++; 2499 } 2500 2501 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 2502 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 2503 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 2504 2505 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2506 pPDADCValues[k++] = vpdTableI[i][ss++]; 2507 } 2508 2509 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 2510 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 2511 /* 2512 * for last gain, pdGainBoundary == Pmax_t2, so will 2513 * have to extrapolate 2514 */ 2515 if (tgtIndex >= maxIndex) { /* need to extrapolate above */ 2516 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2517 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 2518 (ss - maxIndex +1) * vpdStep)); 2519 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 2520 ss++; 2521 } 2522 } /* extrapolated above */ 2523 } /* for all pdGainUsed */ 2524 2525 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 2526 while (i < AR5416_PD_GAINS_IN_MASK) { 2527 pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 2528 i++; 2529 } 2530 2531 while (k < AR5416_NUM_PDADC_VALUES) { 2532 pPDADCValues[k] = pPDADCValues[k-1]; 2533 k++; 2534 } 2535 return; 2536 } 2537 2538 /* 2539 * The linux ath9k driver and (from what I've been told) the reference 2540 * Atheros driver enables the 11n PHY by default whether or not it's 2541 * configured. 2542 */ 2543 static void 2544 ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan) 2545 { 2546 uint32_t phymode; 2547 uint32_t enableDacFifo = 0; 2548 HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */ 2549 2550 if (AR_SREV_KITE_10_OR_LATER(ah)) 2551 enableDacFifo = (OS_REG_READ(ah, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO); 2552 2553 /* Enable 11n HT, 20 MHz */ 2554 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 2555 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 2556 2557 /* Configure baseband for dynamic 20/40 operation */ 2558 if (IEEE80211_IS_CHAN_HT40(chan)) { 2559 phymode |= AR_PHY_FC_DYN2040_EN; 2560 2561 /* Configure control (primary) channel at +-10MHz */ 2562 if (IEEE80211_IS_CHAN_HT40U(chan)) 2563 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 2564 #if 0 2565 /* Configure 20/25 spacing */ 2566 if (ht->ht_extprotspacing == HAL_HT_EXTPROTSPACING_25) 2567 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 2568 #endif 2569 macmode = HAL_HT_MACMODE_2040; 2570 } else 2571 macmode = HAL_HT_MACMODE_20; 2572 OS_REG_WRITE(ah, AR_PHY_TURBO, phymode); 2573 2574 /* Configure MAC for 20/40 operation */ 2575 ar5416Set11nMac2040(ah, macmode); 2576 2577 /* global transmit timeout (25 TUs default)*/ 2578 /* XXX - put this elsewhere??? */ 2579 OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ; 2580 2581 /* carrier sense timeout */ 2582 OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC); 2583 OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 2584 } 2585 2586 void 2587 ar5416GetChannelCenters(struct ath_hal *ah, 2588 const struct ieee80211_channel *chan, CHAN_CENTERS *centers) 2589 { 2590 uint16_t freq = ath_hal_gethwchannel(ah, chan); 2591 2592 centers->ctl_center = freq; 2593 centers->synth_center = freq; 2594 /* 2595 * In 20/40 phy mode, the center frequency is 2596 * "between" the control and extension channels. 2597 */ 2598 if (IEEE80211_IS_CHAN_HT40U(chan)) { 2599 centers->synth_center += HT40_CHANNEL_CENTER_SHIFT; 2600 centers->ext_center = 2601 centers->synth_center + HT40_CHANNEL_CENTER_SHIFT; 2602 } else if (IEEE80211_IS_CHAN_HT40D(chan)) { 2603 centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT; 2604 centers->ext_center = 2605 centers->synth_center - HT40_CHANNEL_CENTER_SHIFT; 2606 } else { 2607 centers->ext_center = freq; 2608 } 2609 } 2610 2611 /* 2612 * Override the INI vals being programmed. 2613 */ 2614 static void 2615 ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 2616 { 2617 uint32_t val; 2618 2619 /* 2620 * Set the RX_ABORT and RX_DIS and clear if off only after 2621 * RXE is set for MAC. This prevents frames with corrupted 2622 * descriptor status. 2623 */ 2624 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 2625 2626 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2627 val = OS_REG_READ(ah, AR_PCU_MISC_MODE2); 2628 val &= (~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE); 2629 if (!AR_SREV_9271(ah)) 2630 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 2631 2632 if (AR_SREV_KIWI_10_OR_LATER(ah)) 2633 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 2634 2635 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 2636 } 2637 2638 /* 2639 * Disable RIFS search on some chips to avoid baseband 2640 * hang issues. 2641 */ 2642 if (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) 2643 (void) ar5416SetRifsDelay(ah, chan, AH_FALSE); 2644 2645 if (!AR_SREV_5416_V20_OR_LATER(ah) || AR_SREV_MERLIN(ah)) 2646 return; 2647 2648 /* 2649 * Disable BB clock gating 2650 * Necessary to avoid issues on AR5416 2.0 2651 */ 2652 OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 2653 } 2654 2655 struct ini { 2656 uint32_t *data; /* NB: !const */ 2657 int rows, cols; 2658 }; 2659 2660 /* 2661 * Override XPA bias level based on operating frequency. 2662 * This is a v14 EEPROM specific thing for the AR9160. 2663 */ 2664 void 2665 ar5416EepromSetAddac(struct ath_hal *ah, const struct ieee80211_channel *chan) 2666 { 2667 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) 2668 MODAL_EEP_HEADER *pModal; 2669 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 2670 struct ar5416eeprom *eep = &ee->ee_base; 2671 uint8_t biaslevel; 2672 2673 if (! AR_SREV_SOWL(ah)) 2674 return; 2675 2676 if (EEP_MINOR(ah) < AR5416_EEP_MINOR_VER_7) 2677 return; 2678 2679 pModal = &(eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]); 2680 2681 if (pModal->xpaBiasLvl != 0xff) 2682 biaslevel = pModal->xpaBiasLvl; 2683 else { 2684 uint16_t resetFreqBin, freqBin, freqCount = 0; 2685 CHAN_CENTERS centers; 2686 2687 ar5416GetChannelCenters(ah, chan, ¢ers); 2688 2689 resetFreqBin = FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)); 2690 freqBin = XPA_LVL_FREQ(0) & 0xff; 2691 biaslevel = (uint8_t) (XPA_LVL_FREQ(0) >> 14); 2692 2693 freqCount++; 2694 2695 while (freqCount < 3) { 2696 if (XPA_LVL_FREQ(freqCount) == 0x0) 2697 break; 2698 2699 freqBin = XPA_LVL_FREQ(freqCount) & 0xff; 2700 if (resetFreqBin >= freqBin) 2701 biaslevel = (uint8_t)(XPA_LVL_FREQ(freqCount) >> 14); 2702 else 2703 break; 2704 freqCount++; 2705 } 2706 } 2707 2708 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: overriding XPA bias level = %d\n", 2709 __func__, biaslevel); 2710 2711 /* 2712 * This is a dirty workaround for the const initval data, 2713 * which will upset multiple AR9160's on the same board. 2714 * 2715 * The HAL should likely just have a private copy of the addac 2716 * data per instance. 2717 */ 2718 if (IEEE80211_IS_CHAN_2GHZ(chan)) 2719 HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 7, 1) = 2720 (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 7, 1) & (~0x18)) | biaslevel << 3; 2721 else 2722 HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 6, 1) = 2723 (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 6, 1) & (~0xc0)) | biaslevel << 6; 2724 #undef XPA_LVL_FREQ 2725 } 2726 2727 static void 2728 ar5416MarkPhyInactive(struct ath_hal *ah) 2729 { 2730 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2731 } 2732