1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_desc.h" 23 #include "ah_internal.h" 24 25 #include "ar5416/ar5416.h" 26 #include "ar5416/ar5416reg.h" 27 #include "ar5416/ar5416desc.h" 28 29 /* 30 * Get the receive filter. 31 */ 32 uint32_t 33 ar5416GetRxFilter(struct ath_hal *ah) 34 { 35 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER); 36 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR); 37 38 if (phybits & AR_PHY_ERR_RADAR) 39 bits |= HAL_RX_FILTER_PHYRADAR; 40 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 41 bits |= HAL_RX_FILTER_PHYERR; 42 return bits; 43 } 44 45 /* 46 * Set the receive filter. 47 */ 48 void 49 ar5416SetRxFilter(struct ath_hal *ah, u_int32_t bits) 50 { 51 uint32_t phybits; 52 53 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff)); 54 phybits = 0; 55 if (bits & HAL_RX_FILTER_PHYRADAR) 56 phybits |= AR_PHY_ERR_RADAR; 57 if (bits & HAL_RX_FILTER_PHYERR) 58 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 59 OS_REG_WRITE(ah, AR_PHY_ERR, phybits); 60 if (phybits) { 61 OS_REG_WRITE(ah, AR_RXCFG, 62 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 63 } else { 64 OS_REG_WRITE(ah, AR_RXCFG, 65 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA); 66 } 67 } 68 69 /* 70 * Start receive at the PCU engine 71 */ 72 void 73 ar5416StartPcuReceive(struct ath_hal *ah) 74 { 75 struct ath_hal_private *ahp = AH_PRIVATE(ah); 76 77 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__); 78 ar5212EnableMibCounters(ah); 79 /* NB: restore current settings */ 80 ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE); 81 /* 82 * NB: must do after enabling phy errors to avoid rx 83 * frames w/ corrupted descriptor status. 84 */ 85 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 86 } 87 88 /* 89 * Stop receive at the PCU engine 90 * and abort current frame in PCU 91 */ 92 void 93 ar5416StopPcuReceive(struct ath_hal *ah) 94 { 95 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 96 97 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__); 98 ar5212DisableMibCounters(ah); 99 } 100 101 /* 102 * Initialize RX descriptor, by clearing the status and setting 103 * the size (and any other flags). 104 */ 105 HAL_BOOL 106 ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 107 uint32_t size, u_int flags) 108 { 109 struct ar5416_desc *ads = AR5416DESC(ds); 110 111 HALASSERT((size &~ AR_BufLen) == 0); 112 113 ads->ds_ctl1 = size & AR_BufLen; 114 if (flags & HAL_RXDESC_INTREQ) 115 ads->ds_ctl1 |= AR_RxIntrReq; 116 117 /* this should be enough */ 118 ads->ds_rxstatus8 &= ~AR_RxDone; 119 120 /* clear the rest of the status fields */ 121 OS_MEMZERO(&(ads->u), sizeof(ads->u)); 122 123 return AH_TRUE; 124 } 125 126 /* 127 * Process an RX descriptor, and return the status to the caller. 128 * Copy some hardware specific items into the software portion 129 * of the descriptor. 130 * 131 * NB: the caller is responsible for validating the memory contents 132 * of the descriptor (e.g. flushing any cached copy). 133 */ 134 HAL_STATUS 135 ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 136 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 137 struct ath_rx_status *rs) 138 { 139 struct ar5416_desc *ads = AR5416DESC(ds); 140 141 if ((ads->ds_rxstatus8 & AR_RxDone) == 0) 142 return HAL_EINPROGRESS; 143 144 rs->rs_status = 0; 145 rs->rs_flags = 0; 146 147 rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen; 148 rs->rs_tstamp = ads->AR_RcvTimestamp; 149 150 /* XXX what about KeyCacheMiss? */ 151 152 rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined); 153 rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00); 154 rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01); 155 rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02); 156 rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10); 157 rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11); 158 rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12); 159 160 if (ads->ds_rxstatus8 & AR_RxKeyIdxValid) 161 rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx); 162 else 163 rs->rs_keyix = HAL_RXKEYIX_INVALID; 164 165 /* NB: caller expected to do rate table mapping */ 166 rs->rs_rate = RXSTATUS_RATE(ah, ads); 167 rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0; 168 169 rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0; 170 rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; 171 rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna); 172 173 if (ads->ds_rxstatus3 & AR_GI) 174 rs->rs_flags |= HAL_RX_GI; 175 if (ads->ds_rxstatus3 & AR_2040) 176 rs->rs_flags |= HAL_RX_2040; 177 178 if (ads->ds_rxstatus8 & AR_PreDelimCRCErr) 179 rs->rs_flags |= HAL_RX_DELIM_CRC_PRE; 180 if (ads->ds_rxstatus8 & AR_PostDelimCRCErr) 181 rs->rs_flags |= HAL_RX_DELIM_CRC_POST; 182 if (ads->ds_rxstatus8 & AR_DecryptBusyErr) 183 rs->rs_flags |= HAL_RX_DECRYPT_BUSY; 184 if (ads->ds_rxstatus8 & AR_HiRxChain) 185 rs->rs_flags |= HAL_RX_HI_RX_CHAIN; 186 187 if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) { 188 /* 189 * These four bits should not be set together. The 190 * 5416 spec states a Michael error can only occur if 191 * DecryptCRCErr not set (and TKIP is used). Experience 192 * indicates however that you can also get Michael errors 193 * when a CRC error is detected, but these are specious. 194 * Consequently we filter them out here so we don't 195 * confuse and/or complicate drivers. 196 */ 197 if (ads->ds_rxstatus8 & AR_CRCErr) 198 rs->rs_status |= HAL_RXERR_CRC; 199 else if (ads->ds_rxstatus8 & AR_PHYErr) { 200 u_int phyerr; 201 202 rs->rs_status |= HAL_RXERR_PHY; 203 phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode); 204 rs->rs_phyerr = phyerr; 205 } else if (ads->ds_rxstatus8 & AR_DecryptCRCErr) 206 rs->rs_status |= HAL_RXERR_DECRYPT; 207 else if (ads->ds_rxstatus8 & AR_MichaelErr) 208 rs->rs_status |= HAL_RXERR_MIC; 209 } 210 211 return HAL_OK; 212 } 213