1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 #include "ah_desc.h" /* NB: for HAL_PHYERR* */ 25 26 #include "ar5416/ar5416.h" 27 #include "ar5416/ar5416reg.h" 28 #include "ar5416/ar5416phy.h" 29 30 #include "ah_eeprom_v14.h" /* for owl_get_ntxchains() */ 31 32 /* 33 * Return the wireless modes (a,b,g,n,t) supported by hardware. 34 * 35 * This value is what is actually supported by the hardware 36 * and is unaffected by regulatory/country code settings. 37 * 38 */ 39 u_int 40 ar5416GetWirelessModes(struct ath_hal *ah) 41 { 42 u_int mode; 43 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 44 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 45 46 mode = ar5212GetWirelessModes(ah); 47 48 /* Only enable HT modes if the NIC supports HT */ 49 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11A)) 50 mode |= HAL_MODE_11NA_HT20 51 | HAL_MODE_11NA_HT40PLUS 52 | HAL_MODE_11NA_HT40MINUS 53 ; 54 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11G)) 55 mode |= HAL_MODE_11NG_HT20 56 | HAL_MODE_11NG_HT40PLUS 57 | HAL_MODE_11NG_HT40MINUS 58 ; 59 return mode; 60 } 61 62 /* 63 * Change the LED blinking pattern to correspond to the connectivity 64 */ 65 void 66 ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state) 67 { 68 static const uint32_t ledbits[8] = { 69 AR_MAC_LED_ASSOC_NONE, /* HAL_LED_INIT */ 70 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_SCAN */ 71 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_AUTH */ 72 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC*/ 73 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 74 AR_MAC_LED_ASSOC_NONE, 75 AR_MAC_LED_ASSOC_NONE, 76 AR_MAC_LED_ASSOC_NONE, 77 }; 78 79 if (AR_SREV_HOWL(ah)) 80 return; 81 82 /* 83 * Set the blink operating mode. 84 */ 85 OS_REG_RMW_FIELD(ah, AR_MAC_LED, 86 AR_MAC_LED_ASSOC, ledbits[state & 0x7]); 87 88 /* XXX Blink slow mode? */ 89 /* XXX Blink threshold? */ 90 /* XXX Blink sleep hystersis? */ 91 92 /* 93 * Set the LED blink configuration to be proportional 94 * to the current TX and RX filter bytes. (Ie, RX'ed 95 * frames that don't match the filter are ignored.) 96 * This means that higher TX/RX throughput will result 97 * in the blink rate increasing. 98 */ 99 OS_REG_RMW_FIELD(ah, AR_MAC_LED, AR_MAC_LED_MODE, 100 AR_MAC_LED_MODE_PROP); 101 } 102 103 /* 104 * Get the current hardware tsf for stamlme 105 */ 106 uint64_t 107 ar5416GetTsf64(struct ath_hal *ah) 108 { 109 uint32_t low1, low2, u32; 110 111 /* sync multi-word read */ 112 low1 = OS_REG_READ(ah, AR_TSF_L32); 113 u32 = OS_REG_READ(ah, AR_TSF_U32); 114 low2 = OS_REG_READ(ah, AR_TSF_L32); 115 if (low2 < low1) { /* roll over */ 116 /* 117 * If we are not preempted this will work. If we are 118 * then we re-reading AR_TSF_U32 does no good as the 119 * low bits will be meaningless. Likewise reading 120 * L32, U32, U32, then comparing the last two reads 121 * to check for rollover doesn't help if preempted--so 122 * we take this approach as it costs one less PCI read 123 * which can be noticeable when doing things like 124 * timestamping packets in monitor mode. 125 */ 126 u32++; 127 } 128 return (((uint64_t) u32) << 32) | ((uint64_t) low2); 129 } 130 131 void 132 ar5416SetTsf64(struct ath_hal *ah, uint64_t tsf64) 133 { 134 OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 135 OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 136 } 137 138 /* 139 * Reset the current hardware tsf for stamlme. 140 */ 141 void 142 ar5416ResetTsf(struct ath_hal *ah) 143 { 144 uint32_t v; 145 int i; 146 147 for (i = 0; i < 10; i++) { 148 v = OS_REG_READ(ah, AR_SLP32_MODE); 149 if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0) 150 break; 151 OS_DELAY(10); 152 } 153 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 154 } 155 156 uint32_t 157 ar5416GetCurRssi(struct ath_hal *ah) 158 { 159 if (AR_SREV_OWL(ah)) 160 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); 161 return (OS_REG_READ(ah, AR9130_PHY_CURRENT_RSSI) & 0xff); 162 } 163 164 HAL_BOOL 165 ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 166 { 167 return AH_TRUE; 168 } 169 170 /* Setup decompression for given key index */ 171 HAL_BOOL 172 ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en) 173 { 174 return AH_TRUE; 175 } 176 177 /* Setup coverage class */ 178 void 179 ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 180 { 181 182 ar5212SetCoverageClass(ah, coverageclass, now); 183 } 184 185 /* 186 * Return the busy for rx_frame, rx_clear, and tx_frame 187 */ 188 HAL_BOOL 189 ar5416GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample) 190 { 191 struct ath_hal_5416 *ahp = AH5416(ah); 192 u_int32_t good = AH_TRUE; 193 194 /* XXX freeze/unfreeze mib counters */ 195 uint32_t rc = OS_REG_READ(ah, AR_RCCNT); 196 uint32_t ec = OS_REG_READ(ah, AR_EXTRCCNT); 197 uint32_t rf = OS_REG_READ(ah, AR_RFCNT); 198 uint32_t tf = OS_REG_READ(ah, AR_TFCNT); 199 uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 200 201 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cc) { 202 /* 203 * Cycle counter wrap (or initial call); it's not possible 204 * to accurately calculate a value because the registers 205 * right shift rather than wrap--so punt and return 0. 206 */ 207 HALDEBUG(ah, HAL_DEBUG_ANY, 208 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 209 good = AH_FALSE; 210 } else { 211 hsample->cycle_count = cc - ahp->ah_cycleCount; 212 hsample->chan_busy = rc - ahp->ah_ctlBusy; 213 hsample->ext_chan_busy = ec - ahp->ah_extBusy; 214 hsample->rx_busy = rf - ahp->ah_rxBusy; 215 hsample->tx_busy = tf - ahp->ah_txBusy; 216 } 217 218 /* 219 * Keep a copy of the MIB results so the next sample has something 220 * to work from. 221 */ 222 ahp->ah_cycleCount = cc; 223 ahp->ah_rxBusy = rf; 224 ahp->ah_ctlBusy = rc; 225 ahp->ah_txBusy = tf; 226 ahp->ah_extBusy = ec; 227 228 return (good); 229 } 230 231 /* 232 * Return approximation of extension channel busy over an time interval 233 * 0% (clear) -> 100% (busy) 234 * 235 * XXX TODO: update this to correctly sample all the counters, 236 * rather than a subset of it. 237 */ 238 uint32_t 239 ar5416Get11nExtBusy(struct ath_hal *ah) 240 { 241 struct ath_hal_5416 *ahp = AH5416(ah); 242 uint32_t busy; /* percentage */ 243 uint32_t cycleCount, ctlBusy, extBusy; 244 245 ctlBusy = OS_REG_READ(ah, AR_RCCNT); 246 extBusy = OS_REG_READ(ah, AR_EXTRCCNT); 247 cycleCount = OS_REG_READ(ah, AR_CCCNT); 248 249 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cycleCount) { 250 /* 251 * Cycle counter wrap (or initial call); it's not possible 252 * to accurately calculate a value because the registers 253 * right shift rather than wrap--so punt and return 0. 254 */ 255 busy = 0; 256 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n", 257 __func__); 258 259 } else { 260 uint32_t cycleDelta = cycleCount - ahp->ah_cycleCount; 261 uint32_t ctlBusyDelta = ctlBusy - ahp->ah_ctlBusy; 262 uint32_t extBusyDelta = extBusy - ahp->ah_extBusy; 263 uint32_t ctlClearDelta = 0; 264 265 /* Compute control channel rxclear. 266 * The cycle delta may be less than the control channel delta. 267 * This could be solved by freezing the timers (or an atomic read, 268 * if one was available). Checking for the condition should be 269 * sufficient. 270 */ 271 if (cycleDelta > ctlBusyDelta) { 272 ctlClearDelta = cycleDelta - ctlBusyDelta; 273 } 274 275 /* Compute ratio of extension channel busy to control channel clear 276 * as an approximation to extension channel cleanliness. 277 * 278 * According to the hardware folks, ext rxclear is undefined 279 * if the ctrl rxclear is de-asserted (i.e. busy) 280 */ 281 if (ctlClearDelta) { 282 busy = (extBusyDelta * 100) / ctlClearDelta; 283 } else { 284 busy = 100; 285 } 286 if (busy > 100) { 287 busy = 100; 288 } 289 #if 0 290 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, " 291 "extBusyDelta 0x%x, ctlClearDelta 0x%x, " 292 "busy %d\n", 293 __func__, cycleDelta, ctlBusyDelta, extBusyDelta, ctlClearDelta, busy); 294 #endif 295 } 296 297 ahp->ah_cycleCount = cycleCount; 298 ahp->ah_ctlBusy = ctlBusy; 299 ahp->ah_extBusy = extBusy; 300 301 return busy; 302 } 303 304 /* 305 * Configure 20/40 operation 306 * 307 * 20/40 = joint rx clear (control and extension) 308 * 20 = rx clear (control) 309 * 310 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz when changing 311 * from 20/40 => 20 only 312 */ 313 void 314 ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 315 { 316 uint32_t macmode; 317 318 /* Configure MAC for 20/40 operation */ 319 if (mode == HAL_HT_MACMODE_2040) { 320 macmode = AR_2040_JOINED_RX_CLEAR; 321 } else { 322 macmode = 0; 323 } 324 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 325 } 326 327 /* 328 * Get Rx clear (control/extension channel) 329 * 330 * Returns active low (busy) for ctrl/ext channel 331 * Owl 2.0 332 */ 333 HAL_HT_RXCLEAR 334 ar5416Get11nRxClear(struct ath_hal *ah) 335 { 336 HAL_HT_RXCLEAR rxclear = 0; 337 uint32_t val; 338 339 val = OS_REG_READ(ah, AR_DIAG_SW); 340 341 /* control channel */ 342 if (val & AR_DIAG_RXCLEAR_CTL_LOW) { 343 rxclear |= HAL_RX_CLEAR_CTL_LOW; 344 } 345 /* extension channel */ 346 if (val & AR_DIAG_RXCLEAR_EXT_LOW) { 347 rxclear |= HAL_RX_CLEAR_EXT_LOW; 348 } 349 return rxclear; 350 } 351 352 /* 353 * Set Rx clear (control/extension channel) 354 * 355 * Useful for forcing the channel to appear busy for 356 * debugging/diagnostics 357 * Owl 2.0 358 */ 359 void 360 ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 361 { 362 /* control channel */ 363 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 364 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 365 } else { 366 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 367 } 368 /* extension channel */ 369 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 370 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 371 } else { 372 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 373 } 374 } 375 376 /* XXX shouldn't be here! */ 377 #define TU_TO_USEC(_tu) ((_tu) << 10) 378 379 HAL_STATUS 380 ar5416SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration, 381 uint32_t nextStart, HAL_QUIET_FLAG flag) 382 { 383 uint32_t period_us = TU_TO_USEC(period); /* convert to us unit */ 384 uint32_t nextStart_us = TU_TO_USEC(nextStart); /* convert to us unit */ 385 if (flag & HAL_QUIET_ENABLE) { 386 if ((!nextStart) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 387 /* Add the nextStart offset to the current TSF */ 388 nextStart_us += OS_REG_READ(ah, AR_TSF_L32); 389 } 390 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 391 nextStart_us += ah->ah_config.ah_sw_beacon_response_time; 392 } 393 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 394 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 395 OS_REG_WRITE(ah, AR_QUIET_PERIOD, period_us); 396 OS_REG_WRITE(ah, AR_NEXT_QUIET, nextStart_us); 397 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 398 } else { 399 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 400 } 401 return HAL_OK; 402 } 403 #undef TU_TO_USEC 404 405 HAL_STATUS 406 ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 407 uint32_t capability, uint32_t *result) 408 { 409 switch (type) { 410 case HAL_CAP_BB_HANG: 411 switch (capability) { 412 case HAL_BB_HANG_RIFS: 413 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 414 case HAL_BB_HANG_DFS: 415 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 416 case HAL_BB_HANG_RX_CLEAR: 417 return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP; 418 } 419 break; 420 case HAL_CAP_MAC_HANG: 421 return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || 422 (ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) || 423 AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? 424 HAL_OK : HAL_ENOTSUPP; 425 case HAL_CAP_DIVERSITY: /* disable classic fast diversity */ 426 return HAL_ENXIO; 427 default: 428 break; 429 } 430 return ar5212GetCapability(ah, type, capability, result); 431 } 432 433 HAL_BOOL 434 ar5416SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 435 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 436 { 437 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 438 439 switch (type) { 440 case HAL_CAP_RX_CHAINMASK: 441 setting &= ath_hal_eepromGet(ah, AR_EEP_RXMASK, NULL); 442 pCap->halRxChainMask = setting; 443 if (owl_get_ntxchains(setting) > 2) 444 pCap->halRxStreams = 2; 445 else 446 pCap->halRxStreams = 1; 447 return AH_TRUE; 448 case HAL_CAP_TX_CHAINMASK: 449 setting &= ath_hal_eepromGet(ah, AR_EEP_TXMASK, NULL); 450 pCap->halTxChainMask = setting; 451 if (owl_get_ntxchains(setting) > 2) 452 pCap->halTxStreams = 2; 453 else 454 pCap->halTxStreams = 1; 455 return AH_TRUE; 456 default: 457 break; 458 } 459 return ar5212SetCapability(ah, type, capability, setting, status); 460 } 461 462 static int ar5416DetectMacHang(struct ath_hal *ah); 463 static int ar5416DetectBBHang(struct ath_hal *ah); 464 465 HAL_BOOL 466 ar5416GetDiagState(struct ath_hal *ah, int request, 467 const void *args, uint32_t argsize, 468 void **result, uint32_t *resultsize) 469 { 470 struct ath_hal_5416 *ahp = AH5416(ah); 471 int hangs; 472 473 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) 474 return AH_TRUE; 475 switch (request) { 476 case HAL_DIAG_EEPROM: 477 return ath_hal_eepromDiag(ah, request, 478 args, argsize, result, resultsize); 479 case HAL_DIAG_CHECK_HANGS: 480 if (argsize != sizeof(int)) 481 return AH_FALSE; 482 hangs = *(const int *) args; 483 ahp->ah_hangs = 0; 484 if (hangs & HAL_BB_HANGS) 485 ahp->ah_hangs |= ar5416DetectBBHang(ah); 486 /* NB: if BB is hung MAC will be hung too so skip check */ 487 if (ahp->ah_hangs == 0 && (hangs & HAL_MAC_HANGS)) 488 ahp->ah_hangs |= ar5416DetectMacHang(ah); 489 *result = &ahp->ah_hangs; 490 *resultsize = sizeof(ahp->ah_hangs); 491 return AH_TRUE; 492 } 493 return ar5212GetDiagState(ah, request, 494 args, argsize, result, resultsize); 495 } 496 497 HAL_BOOL 498 ar5416SetRifsDelay(struct ath_hal *ah, const struct ieee80211_channel *chan, 499 HAL_BOOL enable) 500 { 501 uint32_t val; 502 HAL_BOOL is_chan_2g = AH_FALSE; 503 HAL_BOOL is_ht40 = AH_FALSE; 504 505 if (chan) 506 is_chan_2g = IEEE80211_IS_CHAN_2GHZ(chan); 507 508 if (chan) 509 is_ht40 = IEEE80211_IS_CHAN_HT40(chan); 510 511 /* Only support disabling RIFS delay for now */ 512 HALASSERT(enable == AH_FALSE); 513 514 if (enable == AH_TRUE) 515 return AH_FALSE; 516 517 /* Change RIFS init delay to 0 */ 518 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 519 val &= ~AR_PHY_RIFS_INIT_DELAY; 520 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 521 522 /* 523 * For Owl, RIFS RX parameters are controlled differently; 524 * it isn't enabled in the inivals by default. 525 * 526 * For Sowl/Howl, RIFS RX is enabled in the inivals by default; 527 * the following code sets them back to non-RIFS values. 528 * 529 * For > Sowl/Howl, RIFS RX can be left on by default and so 530 * this function shouldn't be called. 531 */ 532 if ((! AR_SREV_SOWL(ah)) && (! AR_SREV_HOWL(ah))) 533 return AH_TRUE; 534 535 /* Reset search delay to default values */ 536 if (is_chan_2g) 537 if (is_ht40) 538 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x268); 539 else 540 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x134); 541 else 542 if (is_ht40) 543 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x370); 544 else 545 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x1b8); 546 547 return AH_TRUE; 548 } 549 550 static HAL_BOOL 551 ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs, 552 const hal_mac_hang_check_t *check) 553 { 554 int found_states; 555 556 found_states = 0; 557 if (check->states & dcu_chain_state) { 558 int i; 559 560 for (i = 0; i < 6; i++) { 561 if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) == 562 check->dcu_chain_state) 563 found_states |= dcu_chain_state; 564 } 565 for (i = 0; i < 4; i++) { 566 if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) == 567 check->dcu_chain_state) 568 found_states |= dcu_chain_state; 569 } 570 } 571 if (check->states & dcu_complete_state) { 572 if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state) 573 found_states |= dcu_complete_state; 574 } 575 if (check->states & qcu_stitch_state) { 576 if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state) 577 found_states |= qcu_stitch_state; 578 } 579 if (check->states & qcu_fetch_state) { 580 if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state) 581 found_states |= qcu_fetch_state; 582 } 583 if (check->states & qcu_complete_state) { 584 if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state) 585 found_states |= qcu_complete_state; 586 } 587 return (found_states == check->states); 588 } 589 590 #define NUM_STATUS_READS 50 591 592 static int 593 ar5416DetectMacHang(struct ath_hal *ah) 594 { 595 static const hal_mac_hang_check_t hang_sig1 = { 596 .dcu_chain_state = 0x6, 597 .dcu_complete_state = 0x1, 598 .states = dcu_chain_state 599 | dcu_complete_state, 600 }; 601 static const hal_mac_hang_check_t hang_sig2 = { 602 .qcu_stitch_state = 0x9, 603 .qcu_fetch_state = 0x8, 604 .qcu_complete_state = 0x4, 605 .states = qcu_stitch_state 606 | qcu_fetch_state 607 | qcu_complete_state, 608 }; 609 mac_dbg_regs_t mac_dbg; 610 int i; 611 612 mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3); 613 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 614 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 615 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 616 for (i = 1; i <= NUM_STATUS_READS; i++) { 617 if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) || 618 mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) || 619 mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) || 620 mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6)) 621 return 0; 622 } 623 624 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1)) 625 return HAL_MAC_HANG_SIG1; 626 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2)) 627 return HAL_MAC_HANG_SIG2; 628 629 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown MAC hang signature " 630 "DMADBG_3=0x%x DMADBG_4=0x%x DMADBG_5=0x%x DMADBG_6=0x%x\n", 631 __func__, mac_dbg.dma_dbg_3, mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 632 mac_dbg.dma_dbg_6); 633 634 return 0; 635 } 636 637 /* 638 * Determine if the baseband using the Observation Bus Register 639 */ 640 static int 641 ar5416DetectBBHang(struct ath_hal *ah) 642 { 643 #define N(a) (sizeof(a)/sizeof(a[0])) 644 /* 645 * Check the PCU Observation Bus 1 register (0x806c) 646 * NUM_STATUS_READS times 647 * 648 * 4 known BB hang signatures - 649 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 650 * [2] bits 8,9 are 1, bit 11 is 0. State machine state 651 * (bits 25-31) is 0x52 652 * [3] bits 8,9 are 1, bit 11 is 0. State machine state 653 * (bits 25-31) is 0x18 654 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 655 * Rx State (bits 20-24) is 0x7. 656 */ 657 static const struct { 658 uint32_t val; 659 uint32_t mask; 660 int code; 661 } hang_list[] = { 662 /* Reg Value Reg Mask Hang Code XXX */ 663 { 0x1E000000, 0x7E000B00, HAL_BB_HANG_DFS }, 664 { 0x52000B00, 0x7E000B00, HAL_BB_HANG_RIFS }, 665 { 0x18000B00, 0x7E000B00, HAL_BB_HANG_RX_CLEAR }, 666 { 0x00702400, 0x7E7FFFEF, HAL_BB_HANG_RX_CLEAR } 667 }; 668 uint32_t hang_sig; 669 int i; 670 671 hang_sig = OS_REG_READ(ah, AR_OBSERV_1); 672 for (i = 1; i <= NUM_STATUS_READS; i++) { 673 if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1)) 674 return 0; 675 } 676 for (i = 0; i < N(hang_list); i++) 677 if ((hang_sig & hang_list[i].mask) == hang_list[i].val) { 678 HALDEBUG(ah, HAL_DEBUG_HANG, 679 "%s BB hang, signature 0x%x, code 0x%x\n", 680 __func__, hang_sig, hang_list[i].code); 681 return hang_list[i].code; 682 } 683 684 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown BB hang signature! " 685 "<0x806c>=0x%x\n", __func__, hang_sig); 686 687 return 0; 688 #undef N 689 } 690 #undef NUM_STATUS_READS 691