1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 #include "ah_desc.h" /* NB: for HAL_PHYERR* */ 25 26 #include "ar5416/ar5416.h" 27 #include "ar5416/ar5416reg.h" 28 #include "ar5416/ar5416phy.h" 29 30 /* 31 * Return the wireless modes (a,b,g,n,t) supported by hardware. 32 * 33 * This value is what is actually supported by the hardware 34 * and is unaffected by regulatory/country code settings. 35 * 36 */ 37 u_int 38 ar5416GetWirelessModes(struct ath_hal *ah) 39 { 40 u_int mode; 41 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 42 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 43 44 mode = ar5212GetWirelessModes(ah); 45 46 /* Only enable HT modes if the NIC supports HT */ 47 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11A)) 48 mode |= HAL_MODE_11NA_HT20 49 | HAL_MODE_11NA_HT40PLUS 50 | HAL_MODE_11NA_HT40MINUS 51 ; 52 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11G)) 53 mode |= HAL_MODE_11NG_HT20 54 | HAL_MODE_11NG_HT40PLUS 55 | HAL_MODE_11NG_HT40MINUS 56 ; 57 return mode; 58 } 59 60 /* 61 * Change the LED blinking pattern to correspond to the connectivity 62 */ 63 void 64 ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state) 65 { 66 static const uint32_t ledbits[8] = { 67 AR_MAC_LED_ASSOC_NONE, /* HAL_LED_INIT */ 68 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_SCAN */ 69 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_AUTH */ 70 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC*/ 71 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 72 AR_MAC_LED_ASSOC_NONE, 73 AR_MAC_LED_ASSOC_NONE, 74 AR_MAC_LED_ASSOC_NONE, 75 }; 76 77 if (AR_SREV_HOWL(ah)) 78 return; 79 80 /* 81 * Set the blink operating mode. 82 */ 83 OS_REG_RMW_FIELD(ah, AR_MAC_LED, 84 AR_MAC_LED_ASSOC, ledbits[state & 0x7]); 85 86 /* XXX Blink slow mode? */ 87 /* XXX Blink threshold? */ 88 /* XXX Blink sleep hystersis? */ 89 90 /* 91 * Set the LED blink configuration to be proportional 92 * to the current TX and RX filter bytes. (Ie, RX'ed 93 * frames that don't match the filter are ignored.) 94 * This means that higher TX/RX throughput will result 95 * in the blink rate increasing. 96 */ 97 OS_REG_RMW_FIELD(ah, AR_MAC_LED, AR_MAC_LED_MODE, 98 AR_MAC_LED_MODE_PROP); 99 } 100 101 /* 102 * Get the current hardware tsf for stamlme 103 */ 104 uint64_t 105 ar5416GetTsf64(struct ath_hal *ah) 106 { 107 uint32_t low1, low2, u32; 108 109 /* sync multi-word read */ 110 low1 = OS_REG_READ(ah, AR_TSF_L32); 111 u32 = OS_REG_READ(ah, AR_TSF_U32); 112 low2 = OS_REG_READ(ah, AR_TSF_L32); 113 if (low2 < low1) { /* roll over */ 114 /* 115 * If we are not preempted this will work. If we are 116 * then we re-reading AR_TSF_U32 does no good as the 117 * low bits will be meaningless. Likewise reading 118 * L32, U32, U32, then comparing the last two reads 119 * to check for rollover doesn't help if preempted--so 120 * we take this approach as it costs one less PCI read 121 * which can be noticeable when doing things like 122 * timestamping packets in monitor mode. 123 */ 124 u32++; 125 } 126 return (((uint64_t) u32) << 32) | ((uint64_t) low2); 127 } 128 129 void 130 ar5416SetTsf64(struct ath_hal *ah, uint64_t tsf64) 131 { 132 OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 133 OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 134 } 135 136 /* 137 * Reset the current hardware tsf for stamlme. 138 */ 139 void 140 ar5416ResetTsf(struct ath_hal *ah) 141 { 142 uint32_t v; 143 int i; 144 145 for (i = 0; i < 10; i++) { 146 v = OS_REG_READ(ah, AR_SLP32_MODE); 147 if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0) 148 break; 149 OS_DELAY(10); 150 } 151 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 152 } 153 154 uint32_t 155 ar5416GetCurRssi(struct ath_hal *ah) 156 { 157 if (AR_SREV_OWL(ah)) 158 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); 159 return (OS_REG_READ(ah, AR9130_PHY_CURRENT_RSSI) & 0xff); 160 } 161 162 HAL_BOOL 163 ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 164 { 165 return AH_TRUE; 166 } 167 168 /* Setup decompression for given key index */ 169 HAL_BOOL 170 ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en) 171 { 172 return AH_TRUE; 173 } 174 175 /* Setup coverage class */ 176 void 177 ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 178 { 179 AH_PRIVATE(ah)->ah_coverageClass = coverageclass; 180 } 181 182 /* 183 * Return the busy for rx_frame, rx_clear, and tx_frame 184 */ 185 uint32_t 186 ar5416GetMibCycleCountsPct(struct ath_hal *ah, uint32_t *rxc_pcnt, 187 uint32_t *extc_pcnt, uint32_t *rxf_pcnt, uint32_t *txf_pcnt) 188 { 189 struct ath_hal_5416 *ahp = AH5416(ah); 190 u_int32_t good = 1; 191 192 /* XXX freeze/unfreeze mib counters */ 193 uint32_t rc = OS_REG_READ(ah, AR_RCCNT); 194 uint32_t ec = OS_REG_READ(ah, AR_EXTRCCNT); 195 uint32_t rf = OS_REG_READ(ah, AR_RFCNT); 196 uint32_t tf = OS_REG_READ(ah, AR_TFCNT); 197 uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 198 199 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cc) { 200 /* 201 * Cycle counter wrap (or initial call); it's not possible 202 * to accurately calculate a value because the registers 203 * right shift rather than wrap--so punt and return 0. 204 */ 205 HALDEBUG(ah, HAL_DEBUG_ANY, 206 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 207 good = 0; 208 } else { 209 uint32_t cc_d = cc - ahp->ah_cycleCount; 210 uint32_t rc_d = rc - ahp->ah_ctlBusy; 211 uint32_t ec_d = ec - ahp->ah_extBusy; 212 uint32_t rf_d = rf - ahp->ah_rxBusy; 213 uint32_t tf_d = tf - ahp->ah_txBusy; 214 215 if (cc_d != 0) { 216 *rxc_pcnt = rc_d * 100 / cc_d; 217 *rxf_pcnt = rf_d * 100 / cc_d; 218 *txf_pcnt = tf_d * 100 / cc_d; 219 *extc_pcnt = ec_d * 100 / cc_d; 220 } else { 221 good = 0; 222 } 223 } 224 ahp->ah_cycleCount = cc; 225 ahp->ah_rxBusy = rf; 226 ahp->ah_ctlBusy = rc; 227 ahp->ah_txBusy = tf; 228 ahp->ah_extBusy = ec; 229 230 return good; 231 } 232 233 /* 234 * Return approximation of extension channel busy over an time interval 235 * 0% (clear) -> 100% (busy) 236 * 237 */ 238 uint32_t 239 ar5416Get11nExtBusy(struct ath_hal *ah) 240 { 241 struct ath_hal_5416 *ahp = AH5416(ah); 242 uint32_t busy; /* percentage */ 243 uint32_t cycleCount, ctlBusy, extBusy; 244 245 ctlBusy = OS_REG_READ(ah, AR_RCCNT); 246 extBusy = OS_REG_READ(ah, AR_EXTRCCNT); 247 cycleCount = OS_REG_READ(ah, AR_CCCNT); 248 249 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cycleCount) { 250 /* 251 * Cycle counter wrap (or initial call); it's not possible 252 * to accurately calculate a value because the registers 253 * right shift rather than wrap--so punt and return 0. 254 */ 255 busy = 0; 256 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n", 257 __func__); 258 259 } else { 260 uint32_t cycleDelta = cycleCount - ahp->ah_cycleCount; 261 uint32_t ctlBusyDelta = ctlBusy - ahp->ah_ctlBusy; 262 uint32_t extBusyDelta = extBusy - ahp->ah_extBusy; 263 uint32_t ctlClearDelta = 0; 264 265 /* Compute control channel rxclear. 266 * The cycle delta may be less than the control channel delta. 267 * This could be solved by freezing the timers (or an atomic read, 268 * if one was available). Checking for the condition should be 269 * sufficient. 270 */ 271 if (cycleDelta > ctlBusyDelta) { 272 ctlClearDelta = cycleDelta - ctlBusyDelta; 273 } 274 275 /* Compute ratio of extension channel busy to control channel clear 276 * as an approximation to extension channel cleanliness. 277 * 278 * According to the hardware folks, ext rxclear is undefined 279 * if the ctrl rxclear is de-asserted (i.e. busy) 280 */ 281 if (ctlClearDelta) { 282 busy = (extBusyDelta * 100) / ctlClearDelta; 283 } else { 284 busy = 100; 285 } 286 if (busy > 100) { 287 busy = 100; 288 } 289 #if 0 290 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, " 291 "extBusyDelta 0x%x, ctlClearDelta 0x%x, " 292 "busy %d\n", 293 __func__, cycleDelta, ctlBusyDelta, extBusyDelta, ctlClearDelta, busy); 294 #endif 295 } 296 297 ahp->ah_cycleCount = cycleCount; 298 ahp->ah_ctlBusy = ctlBusy; 299 ahp->ah_extBusy = extBusy; 300 301 return busy; 302 } 303 304 /* 305 * Configure 20/40 operation 306 * 307 * 20/40 = joint rx clear (control and extension) 308 * 20 = rx clear (control) 309 * 310 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz when changing 311 * from 20/40 => 20 only 312 */ 313 void 314 ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 315 { 316 uint32_t macmode; 317 318 /* Configure MAC for 20/40 operation */ 319 if (mode == HAL_HT_MACMODE_2040) { 320 macmode = AR_2040_JOINED_RX_CLEAR; 321 } else { 322 macmode = 0; 323 } 324 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 325 } 326 327 /* 328 * Get Rx clear (control/extension channel) 329 * 330 * Returns active low (busy) for ctrl/ext channel 331 * Owl 2.0 332 */ 333 HAL_HT_RXCLEAR 334 ar5416Get11nRxClear(struct ath_hal *ah) 335 { 336 HAL_HT_RXCLEAR rxclear = 0; 337 uint32_t val; 338 339 val = OS_REG_READ(ah, AR_DIAG_SW); 340 341 /* control channel */ 342 if (val & AR_DIAG_RXCLEAR_CTL_LOW) { 343 rxclear |= HAL_RX_CLEAR_CTL_LOW; 344 } 345 /* extension channel */ 346 if (val & AR_DIAG_RXCLEAR_EXT_LOW) { 347 rxclear |= HAL_RX_CLEAR_EXT_LOW; 348 } 349 return rxclear; 350 } 351 352 /* 353 * Set Rx clear (control/extension channel) 354 * 355 * Useful for forcing the channel to appear busy for 356 * debugging/diagnostics 357 * Owl 2.0 358 */ 359 void 360 ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 361 { 362 /* control channel */ 363 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 364 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 365 } else { 366 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 367 } 368 /* extension channel */ 369 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 370 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 371 } else { 372 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 373 } 374 } 375 376 /* XXX shouldn't be here! */ 377 #define TU_TO_USEC(_tu) ((_tu) << 10) 378 379 HAL_STATUS 380 ar5416SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration, 381 uint32_t nextStart, HAL_QUIET_FLAG flag) 382 { 383 uint32_t period_us = TU_TO_USEC(period); /* convert to us unit */ 384 uint32_t nextStart_us = TU_TO_USEC(nextStart); /* convert to us unit */ 385 if (flag & HAL_QUIET_ENABLE) { 386 if ((!nextStart) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 387 /* Add the nextStart offset to the current TSF */ 388 nextStart_us += OS_REG_READ(ah, AR_TSF_L32); 389 } 390 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 391 nextStart_us += ah->ah_config.ah_sw_beacon_response_time; 392 } 393 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 394 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 395 OS_REG_WRITE(ah, AR_QUIET_PERIOD, period_us); 396 OS_REG_WRITE(ah, AR_NEXT_QUIET, nextStart_us); 397 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 398 } else { 399 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 400 } 401 return HAL_OK; 402 } 403 #undef TU_TO_USEC 404 405 HAL_STATUS 406 ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 407 uint32_t capability, uint32_t *result) 408 { 409 switch (type) { 410 case HAL_CAP_BB_HANG: 411 switch (capability) { 412 case HAL_BB_HANG_RIFS: 413 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 414 case HAL_BB_HANG_DFS: 415 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 416 case HAL_BB_HANG_RX_CLEAR: 417 return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP; 418 } 419 break; 420 case HAL_CAP_MAC_HANG: 421 return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || 422 (ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) || 423 AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? 424 HAL_OK : HAL_ENOTSUPP; 425 case HAL_CAP_DIVERSITY: /* disable classic fast diversity */ 426 return HAL_ENXIO; 427 default: 428 break; 429 } 430 return ar5212GetCapability(ah, type, capability, result); 431 } 432 433 static int ar5416DetectMacHang(struct ath_hal *ah); 434 static int ar5416DetectBBHang(struct ath_hal *ah); 435 436 HAL_BOOL 437 ar5416GetDiagState(struct ath_hal *ah, int request, 438 const void *args, uint32_t argsize, 439 void **result, uint32_t *resultsize) 440 { 441 struct ath_hal_5416 *ahp = AH5416(ah); 442 int hangs; 443 444 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) 445 return AH_TRUE; 446 switch (request) { 447 case HAL_DIAG_EEPROM: 448 return ath_hal_eepromDiag(ah, request, 449 args, argsize, result, resultsize); 450 case HAL_DIAG_CHECK_HANGS: 451 if (argsize != sizeof(int)) 452 return AH_FALSE; 453 hangs = *(const int *) args; 454 ahp->ah_hangs = 0; 455 if (hangs & HAL_BB_HANGS) 456 ahp->ah_hangs |= ar5416DetectBBHang(ah); 457 /* NB: if BB is hung MAC will be hung too so skip check */ 458 if (ahp->ah_hangs == 0 && (hangs & HAL_MAC_HANGS)) 459 ahp->ah_hangs |= ar5416DetectMacHang(ah); 460 *result = &ahp->ah_hangs; 461 *resultsize = sizeof(ahp->ah_hangs); 462 return AH_TRUE; 463 } 464 return ar5212GetDiagState(ah, request, 465 args, argsize, result, resultsize); 466 } 467 468 typedef struct { 469 uint32_t dma_dbg_3; 470 uint32_t dma_dbg_4; 471 uint32_t dma_dbg_5; 472 uint32_t dma_dbg_6; 473 } mac_dbg_regs_t; 474 475 typedef enum { 476 dcu_chain_state = 0x1, 477 dcu_complete_state = 0x2, 478 qcu_state = 0x4, 479 qcu_fsp_ok = 0x8, 480 qcu_fsp_state = 0x10, 481 qcu_stitch_state = 0x20, 482 qcu_fetch_state = 0x40, 483 qcu_complete_state = 0x80 484 } hal_mac_hangs_t; 485 486 typedef struct { 487 int states; 488 uint8_t dcu_chain_state; 489 uint8_t dcu_complete_state; 490 uint8_t qcu_state; 491 uint8_t qcu_fsp_ok; 492 uint8_t qcu_fsp_state; 493 uint8_t qcu_stitch_state; 494 uint8_t qcu_fetch_state; 495 uint8_t qcu_complete_state; 496 } hal_mac_hang_check_t; 497 498 HAL_BOOL 499 ar5416SetRifsDelay(struct ath_hal *ah, const struct ieee80211_channel *chan, 500 HAL_BOOL enable) 501 { 502 uint32_t val; 503 HAL_BOOL is_chan_2g = AH_FALSE; 504 HAL_BOOL is_ht40 = AH_FALSE; 505 506 if (chan) 507 is_chan_2g = IEEE80211_IS_CHAN_2GHZ(chan); 508 509 if (chan) 510 is_ht40 = IEEE80211_IS_CHAN_HT40(chan); 511 512 /* Only support disabling RIFS delay for now */ 513 HALASSERT(enable == AH_FALSE); 514 515 if (enable == AH_TRUE) 516 return AH_FALSE; 517 518 /* Change RIFS init delay to 0 */ 519 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 520 val &= ~AR_PHY_RIFS_INIT_DELAY; 521 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 522 523 /* 524 * For Owl, RIFS RX parameters are controlled differently; 525 * it isn't enabled in the inivals by default. 526 * 527 * For Sowl/Howl, RIFS RX is enabled in the inivals by default; 528 * the following code sets them back to non-RIFS values. 529 * 530 * For > Sowl/Howl, RIFS RX can be left on by default and so 531 * this function shouldn't be called. 532 */ 533 if ((! AR_SREV_SOWL(ah)) && (! AR_SREV_HOWL(ah))) 534 return AH_TRUE; 535 536 /* Reset search delay to default values */ 537 if (is_chan_2g) 538 if (is_ht40) 539 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x268); 540 else 541 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x134); 542 else 543 if (is_ht40) 544 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x370); 545 else 546 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x1b8); 547 548 return AH_TRUE; 549 } 550 551 static HAL_BOOL 552 ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs, 553 const hal_mac_hang_check_t *check) 554 { 555 int found_states; 556 557 found_states = 0; 558 if (check->states & dcu_chain_state) { 559 int i; 560 561 for (i = 0; i < 6; i++) { 562 if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) == 563 check->dcu_chain_state) 564 found_states |= dcu_chain_state; 565 } 566 for (i = 0; i < 4; i++) { 567 if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) == 568 check->dcu_chain_state) 569 found_states |= dcu_chain_state; 570 } 571 } 572 if (check->states & dcu_complete_state) { 573 if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state) 574 found_states |= dcu_complete_state; 575 } 576 if (check->states & qcu_stitch_state) { 577 if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state) 578 found_states |= qcu_stitch_state; 579 } 580 if (check->states & qcu_fetch_state) { 581 if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state) 582 found_states |= qcu_fetch_state; 583 } 584 if (check->states & qcu_complete_state) { 585 if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state) 586 found_states |= qcu_complete_state; 587 } 588 return (found_states == check->states); 589 } 590 591 #define NUM_STATUS_READS 50 592 593 static int 594 ar5416DetectMacHang(struct ath_hal *ah) 595 { 596 static const hal_mac_hang_check_t hang_sig1 = { 597 .dcu_chain_state = 0x6, 598 .dcu_complete_state = 0x1, 599 .states = dcu_chain_state 600 | dcu_complete_state, 601 }; 602 static const hal_mac_hang_check_t hang_sig2 = { 603 .qcu_stitch_state = 0x9, 604 .qcu_fetch_state = 0x8, 605 .qcu_complete_state = 0x4, 606 .states = qcu_stitch_state 607 | qcu_fetch_state 608 | qcu_complete_state, 609 }; 610 mac_dbg_regs_t mac_dbg; 611 int i; 612 613 mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3); 614 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 615 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 616 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 617 for (i = 1; i <= NUM_STATUS_READS; i++) { 618 if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) || 619 mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) || 620 mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) || 621 mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6)) 622 return 0; 623 } 624 625 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1)) 626 return HAL_MAC_HANG_SIG1; 627 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2)) 628 return HAL_MAC_HANG_SIG2; 629 630 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown MAC hang signature " 631 "DMADBG_3=0x%x DMADBG_4=0x%x DMADBG_5=0x%x DMADBG_6=0x%x\n", 632 __func__, mac_dbg.dma_dbg_3, mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 633 mac_dbg.dma_dbg_6); 634 635 return 0; 636 } 637 638 /* 639 * Determine if the baseband using the Observation Bus Register 640 */ 641 static int 642 ar5416DetectBBHang(struct ath_hal *ah) 643 { 644 #define N(a) (sizeof(a)/sizeof(a[0])) 645 /* 646 * Check the PCU Observation Bus 1 register (0x806c) 647 * NUM_STATUS_READS times 648 * 649 * 4 known BB hang signatures - 650 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 651 * [2] bits 8,9 are 1, bit 11 is 0. State machine state 652 * (bits 25-31) is 0x52 653 * [3] bits 8,9 are 1, bit 11 is 0. State machine state 654 * (bits 25-31) is 0x18 655 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 656 * Rx State (bits 20-24) is 0x7. 657 */ 658 static const struct { 659 uint32_t val; 660 uint32_t mask; 661 int code; 662 } hang_list[] = { 663 /* Reg Value Reg Mask Hang Code XXX */ 664 { 0x1E000000, 0x7E000B00, HAL_BB_HANG_DFS }, 665 { 0x52000B00, 0x7E000B00, HAL_BB_HANG_RIFS }, 666 { 0x18000B00, 0x7E000B00, HAL_BB_HANG_RX_CLEAR }, 667 { 0x00702400, 0x7E7FFFEF, HAL_BB_HANG_RX_CLEAR } 668 }; 669 uint32_t hang_sig; 670 int i; 671 672 hang_sig = OS_REG_READ(ah, AR_OBSERV_1); 673 for (i = 1; i <= NUM_STATUS_READS; i++) { 674 if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1)) 675 return 0; 676 } 677 for (i = 0; i < N(hang_list); i++) 678 if ((hang_sig & hang_list[i].mask) == hang_list[i].val) { 679 HALDEBUG(ah, HAL_DEBUG_HANG, 680 "%s BB hang, signature 0x%x, code 0x%x\n", 681 __func__, hang_sig, hang_list[i].code); 682 return hang_list[i].code; 683 } 684 685 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown BB hang signature! " 686 "<0x806c>=0x%x\n", __func__, hang_sig); 687 688 return 0; 689 #undef N 690 } 691 #undef NUM_STATUS_READS 692 693 /* 694 * Get the radar parameter values and return them in the pe 695 * structure 696 */ 697 void 698 ar5416GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) 699 { 700 uint32_t val, temp; 701 702 val = OS_REG_READ(ah, AR_PHY_RADAR_0); 703 704 temp = MS(val,AR_PHY_RADAR_0_FIRPWR); 705 temp |= 0xFFFFFF80; 706 pe->pe_firpwr = temp; 707 pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI); 708 pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT); 709 pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI); 710 pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND); 711 712 val = OS_REG_READ(ah, AR_PHY_RADAR_1); 713 temp = val & AR_PHY_RADAR_1_RELPWR_ENA; 714 pe->pe_relpwr = MS(val, AR_PHY_RADAR_1_RELPWR_THRESH); 715 if (temp) 716 pe->pe_relpwr |= HAL_PHYERR_PARAM_ENABLE; 717 temp = val & AR_PHY_RADAR_1_RELSTEP_CHECK; 718 pe->pe_relstep = MS(val, AR_PHY_RADAR_1_RELSTEP_THRESH); 719 if (temp) 720 pe->pe_enabled = 1; 721 else 722 pe->pe_enabled = 0; 723 724 pe->pe_maxlen = MS(val, AR_PHY_RADAR_1_MAXLEN); 725 pe->pe_extchannel = !! (OS_REG_READ(ah, AR_PHY_RADAR_EXT) & 726 AR_PHY_RADAR_EXT_ENA); 727 728 pe->pe_usefir128 = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) & 729 AR_PHY_RADAR_1_USE_FIR128); 730 pe->pe_blockradar = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) & 731 AR_PHY_RADAR_1_BLOCK_CHECK); 732 pe->pe_enmaxrssi = !! (OS_REG_READ(ah, AR_PHY_RADAR_1) & 733 AR_PHY_RADAR_1_MAX_RRSSI); 734 } 735 736 /* 737 * Enable radar detection and set the radar parameters per the 738 * values in pe 739 */ 740 void 741 ar5416EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) 742 { 743 uint32_t val; 744 745 val = OS_REG_READ(ah, AR_PHY_RADAR_0); 746 747 if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) { 748 val &= ~AR_PHY_RADAR_0_FIRPWR; 749 val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR); 750 } 751 if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) { 752 val &= ~AR_PHY_RADAR_0_RRSSI; 753 val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI); 754 } 755 if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) { 756 val &= ~AR_PHY_RADAR_0_HEIGHT; 757 val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT); 758 } 759 if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) { 760 val &= ~AR_PHY_RADAR_0_PRSSI; 761 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI); 762 } 763 if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) { 764 val &= ~AR_PHY_RADAR_0_INBAND; 765 val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND); 766 } 767 768 /*Enable FFT data*/ 769 val |= AR_PHY_RADAR_0_FFT_ENA; 770 771 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA); 772 773 if (pe->pe_usefir128 == 1) 774 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_USE_FIR128); 775 else if (pe->pe_usefir128 == 0) 776 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_USE_FIR128); 777 778 if (pe->pe_enmaxrssi == 1) 779 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_MAX_RRSSI); 780 else if (pe->pe_enmaxrssi == 0) 781 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_MAX_RRSSI); 782 783 if (pe->pe_blockradar == 1) 784 OS_REG_SET_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_BLOCK_CHECK); 785 else if (pe->pe_blockradar == 0) 786 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_1, AR_PHY_RADAR_1_BLOCK_CHECK); 787 788 if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL) { 789 val = OS_REG_READ(ah, AR_PHY_RADAR_1); 790 val &= ~AR_PHY_RADAR_1_MAXLEN; 791 val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN); 792 OS_REG_WRITE(ah, AR_PHY_RADAR_1, val); 793 } 794 795 /* 796 * Enable HT/40 if the upper layer asks; 797 * it should check the channel is HT/40 and HAL_CAP_EXT_CHAN_DFS 798 * is available. 799 */ 800 if (pe->pe_extchannel == 1) 801 OS_REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 802 else if (pe->pe_extchannel == 0) 803 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 804 805 if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL) { 806 val = OS_REG_READ(ah, AR_PHY_RADAR_1); 807 val &= ~AR_PHY_RADAR_1_RELSTEP_THRESH; 808 val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH); 809 OS_REG_WRITE(ah, AR_PHY_RADAR_1, val); 810 } 811 if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL) { 812 val = OS_REG_READ(ah, AR_PHY_RADAR_1); 813 val &= ~AR_PHY_RADAR_1_RELPWR_THRESH; 814 val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH); 815 OS_REG_WRITE(ah, AR_PHY_RADAR_1, val); 816 } 817 } 818 819 /* 820 * Extract the radar event information from the given phy error. 821 * 822 * Returns AH_TRUE if the phy error was actually a phy error, 823 * AH_FALSE if the phy error wasn't a phy error. 824 */ 825 826 /* Flags for pulse_bw_info */ 827 #define PRI_CH_RADAR_FOUND 0x01 828 #define EXT_CH_RADAR_FOUND 0x02 829 #define EXT_CH_RADAR_EARLY_FOUND 0x04 830 831 HAL_BOOL 832 ar5416ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs, 833 uint64_t fulltsf, const char *buf, HAL_DFS_EVENT *event) 834 { 835 HAL_BOOL doDfsExtCh; 836 HAL_BOOL doDfsEnhanced; 837 HAL_BOOL doDfsCombinedRssi; 838 839 uint8_t rssi = 0, ext_rssi = 0; 840 uint8_t pulse_bw_info = 0, pulse_length_ext = 0, pulse_length_pri = 0; 841 uint32_t dur = 0; 842 int pri_found = 1, ext_found = 0; 843 int early_ext = 0; 844 int is_dc = 0; 845 uint16_t datalen; /* length from the RX status field */ 846 847 /* Check whether the given phy error is a radar event */ 848 if ((rxs->rs_phyerr != HAL_PHYERR_RADAR) && 849 (rxs->rs_phyerr != HAL_PHYERR_FALSE_RADAR_EXT)) { 850 return AH_FALSE; 851 } 852 853 /* Grab copies of the capabilities; just to make the code clearer */ 854 doDfsExtCh = AH_PRIVATE(ah)->ah_caps.halExtChanDfsSupport; 855 doDfsEnhanced = AH_PRIVATE(ah)->ah_caps.halEnhancedDfsSupport; 856 doDfsCombinedRssi = AH_PRIVATE(ah)->ah_caps.halUseCombinedRadarRssi; 857 858 datalen = rxs->rs_datalen; 859 860 /* If hardware supports it, use combined RSSI, else use chain 0 RSSI */ 861 if (doDfsCombinedRssi) 862 rssi = (uint8_t) rxs->rs_rssi; 863 else 864 rssi = (uint8_t) rxs->rs_rssi_ctl[0]; 865 866 /* Set this; but only use it if doDfsExtCh is set */ 867 ext_rssi = (uint8_t) rxs->rs_rssi_ext[0]; 868 869 /* Cap it at 0 if the RSSI is a negative number */ 870 if (rssi & 0x80) 871 rssi = 0; 872 873 if (ext_rssi & 0x80) 874 ext_rssi = 0; 875 876 /* 877 * Fetch the relevant data from the frame 878 */ 879 if (doDfsExtCh) { 880 if (datalen < 3) 881 return AH_FALSE; 882 883 /* Last three bytes of the frame are of interest */ 884 pulse_length_pri = *(buf + datalen - 3); 885 pulse_length_ext = *(buf + datalen - 2); 886 pulse_bw_info = *(buf + datalen - 1); 887 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, ext_rssi=%d, pulse_length_pri=%d," 888 " pulse_length_ext=%d, pulse_bw_info=%x\n", 889 __func__, rssi, ext_rssi, pulse_length_pri, pulse_length_ext, 890 pulse_bw_info); 891 } else { 892 /* The pulse width is byte 0 of the data */ 893 if (datalen >= 1) 894 dur = ((uint8_t) buf[0]) & 0xff; 895 else 896 dur = 0; 897 898 if (dur == 0 && rssi == 0) { 899 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: dur and rssi are 0\n", __func__); 900 return AH_FALSE; 901 } 902 903 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d\n", __func__, rssi, dur); 904 905 /* Single-channel only */ 906 pri_found = 1; 907 ext_found = 0; 908 } 909 910 /* 911 * If doing extended channel data, pulse_bw_info must 912 * have one of the flags set. 913 */ 914 if (doDfsExtCh && pulse_bw_info == 0x0) 915 return AH_FALSE; 916 917 /* 918 * If the extended channel data is available, calculate 919 * which to pay attention to. 920 */ 921 if (doDfsExtCh) { 922 /* If pulse is on DC, take the larger duration of the two */ 923 if ((pulse_bw_info & EXT_CH_RADAR_FOUND) && 924 (pulse_bw_info & PRI_CH_RADAR_FOUND)) { 925 is_dc = 1; 926 if (pulse_length_ext > pulse_length_pri) { 927 dur = pulse_length_ext; 928 pri_found = 0; 929 ext_found = 1; 930 } else { 931 dur = pulse_length_pri; 932 pri_found = 1; 933 ext_found = 0; 934 } 935 } else if (pulse_bw_info & EXT_CH_RADAR_EARLY_FOUND) { 936 dur = pulse_length_ext; 937 pri_found = 0; 938 ext_found = 1; 939 early_ext = 1; 940 } else if (pulse_bw_info & PRI_CH_RADAR_FOUND) { 941 dur = pulse_length_pri; 942 pri_found = 1; 943 ext_found = 0; 944 } else if (pulse_bw_info & EXT_CH_RADAR_FOUND) { 945 dur = pulse_length_ext; 946 pri_found = 0; 947 ext_found = 1; 948 } 949 950 } 951 952 /* 953 * For enhanced DFS (Merlin and later), pulse_bw_info has 954 * implications for selecting the correct RSSI value. 955 */ 956 if (doDfsEnhanced) { 957 switch (pulse_bw_info & 0x03) { 958 case 0: 959 /* No radar? */ 960 rssi = 0; 961 break; 962 case PRI_CH_RADAR_FOUND: 963 /* Radar in primary channel */ 964 /* Cannot use ctrl channel RSSI if ext channel is stronger */ 965 if (ext_rssi >= (rssi + 3)) { 966 rssi = 0; 967 }; 968 break; 969 case EXT_CH_RADAR_FOUND: 970 /* Radar in extended channel */ 971 /* Cannot use ext channel RSSI if ctrl channel is stronger */ 972 if (rssi >= (ext_rssi + 12)) { 973 rssi = 0; 974 } else { 975 rssi = ext_rssi; 976 } 977 break; 978 case (PRI_CH_RADAR_FOUND | EXT_CH_RADAR_FOUND): 979 /* When both are present, use stronger one */ 980 if (rssi < ext_rssi) 981 rssi = ext_rssi; 982 break; 983 } 984 } 985 986 /* 987 * If not doing enhanced DFS, choose the ext channel if 988 * it is stronger than the main channel 989 */ 990 if (doDfsExtCh && !doDfsEnhanced) { 991 if ((ext_rssi > rssi) && (ext_rssi < 128)) 992 rssi = ext_rssi; 993 } 994 995 /* 996 * XXX what happens if the above code decides the RSSI 997 * XXX wasn't valid, an sets it to 0? 998 */ 999 1000 /* 1001 * Fill out dfs_event structure. 1002 */ 1003 event->re_full_ts = fulltsf; 1004 event->re_ts = rxs->rs_tstamp; 1005 event->re_rssi = rssi; 1006 event->re_dur = dur; 1007 1008 event->re_flags = 0; 1009 if (pri_found) 1010 event->re_flags |= HAL_DFS_EVENT_PRICH; 1011 if (ext_found) 1012 event->re_flags |= HAL_DFS_EVENT_EXTCH; 1013 if (early_ext) 1014 event->re_flags |= HAL_DFS_EVENT_EXTEARLY; 1015 if (is_dc) 1016 event->re_flags |= HAL_DFS_EVENT_ISDC; 1017 1018 return AH_TRUE; 1019 } 1020 1021 /* 1022 * Return whether fast-clock is currently enabled for this 1023 * channel. 1024 */ 1025 HAL_BOOL 1026 ar5416IsFastClockEnabled(struct ath_hal *ah) 1027 { 1028 struct ath_hal_private *ahp = AH_PRIVATE(ah); 1029 1030 return IS_5GHZ_FAST_CLOCK_EN(ah, ahp->ah_curchan); 1031 } 1032