1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 #include "ah_desc.h" /* NB: for HAL_PHYERR* */ 25 26 #include "ar5416/ar5416.h" 27 #include "ar5416/ar5416reg.h" 28 #include "ar5416/ar5416phy.h" 29 30 #include "ah_eeprom_v14.h" /* for owl_get_ntxchains() */ 31 32 /* 33 * Return the wireless modes (a,b,g,n,t) supported by hardware. 34 * 35 * This value is what is actually supported by the hardware 36 * and is unaffected by regulatory/country code settings. 37 * 38 */ 39 u_int 40 ar5416GetWirelessModes(struct ath_hal *ah) 41 { 42 u_int mode; 43 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 44 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 45 46 mode = ar5212GetWirelessModes(ah); 47 48 /* Only enable HT modes if the NIC supports HT */ 49 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11A)) 50 mode |= HAL_MODE_11NA_HT20 51 | HAL_MODE_11NA_HT40PLUS 52 | HAL_MODE_11NA_HT40MINUS 53 ; 54 if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11G)) 55 mode |= HAL_MODE_11NG_HT20 56 | HAL_MODE_11NG_HT40PLUS 57 | HAL_MODE_11NG_HT40MINUS 58 ; 59 return mode; 60 } 61 62 /* 63 * Change the LED blinking pattern to correspond to the connectivity 64 */ 65 void 66 ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state) 67 { 68 static const uint32_t ledbits[8] = { 69 AR_MAC_LED_ASSOC_NONE, /* HAL_LED_INIT */ 70 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_SCAN */ 71 AR_MAC_LED_ASSOC_PEND, /* HAL_LED_AUTH */ 72 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC*/ 73 AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 74 AR_MAC_LED_ASSOC_NONE, 75 AR_MAC_LED_ASSOC_NONE, 76 AR_MAC_LED_ASSOC_NONE, 77 }; 78 79 if (AR_SREV_HOWL(ah)) 80 return; 81 82 /* 83 * Set the blink operating mode. 84 */ 85 OS_REG_RMW_FIELD(ah, AR_MAC_LED, 86 AR_MAC_LED_ASSOC, ledbits[state & 0x7]); 87 88 /* XXX Blink slow mode? */ 89 /* XXX Blink threshold? */ 90 /* XXX Blink sleep hystersis? */ 91 92 /* 93 * Set the LED blink configuration to be proportional 94 * to the current TX and RX filter bytes. (Ie, RX'ed 95 * frames that don't match the filter are ignored.) 96 * This means that higher TX/RX throughput will result 97 * in the blink rate increasing. 98 */ 99 OS_REG_RMW_FIELD(ah, AR_MAC_LED, AR_MAC_LED_MODE, 100 AR_MAC_LED_MODE_PROP); 101 } 102 103 /* 104 * Get the current hardware tsf for stamlme 105 */ 106 uint64_t 107 ar5416GetTsf64(struct ath_hal *ah) 108 { 109 uint32_t low1, low2, u32; 110 111 /* sync multi-word read */ 112 low1 = OS_REG_READ(ah, AR_TSF_L32); 113 u32 = OS_REG_READ(ah, AR_TSF_U32); 114 low2 = OS_REG_READ(ah, AR_TSF_L32); 115 if (low2 < low1) { /* roll over */ 116 /* 117 * If we are not preempted this will work. If we are 118 * then we re-reading AR_TSF_U32 does no good as the 119 * low bits will be meaningless. Likewise reading 120 * L32, U32, U32, then comparing the last two reads 121 * to check for rollover doesn't help if preempted--so 122 * we take this approach as it costs one less PCI read 123 * which can be noticeable when doing things like 124 * timestamping packets in monitor mode. 125 */ 126 u32++; 127 } 128 return (((uint64_t) u32) << 32) | ((uint64_t) low2); 129 } 130 131 void 132 ar5416SetTsf64(struct ath_hal *ah, uint64_t tsf64) 133 { 134 OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 135 OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 136 } 137 138 /* 139 * Reset the current hardware tsf for stamlme. 140 */ 141 void 142 ar5416ResetTsf(struct ath_hal *ah) 143 { 144 uint32_t v; 145 int i; 146 147 for (i = 0; i < 10; i++) { 148 v = OS_REG_READ(ah, AR_SLP32_MODE); 149 if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0) 150 break; 151 OS_DELAY(10); 152 } 153 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 154 } 155 156 uint32_t 157 ar5416GetCurRssi(struct ath_hal *ah) 158 { 159 if (AR_SREV_OWL(ah)) 160 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); 161 return (OS_REG_READ(ah, AR9130_PHY_CURRENT_RSSI) & 0xff); 162 } 163 164 HAL_BOOL 165 ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 166 { 167 return AH_TRUE; 168 } 169 170 /* Setup decompression for given key index */ 171 HAL_BOOL 172 ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en) 173 { 174 return AH_TRUE; 175 } 176 177 /* Setup coverage class */ 178 void 179 ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 180 { 181 AH_PRIVATE(ah)->ah_coverageClass = coverageclass; 182 } 183 184 /* 185 * Return the busy for rx_frame, rx_clear, and tx_frame 186 */ 187 HAL_BOOL 188 ar5416GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample) 189 { 190 struct ath_hal_5416 *ahp = AH5416(ah); 191 u_int32_t good = AH_TRUE; 192 193 /* XXX freeze/unfreeze mib counters */ 194 uint32_t rc = OS_REG_READ(ah, AR_RCCNT); 195 uint32_t ec = OS_REG_READ(ah, AR_EXTRCCNT); 196 uint32_t rf = OS_REG_READ(ah, AR_RFCNT); 197 uint32_t tf = OS_REG_READ(ah, AR_TFCNT); 198 uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 199 200 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cc) { 201 /* 202 * Cycle counter wrap (or initial call); it's not possible 203 * to accurately calculate a value because the registers 204 * right shift rather than wrap--so punt and return 0. 205 */ 206 HALDEBUG(ah, HAL_DEBUG_ANY, 207 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 208 good = AH_FALSE; 209 } else { 210 hsample->cycle_count = cc - ahp->ah_cycleCount; 211 hsample->chan_busy = rc - ahp->ah_ctlBusy; 212 hsample->ext_chan_busy = ec - ahp->ah_extBusy; 213 hsample->rx_busy = rf - ahp->ah_rxBusy; 214 hsample->tx_busy = tf - ahp->ah_txBusy; 215 } 216 217 /* 218 * Keep a copy of the MIB results so the next sample has something 219 * to work from. 220 */ 221 ahp->ah_cycleCount = cc; 222 ahp->ah_rxBusy = rf; 223 ahp->ah_ctlBusy = rc; 224 ahp->ah_txBusy = tf; 225 ahp->ah_extBusy = ec; 226 227 return (good); 228 } 229 230 /* 231 * Return approximation of extension channel busy over an time interval 232 * 0% (clear) -> 100% (busy) 233 * 234 * XXX TODO: update this to correctly sample all the counters, 235 * rather than a subset of it. 236 */ 237 uint32_t 238 ar5416Get11nExtBusy(struct ath_hal *ah) 239 { 240 struct ath_hal_5416 *ahp = AH5416(ah); 241 uint32_t busy; /* percentage */ 242 uint32_t cycleCount, ctlBusy, extBusy; 243 244 ctlBusy = OS_REG_READ(ah, AR_RCCNT); 245 extBusy = OS_REG_READ(ah, AR_EXTRCCNT); 246 cycleCount = OS_REG_READ(ah, AR_CCCNT); 247 248 if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cycleCount) { 249 /* 250 * Cycle counter wrap (or initial call); it's not possible 251 * to accurately calculate a value because the registers 252 * right shift rather than wrap--so punt and return 0. 253 */ 254 busy = 0; 255 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n", 256 __func__); 257 258 } else { 259 uint32_t cycleDelta = cycleCount - ahp->ah_cycleCount; 260 uint32_t ctlBusyDelta = ctlBusy - ahp->ah_ctlBusy; 261 uint32_t extBusyDelta = extBusy - ahp->ah_extBusy; 262 uint32_t ctlClearDelta = 0; 263 264 /* Compute control channel rxclear. 265 * The cycle delta may be less than the control channel delta. 266 * This could be solved by freezing the timers (or an atomic read, 267 * if one was available). Checking for the condition should be 268 * sufficient. 269 */ 270 if (cycleDelta > ctlBusyDelta) { 271 ctlClearDelta = cycleDelta - ctlBusyDelta; 272 } 273 274 /* Compute ratio of extension channel busy to control channel clear 275 * as an approximation to extension channel cleanliness. 276 * 277 * According to the hardware folks, ext rxclear is undefined 278 * if the ctrl rxclear is de-asserted (i.e. busy) 279 */ 280 if (ctlClearDelta) { 281 busy = (extBusyDelta * 100) / ctlClearDelta; 282 } else { 283 busy = 100; 284 } 285 if (busy > 100) { 286 busy = 100; 287 } 288 #if 0 289 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, " 290 "extBusyDelta 0x%x, ctlClearDelta 0x%x, " 291 "busy %d\n", 292 __func__, cycleDelta, ctlBusyDelta, extBusyDelta, ctlClearDelta, busy); 293 #endif 294 } 295 296 ahp->ah_cycleCount = cycleCount; 297 ahp->ah_ctlBusy = ctlBusy; 298 ahp->ah_extBusy = extBusy; 299 300 return busy; 301 } 302 303 /* 304 * Configure 20/40 operation 305 * 306 * 20/40 = joint rx clear (control and extension) 307 * 20 = rx clear (control) 308 * 309 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz when changing 310 * from 20/40 => 20 only 311 */ 312 void 313 ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 314 { 315 uint32_t macmode; 316 317 /* Configure MAC for 20/40 operation */ 318 if (mode == HAL_HT_MACMODE_2040) { 319 macmode = AR_2040_JOINED_RX_CLEAR; 320 } else { 321 macmode = 0; 322 } 323 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 324 } 325 326 /* 327 * Get Rx clear (control/extension channel) 328 * 329 * Returns active low (busy) for ctrl/ext channel 330 * Owl 2.0 331 */ 332 HAL_HT_RXCLEAR 333 ar5416Get11nRxClear(struct ath_hal *ah) 334 { 335 HAL_HT_RXCLEAR rxclear = 0; 336 uint32_t val; 337 338 val = OS_REG_READ(ah, AR_DIAG_SW); 339 340 /* control channel */ 341 if (val & AR_DIAG_RXCLEAR_CTL_LOW) { 342 rxclear |= HAL_RX_CLEAR_CTL_LOW; 343 } 344 /* extension channel */ 345 if (val & AR_DIAG_RXCLEAR_EXT_LOW) { 346 rxclear |= HAL_RX_CLEAR_EXT_LOW; 347 } 348 return rxclear; 349 } 350 351 /* 352 * Set Rx clear (control/extension channel) 353 * 354 * Useful for forcing the channel to appear busy for 355 * debugging/diagnostics 356 * Owl 2.0 357 */ 358 void 359 ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 360 { 361 /* control channel */ 362 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 363 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 364 } else { 365 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW); 366 } 367 /* extension channel */ 368 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 369 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 370 } else { 371 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW); 372 } 373 } 374 375 /* XXX shouldn't be here! */ 376 #define TU_TO_USEC(_tu) ((_tu) << 10) 377 378 HAL_STATUS 379 ar5416SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration, 380 uint32_t nextStart, HAL_QUIET_FLAG flag) 381 { 382 uint32_t period_us = TU_TO_USEC(period); /* convert to us unit */ 383 uint32_t nextStart_us = TU_TO_USEC(nextStart); /* convert to us unit */ 384 if (flag & HAL_QUIET_ENABLE) { 385 if ((!nextStart) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 386 /* Add the nextStart offset to the current TSF */ 387 nextStart_us += OS_REG_READ(ah, AR_TSF_L32); 388 } 389 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 390 nextStart_us += ah->ah_config.ah_sw_beacon_response_time; 391 } 392 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 393 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 394 OS_REG_WRITE(ah, AR_QUIET_PERIOD, period_us); 395 OS_REG_WRITE(ah, AR_NEXT_QUIET, nextStart_us); 396 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 397 } else { 398 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET); 399 } 400 return HAL_OK; 401 } 402 #undef TU_TO_USEC 403 404 HAL_STATUS 405 ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 406 uint32_t capability, uint32_t *result) 407 { 408 switch (type) { 409 case HAL_CAP_BB_HANG: 410 switch (capability) { 411 case HAL_BB_HANG_RIFS: 412 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 413 case HAL_BB_HANG_DFS: 414 return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP; 415 case HAL_BB_HANG_RX_CLEAR: 416 return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP; 417 } 418 break; 419 case HAL_CAP_MAC_HANG: 420 return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || 421 (ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) || 422 AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? 423 HAL_OK : HAL_ENOTSUPP; 424 case HAL_CAP_DIVERSITY: /* disable classic fast diversity */ 425 return HAL_ENXIO; 426 default: 427 break; 428 } 429 return ar5212GetCapability(ah, type, capability, result); 430 } 431 432 HAL_BOOL 433 ar5416SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 434 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 435 { 436 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 437 438 switch (type) { 439 case HAL_CAP_RX_CHAINMASK: 440 setting &= ath_hal_eepromGet(ah, AR_EEP_RXMASK, NULL); 441 pCap->halRxChainMask = setting; 442 if (owl_get_ntxchains(setting) > 2) 443 pCap->halRxStreams = 2; 444 else 445 pCap->halRxStreams = 1; 446 return AH_TRUE; 447 case HAL_CAP_TX_CHAINMASK: 448 setting &= ath_hal_eepromGet(ah, AR_EEP_TXMASK, NULL); 449 pCap->halTxChainMask = setting; 450 if (owl_get_ntxchains(setting) > 2) 451 pCap->halTxStreams = 2; 452 else 453 pCap->halTxStreams = 1; 454 return AH_TRUE; 455 default: 456 break; 457 } 458 return ar5212SetCapability(ah, type, capability, setting, status); 459 } 460 461 static int ar5416DetectMacHang(struct ath_hal *ah); 462 static int ar5416DetectBBHang(struct ath_hal *ah); 463 464 HAL_BOOL 465 ar5416GetDiagState(struct ath_hal *ah, int request, 466 const void *args, uint32_t argsize, 467 void **result, uint32_t *resultsize) 468 { 469 struct ath_hal_5416 *ahp = AH5416(ah); 470 int hangs; 471 472 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) 473 return AH_TRUE; 474 switch (request) { 475 case HAL_DIAG_EEPROM: 476 return ath_hal_eepromDiag(ah, request, 477 args, argsize, result, resultsize); 478 case HAL_DIAG_CHECK_HANGS: 479 if (argsize != sizeof(int)) 480 return AH_FALSE; 481 hangs = *(const int *) args; 482 ahp->ah_hangs = 0; 483 if (hangs & HAL_BB_HANGS) 484 ahp->ah_hangs |= ar5416DetectBBHang(ah); 485 /* NB: if BB is hung MAC will be hung too so skip check */ 486 if (ahp->ah_hangs == 0 && (hangs & HAL_MAC_HANGS)) 487 ahp->ah_hangs |= ar5416DetectMacHang(ah); 488 *result = &ahp->ah_hangs; 489 *resultsize = sizeof(ahp->ah_hangs); 490 return AH_TRUE; 491 } 492 return ar5212GetDiagState(ah, request, 493 args, argsize, result, resultsize); 494 } 495 496 typedef struct { 497 uint32_t dma_dbg_3; 498 uint32_t dma_dbg_4; 499 uint32_t dma_dbg_5; 500 uint32_t dma_dbg_6; 501 } mac_dbg_regs_t; 502 503 typedef enum { 504 dcu_chain_state = 0x1, 505 dcu_complete_state = 0x2, 506 qcu_state = 0x4, 507 qcu_fsp_ok = 0x8, 508 qcu_fsp_state = 0x10, 509 qcu_stitch_state = 0x20, 510 qcu_fetch_state = 0x40, 511 qcu_complete_state = 0x80 512 } hal_mac_hangs_t; 513 514 typedef struct { 515 int states; 516 uint8_t dcu_chain_state; 517 uint8_t dcu_complete_state; 518 uint8_t qcu_state; 519 uint8_t qcu_fsp_ok; 520 uint8_t qcu_fsp_state; 521 uint8_t qcu_stitch_state; 522 uint8_t qcu_fetch_state; 523 uint8_t qcu_complete_state; 524 } hal_mac_hang_check_t; 525 526 HAL_BOOL 527 ar5416SetRifsDelay(struct ath_hal *ah, const struct ieee80211_channel *chan, 528 HAL_BOOL enable) 529 { 530 uint32_t val; 531 HAL_BOOL is_chan_2g = AH_FALSE; 532 HAL_BOOL is_ht40 = AH_FALSE; 533 534 if (chan) 535 is_chan_2g = IEEE80211_IS_CHAN_2GHZ(chan); 536 537 if (chan) 538 is_ht40 = IEEE80211_IS_CHAN_HT40(chan); 539 540 /* Only support disabling RIFS delay for now */ 541 HALASSERT(enable == AH_FALSE); 542 543 if (enable == AH_TRUE) 544 return AH_FALSE; 545 546 /* Change RIFS init delay to 0 */ 547 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 548 val &= ~AR_PHY_RIFS_INIT_DELAY; 549 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 550 551 /* 552 * For Owl, RIFS RX parameters are controlled differently; 553 * it isn't enabled in the inivals by default. 554 * 555 * For Sowl/Howl, RIFS RX is enabled in the inivals by default; 556 * the following code sets them back to non-RIFS values. 557 * 558 * For > Sowl/Howl, RIFS RX can be left on by default and so 559 * this function shouldn't be called. 560 */ 561 if ((! AR_SREV_SOWL(ah)) && (! AR_SREV_HOWL(ah))) 562 return AH_TRUE; 563 564 /* Reset search delay to default values */ 565 if (is_chan_2g) 566 if (is_ht40) 567 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x268); 568 else 569 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x134); 570 else 571 if (is_ht40) 572 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x370); 573 else 574 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x1b8); 575 576 return AH_TRUE; 577 } 578 579 static HAL_BOOL 580 ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs, 581 const hal_mac_hang_check_t *check) 582 { 583 int found_states; 584 585 found_states = 0; 586 if (check->states & dcu_chain_state) { 587 int i; 588 589 for (i = 0; i < 6; i++) { 590 if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) == 591 check->dcu_chain_state) 592 found_states |= dcu_chain_state; 593 } 594 for (i = 0; i < 4; i++) { 595 if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) == 596 check->dcu_chain_state) 597 found_states |= dcu_chain_state; 598 } 599 } 600 if (check->states & dcu_complete_state) { 601 if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state) 602 found_states |= dcu_complete_state; 603 } 604 if (check->states & qcu_stitch_state) { 605 if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state) 606 found_states |= qcu_stitch_state; 607 } 608 if (check->states & qcu_fetch_state) { 609 if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state) 610 found_states |= qcu_fetch_state; 611 } 612 if (check->states & qcu_complete_state) { 613 if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state) 614 found_states |= qcu_complete_state; 615 } 616 return (found_states == check->states); 617 } 618 619 #define NUM_STATUS_READS 50 620 621 static int 622 ar5416DetectMacHang(struct ath_hal *ah) 623 { 624 static const hal_mac_hang_check_t hang_sig1 = { 625 .dcu_chain_state = 0x6, 626 .dcu_complete_state = 0x1, 627 .states = dcu_chain_state 628 | dcu_complete_state, 629 }; 630 static const hal_mac_hang_check_t hang_sig2 = { 631 .qcu_stitch_state = 0x9, 632 .qcu_fetch_state = 0x8, 633 .qcu_complete_state = 0x4, 634 .states = qcu_stitch_state 635 | qcu_fetch_state 636 | qcu_complete_state, 637 }; 638 mac_dbg_regs_t mac_dbg; 639 int i; 640 641 mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3); 642 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 643 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 644 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 645 for (i = 1; i <= NUM_STATUS_READS; i++) { 646 if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) || 647 mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) || 648 mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) || 649 mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6)) 650 return 0; 651 } 652 653 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1)) 654 return HAL_MAC_HANG_SIG1; 655 if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2)) 656 return HAL_MAC_HANG_SIG2; 657 658 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown MAC hang signature " 659 "DMADBG_3=0x%x DMADBG_4=0x%x DMADBG_5=0x%x DMADBG_6=0x%x\n", 660 __func__, mac_dbg.dma_dbg_3, mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 661 mac_dbg.dma_dbg_6); 662 663 return 0; 664 } 665 666 /* 667 * Determine if the baseband using the Observation Bus Register 668 */ 669 static int 670 ar5416DetectBBHang(struct ath_hal *ah) 671 { 672 #define N(a) (sizeof(a)/sizeof(a[0])) 673 /* 674 * Check the PCU Observation Bus 1 register (0x806c) 675 * NUM_STATUS_READS times 676 * 677 * 4 known BB hang signatures - 678 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 679 * [2] bits 8,9 are 1, bit 11 is 0. State machine state 680 * (bits 25-31) is 0x52 681 * [3] bits 8,9 are 1, bit 11 is 0. State machine state 682 * (bits 25-31) is 0x18 683 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 684 * Rx State (bits 20-24) is 0x7. 685 */ 686 static const struct { 687 uint32_t val; 688 uint32_t mask; 689 int code; 690 } hang_list[] = { 691 /* Reg Value Reg Mask Hang Code XXX */ 692 { 0x1E000000, 0x7E000B00, HAL_BB_HANG_DFS }, 693 { 0x52000B00, 0x7E000B00, HAL_BB_HANG_RIFS }, 694 { 0x18000B00, 0x7E000B00, HAL_BB_HANG_RX_CLEAR }, 695 { 0x00702400, 0x7E7FFFEF, HAL_BB_HANG_RX_CLEAR } 696 }; 697 uint32_t hang_sig; 698 int i; 699 700 hang_sig = OS_REG_READ(ah, AR_OBSERV_1); 701 for (i = 1; i <= NUM_STATUS_READS; i++) { 702 if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1)) 703 return 0; 704 } 705 for (i = 0; i < N(hang_list); i++) 706 if ((hang_sig & hang_list[i].mask) == hang_list[i].val) { 707 HALDEBUG(ah, HAL_DEBUG_HANG, 708 "%s BB hang, signature 0x%x, code 0x%x\n", 709 __func__, hang_sig, hang_list[i].code); 710 return hang_list[i].code; 711 } 712 713 HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown BB hang signature! " 714 "<0x806c>=0x%x\n", __func__, hang_sig); 715 716 return 0; 717 #undef N 718 } 719 #undef NUM_STATUS_READS 720