1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5416/ar5416.h" 25 #include "ar5416/ar5416reg.h" 26 27 /* 28 * Checks to see if an interrupt is pending on our NIC 29 * 30 * Returns: TRUE if an interrupt is pending 31 * FALSE if not 32 */ 33 HAL_BOOL 34 ar5416IsInterruptPending(struct ath_hal *ah) 35 { 36 uint32_t isr; 37 38 if (AR_SREV_HOWL(ah)) 39 return AH_TRUE; 40 41 /* 42 * Some platforms trigger our ISR before applying power to 43 * the card, so make sure the INTPEND is really 1, not 0xffffffff. 44 */ 45 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE); 46 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0) 47 return AH_TRUE; 48 49 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 50 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT)) 51 return AH_TRUE; 52 53 return AH_FALSE; 54 } 55 56 /* 57 * Reads the Interrupt Status Register value from the NIC, thus deasserting 58 * the interrupt line, and returns both the masked and unmasked mapped ISR 59 * values. The value returned is mapped to abstract the hw-specific bit 60 * locations in the Interrupt Status Register. 61 * 62 * (*masked) is cleared on initial call. 63 * 64 * Returns: A hardware-abstracted bitmap of all non-masked-out 65 * interrupts pending, as well as an unmasked value 66 */ 67 HAL_BOOL 68 ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 69 { 70 uint32_t isr, isr0, isr1, sync_cause = 0; 71 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 72 73 /* 74 * Verify there's a mac interrupt and the RTC is on. 75 */ 76 if (AR_SREV_HOWL(ah)) { 77 *masked = 0; 78 isr = OS_REG_READ(ah, AR_ISR); 79 } else { 80 if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 81 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 82 isr = OS_REG_READ(ah, AR_ISR); 83 else 84 isr = 0; 85 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 86 sync_cause &= AR_INTR_SYNC_DEFAULT; 87 *masked = 0; 88 89 if (isr == 0 && sync_cause == 0) 90 return AH_FALSE; 91 } 92 93 if (isr != 0) { 94 struct ath_hal_5212 *ahp = AH5212(ah); 95 uint32_t mask2; 96 97 mask2 = 0; 98 if (isr & AR_ISR_BCNMISC) { 99 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); 100 if (isr2 & AR_ISR_S2_TIM) 101 mask2 |= HAL_INT_TIM; 102 if (isr2 & AR_ISR_S2_DTIM) 103 mask2 |= HAL_INT_DTIM; 104 if (isr2 & AR_ISR_S2_DTIMSYNC) 105 mask2 |= HAL_INT_DTIMSYNC; 106 if (isr2 & (AR_ISR_S2_CABEND )) 107 mask2 |= HAL_INT_CABEND; 108 if (isr2 & AR_ISR_S2_GTT) 109 mask2 |= HAL_INT_GTT; 110 if (isr2 & AR_ISR_S2_CST) 111 mask2 |= HAL_INT_CST; 112 if (isr2 & AR_ISR_S2_TSFOOR) 113 mask2 |= HAL_INT_TSFOOR; 114 115 /* 116 * Don't mask out AR_BCNMISC; instead mask 117 * out what causes it. 118 */ 119 OS_REG_WRITE(ah, AR_ISR_S2, isr2); 120 isr &= ~AR_ISR_BCNMISC; 121 } 122 123 if (isr == 0xffffffff) { 124 *masked = 0; 125 return AH_FALSE; 126 } 127 128 *masked = isr & HAL_INT_COMMON; 129 130 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 131 *masked |= HAL_INT_RX; 132 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 133 *masked |= HAL_INT_TX; 134 135 /* 136 * When doing RX interrupt mitigation, the RXOK bit is set 137 * in AR_ISR even if the relevant bit in AR_IMR is clear. 138 * Since this interrupt may be due to another source, don't 139 * just automatically set HAL_INT_RX if it's set, otherwise 140 * we could prematurely service the RX queue. 141 * 142 * In some cases, the driver can even handle all the RX 143 * frames just before the mitigation interrupt fires. 144 * The subsequent RX processing trip will then end up 145 * processing 0 frames. 146 */ 147 #ifdef AH_AR5416_INTERRUPT_MITIGATION 148 if (isr & AR_ISR_RXERR) 149 *masked |= HAL_INT_RX; 150 #else 151 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 152 *masked |= HAL_INT_RX; 153 #endif 154 155 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | 156 AR_ISR_TXEOL)) { 157 *masked |= HAL_INT_TX; 158 159 isr0 = OS_REG_READ(ah, AR_ISR_S0); 160 OS_REG_WRITE(ah, AR_ISR_S0, isr0); 161 isr1 = OS_REG_READ(ah, AR_ISR_S1); 162 OS_REG_WRITE(ah, AR_ISR_S1, isr1); 163 164 /* 165 * Don't clear the primary ISR TX bits, clear 166 * what causes them (S0/S1.) 167 */ 168 isr &= ~(AR_ISR_TXOK | AR_ISR_TXDESC | 169 AR_ISR_TXERR | AR_ISR_TXEOL); 170 171 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK); 172 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC); 173 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); 174 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 175 } 176 177 if ((isr & AR_ISR_GENTMR) || (! pCap->halAutoSleepSupport)) { 178 uint32_t isr5; 179 isr5 = OS_REG_READ(ah, AR_ISR_S5); 180 OS_REG_WRITE(ah, AR_ISR_S5, isr5); 181 isr &= ~AR_ISR_GENTMR; 182 183 if (! pCap->halAutoSleepSupport) 184 if (isr5 & AR_ISR_S5_TIM_TIMER) 185 *masked |= HAL_INT_TIM_TIMER; 186 } 187 *masked |= mask2; 188 } 189 190 /* 191 * Since we're not using AR_ISR_RAC, clear the status bits 192 * for handled interrupts here. For bits whose interrupt 193 * source is a secondary register, those bits should've been 194 * masked out - instead of those bits being written back, 195 * their source (ie, the secondary status registers) should 196 * be cleared. That way there are no race conditions with 197 * new triggers coming in whilst they've been read/cleared. 198 */ 199 OS_REG_WRITE(ah, AR_ISR, isr); 200 /* Flush previous write */ 201 OS_REG_READ(ah, AR_ISR); 202 203 if (AR_SREV_HOWL(ah)) 204 return AH_TRUE; 205 206 if (sync_cause != 0) { 207 if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) { 208 *masked |= HAL_INT_FATAL; 209 } 210 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 211 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n", 212 __func__); 213 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 214 OS_REG_WRITE(ah, AR_RC, 0); 215 *masked |= HAL_INT_FATAL; 216 } 217 /* 218 * On fatal errors collect ISR state for debugging. 219 */ 220 if (*masked & HAL_INT_FATAL) { 221 AH_PRIVATE(ah)->ah_fatalState[0] = isr; 222 AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause; 223 HALDEBUG(ah, HAL_DEBUG_ANY, 224 "%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n", 225 __func__, isr, sync_cause); 226 } 227 228 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 229 /* NB: flush write */ 230 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 231 } 232 return AH_TRUE; 233 } 234 235 /* 236 * Atomically enables NIC interrupts. Interrupts are passed in 237 * via the enumerated bitmask in ints. 238 */ 239 HAL_INT 240 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) 241 { 242 struct ath_hal_5212 *ahp = AH5212(ah); 243 uint32_t omask = ahp->ah_maskReg; 244 uint32_t mask, mask2; 245 246 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 247 __func__, omask, ints); 248 249 if (omask & HAL_INT_GLOBAL) { 250 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 251 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 252 (void) OS_REG_READ(ah, AR_IER); 253 254 if (! AR_SREV_HOWL(ah)) { 255 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 256 (void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE); 257 258 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 259 (void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE); 260 } 261 } 262 263 mask = ints & HAL_INT_COMMON; 264 mask2 = 0; 265 266 #ifdef AH_AR5416_INTERRUPT_MITIGATION 267 /* 268 * Overwrite default mask if Interrupt mitigation 269 * is specified for AR5416 270 */ 271 if (ints & HAL_INT_RX) 272 mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM; 273 #else 274 if (ints & HAL_INT_RX) 275 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 276 #endif 277 if (ints & HAL_INT_TX) { 278 if (ahp->ah_txOkInterruptMask) 279 mask |= AR_IMR_TXOK; 280 if (ahp->ah_txErrInterruptMask) 281 mask |= AR_IMR_TXERR; 282 if (ahp->ah_txDescInterruptMask) 283 mask |= AR_IMR_TXDESC; 284 if (ahp->ah_txEolInterruptMask) 285 mask |= AR_IMR_TXEOL; 286 } 287 if (ints & (HAL_INT_BMISC)) { 288 mask |= AR_IMR_BCNMISC; 289 if (ints & HAL_INT_TIM) 290 mask2 |= AR_IMR_S2_TIM; 291 if (ints & HAL_INT_DTIM) 292 mask2 |= AR_IMR_S2_DTIM; 293 if (ints & HAL_INT_DTIMSYNC) 294 mask2 |= AR_IMR_S2_DTIMSYNC; 295 if (ints & HAL_INT_CABEND) 296 mask2 |= (AR_IMR_S2_CABEND ); 297 if (ints & HAL_INT_CST) 298 mask2 |= AR_IMR_S2_CST; 299 if (ints & HAL_INT_TSFOOR) 300 mask2 |= AR_IMR_S2_TSFOOR; 301 } 302 303 if (ints & (HAL_INT_GTT | HAL_INT_CST)) { 304 mask |= AR_IMR_BCNMISC; 305 if (ints & HAL_INT_GTT) 306 mask2 |= AR_IMR_S2_GTT; 307 if (ints & HAL_INT_CST) 308 mask2 |= AR_IMR_S2_CST; 309 } 310 311 /* Write the new IMR and store off our SW copy. */ 312 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 313 OS_REG_WRITE(ah, AR_IMR, mask); 314 mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 315 AR_IMR_S2_DTIM | 316 AR_IMR_S2_DTIMSYNC | 317 AR_IMR_S2_CABEND | 318 AR_IMR_S2_CABTO | 319 AR_IMR_S2_TSFOOR | 320 AR_IMR_S2_GTT | 321 AR_IMR_S2_CST); 322 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2); 323 324 ahp->ah_maskReg = ints; 325 326 /* Re-enable interrupts if they were enabled before. */ 327 if (ints & HAL_INT_GLOBAL) { 328 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 329 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 330 331 if (! AR_SREV_HOWL(ah)) { 332 mask = AR_INTR_MAC_IRQ; 333 if (ints & HAL_INT_GPIO) 334 mask |= SM(AH5416(ah)->ah_gpioMask, 335 AR_INTR_ASYNC_MASK_GPIO); 336 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask); 337 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask); 338 339 mask = AR_INTR_SYNC_DEFAULT; 340 if (ints & HAL_INT_GPIO) 341 mask |= SM(AH5416(ah)->ah_gpioMask, 342 AR_INTR_SYNC_MASK_GPIO); 343 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask); 344 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask); 345 } 346 } 347 348 return omask; 349 } 350