1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5416/ar5416.h" 25 #include "ar5416/ar5416reg.h" 26 27 /* 28 * Checks to see if an interrupt is pending on our NIC 29 * 30 * Returns: TRUE if an interrupt is pending 31 * FALSE if not 32 */ 33 HAL_BOOL 34 ar5416IsInterruptPending(struct ath_hal *ah) 35 { 36 uint32_t isr; 37 38 if (AR_SREV_HOWL(ah)) 39 return AH_TRUE; 40 41 /* 42 * Some platforms trigger our ISR before applying power to 43 * the card, so make sure the INTPEND is really 1, not 0xffffffff. 44 */ 45 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE); 46 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0) 47 return AH_TRUE; 48 49 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 50 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT)) 51 return AH_TRUE; 52 53 return AH_FALSE; 54 } 55 56 /* 57 * Reads the Interrupt Status Register value from the NIC, thus deasserting 58 * the interrupt line, and returns both the masked and unmasked mapped ISR 59 * values. The value returned is mapped to abstract the hw-specific bit 60 * locations in the Interrupt Status Register. 61 * 62 * (*masked) is cleared on initial call. 63 * 64 * Returns: A hardware-abstracted bitmap of all non-masked-out 65 * interrupts pending, as well as an unmasked value 66 */ 67 HAL_BOOL 68 ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 69 { 70 uint32_t isr, isr0, isr1, sync_cause = 0; 71 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 72 73 #ifdef AH_INTERRUPT_DEBUGGING 74 /* 75 * Blank the interrupt debugging area regardless. 76 */ 77 bzero(&ah->ah_intrstate, sizeof(ah->ah_intrstate)); 78 #endif 79 80 /* 81 * Verify there's a mac interrupt and the RTC is on. 82 */ 83 if (AR_SREV_HOWL(ah)) { 84 *masked = 0; 85 isr = OS_REG_READ(ah, AR_ISR); 86 } else { 87 if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 88 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 89 isr = OS_REG_READ(ah, AR_ISR); 90 else 91 isr = 0; 92 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 93 sync_cause &= AR_INTR_SYNC_DEFAULT; 94 *masked = 0; 95 96 if (isr == 0 && sync_cause == 0) 97 return AH_FALSE; 98 } 99 100 #ifdef AH_INTERRUPT_DEBUGGING 101 ah->ah_intrstate[0] = isr; 102 ah->ah_intrstate[1] = OS_REG_READ(ah, AR_ISR_S0); 103 ah->ah_intrstate[2] = OS_REG_READ(ah, AR_ISR_S1); 104 ah->ah_intrstate[3] = OS_REG_READ(ah, AR_ISR_S2); 105 ah->ah_intrstate[4] = OS_REG_READ(ah, AR_ISR_S3); 106 ah->ah_intrstate[5] = OS_REG_READ(ah, AR_ISR_S4); 107 ah->ah_intrstate[6] = OS_REG_READ(ah, AR_ISR_S5); 108 #endif 109 110 if (isr != 0) { 111 struct ath_hal_5212 *ahp = AH5212(ah); 112 uint32_t mask2; 113 114 mask2 = 0; 115 if (isr & AR_ISR_BCNMISC) { 116 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); 117 if (isr2 & AR_ISR_S2_TIM) 118 mask2 |= HAL_INT_TIM; 119 if (isr2 & AR_ISR_S2_DTIM) 120 mask2 |= HAL_INT_DTIM; 121 if (isr2 & AR_ISR_S2_DTIMSYNC) 122 mask2 |= HAL_INT_DTIMSYNC; 123 if (isr2 & (AR_ISR_S2_CABEND )) 124 mask2 |= HAL_INT_CABEND; 125 if (isr2 & AR_ISR_S2_GTT) 126 mask2 |= HAL_INT_GTT; 127 if (isr2 & AR_ISR_S2_CST) 128 mask2 |= HAL_INT_CST; 129 if (isr2 & AR_ISR_S2_TSFOOR) 130 mask2 |= HAL_INT_TSFOOR; 131 132 /* 133 * Don't mask out AR_BCNMISC; instead mask 134 * out what causes it. 135 */ 136 OS_REG_WRITE(ah, AR_ISR_S2, isr2); 137 isr &= ~AR_ISR_BCNMISC; 138 } 139 140 if (isr == 0xffffffff) { 141 *masked = 0; 142 return AH_FALSE; 143 } 144 145 *masked = isr & HAL_INT_COMMON; 146 147 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 148 *masked |= HAL_INT_RX; 149 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 150 *masked |= HAL_INT_TX; 151 152 /* 153 * When doing RX interrupt mitigation, the RXOK bit is set 154 * in AR_ISR even if the relevant bit in AR_IMR is clear. 155 * Since this interrupt may be due to another source, don't 156 * just automatically set HAL_INT_RX if it's set, otherwise 157 * we could prematurely service the RX queue. 158 * 159 * In some cases, the driver can even handle all the RX 160 * frames just before the mitigation interrupt fires. 161 * The subsequent RX processing trip will then end up 162 * processing 0 frames. 163 */ 164 #ifdef AH_AR5416_INTERRUPT_MITIGATION 165 if (isr & AR_ISR_RXERR) 166 *masked |= HAL_INT_RX; 167 #else 168 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 169 *masked |= HAL_INT_RX; 170 #endif 171 172 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | 173 AR_ISR_TXEOL)) { 174 *masked |= HAL_INT_TX; 175 176 isr0 = OS_REG_READ(ah, AR_ISR_S0); 177 OS_REG_WRITE(ah, AR_ISR_S0, isr0); 178 isr1 = OS_REG_READ(ah, AR_ISR_S1); 179 OS_REG_WRITE(ah, AR_ISR_S1, isr1); 180 181 /* 182 * Don't clear the primary ISR TX bits, clear 183 * what causes them (S0/S1.) 184 */ 185 isr &= ~(AR_ISR_TXOK | AR_ISR_TXDESC | 186 AR_ISR_TXERR | AR_ISR_TXEOL); 187 188 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK); 189 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC); 190 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); 191 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 192 } 193 194 if ((isr & AR_ISR_GENTMR) || (! pCap->halAutoSleepSupport)) { 195 uint32_t isr5; 196 isr5 = OS_REG_READ(ah, AR_ISR_S5); 197 OS_REG_WRITE(ah, AR_ISR_S5, isr5); 198 isr &= ~AR_ISR_GENTMR; 199 200 if (! pCap->halAutoSleepSupport) 201 if (isr5 & AR_ISR_S5_TIM_TIMER) 202 *masked |= HAL_INT_TIM_TIMER; 203 } 204 *masked |= mask2; 205 } 206 207 /* 208 * Since we're not using AR_ISR_RAC, clear the status bits 209 * for handled interrupts here. For bits whose interrupt 210 * source is a secondary register, those bits should've been 211 * masked out - instead of those bits being written back, 212 * their source (ie, the secondary status registers) should 213 * be cleared. That way there are no race conditions with 214 * new triggers coming in whilst they've been read/cleared. 215 */ 216 OS_REG_WRITE(ah, AR_ISR, isr); 217 /* Flush previous write */ 218 OS_REG_READ(ah, AR_ISR); 219 220 if (AR_SREV_HOWL(ah)) 221 return AH_TRUE; 222 223 if (sync_cause != 0) { 224 if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) { 225 *masked |= HAL_INT_FATAL; 226 } 227 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 228 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n", 229 __func__); 230 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 231 OS_REG_WRITE(ah, AR_RC, 0); 232 *masked |= HAL_INT_FATAL; 233 } 234 /* 235 * On fatal errors collect ISR state for debugging. 236 */ 237 if (*masked & HAL_INT_FATAL) { 238 AH_PRIVATE(ah)->ah_fatalState[0] = isr; 239 AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause; 240 HALDEBUG(ah, HAL_DEBUG_ANY, 241 "%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n", 242 __func__, isr, sync_cause); 243 } 244 245 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 246 /* NB: flush write */ 247 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 248 } 249 return AH_TRUE; 250 } 251 252 /* 253 * Atomically enables NIC interrupts. Interrupts are passed in 254 * via the enumerated bitmask in ints. 255 */ 256 HAL_INT 257 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) 258 { 259 struct ath_hal_5212 *ahp = AH5212(ah); 260 uint32_t omask = ahp->ah_maskReg; 261 uint32_t mask, mask2; 262 263 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 264 __func__, omask, ints); 265 266 if (omask & HAL_INT_GLOBAL) { 267 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 268 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 269 (void) OS_REG_READ(ah, AR_IER); 270 271 if (! AR_SREV_HOWL(ah)) { 272 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 273 (void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE); 274 275 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 276 (void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE); 277 } 278 } 279 280 mask = ints & HAL_INT_COMMON; 281 mask2 = 0; 282 283 #ifdef AH_AR5416_INTERRUPT_MITIGATION 284 /* 285 * Overwrite default mask if Interrupt mitigation 286 * is specified for AR5416 287 */ 288 if (ints & HAL_INT_RX) 289 mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM; 290 #else 291 if (ints & HAL_INT_RX) 292 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 293 #endif 294 if (ints & HAL_INT_TX) { 295 if (ahp->ah_txOkInterruptMask) 296 mask |= AR_IMR_TXOK; 297 if (ahp->ah_txErrInterruptMask) 298 mask |= AR_IMR_TXERR; 299 if (ahp->ah_txDescInterruptMask) 300 mask |= AR_IMR_TXDESC; 301 if (ahp->ah_txEolInterruptMask) 302 mask |= AR_IMR_TXEOL; 303 } 304 if (ints & (HAL_INT_BMISC)) { 305 mask |= AR_IMR_BCNMISC; 306 if (ints & HAL_INT_TIM) 307 mask2 |= AR_IMR_S2_TIM; 308 if (ints & HAL_INT_DTIM) 309 mask2 |= AR_IMR_S2_DTIM; 310 if (ints & HAL_INT_DTIMSYNC) 311 mask2 |= AR_IMR_S2_DTIMSYNC; 312 if (ints & HAL_INT_CABEND) 313 mask2 |= (AR_IMR_S2_CABEND ); 314 if (ints & HAL_INT_CST) 315 mask2 |= AR_IMR_S2_CST; 316 if (ints & HAL_INT_TSFOOR) 317 mask2 |= AR_IMR_S2_TSFOOR; 318 } 319 320 if (ints & (HAL_INT_GTT | HAL_INT_CST)) { 321 mask |= AR_IMR_BCNMISC; 322 if (ints & HAL_INT_GTT) 323 mask2 |= AR_IMR_S2_GTT; 324 if (ints & HAL_INT_CST) 325 mask2 |= AR_IMR_S2_CST; 326 } 327 328 /* Write the new IMR and store off our SW copy. */ 329 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 330 OS_REG_WRITE(ah, AR_IMR, mask); 331 mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 332 AR_IMR_S2_DTIM | 333 AR_IMR_S2_DTIMSYNC | 334 AR_IMR_S2_CABEND | 335 AR_IMR_S2_CABTO | 336 AR_IMR_S2_TSFOOR | 337 AR_IMR_S2_GTT | 338 AR_IMR_S2_CST); 339 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2); 340 341 ahp->ah_maskReg = ints; 342 343 /* Re-enable interrupts if they were enabled before. */ 344 if (ints & HAL_INT_GLOBAL) { 345 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 346 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 347 348 if (! AR_SREV_HOWL(ah)) { 349 mask = AR_INTR_MAC_IRQ; 350 if (ints & HAL_INT_GPIO) 351 mask |= SM(AH5416(ah)->ah_gpioMask, 352 AR_INTR_ASYNC_MASK_GPIO); 353 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask); 354 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask); 355 356 mask = AR_INTR_SYNC_DEFAULT; 357 if (ints & HAL_INT_GPIO) 358 mask |= SM(AH5416(ah)->ah_gpioMask, 359 AR_INTR_SYNC_MASK_GPIO); 360 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask); 361 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask); 362 } 363 } 364 365 return omask; 366 } 367